 
  
FEATURES
APPLICATIONS
DESCRIPTION
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
24-Bit, 192-kHz Sampling, 6-Channel, Enhanced Multilevel,Delta-Sigma Digital-to-Analog Converter
•Dual-Supply Operation:•24-Bit Resolution – 5-V Analog•Analog Performance: – 3.3-V Digital– Dynamic Range: •5-V Tolerant Digital Logic Inputs•100 dB, Typical (PCM1602Y) •Package: LQFP-48•105 dB, Typical (PCM1602KY)– SNR:
•Integrated A/V Receivers•100 dB, Typical (PCM1602Y)
•DVD Movie and Audio Players•105 dB, Typical (PCM1602KY)
•HDTV Receivers– THD+N:
•Car Audio Systems•0.003%, Typical (PCM1602Y)
•DVD Add-On Cards for High-End PCs•0.002%, Typical (PCM1602KY)
•Digital Audio Workstations– Full-Scale Output: 3.1 Vp-p, Typical
•Other Multichannel Audio Systems•4×/8× Oversampling Interpolation Filter:– Stop-Band Attenuation: –55 dB– Pass-Band Ripple: ±0.03 dB
The PCM1602 is a CMOS, monolithic integratedcircuit that features six 24-bit audio digital-to-analog•Sampling Frequency:
converters (DACs) and support circuitry in a small– 5 kHz to 200 kHz (Channels 1 and 2)
LQFP-48 package. The DACs use Texas Instruments'– 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)
enhanced multilevel, delta-sigma architecture thatemploys fourth-order noise shaping and 8-level ampli-•Accepts 16-, 18-, 20-, and 24-Bit Audio Data
tude quantization to achieve excellent signal-to-noise•Data Formats: Standard, I
2
S, and
performance and a high tolerance to clock jitter.Left-Justified
The PCM1602 accepts industry-standard audio data•System Clock: 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
,
formats with 16- to 24-bit audio data. Sampling rates512 f
S
, or 768 f
S
up to 200 kHz (channels 1 and 2) or 100 kHz•User-Programmable Functions:
(channels 3, 4, 5, and 6) are supported. A full set ofuser-programmable functions is accessible through a– Digital Attenuation: 0 dB to –63 dB,
4-wire serial control port that supports register write0.5 dB/Step
and read functions.– Soft Mute– Zero Flags Can Be Used As General-Purpose Logic Output– Digital De-Emphasis
– Digital Filter Rolloff: Sharp or Slow
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.FilterPro is a trademark of Texas Instruments.System Two, Audio Precision are trademarks of Audio Precision, Inc.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
over operating free-air temperature range (unless otherwise noted)
V
DD
–0.3 V to 4 VPower supply voltageV
CC
–0.3 V to 6.5 VV
CC
, V
DD
Supply voltage difference V
CC
– V
DD
< 3 VGround voltage differences ±0.1 VDigital input voltage –0.3 V to 6.5 VInput current (except power supply pins) ±10 mAOperating temperature under bias –40°C to 125°CStorage temperature –55°C to 150°CJunction temperature 150°CLead temperature (soldering) 260°C, 5 sPackage temperature (IR reflow, peak) 235°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range
MIN NOM MAX UNIT
Digital supply voltage, V
DD
3 3.3 3.6 VAnalog supply voltage, V
CC
4.5 5 5.5 VDigital input logic family TTLSystem clock 8.192 36.864 MHzDigital input clock frequency Sampling clock, V
OUT
1, V
OUT
2 32 192
kHzSampling clock, V
OUT
3, V
OUT
4, V
OUT
5, V
OUT
6 32 96Analog output load resistance 5 k ΩAnalog output load capacitance 50 pFDigital output load capacitance 20 pFOperating free-air temperature, T
A
–25 85 °C
2
www.ti.com
ELECTRICAL CHARACTERISTICS
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, system clock = 384 f
S
(f
S
= 44.1 kHz), and 24-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 24 Bits
DATA FORMAT
Audio data interface formats Standard, I
2
S, left-justifiedAudio data bit length 16-, 18-, 20-, 24-bit, selectableAudio data format MSB-first, binary 2s complementV
OUT
1, V
OUT
2 5 200f
S
Sampling frequency kHzV
OUT
3, V
OUT
4, V
OUT
5, V
OUT
6 5 100128 f
S
, 192 f
S
, 256 f
S
,System clock frequency
384 f
S
, 512 f
S
, 768 f
S
DIGITAL INPUT/OUTPUT
Logic family TTL-compatibleV
IH
2Input logic level VdcV
IL
0.8I
IH
(1)
V
IN
= V
DD
10I
IL
(1)
V
IN
= 0 V –10Input logic current µAI
IH
(2)
V
IN
= V
DD
65 100I
IL
(2)
V
IN
= 0 V –10V
OH
I
OH
= –4 mA 2.4Output logic level VdcV
OL
I
OL
= 4 mA 1
DYNAMIC PERFORMANCE
(3) (4)
PCM1602Y
V
OUT
= 0 dB, f
S
= 44.1 kHz 0.003% 0.009%V
OUT
= 0 dB, f
S
= 96 kHz 0.005%V
OUT
= 0 dB, f
S
= 192 kHz 0.006%THD+N Total harmonic distortion + noise
V
OUT
= –60 dB, f
S
= 44.1 kHz 1.25%V
OUT
= –60 dB, f
S
= 96 kHz 1.4%V
OUT
= –60 dB, f
S
= 192 kHz 1.65%EIAJ, A-weighted, f
S
= 44.1 kHz 94 100Dynamic range A-weighted, f
S
= 96 kHz 99 dBA-weighted, f
S
= 192 kHz 98EIAJ, A-weighted, f
S
= 44.1 kHz 94 100SNR Signal-to-noise ratio A-weighted, f
S
= 96 kHz 99 dBA-weighted, f
S
= 192 kHz 98f
S
= 44.1 kHz 91 98Channel separation f
S
= 96 kHz 97 dBf
S
= 192 kHz 96Level linearity error V
OUT
= –90 dB ±0.5 dB
(1) Pins 38, 40, 41, 45–47 (SCKI, BCK, LRCK, DATA1, DATA2, DATA3)(2) Pins 34–37 (MDI, MC, ML, RST)(3) Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ in theaveraging mode. The load connected to the analog output is 5 k Ωor larger, via capacitive loading.(4) Conditions in 192-kHz operation are: system clock = 128 f
S
, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 f
Sin register 12.
3
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, system clock = 384 f
S
(f
S
= 44.1 kHz), and 24-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PCM1602KY
V
OUT
= 0 dB, f
S
= 44.1 kHz 0.002% 0.007%V
OUT
= 0 dB, f
S
= 96 kHz 0.004%V
OUT
= 0 dB, f
S
= 192 kHz 0.005%THD+N Total harmonic distortion + noise
V
OUT
= –60 dB, f
S
= 44.1 kHz 0.7%V
OUT
= –60 dB, f
S
= 96 kHz 0.9%V
OUT
= –60 dB, f
S
= 192 kHz 1%EIAJ, A-weighted, f
S
= 44.1 kHz 99 105Dynamic range A-weighted, f
S
= 96 kHz 103 dBA-weighted, f
S
= 192 kHz 102EIAJ, A-weighted, f
S
= 44.1 kHz 99 105SNR Signal-to-noise ratio A-weighted, f
S
= 96 kHz 103 dBA-weighted, f
S
= 192 kHz 102f
S
= 44.1 kHz 96 103Channel separation f
S
= 96 kHz 101 dBf
S
= 192 kHz 100Level linearity error V
OUT
= –90 dB ±0.5 dB
DC ACCURACY
Gain error ±1 ±6 % of FSRGain mismatch, channel-to-channel ±1 ±3 % of FSRBipolar zero error V
OUT
= 0.5 V
CC
at bipolar zero ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (–0 dB) 0.62 V
CC
Vp-pCenter voltage 0.5 V
CC
VdcLoad impedance AC load 5 k Ω
DIGITAL FILTER PERFORMANCE
Group delay time 20/f
S
De-emphasis error ±0.1 dB
Filter Characteristics 1, Sharp Rolloff
Pass band ±0.03 dB 0.454 f
S
Pass band –3 dB 0.487 f
S
Stop band 0.546 f
S
Pass-band ripple ±0.03 dBStop-band attenuation Stop band = 0.546 f
S
–50 dBStop-band attenuation Stop band = 0.567 f
S
–55 dB
Filter Characteristics 2, Slow Rolloff
Pass band ±0.5 dB 0.198 f
S
Pass band –3 dB 0.39 f
S
Stop band 0.884 f
S
Pass-band ripple ±0.5 dBStop-band attenuation Stop band = 0.884 f
S
–40 dB
ANALOG FILTER PERFORMANCE
f = 20 kHz –0.03Frequency response dBf = 44 kHz –0.2
4
www.ti.com
Output Amp and
Low-Pass Filter
System Clock
Manager
Enhanced
Multilevel
Delta-Sigma
Modulator
DAC
Serial
Input
I/F
Function
Control
I/F
System Clock
Zero Detect Power Supply
DAC Output Amp and
DAC
DAC Output Amp and
DAC Output Amp and
DAC Output Amp and
VOUT1
VOUT2
VOUT3
VOUT4
VCOM
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Output Amp and
B0033-02
ZERO1/GPO1
BCK
LRCK
DATA1 (1,2)
TEST
DATA2 (3,4)
DATA3 (5,6)
RST
ML
MC
MDI
MDO
SCKI
AGND1−6
SCKO
VCC1−5
VDD
DGND
ZEROA
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
4× / 8×
Oversampling
Digital Filter
With
Function
Controller
VOUT6
VOUT5
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, system clock = 384 f
S
(f
S
= 44.1 kHz), and 24-bit data, unlessotherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-SUPPLY REQUIREMENTS
(5)
V
DD
3 3.3 3.6Voltage range VdcV
CC
4.5 5 5.5f
S
= 44.1 kHz 11 15I
DD
(6)
f
S
= 96 kHz 24f
S
= 192 kHz 19Supply current mAf
S
= 44.1 kHz 27 38I
CC
f
S
= 96 kHz 28f
S
= 192 kHz 28f
S
= 44.1 kHz 171 240Power dissipation f
S
= 96 kHz 219 mWf
S
= 192 kHz 203
TEMPERATURE RANGE
T
A
Operation temperature –25 85 °Cθ
JA
Thermal resistance 100 °C/W
(5) Conditions in 192-kHz operation are: system clock = 128 f
S
, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 f
Sin register 12.(6) SCKO is disabled.
FUNCTIONAL BLOCK DIAGRAM
5
www.ti.com
37 VCC3
AGND3
VCC4
AGND4
NC
AGND6
VCC5
AGND5
NC
VCOM
VOUT1
VOUT2
25
24
RST
SCKI
SCKO
BCK
LRCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
12
26
11
27
10
28
9
29
8
30
7
31
6
32
5
33
4
34
3
35
2
36
1
PT PACKAGE
(TOP VIEW)
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
ML
MC
MDI
MDO
NC
NC
NC
NC
VCC1
AGND1
VCC2
AGND2
P0028-01
PCM1602
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND1 27 – Analog groundAGND2 25 – Analog groundAGND3 23 – Analog groundAGND4 21 – Analog groundAGND5 17 – Analog groundAGND6 19 – Analog groundBCK 40 I Shift clock input for serial audio data. Clock must be one of 32 f
S
, 48 f
S
, or 64 f
S
.
(1)
DATA1 45 I Serial audio data input for V
OUT
1 and V
OUT
2
(1)
DATA2 46 I Serial audio data input for V
OUT
3 and V
OUT
4
(1)
DATA3 47 I Serial audio data input for V
OUT
5 and V
OUT
6
(1)
DGND 44 – Digital groundLRCK 41 I Left and right clock input. This clock is equal to the sampling rate, f
S
.
(1)
MC 35 I Shift clock for serial control port
(2)
MDI 34 I Serial data input for serial control port
(2)
MDO 33 O Serial data output for serial control port
(3)
ML 36 I Latch enable for serial control port
(2)
(1) Schmitt-trigger input, 5-V tolerant(2) Schmitt-trigger input with internal pulldown, 5-V tolerant(3) 3-state output
6
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
7, 8, 16, 20, 29,NC – No connection30, 31, 32RST 37 I System reset, active-low
(2)
System clock input. Input frequency is one of 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
.SCKI 38 I
(1)
Buffered clock output. Output frequency is one of 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, orSCKO 39 O
768 f
S
, or one-half of 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
.TEST 42 – Test pin. This pin should be connected to DGND.
(2)
V
CC
1 28 – Analog power supply, 5-VV
CC
2 26 – Analog power supply, 5-VV
CC
3 24 – Analog power supply, 5-VV
CC
4 22 – Analog power supply, 5-VV
CC
5 18 – Analog power supply, 5-VV
COM
15 O Common voltage output. This pin should be bypassed with a 10- µF capacitor to AGND.V
DD
43 – Digital power supply, 3.3-VV
OUT
1 14 O Voltage output of audio signal corresponding to Lch on DATA1. Up to 192 kHz.V
OUT
2 13 O Voltage output of audio signal corresponding to Rch on DATA1. Up to 192 kHz.V
OUT
3 12 O Voltage output of audio signal corresponding to Lch on DATA2. Up to 96 kHz.V
OUT
4 11 O Voltage output of audio signal corresponding to Rch on DATA2. Up to 96 kHz.V
OUT
5 10 O Voltage output of audio signal corresponding to Lch on DATA3. Up to 96 kHz.V
OUT
6 9 O Voltage output of audio signal corresponding to Rch on DATA3. Up to 96 kHz.ZERO1/GPO1 1 O Zero-data flag for V
OUT
1. Can also be used as GPO pin.ZERO2/GPO2 2 O Zero-data flag for V
OUT
2. Can also be used as GPO pin.ZERO3/GPO3 3 O Zero-data flag for V
OUT
3. Can also be used as GPO pin.ZERO4/GPO4 4 O Zero-data flag for V
OUT
4. Can also be used as GPO pin.ZERO5/GPO5 5 O Zero-data flag for V
OUT
5. Can also be used as GPO pin.ZERO6/GPO6 6 O Zero-data flag for V
OUT
6. Can also be used as GPO pin.ZEROA 48 O Zero-data flag. Logical AND of ZERO1 through ZERO6
7
www.ti.com
TYPICAL PERFORMANCE CURVES
Digital Filter (De-Emphasis Off)
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
01234
Amplitude − dB
G001
Frequency [× fS]
−0.05
−0.04
−0.03
−0.02
−0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G002
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
01234
Amplitude − dB
G003
Frequency [× fS]
−5
−4
−3
−2
−1
0
1
2
3
4
5
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G004
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit input data, unlessotherwise noted
FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)
Figure 1. Figure 2.
FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF)
Figure 3. Figure 4.
8
www.ti.com
TYPICAL PERFORMANCE CURVES (continued)
Digital Filter (De-Emphasis Curves)
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14
Level − dB
G005
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14
Error − dB
G006
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20
Level − dB
G007
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20
Error − dB
G008
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20 22
Level − dB
G009
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20 22
Error − dB
G010
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit input data, unlessotherwise noted
DE-EMPHASIS (f
S
= 32 kHz) DE-EMPHASIS ERROR (f
S
= 32 kHz)
Figure 5. Figure 6.
DE-EMPHASIS (f
S
= 44.1 kHz) DE-EMPHASIS ERROR (f
S
= 44.1 kHz)
Figure 7. Figure 8.
DE-EMPHASIS (f
S
= 48 kHz) DE-EMPHASIS ERROR (f
S
= 48 kHz)
Figure 9. Figure 10.
9
www.ti.com
TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE
Supply-Voltage Characteristics
VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Dynamic Range − dB
G012
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
VCC − Supply Voltage − V
4.0 4.5 5.0 5.5 6.0
THD+N − Total Harmonic Distortion + Noise − %
10
0.01
0.001
0.0001
G011
0.1
1
−60 dB/192 kHz, 128 fS
0 dB/192 kHz, 128 fS0 dB/96 kHz, 384 fS
−60 dB/44.1 kHz, 384 fS
0 dB/44.1 kHz, 384 fS
−60 dB/96 kHz, 384 fS
VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
SNR − Signal-to-Noise Ratio − dB
G013
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Channel Separation − dB
G014
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHzoperation are system clock = 128 f
S
, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 f
S
(set by OVERbit in register 12).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGEvs vsV
CC
(V
DD
= 3.3 V) V
CC
(V
DD
= 3.3 V)
Figure 11. Figure 12.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsV
CC
(V
DD
= 3.3 V) V
CC
(V
DD
= 3.3 V)
Figure 13. Figure 14.
10
www.ti.com
TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE (continued)
Temperature Characteristics
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Dynamic Range − dB
G016
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
−50 −25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harmonic Distortion + Noise − %
10
0.01
0.001
0.0001
G015
0.1
1
0 dB/192 kHz, 128 fS
0 dB/96 kHz, 384 fS
−60 dB/96 kHz, 384 fS
−60 dB/44.1 kHz, 384 fS
0 dB/44.1 kHz, 384 fS
−60 dB/192 kHz, 128 fS
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
SNR − Signal-to-Noise Ratio − dB
G017
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Channel Separation − dB
G018
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHzoperation are system clock = 128 f
S
, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 f
S
(set by OVERbit in register 12).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGEvs vsTEMPERATURE (T
A
) TEMPERATURE (T
A
)
Figure 15. Figure 16.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsTEMPERATURE (T
A
) TEMPERATURE (T
A
)
Figure 17. Figure 18.
11
www.ti.com
SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
SYSTEM CLOCK OUTPUT
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The PCM1602 requires a system clock for operating the digital interpolation filters and multilevel delta-sigmamodulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clockfrequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important touse a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments isan excellent choice for providing the PCM1602 system clock.
The 192-kHz sampling frequency operation is available on DATA1 for V
OUT
1 and V
OUT
2. It is recommended thatV
OUT
3, V
OUT
4, V
OUT
5, and V
OUT
6 be forced to the bipolar zero level using the DAC3, DAC4, DAC5, and DAC6bits of register 8 when operating at 192 kHz.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)(kHz)
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
8
(1) (1)
2.048 3.072 4.096 6.14416
(1) (1)
4.096 6.144 8.192 12.28832
(1) (1)
8.192 12.288 16.384 24.57644.1
(1) (1)
11.2896 16.9344 22.5792 33.868848
(1) (1)
12.288 18.432 24.576 36.86496
(1) (1)
24.576 36.864 49.152
(1)
192 24.576 36.864
(1) (1) (1) (1)
(1) This system clock is not supported for the given sampling frequency.
SYMBOL PARAMETER MIN MAX UNIT
t
w(SCKH)
System clock pulse duration, HIGH 7 nst
w(SCKL)
System clock pulse duration, LOW 7 ns
(1) 1/128 f
S
, ½56 f
S
, 1/384 f
S
, 1/512 f
S
, and 1/768 f
S
.
Figure 19. System Clock Timing
A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate ateither full (f
SCKI
) or half (f
SCKI
/2) rate. The SCKO output frequency can be programmed using the CLKD bit ofregister 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKOoutput is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.
12
www.ti.com
POWER-ON AND EXTERNAL RESET FUNCTIONS
Reset Reset Removal
VDD
2.4 V
2 V
1.6 V
Internal Reset
System Clock
T0014-08
0 V
Don’t Care 1024 System Clocks
Reset Removal
1024 System Clocks
RST
Internal Reset
System Clock
Reset
T0015-06
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The PCM1602 includes a power-on-reset function, as shown in Figure 20 . With the system clock active, and V
DD> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024system clocks from the time V
DD
> 2 V. After the initialization period, the PCM1602 is set to its reset defaultstate, as described in the Mode Control Registers section of this data sheet.
The PCM1602 also includes an external reset capability using the RST input (pin 37). This allows an externalcontroller or master reset circuit to force the PCM1602 to initialize to its reset default state. For normal operation,RST should be set to a logic-1.
The external reset operation and timing is shown in Figure 21 . The RST pin is set to logic-0 for a minimum of20 ns. After the initialization sequence is completed, the PCM1602 is set to its reset default state, as described inthe Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or V
CC
/2).After the reset period, the internal registers are initialized in the next 1/f
S
period and, if SCKI, BCK, and LRCKare provided continuously, the PCM1602 provides proper analog output with the group delay time given in theElectrical Characteristics section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1602 power-up andsystem-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock hasbeen activated.
Figure 20. Power-On-Reset Timing
Figure 21. External Reset Timing
13
www.ti.com
AUDIO SERIAL INTERFACE
AUDIO DATA FORMATS AND TIMING
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The audio serial interface for the PCM1602 consists of a 5-wire synchronous serial port. It includes LRCK (pin41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and DATA3 (pin 47). BCK is the serial audio bit clock, and isused to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift register.Serial data is clocked into the PCM1602 on the rising edge of BCK. LRCK is the serial audio left/right clock. It isused to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCKbe derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (f
S
). BCK can beoperated at 32, 48, or 64 times the sampling frequency (I
2
S format does not support BCK = 32 f
S
).
Internal operation of the PCM1602 is synchronized with LRCK. Accordingly, internal operation of the device issuspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least fora 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internaloperation is resynchronized automatically within a period of less than 3/f
S
. During this resynchronization periodand for a 3/f
S
time thereafter, the analog outputs are forced to the bipolar zero level, V
CC
/2. External resetting isnot required.
The PCM1602 supports industry-standard audio data formats, including standard, I
2
S, and left-justified (seeFigure 22 ). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailedtiming diagram of the serial audio interface.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. Theleft-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 2shows the mapping of the digital input data to the analog output pins.
14
www.ti.com
LRCK
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
MSB LSB
1/fS
(= 32 fS, 48 fS, or 64 fS)
18-Bit Right-Justified
1/fS
(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
MSB LSB
20-Bit Right-Justified
MSB LSB
24-Bit Right-Justified
1/fS
(= 48 fS, or 64 fS)
LSB
16-Bit Right-Justified, BCK = 48 fS or 64 fS
16-Bit Right-Justified, BCK = 32 fS
LSB
L-Channel R-Channel
BCK
DATA 14 15 16 14 15 16
14 15 16 14 15 16
16 17 18
DATA
DATA
DATA
DATA
1 2 3 16 17 18
18 19 20 1 2 3 18 19 20
22 23 24 1 2 3
MSB LSB
MSB LSB
LSB
MSB LSB
1 2 3 14 15 16
14 15 16
1 2 3 16 17 18
1 2 3 18 19 20
22 23 24
MSB LSB
1 2 3 22 23 24
L-Channel R-ChannelLRCK
BCK
DATA 1 2 3 1 2
MSB
N–2 N
N–1
LSB
L-Channel R-Channel
LRCK
BCK
DATA
T0009-05
MSB
123
MSB
1 2 3
MSB
123
123
MSB
N–2 N
N–1
LSB
1 2 3
MSB
N–2 N
N–1
LSB
123
MSB
N–2 N
N–1
LSB
(= 48 fS, or 64 fS)
1 2
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
Figure 22. Audio Data Input Formats
15
www.ti.com
DATA1, DATA2,
DATA3
t(BCH)
1.4 V
BCK
LRCK
t(BCL) t(LB)
t(BCY) t(BL)
t(DS) t(DH) T0010-06
1.4 V
1.4 V
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
SYMBOL PARAMETER MIN MAX UNITS
t
(BCY)
BCK pulse cycle time 1/(64 f
S
)
(1)
t
(BCH)
BCK high-level time 35 nst
(BCL)
BCK low-level time 35 nst
(BL)
BCK rising edge to LRCK edge 10 nst
(LB)
LRCK falling edge to BCK rising edge 10 nst
(DS)
DATA setup time 10 nst
(DH)
DATA hold time 10 ns
(1) f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.)
Figure 23. Audio Interface Timing
Table 2. Audio Input Data to Analog Output Mapping
DATA INPUT CHANNEL ANALOG OUTPUT
DATA1 Left V
OUT
1
(1)
DATA1 Right V
OUT
2
(1)
DATA2 Left V
OUT
3
(2)
DATA2 Right V
OUT
4
(2)
DATA3 Left V
OUT
5
(2)
DATA3 Right V
OUT
6
(2)
(1) Up to 192 kHz(2) Up to 96 kHz
16
www.ti.com
SERIAL CONTROL INTERFACE
REGISTER WRITE OPERATION
R0001-02
IDX6
MSB LSB
IDX5 IDX4R/W IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0
Register Index (or Address) Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (Register Index is Ignored)
IDX0 D7 D6 D4D5 D3 D2 D1 D0R/W
ML
MC
MDI X R/W IDX6
X
IDX1IDX2IDX3IDX4IDX5IDX6
X
T0048-02
SINGLE REGISTER READ OPERATION
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audiointerface. The serial control interface is used to program and read the on-chip mode registers. The controlinterface includes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO is the serial data output, usedto read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;MC is the serial bit clock, used to shift data in and out of the control port; and ML is the control port latch clock.
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data wordformat. The most significant bit is the read/write R/ W) bit. When set to 0, this bit indicates a write operation.Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eightbits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
Figure 25 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 stateuntil a register is to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are thenprovided on MC, corresponding to the 16 bits of the control data word on MDI. After the sixteenth clock cycle hascompleted, ML is set to logic-1 to latch the data into the indexed mode control register.
Figure 24. Control Data Word Format for MDI
Figure 25. Write Operation Timing
Read operations use the 16-bit control word format shown in Figure 24 . For read operations, the R/ W bit is setto 1. Read operations ignore the index bits, IDX[6:0], of the control data word. Instead, the REG[6:0] bits incontrol register 11 are used to set the index of the register that is to be read during the read operation. BitsIDX[6:0] should be set to 00h for read operations.
The details of the read operation are shown in Figure 26 . First, control register 11 must be written with the indexof the register to be read back. Additionally, the INC bit must be set to logic-0 in order to disable theauto-increment read function. The read cycle is then initiated by setting ML to logic-0 and setting the R/ W bit ofthe control data word to logic-1, indicating a read operation. MDO remains in a high-impedance state until thelast eight bits of the 16-bit read cycle, which correspond to the eight data bits of the register indexed by theREG[6:0] bits of control register 11. The read cycle is completed when ML is set to 1, immediately after the MCclock cycle for the least-significant bit of the indexed control register has completed.
17
www.ti.com
INC = 1 (Auto-Increment Read)
INDEX “N”
ML
1 0 0 0 0 0 0 0 X X X X X X X X
D0D1D2D3D4D5D6D7High Impedance
MC
MDI
MDO
INDEX “Y”
ML
XXXXXXXXXXXXXXXX
D0D1D2D3D4D5D6D7 High Impedance
MC
MDI
MDO
INDEX “N + 1”
D0D1D2D3D4D5D6D7
INC = 0 (Single-Register Read)
INDEX “N”
ML
1 0 0 0 0 0 0 0 X X X X X X X X
D0D1D2D3D4D5D6D7High Impedance
MC
MDI
MDO
T0075-01
AUTO-INCREMENT READ OPERATION
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
NOTES: X = Don’t carew
Y = Last register to be readw
In single-register read (INC = 0), the index which indicates the register to be read in read operation can be set byREG[6:0] in register 11. For example, setting REG[6:0] = 000 1001b means reading from register 9.In auto-increment read (INC = 1), the index REG[6:0] indicates the first register to be read. For example, settingREG[6:0] = 000 1001b means reading registers from 9 to Y. Y is determined by the low-to-high transition of ML inserial mode control.
Figure 26. Read Operation Timing
The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment readfunction is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the registerindexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for theleast-significant bit of last register.
18
www.ti.com
CONTROL INTERFACE TIMING REQUIREMENTS
t(MCH)
1.4 V
ML
t(MLS)
LSB
1.4 V
t(MCL)
t(MHH)
t(MLH)
t(MCY)
t(MDH)
t(MDS)
MC
MDI
LSB
MDI
T0013-05
LSB
50% of VDD
MDO
t(MOS)
1.4 V
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual readoperation starts on the next HIGH-to-LOW transition of the ML pin.
The read cycle starts by setting the R/ W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. Allsubsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO isset to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the datacontained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, andwhere Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after theMC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clockcontinues beyond the last physical register (register 12), the read operation returns to control register 1 andsubsequent control registers, continuing until ML is set to 1.
Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup andhold times, as well as t
(MLS)
and t
(MLH)
, which define minimum delays between the edges of the ML and MCclocks. These timing parameters are critical for proper control-port operation.
SYMBOL PARAMETER MIN MAX UNITS
t
(MCY)
MC pulse cycle time 100 nst
(MCL)
MC low-level time 50 nst
(MCH)
MC high-level time 50 nst
(MHH)
ML high-level time 300 nst
(MLS)
ML falling edge to MC rising edge 20 nst
(MLH)
ML hold time
(1)
20 nst
(MDH)
MDI hold time 15 nst
(MDS)
MDL setup time 20 nst
(MOS)
MC falling edge to MDO stable 30 ns
(1) MC rising edge for LSB to ML rising edge.
Figure 27. Control Interface Timing
19
www.ti.com
MODE CONTROL REGISTERS
User-Programmable Mode Controls
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The PCM1602 includes a number of user-programmable functions that are accessed via control registers. Theregisters are programmed using the serial control interface that is previously discussed in this data sheet.Table 3 lists the available mode control functions, along with their reset default conditions and associated registerindex.
Table 3. User-Programmable Mode Controls
CONTROLFUNCTION RESET DEFAULT BIT(S), INDEXREGISTER
AT1[7:0], AT2[7:0],Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation 1 through 6 AT3[7:0], AT4[7:0],AT51[7:0], AT6[7:0]Soft mute control Mute disabled 7 MUT[6:1]DAC1–DAC6 operation control DAC1–DAC6 enabled 8 DAC[6:1]Audio data format control 24-bit standard format 9 FMT[2:0]Digital filter rolloff control Sharp rolloff 9 FLTSCKO frequency selection Full rate (= f
SCKI
) 9 CLKDSCKO output enable SCKO enabled 9 CLKEDe-emphasis, all channelsDe-emphasis all-channel function control 10 DMCdisabledDe-emphasis all-channel sample rate selection 44.1 kHz 10 DMF[1:0]Output phase select Normal phase 10 DREVZero-flag polarity select High 10 ZREVRead-register index control REG[6:0] = 01h 11 REG[6:0]Read auto-increment control Auto-increment disabled 11 INCGeneral-purpose output enable Zero-flag enabled 12 GPOEGeneral-purpose output bits (GPO1–GPO6) Disabled 12 GPO[6:1]Oversampling rate control 64 ×12 OVER
20
www.ti.com
Reserved Registers
Register Map
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
Register 0 is reserved for factory use. To ensure proper operation, the user should not write to or read fromthese registers.
The mode control register map is shown in Table 4 . Each register includes an R/ W bit that determines whether aregister read R/ W = 1) or write R/ W = 0) operation is performed. Each register also includes an index (oraddress) indicated by the IDX[6:0] bits.
Table 4. Mode Control Register MapIDX REGIS- B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(B14–B8) TER
01h 1 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
02h 2 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
03h 3 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30
04h 4 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40
05h 5 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50
06h 6 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60
07h 7 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
MUT6 MUT5 MUT4 MUT3 MUT2 MUT1
08h 8 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
DAC6 DAC5 DAC4 DAC3 DAC2 DAC1
09h 9 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
FLT CLKD CLKE FMT2 FMT1 FMT0
0Ah 10 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
ZREV DREV DMF1 DMF0 DMC DMC DMC
0Bh 11 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0
0Ch 12 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1
(1) Reserved for test operation. It should be set to 0 during normal operation.
21
www.ti.com
Register Definitions
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 1 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
REGISTER 2 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
REGISTER 3 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30
REGISTER 4 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40
REGISTER 5 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50
REGISTER 6 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
ATx[7:0] – Digital Attenuation Level Setting
where x = 1 through 6, corresponding to the DAC output V
OUT
x.
These bits are read/write.
Default value: 1111 1111b
Each DAC output, V
OUT
1 through V
OUT
6, includes a digital attenuator function. The attenuation level can be setfrom 0 dB to –63 dB in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementingby one step (0.5 dB) for every 8/f
S
time interval until the programmed attenuator setting is reached. Alternatively,the attenuation level can be set to infinite attenuation, or mute.
The attenuation level is calculated using the following formula:
Attenuation level (dB) = 0.5 (ATx[7:0]
DEC
– 255)
where ATx[7:0]
DEC
= 0 through 255.
For ATx[7:0]
DEC
= 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuation levels for various settings.ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING
1111 1111b 255 0 dB, no attenuation (default)1111 1110b 254 –0.5 dB1111 1101b 253 –1 dB:::1000 0011b 131 –62 dB1000 0010b 130 –62.5 dB1000 0001b 129 –63 dB1000 0000b 128 Mute:::0000 0000b 0 Mute
22
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 7 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
MUTx – Soft Mute Control
Where x = 1 through 6, corresponding to the DAC output V
OUT
x.
These bits are read/write.
Default value: 0MUTx = 0 Mute disabled (default)MUTx = 1 Mute enabled
The mute bits, MUT1 through MUT6, are used to enable or disable the soft mute function for the correspondingDAC outputs, V
OUT
1 through V
OUT
6. The soft mute function is incorporated into the digital attenuators. Whenmute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by settingMUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infiniteattenuation setting, one attenuator step (0.5 dB) at a time. This provides a quiet, pop-free muting of the DACoutput. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to thepreviously programmed attenuation level.B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 8 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV DAC6 DAC5 DAC4 DAC3 DAC2 DAC1
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
DACx – DAC Operation Control
Where x = 1 through 6, corresponding to the DAC output V
OUT
x.
These bits are read/write.
Default value: 0DACx = 0 DAC operation enabled (default)DACx = 1 DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
OUT
1 through V
OUT
6. WhenDACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier inputis switched to the dc common-mode voltage (V
COM
), equal to V
CC
/2.
23
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 9 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT CLKD CLKE FMT2 FMT1 FMT0
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
FLT – Digital Filter Rolloff Control
This bit is read/write.Default value: 0FLT = 0 Sharp rolloff (default)FLT = 1 Slow rolloff
The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloffselections are available: sharp or slow. The filter responses for these selections are shown in the TypicalPerformance Curves section of this data sheet.
CLKD – SCKO Frequency Selection
This bit is read/write.Default value: 0CLKD = 0 Full-rate, f
SCKO
= f
SCKI
(default)CLKD = 1 Half-rate, f
SCKO
= f
SCKI
/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.
CLKE – SCKO Output Enable
This bit is read/write.Default value: 0CLKE = 0 SCKO enabled (default)CLKE = 1 SCKO disabled
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it outputseither a full- or half-rate clock, based on the setting of the CLKD bit. When SCKO is disabled, it is set to a LOWlevel.
FMT[2:0] – Audio Interface Data Format
These bits are read/write.Default value: 000bFMT[2:0] Audio Data Format Selection
000 24-bit standard format, right-justified data (default)001 20-bit standard format, right-justified data010 18-bit standard format, right-justified data011 16-bit standard format, right-justified data100 I
2
S format, 16- to 24-bit101 Left-justified format, 16- to 24-bit110 Reserved111 Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
24
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 10 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV ZREV DREV DMF1 DMF0 DMC DMC DMC
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
ZREV – Zero-Flag Polarity Select
Default value: 0ZREV = 0 Zero-flag pins HIGH at a zero detect (default)ZREV = 1 Zero-flag pins LOW at a zero detect
The ZREV bit allows the user to select the polarity of zero-flag pins.
DREV – Output Phase Select
Default value: 0DREV = 0 Normal output (default)DREV = 1 Inverted output
The DREV bit allows the user to select the phase of the analog output signal.
DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function
These bits are read/write.
Default value: 00bDMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)01 48 kHz10 32 kHz11 Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it isenabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. Thepreceding table shows the available sampling frequencies.
DMC – Digital De-Emphasis, All-Channel Function Control
This bit is read/write.
Default value: 0DMC = 0 De-emphasis disabled for all channels (default)DMC = 1 De-emphasis enabled for all channels
The DMC bits are used to enable or disable the de-emphasis function for all channels. The three DMC bits areORed together. Setting any one DMC bit, any combination of two DMC bits, or all three DMC bits to 1 enablesdigital de-emphasis for all channels. Setting all three DMC bits to 0 disables digital de-emphasis for all channels.
25
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 11 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
INC – Auto-Increment Read Control
This bit is read/write.
Default value: 0INC = 0 Auto-increment read disabled (default)INC = 1 Auto-increment read enabled
The INC bit is used to enable or disable the auto-increment read feature of the serial control interface. See theSerial Control Interface section of this data sheet for details regarding auto-increment read operation.
REG[6:0] – Read Register Index
These bits are read/write.
Default value: 01h
The REG[6:0] bits are used to set the index of the register to be read when performing the single-register readoperation. In the case of an auto-increment read operation, the REG[6:0] bits indicate the index of the lastregister to be read in the auto-increment read sequence. For example, if registers 1 through 6 are to be readduring an auto-increment read operation, the REG[6:0] bits would be set to 06h. See the Serial Control Interfacesection of this data sheet for details regarding the single-register and auto-increment read operations.
26
www.ti.com
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 12 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1
R/ W – Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
OVER – Oversampling Rate Control
These bits are read/write.
Default value: 0x
System clock rate = 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
:OVER = 0 64 ×oversampling (default)OVER = 1 128 ×oversampling
x
System clock rate = 128 f
S
or 192 f
S
:OVER = 0 32 ×oversampling (default)OVER = 1 64 ×oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting isrecommended when the oversampling rate is 192 kHz (system clock rate is 128 f
S
or 192 f
S
).
GPOE – General-Purpose Output Enable
This bit is read/write.
Default value: 0GPOE = 0 General-purpose outputs disabled (default)Pins default to zero-flag function (ZERO1 through ZERO6).GPOE = 1 General-purpose outputs enabledData written to GPO1 through GPO6 appears at the corresponding pins.
GPOx – General-Purpose Logic Output
Where: x = 1 through 6, corresponding pins GPO1 through GPO6.
These bits are read/write.
Default value: 0GPOx = 0 Set GPOx to 0 (default)GPOx = 1 Set GPOx to 1
The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are usedas general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs aredisabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.
27
www.ti.com
ANALOG OUTPUTS
f − Frequency − Hz
−100
−80
−60
−40
−20
0
20
Level − dB
1 100 1k 10M
G019
10 10k 100k 1M
V
COM
OUTPUT
–
VCOM
OPA337
+
10 µF
+
PCM1602
S0054-02
15
4
31VBIAS VCC
2
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The PCM1602 includes six independent output channels, V
OUT
1 through V
OUT
6. These are unbalanced outputs,each capable of driving 3.1 Vp-p typical into a 5-k Ωac load with V
CC
= 5 V. The internal output amplifiers forV
OUT
1 through V
OUT
6 are dc biased to the common-mode (or bipolar zero) voltage, equal to V
CC
/2.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energypresent at the DAC outputs due to the noise-shaping characteristics of the PCM1602 delta-sigma DACs. Thefrequency response of this filter is shown in Figure 28 . By itself, this filter is not enough to attenuate theout-of-band noise to an acceptable level for most applications. An external low-pass filter is required to providesufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the ApplicationInformation section of this data sheet.
Figure 28. Output-Filter Frequency Response
One unbuffered, common-mode voltage output pin, V
COM
(pin 15), is brought out for decoupling purposes. Thispin is nominally biased to a dc voltage level equal to V
CC
/2. If this pin is to be used to bias external circuitry, avoltage follower is required for buffering purposes. Figure 29 shows an example of using the V
COM
pin forexternal biasing applications.
Figure 29. Biasing External Circuits Using the V
COM
Pin
28
www.ti.com
ZERO FLAG
Zero-Detect Condition
Zero Output Flags
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
Zero detection for each output channel is independent from the others. If the data for a given channel remains ata 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are setto a logic-1 state. Each channel, ZERO1 through ZERO6 (pins 1 through 6), has zero-flag pins. In addition, all sixzero flags are logically ANDed together, and the result is provided at the ZEROA pin (pin 48), which is set to alogic-1 state when all channels indicate a zero-detect condition. The zero-flag pins can be used to operateexternal mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitallycontrolled function.
The active polarity of the zero-flag output can be inverted by setting to 1 the ZREV bit of control register 10. Thereset default is active-high output, or ZREV = 0.
29
www.ti.com
APPLICATION INFORMATION
CONNECTION DIAGRAMS
10 µF
10 µF
10 µF
ZERO1−6
+5V Power Supply
S0090-01
PLL170x
SCKO3
ML
MC
MD
Regulator
Microcontroller
LPF
LPF
LPF
LPF
LPF
LPF
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
LRCK
RST
BCK
DATA1
DATA2
DATA3
ZEROA
3536 25262728293031323334
VCC3
AGND3
VCC4
AGND4
NC
AGND6
VCC5
AGND5
NC
VCOM
VOUT1
VOUT2
24
23
22
21
20
19
18
17
16
15
14
13
PCM1602
37
38
39
40
41
42
43
44
45
46
47
48
RST
SCKI
SCKO
BCK
LRCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
21 1211109876543
ML
MC
MDI
MDO
NC
NC
NC
NC
VCC1
AGND1
VCC2
AGND2
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
A basic connection diagram with the necessary power-supply bypassing and decoupling components is shown inFigure 30 . Texas Instruments recommends using the component values shown in Figure 30 for all designs.
Figure 30. Basic Connection Diagram
30
www.ti.com
0.1 µF+5V Analog
S0091-01
µC/µP(1)
LF
3536 25262728293031323334
VCC3
AGND3
VCC4
AGND4
NC
AGND6
VCC5
AGND5
NC
VCOM
VOUT1
VOUT2
24
23
22
21
20
19
18
17
16
15
14
13
PCM1602
37
38
39
40
41
42
43
44
45
46
47
48
RST
SCKI
SCKO
BCK
LRCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
21 1211109876543
ML
MC
MDI
MDO
NC
NC
NC
NC
VCC1
AGND1
VCC2
AGND2
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
Zero Flag or
General−Purpose
Outputs
for Mute Circuits,
Microcontroller, or
DSP/Decoder
10 µF
REG1117
+3.3V
+3.3V for VDD
+
10 µF
+
Output
Low-Pass
Filters(4)
10 µF
+
10 µF
+
RF
LS
10 µF
+
10 µF
+
RS
10 µF
+
CTR
10 µF
+
SUB
DIGITAL SECTION ANALOG SECTION
C11
10 µF+
+3.3V
for VDD
C10
0.1 µF
RS(3)
PLL170x Buffer
SCKO3(2)
XT1
27MHz
Master Clock
RS
RS
Audio DSP
or
Decoder
RS
RS
RS
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
APPLICATION INFORMATION (continued)
(1) Serial control and reset functions can be provided by DSP/decoder GPIO pins.(2) Actual clock output used is determined by the application.(3) R
S
= 22 Ωto 100 Ω.(4) See the Application Information section of this datasheet for more information.
Figure 31. Typical Application Diagram
31
www.ti.com
POWER SUPPLIES AND GROUNDING
DAC OUTPUT FILTER CIRCUITS
–
2
31
OPA2134
+VOUT
R4
C2
C1
R3
R2
R1
VIN
AV R2
R1S0053-02
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
APPLICATION INFORMATION (continued)A typical application diagram is shown in Figure 31 . The REG1117-3.3 from Texas Instruments is used togenerate 3.3 V for V
DD
from the 5-V analog power supply. The PLL170x from Texas Instruments is used togenerate the system clock input at SCKI, as well as generating the clock for the audio signal processor.
Series resistors (22- Ωto 100- Ω) are recommended for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3. Theseries resistor combines with the stray PCB and device input capacitance to form a low-pass filter which removeshigh-frequency noise from the digital signal, thus reducing high-frequency emission.
The PCM1602 requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DACanalog and output filter circuitry, whereas the 3.3-V supply is used to power the digital filter and serial interfacecircuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using a linear regulator(see Figure 31 ).
Two capacitors are required for supply bypassing (see Figure 30 ). These capacitors should be located as closeas possible to the PCM1602 package. The 10- µF capacitors should be tantalum or aluminum electrolytic,whereas the 0.1- µF capacitors are ceramic (X7R type is recommended for surface-mount applications).
Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance atthe expense of generating increased out-of-band noise above the Nyquist frequency, or f
S
/2. The out-of-bandnoise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by acombination of on-chip and external low-pass filtering.
Figure 32 and Figure 33 show the recommended external low-pass active filter circuits for dual- andsingle-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB)circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature.For more information regarding MFB active filter design, see the FilterPro™ MFB and Sallen-Key Low-Pass FilterDesign Program application report (SBFA001 ), available from the TI Web site (www.ti.com).
Because the overall system performance is defined by the quality of the DACs and their associated analogoutput circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2134and OPA2353 dual operational amplifiers from Texas Instruments are shown in Figure 32 and Figure 33 , and arerecommended for use with the PCM1602.
Figure 32. Dual-Supply Filter Circuit
32
www.ti.com
–
PCM1602
AV R2
R1
VCOM
OPA2134
+
2
31
C1
R3
R2
C2
R1
C3
10 µF
+
S0056-02
R4
+
OPA337
−
To Additional
Low-Pass
Filter Circuits
VOUT
VIN
PCB LAYOUT GUIDELINES
Digital Logic
and
Audio
Processor
Digital Power
+VDDGND
Digital Section Analog Section
Return Path for Digital Signals
Analog Power
+VS
AGND −VS
+5VA
Digital
Ground
Analog
Ground
Output
Circuits
PCM1602
AGND
VCC
VDD
DGND
REG
B0031-03
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
APPLICATION INFORMATION (continued)
Figure 33. Single-Supply Filter Circuit
A typical PCB floor plan for the PCM1602 is shown in Figure 34 . A ground plane is recommended, with theanalog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1602should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connectionsto the digital audio interface and control signals originating from the digital section of the board.
Figure 34. Recommended PCB Layout
33
www.ti.com
VDD
Digital Section Analog Section
RF Choke or Ferrite Bead Power Supplies
Common
Ground
Output
Circuits
AGND
VCC
+VS
+5V −VS
AGND
VDD
DGND
REG
PCM1602
B0032-03
Digital Logic
and
Audio
Processor
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
PCB LAYOUT GUIDELINES (continued)Separate power supplies are recommended for the digital and analog sections of the board. This prevents theswitching noise present on the digital supply from contaminating the analog power supply and degrading thedynamic performance of the DACs. In cases where a common 5-V supply must be used for the analog anddigital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-Vsupply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 shows therecommended approach for single-supply applications.
Figure 35. Single-Supply PCB Layout
34
www.ti.com
THEORY OF OPERATION
B0008-03
+
+
−
Z–1
+
+ +
+
+
+
8-Level Quantizer
−Z–1
IN
8 fS
OUT
64 fS
+
+Z–1 +
+Z–1
+
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
The DAC section of the PCM1602 is based on a multi-bit delta-sigma architecture. This architecture uses afourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A blockdiagram of the delta-sigma modulator is shown in Figure 36 . This architecture has the advantage of stability andimproved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs.
Figure 36. Eight-Level Delta-Sigma Modulator
The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 f
S
, 64 f
S
, or128 f
S
. The total oversampling rate is determined by the desired sampling frequency. If f
S
≤96 kHz, then theOVER bit in register 12 can be set to an oversampling rate of 64 f
S
or 128 f
S
. If f
S
> 96 kHz, then the OVER bitcan be used to set the oversampling rate to 32 f
S
or 64 f
S
.Figure 37 shows the out-of-band quantization-noiseplots for both the 64 ×and 128 ×oversampling scenarios. Notice that the 128 ×oversampling plot showssignificantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at theoutput of the DAC.
35
www.ti.com
Frequency [fS]
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
012345678
Amplitude − dB
G021
Frequency [fS]
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
012345678
Amplitude − dB
G022
Jitter − ps
90
95
100
105
110
115
120
125
0 100 200 300 400 500 600
Dynamic Range − dB
G020
KEY PERFORMANCE PARAMETERS AND MEASUREMENT
TOTAL HARMONIC DISTORTION + NOISE
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
THEORY OF OPERATION (continued)
QUANTIZATION NOISE SPECTRUM QUANTIZATION NOISE SPECTRUM(64 ×OVERSAMPLING) vs(128 ×OVERSAMPLING)
Figure 37. Quantization-Noise Spectrum
Figure 38 illustrates the simulated jitter sensitivity of the PCM1602. To achieve best performance, the systemclock jitter should be less than 300 picoseconds. This is easily achieved using a quality clock generation IC, likethe PLL170x from Texas Instruments.
JITTER DEPENDENCE
(64 ×OVERSAMPLING)
Figure 38. Jitter Sensitivity
This section provides information on how to measure key dynamic performance parameters for the PCM1602. Inall cases, a System Two Cascade audio measurement system by Audio Precision or equivalent is used toperform the testing.
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes intoaccount both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rmsvalue of the distortion and noise is referred to as THD+N. The test setup for THD+N measurements is shown inFigure 39 .
36
www.ti.com
S/PDIF
Receiver
Evaluation Board
DEM-DAI1602
PCM1602 2nd-Order
Low-Pass
Filter
Notch FilterBand Limit
Analyzer
and
Display
Digital
Generator
S/PDIF
Output 100% Full-Scale
24-Bit, 1-kHz
Sine Wave
rms Mode HPF = 22 Hz(1)
LPF = 30 kHz(1)
Option = 20 kHz Apogee Filter(2)
fC = 1 kHz
f–3 dB = 54 kHz
B0062-01
DYNAMIC RANGE
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)
(1) There is little difference in measured THD+N when using the various settings for these filters.(2) Required for THD+N test
Figure 39. Test Setup for THD+N Measurements
For the PCM1602 DACs, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at theinput of the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1 kHzor 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurementsystem. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the DEM-DAI1602demonstration board. The receiver is then configured to output 24-bit data in either I
2
S or left-justified dataformat. The DAC audio interface format is programmed to match the receiver output format. The analog output isthen taken from the DAC post filter and connected to the analog analyzer input of the measurement system. Theanalog input is band-limited, using filters resident in the analyzer. The resulting THD+N is measured by theanalyzer and displayed by the measurement system.
Dynamic range is specified as A-weighted THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulusat the input of the DAC. This measurement is designed to give a good indication of how the DAC performs, givena low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 40 , and is similar to the THD+Ntest setup discussed previously. The differences include the band-limit filter selection, the additional A-weightingfilter, and the –60-dBFS input level.
37
www.ti.com
S/PDIF
Receiver
Evaluation Board
DEM-DAI1602
PCM1602(1) 2nd-Order
Low-Pass
Filter
Band Limit
A-Weight
Filter(1)
Analyzer
and
Display
Digital
Generator
S/PDIF
Output 0% Full-Scale,
Dither Off (SNR)
–60 dB FS,
1 kHz Sine Wave
(Dynamic Range)
rms Mode HPF = 22 Hz
LPF = 22 kHz
Option = A-Weighting(2)
B0063-01
f–3 dB = 54 kHz
fC = 1 kHz
Notch Filter
IDLE-CHANNEL SIGNAL-TO-NOISE RATIO
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)
(1) Infinite-zero-detect mute disabled(2) Results without A-weighting are approximately 3 dB worse.
Figure 40. Test Setup for Dynamic Range and SNR Measurements
The SNR test provides a measure of the noise of the DAC. The input to the DAC is in all-0s data, and the DACinfinite-zero-detect mute function must be disabled (default condition at power up for the PCM1602). Thisensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (ifpresent) can be observed at the output. The dither function of the digital signal generator must also be disabledto ensure an all-0s data stream at the input of the DAC.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the inputsignal level (see the notes provided in Figure 40 ).
38
www.ti.com
Revision History
PCM1602
SBAS163A – DECEMBER 2000 – REVISED JULY 2005
DATE REV PAGE SECTION DESCRIPTION
11 JUL 05 A – Global Changed to new format2 Absolute Maximum Changed values for power supply voltage, digital input voltage, leadRatings temperature, and package temperature, added supply voltage difference,V
CC
– V
DD
< 3 V.2 Recommended New table added to data sheetOperating Conditions4 Package/Ordering In- Table removed from page 4, reformatted, and inserted at end of data sheet.formation10, 11 Typical Performance In Figure 11 through Figure 18, corrected condition for 192 kHz.Curves12 System Clock Input In text, corrected register number from 9 to 8.14 Audio Serial Interface In text, corrected clock numbers from "one clock cycle" to "3-bit clockcycle".15, 16 Audio Data Formats In Figure 22, Audio Data Input Formats, removed 32-f
S
availability fromand Timing left-justified format, corrected relative relation between BCK and DATA. InFigure 23, Audio Interface Timing, corrected specification for BCK pulsecycle time, changed transition voltage.18, 19 Serial Control Interface In Figure 26, Read Operation Timing, corrected index numbers for Inc = 1(Auto-Increment Read) , corrected description of notes. In text, AutoIncrement Read Operation, corrected wrong descriptions and numbers sothat it describes right operation along with Figure 26. In Figure 27, ControlInterface Timing, corrected transition voltage.21 Mode Control Registers In text, Reserved Registers, corrected wrong register numbers from "0 and12" to "0". In Table 4, Mode Control Register Map, removed row for register00h.31 Application Information In Figure 31, Typical Application Diagram, corrected connections to pins25–29 and capacitance of C
10
.15 DEC * – – Original version00
39
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM1602KY NRND LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602KY/2K NRND LQFP PT 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602KY/2KG4 NRND LQFP PT 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602KYG4 NRND LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602Y NRND LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602Y/2K NRND LQFP PT 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602Y/2KG4 NRND LQFP PT 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1602YG4 NRND LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1602KY/2K LQFP PT 48 2000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q1
PCM1602Y/2K LQFP PT 48 2000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1602KY/2K LQFP PT 48 2000 346.0 346.0 33.0
PCM1602Y/2K LQFP PT 48 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK
4040052/C 1 1/96
0,13 NOM
0,17
0,27
25
24
SQ
12
13
36
37
6,80
7,20
1
48
5,50 TYP
0,25
0,45
0,75
0,05 MIN
SQ
9,20
8,80
1,35
1,45
1,60 MAX
Gage Plane
Seating Plane
0,10
0°–7°
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers amplifier.ti.com Audio www.ti.com/audioData Converters dataconverter.ti.com Automotive www.ti.com/automotiveDLP® Products www.dlp.com Broadband www.ti.com/broadbandDSP dsp.ti.com Digital Control www.ti.com/digitalcontrolClocks and Timers www.ti.com/clocks Medical www.ti.com/medicalInterface interface.ti.com Military www.ti.com/militaryLogic logic.ti.com Optical Networking www.ti.com/opticalnetworkPower Mgmt power.ti.com Security www.ti.com/securityMicrocontrollers microcontroller.ti.com Telephony www.ti.com/telephonyRFID www.ti-rfid.com Video & Imaging www.ti.com/videoRF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated