a FEATURES 170 MSPS Update Rate TTL/High Speed CMOS-Compatible Inputs Wideband SFDR: 66 dB @ 2 MHz/50 dB @ 65 MHz Pin-Compatible, Lower Cost Replacement for Industry Standard AD9721 DAC Low Power: 439 mW @ 170 MSPS Fast Settling: 3.8 ns to 1/2 LSB Internal Reference Two Package Styles: 28-Lead SOIC and SSOP APPLICATIONS Digital Communications Direct Digital Synthesis Waveform Reconstruction High Speed Imaging 5 MHz to 65 MHz HFC Upstream Path 10-Bit, 170 MSPS D/A Converter AD9731 FUNCTIONAL BLOCK DIAGRAM D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ANALOG RETURN TTL DRIVE LOGIC DECODERS AND DRIVERS REGISTER SWITCH NETWORK IOUT IOUT REF IN CLOCK CONTROL AMP INTERNAL VOLTAGE REFERENCE RSET REF OUT CONTROL AMP IN AMP OUT DIGITAL DIGITAL ANALOG +VS -VS -VS GENERAL DESCRIPTION The AD9731 is a 10-bit, 170 MSPS, bipolar D/A converter that is optimized to provide high dynamic performance, yet offer lower power dissipation and more economical pricing than afforded by previous bipolar high performance DAC solutions. The AD9731 was designed primarily for demanding communications systems applications where wideband spurious-free dynamic range (SFDR) requirements are strenuous and could previously only be met by using a high performance DAC such as the industry-standard AD9721. The proliferation of digital communications into base station and high volume subscriber-end markets has created a demand for excellent DAC performance delivered at reduced levels of power dissipation and cost. The AD9731 is the answer to that demand. Optimized for direct digital synthesis (DDS) waveform reconstruction, the AD9731 provides 50 dB of wideband harmonic suppression over a dc-to-65 MHz analog output bandwidth. This signal bandwidth addresses the transmit spectrum in many of the emerging digital communications applications where signal purity is critical. Narrowband, the AD9731 provides an SFDR of greater than 79 dB. This excellent wideband and narrowband ac performance, coupled with a lower pricing structure, make the AD9731 the optimum high performance DAC value. The AD9731 is packaged in 28-lead SOIC (same footprint as the industry-standard AD9721) and super space-saving 28-lead SSOP; both are specified to operate over the extended industrial temperature range of -40C to +85C. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9731-SPECIFICATIONS Parameter (+VS = +5 V, -VS = -5.2 V, CLOCK = 125 MHz, RSET = 1.96 k for 20.4 mA IOUT, VREF = -1.25 V, unless otherwise noted.) Test Level Temp RESOLUTION MAX CONVERSION RATE Min Typ Max Unit 10 Bits 170 MHz -40C to +85C IV 25C Full 25C Full I VI I VI 0.25 0.35 0.6 0.7 1 1.5 1 1.5 LSB LSB LSB LSB 25C Full 25C Full I VI I VI V 35 40 2.5 2.5 0.04 70 100 5 5 mA mA % FS % FS mA/C REFERENCE/CONTROL AMP Internal Reference Voltage2 Internal Reference Voltage Drift Internal Reference Output Current3 Amplifier Input Impedance Amplifier Bandwidth 25C Full Full 25C 25C I IV VI V V -1.25 100 -1.15 50 2.5 V mV/C mA kW MHz REFERENCE INPUT4 Reference Input Impedance Reference Multiplying Bandwidth5 25C 25C V V 4.6 75 kW MHz OUTPUT PERFORMANCE Output Current4, 6 Output Compliance Output Resistance Output Capacitance Voltage Settling Time to 1/2 LSB (tST)7 Propagation Delay (tPD)8 Glitch Impulse9 Output Slew Rate10 Output Rise Time10 Output Fall Time10 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C V IV V V V V V V V V Full Full Full 25C 25C 25C Full 25C Full 25C 25C IV VI VI VI VI IV IV IV IV IV IV 25C 25C 25C 25C 25C 25C V V V V V V DC ACCURACY Differential Nonlinearity Integral Nonlinearity INITIAL OFFSET ERROR Zero-Scale Offset Error Full-Scale Gain Error1 Offset Drift Coefficient DIGITAL INPUTS Input Capacitance Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Data Setup Time (tS)11 Data Hold Time (tH)12 Clock Pulsewidth Low (pwMIN) Clock Pulsewidth High (pwMAX) SFDR PERFORMANCE (Wideband) 13 AOUT = 0 dBFS 2 MHz fOUT 10 MHz fOUT 20 MHz fOUT 40 MHz fOUT 65 MHz fOUT (Clock = 170 MHz) 70 MHz fOUT (Clock = 170 MHz) -2- -1.35 -50 +500 20 -1.5 +3 240 5 3.8 2.9 4.1 400 1 1 2 2.0 8 30 2 2.5 1.0 1.0 2 2 0.1 0.1 66 62 61 55 50 47 0.8 50 100 mA V W pF ns ns pVs V/ms ns ns pF V V mA mA ns ns ns ns ns ns dB dB dB dB dB dB REV. B AD9731 SPECIFICATIONS Temp Test Level SFDR PERFORMANCE (Narrowband) 2 MHz; 2 MHz Span 25 MHz, 2 MHz Span 10 MHz, 5 MHz Span (Clock = 170 MHz) 25C 25C 25C V V V 79 61 73 dB dB dB INTERMODULATION DISTORTION14 F1 = 800 kHz, F2 = 900 kHz 25C V 58 dB 25C Full 25C Full 25C Full 25C Full 25C I VI I VI I VI V V V 27 27 45 45 13 15 439 449 100 Parameter Min Typ Max Unit 13 POWER SUPPLY15 Digital -V Supply Current Analog -V Supply Current Digital +V Supply Current Power Dissipation PSRR 37 42 53 66 20 22 mA mA mA mA mA mA mW mW mA/V NOTES 1 Measured as an error in ratio of full-scale current to current through R SET (640 mA nominal); ratio is nominally 32. DAC load is virtual ground. 2 Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification. 3 Internal reference output current defines load conditions applied during Internal Reference Voltage test. 4 Full-scale current variations among devices are higher when driving REFERENCE IN directly. 5 Frequency at which a 3 dB change in output of DAC is observed; R L = 50 W; 100 mV modulation at midscale. 6 Based on I FS = 32 (CONTROL AMP IN/R SET) when using internal control amplifier. DAC load is virtual ground. 7 Measured as voltage settling at midscale transition to 0.5 LSB, RL = 50 W. 8 Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal. 9 Peak glitch impulse is measured as the largest area under a single positive or negative transient. 10 Measured with RL = 50 W and DAC operating in latched mode. 11 Data must remain stable for specified time prior to rising edge of CLOCK. 12 Data must remain stable for specified time after rising edge of CLOCK. 13 SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst-case spurious frequencies in the output spectrum window. The frequency span is dc-to-Nyquist unless otherwise noted. 14 Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products created will manifest themselves at (2F 2-F1) and (2F1-F2) of the two tones. 15 Supply voltages should remain stable within 5% for nominal operation. Specifications subject to change without notice. pw MIN pw MAX CLOCK tS tH CODE 1 DATA DATA CODE 2 DATA CODE 3 DATA CODE 4 DATA CODE 2 CODE 4 ANALOG OUTPUT CODE 1 CODE 3 DETAIL OF SETTLING TIME GLITCH AREA = 1/2 HEIGHT WIDTH CLOCK SPECIFIED ERROR BAND t PD H ANALOG OUTPUT W t ST Figure 1. Timing Diagrams REV. B -3- AD9731 EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS* Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS to +VS +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 V to +VS -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Control Amplifier Input Voltage Range . . . . . . . . 0 V to -4 V Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to -VS Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Internal Reference Output Current . . . . . . . . . . . . . . . 500 mA Lead Temperature (10 sec Soldering) . . . . . . . . . . . . . 300C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +165C Control Amplifier Output Current . . . . . . . . . . . . . 2.5 mA Test Level Definition I II 100% production tested The parameter is 100% production tested at 25C; sampled at temperature production. Sample tested only Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range devices. III IV V VI *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Options AD9731BR AD9731BR-REEL AD9731BRS AD9731BRS-REEL AD9731-PCB -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to 70C 28-Lead Wide Body (SOIC) 28-Lead Wide Body (SOIC) 28-Lead Shrink Small (SSOP) 28-Lead Shrink Small (SSOP) PCB R-28 R-28 RS-28 RS-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9731 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. B AD9731 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2-9 10 11 12, 13 14 15, 18, 28 16 17 D9(MSB) D8-D1 D0(LSB) CLOCK NC DIGITAL +VS GND DIGITAL -VS RSET 19 ANALOG RETURN 20 IOUT 21 IOUTB 22 23 ANALOG -VS REF IN 24 CONTROL AMP OUT 25 REF OUT 26 27 CONTROL AMP IN DIGITAL -VS Most significant data bit of digital input word Eight bits of 10-bit digital input word Least significant data bit of digital input word TTL-compatible edge-triggered latch enable signal for on-board registers No internal connection to this pin 5 V supply voltage for digital circuitry Converter ground -5.2 V supply voltage for digital circuitry Connection for external reference set resistor; nominal 1.96 kW. Full-scale output current = 32 (control amp in V/RSET). Analog return. This point and the reference side of the DAC load resistors should be connected to the same potential (nominally ground). Analog current output; full-scale current occurs with a digital word input of all "1s." With external load resistor, output voltage = IOUT (RLOADRINTERNAL). RINTERNAL is nominally 240 W. Complementary analog current output; full-scale current occurs with a digital word input of all "0s." Negative analog supply, nominally -5.2 V Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current source network. Voltage changes (noise) at this point have a direct effect on the full-scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/RSET) when using the internal amplifier. DAC load is virtual ground. Normally connected to REF IN (Pin 23). Output of internal control amplifier that provides a reference for the current switch network. Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference, nominally -1.25 V. Normally connected to REF Out (Pin 25) if not connected to external reference. Negative digital supply, nominally -5.2 V. PIN CONFIGURATION D9(MSB) 1 28 GND D8 2 27 DIGITAL -VS D7 3 26 CONTROL AMP IN D6 4 25 REF OUT D5 5 24 CONTROL AMP OUT 23 REF IN D4 6 AD9731 D3 7 TOP VIEW 22 ANALOG -VS D2 8 (Not to Scale) 21 IOUTB D1 9 20 IOUT D0(LSB) 10 19 ANALOG RETURN CLOCK 11 18 GND NC 12 17 RSET NC 13 16 DIGITAL -VS DIGITAL +VS 14 15 GND NC = NO CONNECT REV. B -5- AD9731-Typical Performance Characteristics 75 80 70 75 0dBFS 65 -6dBFS SFDR - dB SFDR - dB 70 65 60 55 -12dBFS 60 50 55 45 50 10 20 30 40 50 60 70 40 80 0 10 20 30 40 50 fOUT - MHz fOUT - MHz TPC 1. Narrowband SFDR (Clock = 170 MHz) vs. fOUT Frequency TPC 4. Wideband SFDR, fCLK = 125 MSPS 70 85 65 75 60 SFDR - dB SFDR - dB 0dBFS 80 70 65 -6dBFS 55 50 60 -12dBFS 45 55 40 50 10 20 30 40 50 60 0 10 20 30 40 50 60 70 80 fOUT - MHz fOUT - MHz TPC 2. Narrowband SFDR (Clock = 125 MHz) vs. fOUT Frequency TPC 5. Wideband SFDR, fCLK = 170 MSPS 60 75 fOUT = 1MHz 0dBFS 70 55 65 fOUT = 10MHz SINAD - dB SFDR - dB -6dBFS 60 55 50 fOUT = 20MHz 45 -12dBFS 50 40 fOUT = 40MHz 45 40 35 0 5 10 15 20 0 50 100 150 200 fCLK - MHz fOUT - MHz TPC 3. Wideband SFDR, fCLK = 50 MSPS TPC 6. SINAD, AOUT = 0 dBFS -6- REV. B AD9731 60 -10 -20 SFDR - dB 55 ENCODE = 125MHz fOUT = 2MHz SPAN = 62.5MHz -30 -40 -50 50 -60 -70 45 -80 -90 40 -100 20 18 16 14 10 12 IOUT - mA 8 6 4 2 0Hz START TPC 7. SFDR vs. IOUT (Clock =125 MHz/fOUT = 40 MHz) 6.25MHz/DIV 62.5MHz STOP TPC 10. Wideband SFDR 2 MHz fOUT; 125 MHz Clock 0.4 -10 0.3 -20 0.2 -30 -40 0.1 LSB ENCODE = 125MHz fOUT = 10MHz SPAN = 62.5MHz -50 0 -60 -0.1 -70 -0.2 -80 -90 -0.3 -100 -0.4 0Hz START 6.25MHz/DIV 62.5MHz STOP TPC 11. Wideband SFDR 10 MHz fOUT; 125 MHz Clock TPC 8. Typical Differential Nonlinearity Performance (DNL) 0.6 -10 -20 0.4 ENCODE = 125MHz fOUT = 20MHz SPAN = 62.5MHz -30 0.2 LSB -40 -50 0 -60 -70 -0.2 -80 -0.4 -90 -100 -0.6 0Hz START 62.5MHz STOP TPC 12. Wideband SFDR 20 MHz fOUT; 125 MHz Clock TPC 9. Typical Integral Nonlinearity Performance (INL) REV. B 6.25MHz/DIV -7- AD9731 -10 -10 ENCODE = 125MHz fOUT = 40MHz SPAN = 62.5MHz -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 ENCODE = 125MHz AOUT1 = 800kHz AOUT2 = 900kHz SPAN = 2MHz -100 -100 0Hz START 6.25MHz/DIV 0Hz START 62.5MHz STOP 200kHz/DIV 2MHz STOP TPC 16. Wideband Intermodulation Distortion F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz TPC 13. Wideband SFDR 40 MHz fOUT; 125 MHz Clock 0 -10 ENCODE = 170MHz fOUT = 65MHz SPAN = 85MHz -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 0Hz START 8.5MHz/DIV 0Hz START 85MHz STOP ENCODE = 125MHz AOUT1 = 800kHz AOUT2 = 900kHz SPAN = 62.5MHz 6.25MHz/DIV 62.5MHz STOP TPC 17. Wideband Intermodulation Distortion F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz TPC 14. Wideband SFDR 65 MHz fOUT; 170 MHz Clock -10 ENCODE = 170MHz fOUT = 70MHz SPAN = 85MHz -20 -30 -40 -50 -60 -70 -80 -90 -100 0Hz START 8.5MHz/DIV 85MHz STOP TPC 15. Wideband SFDR 70 MHz fOUT; 170 MHz Clock -8- REV. B AD9731 THEORY AND APPLICATIONS References The AD9731 high speed digital-to-analog converter utilizes most significant bit decoding and segmentation techniques to reduce glitch impulse and deliver high dynamic performance on lower power consumption than previous bipolar DAC technologies. The internal band gap reference, control amplifier, and reference input are pinned out to provide maximum user flexibility in configuring the reference circuitry for the AD9731. When using the internal reference, REF OUT (Pin 25) should be connected to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin 24) should be connected to REF IN (Pin 23). A 0.1 mF ceramic capacitor connected from Pin 23 to Analog -VS (Pin 22) improves settling time by decoupling switching noise from the current sink baseline. A reference current cell provides feedback to the control amplifier by sinking current through RSET (Pin 17). The design is based on four main subsections: the decoder/ driver circuits, the edge-triggered data register, the switch network, and the control amplifier. An internal band gap reference is included to allow operation of the device with minimum external support components. Digital Inputs/Timing The AD9731 has TTL/high speed CMOS-compatible single-ended inputs for data inputs and clock. The switching threshold is 1.5 V. Full-scale current is determined by CONTROL AMP IN and RSET according to the following equation: IOUT (FS) = 32(CONTROL AMP IN/RSET) In the decoder/driver section, the three MSBs are decoded to seven "thermometer code" lines. An equalizing delay is included for the seven least significant bits and the clock signals. This delay minimizes data skew and data setup and hold times at the register inputs. The internal reference is nominally -1.25 V with a tolerance of 8% and typical drift over temperature of 100 ppm/C. If greater accuracy or temperature stability is required, an external reference can be used. The AD589 reference features 10 ppm/C drift over the 0C to 70C temperature range. The on-board register is rising edge triggered and should be used to synchronize data to the current switches by applying a pulse with proper data setup and hold times as shown in the timing diagram. Although the AD9731 is designed to provide isolation of the digital inputs to the analog output, some coupling of digital transitions is inevitable. Digital feedthrough can be minimized by forming a low pass filter at the digital input by using a resistor in series with the capacitance of each digital input. This common high speed DAC application technique has the effect of isolating digital input noise from the analog output. Two modes of multiplying operation are possible with the AD9731. Signals with bandwidths up to 2.5 MHz and input swings from -0.6 V to -1.2 V can be applied to the CONTROL AMP IN pin as shown in Figure 3. Because the control amplifier is internally compensated, the 0.1 mF capacitor discussed above can be reduced to maximize the multiplying bandwidth. However, it should be noted that output settling time, for changes in the digital word, will be degraded. Input Clock and Data Timing Relationship RSET SINAD in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9731 is rising edge triggered, and so exhibits SINAD sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9731 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 2 shows the relationship of SINAD to clock placement from the AD9731 and a competitive part, both sampling at 125 MSPS. The AD9731 has excellent performance as far as the narrowness of the "window" in which it is sensitive to SINAD. 60 RT CONTROL AMP OUT REFERENCE IN 0.1F AD9731 ANALOG -VS Figure 3. Low Frequency Multiplying Circuit SINAD - dB 40 COMPETITION 30 20 10 -3 -2 -1 0 1 2 3 TIME OF DATA PLACEMENT RELATIVE TO RISING EDGE OF CLOCK - ns 4 Figure 2. SINAD vs. Clock Placement; fCLK = 125 MSPS, fOUT = 20 MHz REV. B CONTROL AMP IN -0.6 TO -1.2V 2.5MHz TYPICAL 50 0 -4 AD9731 RSET -9- AD9731 The REFERENCE IN pin can also be driven directly for wider bandwidth multiplying operation. The analog signal for this mode of operation must have a signal swing in the range of -3.3 V to -4.25 V. This can be implemented by capacitively coupling into REFERENCE IN a signal with a dc bias of -3.3 V (IOUT 22.5 mA) to -4.25 V (IOUT 3 mA), as shown in Figure 4, or by dividing REFERENCE IN with a low impedance op amp whose signal swing is limited to the stated range. An operational amplifier can also be used to perform the I-to-V conversion of the DAC output. Figure 5 shows an example of a circuit that uses the AD9631, a high speed, current feedback amplifier. The resistor values in Figure 5 provide a 4.096 V swing, centered at ground, at the output of the AD9631 amplifier. 10k 1/2 AD708 NOTE: When using an external reference, the external reference voltage must be applied prior to applying -VS. 10k 1/2 AD708 IFS R1 200 R2 100 AD9731 REF CONTROL AMP IN OUT APPROX -3.8V IOUT IFS RL 25 RFF 25 RFB 400 AD9631 2048V VOUT AD9731 REFERENCE IN -VS IOUTB 25 -VS Figure 5. I-to-V Conversion Using a Current Feedback Amplifier Figure 4. Wideband Multiplying Circuit Analog Output The switch network provides complementary current outputs IOUT and IOUTB. The design of the AD9731 is based on statistical current source matching, which provides a 10-bit linearity without trim. Current is steered to either IOUT or IOUTB in proportion to the digital input word. The sum of the two currents is always equal to the full-scale output current minus 1 LSB. The current can be converted to a voltage by resistive loading as shown in the block diagram. Both IOUT and IOUTB should be equally loaded for best overall performance. The voltage that is developed is the product of the output current and the value of the load resistor. EVALUATION BOARD The performance characteristics of the AD9731 make it ideally suited for direct digital synthesis (DDS) and other waveform synthesis applications. The AD9731 evaluation board provides a platform for analyzing performance under optimum layout conditions. The AD9731 also provides a reference for high speed circuit board layout techniques. -10- REV. B REV. B 29 28 27 26 25 24 23 22 20 18 16 14 12 -11- Figure 6. PCB Evaluation Board Schematic 37 36 35 34 33 32 31 30 2 IEN 1 II PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 15 GND4 13 GND5 11 GND6 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 10 9 8 7 6 5 4 3 21 GND1 19 GND2 17 GND3 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 +5V1 +5V2 +12V -12V -5V C37DRPF CON1 DGND DGND E3 E1 E7 DGND E9 E5 R11 4.9k +V DIG BNC1 E4 E2 E6 R12 50 Y1 DG2020 DATA GENERATOR E8 TO E10 EXT. CLK TO E7 J1 BNC E6 TO E8 E6 TO E8 CON 1 PIN 10 E5 TO E7 EXT. GND TO E9 +V DIG OPTIONAL RP2 4.9k REMOVE R12 REMOVE Y1 -V DIG DGND +V DIG U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 DGND C7 10F 14 U21 1 U20 2 U19 3 U18 4 U17 5 U16 6 U15 7 U14 8 U13 9 U12 10 11 12 13 +V DIG -V DIG R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 C8 0.1F NC1 NC2 +5 DIG +V DIG GND3 DIGITAL -VS DGND GND 2 OUT PWR 4 C9 0.1F -VA DIGITAL -VS GND ANA RETURN GND1 RSET 3 DGND C6 0.1F +VD R14 1960 BNC1J2 R16 50 DGND C3 10F AGND R15 25 -V ANA C2 10F AGND AGND -V DIG AGND C1 0.1F -V DIG DGND AGND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 BNC DGND C5 0.1F CONTROL AMP IN REF OUT CONTROL AMP OUT REF IN ANALOG -VS IOUT IOUT U1 AD9731 Y1 OSCILLATOR OPTIONAL D5 D6 D7 D8 D9 D10 DAC CLOCK D2 D3 D4 D1 -V GND +V PWR3 NOTE: R1-R10 = 50 +V DIG COMPUTER PROVIDES CLOCK NOTES CLOCK SWITCH MATRIX DGND 10 9 20 8 19 7 18 6 17 5 16 4 15 3 14 2 13 1 12 11 SOURCE P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 JUMPER DGND R13 50 E10 E8 BNC J1 DGND -VD +VD OPTIONAL RP1 4.9k C4 0.1F AD9731 AD9731 OUTLINE DIMENSIONS 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) C00609-0-5/03(B) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 14 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 45 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 0 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) PLANE BSC 0.33 (0.0130) 0.23 (0.0091) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 1.85 1.75 1.65 2.00 MAX 0.10 COPLANARITY 0.25 0.09 0.05 MIN 0.38 0.22 0.65 BSC SEATING PLANE 8 4 0 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH Revision History Location Page 5/03-Data Sheet changed from REV. A to REV. B. Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated TPCs 1, 2, 7, 10-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added TPCs 3, 4, 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added Input Clock and Data Timing Relationship section and Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Updated Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -12- REV. B