General Description
The MAX17075 includes a high-voltage boost regulator,
one high-current operational amplifier, two regulated
charge pumps, and one MLG block for gate-driver
supply modulation.
The step-up DC-DC converter is a 1.2MHz current-
mode boost regulator with a built-in power MOSFET. It
provides fast load-transient response to pulsed loads
while producing efficiencies over 85%. The built-in
160mΩ(typ) power MOSFET allows output voltages as
high as 18V boosted from inputs ranging from 2.5V to
5.5V. A built-in 7-bit digital soft-start function controls
startup inrush currents.
The gate-on and gate-off charge pumps provide regu-
lated TFT gate-on and gate-off supplies. Both output
voltages can be adjusted with external resistive
voltage-dividers.
The operational amplifier, typically used to drive the
LCD backplane (VCOM), features high-output short-cir-
cuit current (±500mA), fast slew-rate (45V/µs), wide
bandwidth (20MHz), and rail-to-rail outputs.
The MAX17075 is available in a 24-pin thin QFN pack-
age with 0.5mm lead spacing. The package is a square
(4mm x 4mm) with a maximum thickness of 0.8mm for
ultra-thin LCD design. It operates over the -40°C to
+85°C temperature range.
Applications
Notebook Computer Displays
LCD Monitor Panels
LCD TVs
Features
o2.5V to 5.5V Input Operating Range
oCurrent Mode Step-Up Regulator
Fast-Transient Response
Built-In 20V, 3A, 0.16Ωn-Channel Power MOSFET
Cycle-by-Cycle Current Limit
87% Efficiency (5V Input to 13V Output)
1.2MHz Switching Frequency
±1% Output Voltage Regulation Accuracy
oHigh-Current 18V VCOM Buffer
±500mA Output Short-Circuit Current
45V/µs Slew Rate
20MHz -3dB Bandwidth
Rail-to-Rail Output
oRegulated Charge Pump for TFT Gate-On Supply
oRegulated Charge Pump for TFT Gate-Off Supply
oLogic-Controlled High-Voltage Switches with
Adjustable Delay
oSoft-Start and Timed Delay Fault Latch for All
Outputs
oOverload and Thermal Protection
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
MAX17075
AGND
VCC
BGND
DRVN
REF
FBN
POS
NEG
OUT
LX
PGND
RSTIN
FB
COMP
DRN
RST
COM
SRC
DRVP
FBP
SUP CTL EP DEL
R1
10Ω
C5
1µF
VAVDD
TO VCOM
BGND
VIN
2.5V TO 5.5V
VGON
VGOFF
FROM
SYSTEM
3.3V
VIN
VMAIN
FROM
TCON
Simplified Operating Circuit
19-4353; Rev 1; 5/12
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX17075ETG+ -40°C to +85°C 24 TQFN-EP*
*
EP = Exposed paddle.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VVCC = +5V, Circuit of Figure 1, VAVDD = VSUP = +13V, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, CTL, RSTIN, RST to AGND ..........................-0.3V to +7.5V
DEL, REF, COMP, FB, FBN,
FBP to AGND .......................................-0.3V to (VVCC + 0.3V)
PGND, BGND to AGND.........................................-0.3V to +0.3V
LX to PGND ............................................................-0.3V to +20V
SUP to PGND .........................................................-0.3V to +20V
DRVN, DRVP to PGND..............................-0.3V to (VSUP + 0.3V)
SRC, COM, DRN to AGND .....................................-0.3V to +40V
DRN to COM............................................................-30V to +30V
SRC to SUP ............................................................................23V
REF Short Circuit to AGND.........................................Continuous
POS, NEG, OUT to AGND...........................-0.3V to (VSUP + 0.3)
DRVN, DRVP RMS Current ...............................................200mA
LX, PGND RMS Current Rating.............................................2.4A
Continuous Power Dissipation (TA= +70°C)
24-Pin TQFN (derate 27.8mW/°C above +70°C).......2222mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Supply Range 2.5 5.5 V
VCC Undervoltage-Lockout (UVLO) Threshold VCC rising, hysteresis (typ) = 50mV 2.05 2.25 2.45 V
VCC Shutdown Current VCC = 2V 100 200 µA
VFB = 1.3V, not switching 1 1.5
VCC Quiescent Current VFB = 1.0V, switching 4 5 mA
REFERENCE
REF Output Voltage No external load 1.238 1.250 1.262 V
REF Load Regulation 0n < ILOAD < 50µA 6 mV
REF Sink Current In regulation 10 µA
REF Undervoltage-Lockout Threshold Rising edge, hysteresis (typ) = 200mV 1 1.17 V
OSCILLATOR AND TIMING
Frequency 1000 1200 1400 kHz
Oscillator Maximum Duty Cycle 87 90 93 %
Duration to Trigger Fault Condition FB or FBP or FBN below threshold 47 55 65 ms
DEL Capacitor Charge Current During startup, VDEL = 1.0V 4 5 6 µA
DEL Turn-On Threshold 1.19 1.25 1.31 V
DEL Discharge Switch On-Resistance 20
STEP-UP REGULATOR
Output Voltage Range VVCC 18 V
FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.238 1.250 1.262 V
FB Fault Trip Level Falling edge 0.96 1 1.04 V
FB Load Regulation 0 < ILOAD < full, transient only -1 %
FB Line Regulation VCC = 2.5V to 5.5V -0.2 0 +0.2 %/V
FB Input Bias Current VFB = 1.25V 50 125 200 nA
FB Transconductance I = ±2.5µA at COMP, FB = COMP 75 160 280 µS
FB Voltage Gain FB to COMP 2600 V/V
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
LX Current Limit VFB = 1.1V, duty cycle = 75% 2.5 3.0 3.5 A
LX On-Resistance ILX = 200mA 0.16 0.25
LX Leakage Current VLX = 19V, TA = +25°C 10 20 µA
Current-Sense Transresistance 0.1 0.2 0.3 V/A
Soft-Start Period 7-bit current ramp 14 ms
POSITIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 6 18 V
VSUP Overvoltage Threshold VSUP = rising, hysteresis = 200mV 19 20 21 V
Operating Frequency 0.5 x
fOSC Hz
FBP Regulation Voltage -1.5% 1.250 +1.5% V
FBP Line Regulation Error VSUP = 12V to 18V, VGON = 30V 0.2 %/V
FBP Input Bias Current VFBP = 1.5V, TA = +25°C -50 +50 nA
DRVP Current Limit Not in dropout 400 mA
DRVP PCH On-Resistance 4 6
DRVP NCH On-Resistance 1.5 3
FBP Fault Trip Level Falling edge 0.96 1 1.04 V
Positive Charge-Pump Soft-Start Period 7-bit voltage ramp with filtering to prevent
high peak currents 3 5 ms
NEGATIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 6 18 V
Operating Frequency 0.5 x
fOSC Hz
FBN Regulation Voltage (VREF - VFBN) VREF - VFBN = 1V -1.5% 1 +1.5% V
FBN Input Bias Current VFBN = 0V, TA = +25°C -50 +50 nA
FBN Line Regulation Error VSUP = 9V to 18V, VGOFF = -7V 0.2 %/V
DRVN PCH On-Resistance 4 6
DRVN NCH On-Resistance 1.5 3
DRVN Current Limit Not in dropout 400 mA
FBN Fault Trip level Rising edge 450 mV
Negative Charge-Pump Soft-Start Period 7-bit voltage ramp with filtering to prevent
high peak currents 3 5 ms
POSITIVE GATE DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 2 V
CTL Input Current VCTL = 0V or VVCC, TA = +25°C -1 +1 µA
CTL-to-COM Rising Propagation Delay CLOAD = 100pF 250 ns
SRC Input Voltage Range 36 V
SRC-to-COM Switch On-Resistance VDEL = 1.5V, CTL = VCC 5 10
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = +5V, Circuit of Figure 1, VAVDD = VSUP = +13V, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = +5V, Circuit of Figure 1, VAVDD = VSUP = +13V, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
DRN-to-COM Switch On-Resistance VDEL = 1.5V, CTL = AGND 30 60
COM-to-GND Pulldown VDEL = 0V 1.5 2.5 k
VDEL = 1.5V, CTL = VCC 300 600
SRC Input Current VDEL = 1.5V, CTL = AGND 200 360 µA
OPERATIONAL AMPLIFIERS
SUP Supply Range 6 18 V
VSUP Undervoltage Threshold 3.8 4 4.2 V
SUP Supply Current Buffer configuration, VPOS = VSUP/2, no load 4 6.5 mA
Input Offset Voltage VNEG, VPOS = VSUP/2, TA = +25°C 12 mV
Input Bias Current VNEG, VPOS = VSUP/2, TA = +25°C -1 +1 µA
Input Common-Mode Voltage Range 0 VSUP V
Input Common-Mode Rejection Ratio 80 dB
Output-Voltage-Swing High IOUT = 50mA VSUP -
350 mV
Output-Voltage-Swing Low IOUT = -50mA 350 mV
Large-Signal Voltage Gain VOUT = 1V to (VSUP - 1)V 80 dB
Slew Rate 45 V/µs
-3dB Bandwidth 20 MHz
Sourcing 500
Short-Circuit Current Sinking 500
mA
XAO CONTROL
Falling edge at VCC = 5V 1.225 1.250 1.275
RSTIN Threshold Falling edge at VCC = 1.8V 1.213 1.250 1.287 V
RSTIN Input Current TA = +25°C -1 +1 µA
RSTIN Hysteresis 50 mV
RST Output Voltage ISINK = 1mA 0.4 V
RST Blanking Time Counting from VVCC crossing 2.25V 160 220 280 ms
XAO UVLO VVCC rising with hysteresis of 50mV 1.5 1.7 V
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(VCC = +5V, Circuit of Figure 1, VAVDD = VSUP = +13V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Supply Range 2.5 5.5 V
VCC Undervoltage-Lockout Threshold VCC rising, hysteresis (typ) = 50mV 2.05 2.45 V
VCC Shutdown Current 200 µA
VFB = 1.3V, not switching 1.5
VCC Quiescent Current VFB = 1.0V, switching 5 mA
REFERENCE
REF Output Voltage No external load 1.230 1.267 V
REF Load Regulation 0 < ILOAD < 50µA 6 mV
REF Sink Current In regulation 10 µA
REF Undervoltage-Lockout Threshold Rising edge, hysteresis (typ) = 200mV 1.15 V
OSCILLATOR AND TIMING
Frequency 1000 1400 kHz
Oscillator Maximum Duty Cycle 86 94 %
Duration to Trigger Fault Condition FB or FBP or FBN below threshold 47 65 ms
DEL Capacitor Charge Current During startup, VDEL = 1.0V 4 6 µA
DEL Turn-On Threshold 1.19 1.31 V
STEP-UP REGULATOR
Output Voltage Range VIN 18 V
FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.230 1.267 V
FB Fault Trip Level Falling edge 0.96 1.04 V
FB Line Regulation VCC = 2.5V to 5.5V -0.25 +0.25 %/V
FB Input Bias Current VFB = 1.25V 50 200 nA
FB Transconductance I = ±2.5µA at COMP, FB = COMP 75 280 µS
LX Current Limit VFB = 1.1V, duty cycle = 75% 2.5 3.5 A
LX On-Resistance ILX = 200mA 0.25
Current-Sense Transresistance 0.10 0.30 V/A
POSITIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 6 18 V
VSUP Overvoltage Threshold VSUP = rising, hysteresis = 200mV 19 21 V
FBP Regulation Voltage -2% 1.25 +2% V
FBP Line Regulation Error VSUP = 8V to 18V, VGON = 30V 0.2 %/V
FBP Input Bias Current VFBP = 1.5V, TA = +25°C -50 +50 nA
DRVP PCH On-Resistance 6
DRVP NCH On-Resistance 3
FBP Fault Trip Level Falling edge 0.96 1.04 V
Positive Charge-Pump Soft-Start Period 7-bit voltage ramp with filtering to prevent
high peak currents 5 ms
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, VAVDD = VSUP = +13V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
NEGATIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 6 18 V
FBN Regulation Voltage (VREF - VFBN) VREF - VFBN = 1V -2% 1 +2% V
FBN Input Bias Current VFBN = 0V, TA = +25°C -50 +50 nA
FBN Line Regulation Error VSUP = 9V to 18V, VGOFF = -7V 0.2 %/V
DRVN PCH On-Resistance 6
DRVN NCH On-Resistance 3
Negative Charge-Pump Soft-Start Period 7-bit voltage ramp with filtering to prevent
high peak currents 5 ms
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 2 V
CTL Input Current VCTL = 0V or VVCC, TA = +25°C -1 +1 µA
SRC Input Voltage Range 36 V
SRC-to-COM Switch On-Resistance VDEL = 1.5V, CTL = VCC 10
DRN-to-COM Switch On-Resistance VDEL = 1.5V, CTL = AGND 60
COM-to-GND Pulldown VDEL = 0V 1.5 2.5 k
VDEL = 1.5V, CTL = VCC 600 µA
SRC Input Current VDEL = 1.5V, CTL = AGND 360 µA
OPERATIONAL AMPLIFIERS
SUP Supply Range 6 18 V
VSUP Undervoltage Threshold 3.8 4 4.2 V
SUP Supply Current Buffer configuration, VPOS = VSUP/2, no load 6.5 mA
Input Offset Voltage VNEG, VPOS = VSUP/2, TA = +25°C 8 mV
Input Bias Current VNEG, VPOS = VSUP/2, TA = +25°C -1 +1 µA
Input Common-Mode Voltage Range 0 VSUP V
Output-Voltage-Swing High IOUT = 50mA VSUP -
350 mV
Output-Voltage-Swing Low IOUT = -50mA 350 mV
Sourcing 500
Short-Circuit Current Sinking 500
mA
XAO CONTROL
RSTIN Threshold Falling edge 1.22 1.28 V
RSTIN Input Current TA = +25°C -1 +1 µA
RST Output Voltage ISINK = 1mA 0.4 V
RST Blanking Time Counting from VVCC crossing 2.25V 160 280 ms
XAO UVLO VCC rising with typical hysteresis of 50mV 1.7 V
Note 1: -40°C specifcations are guaranteed by design, not production tested.
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
_______________________________________________________________________________________
7
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17075 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010
10
20
30
40
50
60
70
80
90
100
0
1 1000
VIN = 5V
VIN = 3.3V
VIN = 2.5V
STEP-UP REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17075 toc02
LOAD CURRENT (mA)
OUTPUT ERROR (%)
700 800 900100 200 300 400 500 600
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-1.0
0 1000
STEP-UP REGULATOR LINE REGULATION
UNDER DIFFERENT LOADS
MAX17075 toc03
INPUT VOLTAGE (V)
OUTPUT ERROR (%)
4.53.0 3.5 4.0
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-0.20
2.5 5.0
300mA LOAD
100mA LOAD
200mA LOAD
NO
LOAD
STEP-UP REGULATOR SWITCHING
FREQUENCY vs. INPUT VOLTAGE
MAX17075 toc04
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
4.53.0 3.5 4.0
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.16
2.5 5.0
150mA LOAD
STEP-UP REGULATOR STARTUP
WITH HEAVY LOAD (600mA)
MAX17075 toc05
2ms/div
0V
VIN
5V/div
VAVDD
5V/div
LX
10V/div
IL
1A/div
0V
0A
0V
STEP-UP REGULATOR LOAD-TRANSIENT
RESPONSE (100mA TO 800mA)
MAX17075 toc06
40µs/div
RCOMP = 82kΩ
CCOMP1 = 220pF
CCOMP2 = 18pF
0V VAVDD
(AC-COUPLED)
500mV/div
LOAD CURRENT
500mA/div
IL
2A/div
0A
0A
MAX17075 toc07
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE (80mA TO 2.08mA)
10µs/div
RCOMP = 82kΩ
CCOMP1 = 220pF
CCOMP2 = 18pF
0V
VAVDD
(AC-COUPLED)
500mV/div
LOAD CURRENT
1A/div
IL
2A/div
0A
0A
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
8 _______________________________________________________________________________________
IN SUPPLY QUIESCENT CURRENT
vs. IN SUPPLY VOLTAGE
MAX17075 toc08
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
4.53.0 3.5 4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2.5 5.0
200mA LOAD
NO SWITCHING
MAX17075 toc09
POWER-UP SEQUENCE OF
ALL SUPPLY OUTPUTS
4ms/div
VIN : 5V/div
REF : 1V/div
AVDD : 10V/div
VCOM : 5V/div
SRC : 20V/div
GOFF : 5V/div
GON : 20V/div
DEL : 2V/div
0V
0V
0V
0V
0V
0V
VIN
AVDD
VCOM
SRC
REF
DEL
GOFF
GON
POSITIVE CHARGE-PUMP REGULATOR
LINE REGULATION
MAX17075 toc10
SUPPLY VOLTAGE (V)
OUTPUT ERROR (%)
15 16 1712 13 14
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
-0.30
11 18
POSITIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
MAX17075 toc11
LOAD CURRENT (mA)
OUTPUT ERROR (%)
40 50 706010 20 30
-1.6
-1.2
-0.8
-0.4
0
0.4
-2.0
080
VSRC
GON
MAX17075 toc12
POSITIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE (10mA TO 100mA)
4
µ
s/div
0V
0A
GON
(AC-COUPLED)
200mV/div
LOAD CURRENT
50mA/div
NEGATIVE CHARGE-PUMP REGULATOR
LINE REGULATION
MAX17075 toc13
SUPPLY VOLTAGE (V)
OUTPUT ERROR (%)
14.511.5 12.5 13.5
0
0.2
-0.2
10.5 17.515.5 16.5
NEGATIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
MAX17075 toc14
LOAD CURRENT (mA)
OUTPUT ERROR (%)
6020 40
0
0.2
-0.2
0 12080 100
NEGATIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE (10mA TO 100mA)
MAX17075 toc15
4
µ
s/div
0V
GOFF
(AC-COUPLED)
100mV/div
LOAD CURRENT
50mA/div
0A
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
_______________________________________________________________________________________
9
OPERATION AMPLIFIER
FREQUENCY RESPONSE
MAX17075 toc16
FREQUENCY (kHz)
GAIN (dB)
1k 10k
-6
-5
-4
-3
-1
-2
0
1
2
-8
-7
100 100k
100pF LOAD
NO LOAD
OPERATIONAL AMPLIFIER RAIL-TO-RAIL
INPUT/OUPUT WAVEFORMS
MAX17075 toc17
2
µ
s/div
0V
VPOS
5V/div
VVCOM
5V/div
0V
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX17075 toc18
2
µ
s/div
0V
VVCOM
(AC-COUPLED)
200mV/div
IVCOM
50mV/div
0A
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
MAX17075 toc19
40
µ
s/div
0V
0V
VPOS
5V/div
VVCOM
5V/div
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX17075 toc20
40
µ
s/div
0mV
0mV
VPOS
(AC-COUPLED)
100mV/div
VVCOM
(AC-COUPLED)
100mV/div
SUP SUPPLY CURRENT
vs. SUP SUPPLY VOLTAGE
MAX17075 toc22
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
14 1681012
3.55
3.65
3.60
3.70
3.75
3.80
3.90
3.85
3.95
4.00
3.50
618
NO SWITCHING
HIGH-VOLTAGE SWITCH
CONTROL FUNCTION
MAX17075 toc21
10
µ
s/div
0V
0V
VGON
10V/div
VCTL
5V/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 POS Operational Amplifier Noninverting Input
2 NEG Operational Amplifier Inverting Input
3 OUT Operational Amplifier Output
4 BGND Analog Ground for Operational Amplifier and Charge Pump. Connect to AGND underneath the IC.
5 SUP
Operational Amplifier and Charge-Pump Supply Input. Connect this pin to the output of the boost
regulator (AVDD) and bypass to BGND with a minimum1µF capacitor.
6 DRVP Positive Charge-Pump Driver Output
7 DRVN Negative Charge-Pump Driver Output
8 CTL
High-Voltage Switch Control Input. When CTL is high, the switch between GON and SRC is on and the
switch between GON and DRN is off. When CTL is low, the switch between GON and DRN is on and the
switch between GON and SRC is off. CTL is inhibited by VCC UVLO and when DEL is less than 1.25V.
9 RST Reset Output. RST is an open-drain output.
10 FBP
Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-
divider between the positive charge-pump regulator output and AGND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
11 FBN
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-
divider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
12 REF
Reference Output. Connect a 0.22µF capacitor from REF to AGND. All power outputs are disabled until
REF exceeds its UVLO threshold.
13 VCC
Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage
and bypass VCC to AGND with a minimum 1µF ceramic capacitor.
14 AGND
Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power ground (PGND)
underneath the IC.
15 RSTIN Reset Input. Connect to the center of a resistor-divider from VIN.
16 COMP Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND.
17 FB
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the
step-up regulator output and AGND to set the regulator’s output voltage. Place the resistive voltage-
divider within 5mm of FB.
18, 19 PGND Power Ground
20 LX
Step-Up Regulator Switching Node. Connect inductor and catch diode here and minimize trace area for
lowest EMI power ground.
21 DRN Switch Input. Drain of the internal high-voltage back-to-back p-channel FET connects to COM.
22 COM Internal High-Voltage MOSFET Switch Common Terminal
23 SRC
Switch Input. Source of the internal high-voltage pFET. Bypass SRC to PGND with a minimum 0.1µF
capacitor close to the pin.
24 DEL High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set delay.
— EP Exposed Pad. Connect to AGND.
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 11
MAX17075
AGND
VCC
BGND
DRVN
REF
FBN
POS
NEG
OUT
LX
PGND
RSTIN
FB
COMP
DRN
RST
COM
SRC
DRVP
FBP
SUP CTL DEL
C11
0.1µF
R14
1kΩ
R10
100kΩ
R6
13.7kΩ
R7
100kΩ
R3
100kΩ
R1
10Ω
R12
20kΩ
R15
464kΩ
R11
R13
10kΩ
R8
187kΩ
R9
20kΩ
C12
220pF
C10
1µF
C9
0.22µF
C5
1µF
C13
0.01µF
R16
20kΩ
VAVDD
TO VCOM
D4
VIN
2.5V TO 5.5V
(4.5 TO 5.5V FOR FULL LOAD)
VAVDD
13V/500mA
VGON
30V/20mA
VGOFF
-7V/20mA
C15
0.1µF
D2
C17
0.1µF
D3
C1
10µF
6.3V
C2
10µF
6.3V
C14
1µF
C6
1µF
C16
1µF
C3
10µF
25V
C4
10µF
25V
L1
3.0µHD1
FROM SYSTEM
3.3V
VIN
VAVDD
VAVDD
VAVDD
FROM TCON
C8
0.033µF
EP
Figure 1. Typical Operating Circuit
Typical Operating Circuit
The typical operating circuit (Figure 1) of the
MAX17075 is a complete power-supply system for TFT
LCD panels in monitors and TVs. The circuit generates
a +13V source driver supply, a +30V positive gate-dri-
ver supply, and a -7V negative gate-driver supply from
a +2.5V to +5.5V input supply. Table 1 lists some
selected components, and Table 2 lists the contact
information for component suppliers.
Detailed Description
The MAX17075 contains a step-up switching regulator
to generate the source driver supply, and two charge-
pump regulators to generate the gate-driver supplies.
Each regulator features adjustable output voltage, digi-
tal soft-start, and timer-delayed fault protection. The
step-up regulator uses fixed-frequency current-mode
control architecture. The MAX17075 also includes one
high-performance operational amplifier designed to
drive the LCD backplane (VCOM). The amplifier fea-
tures high output current, fast slew rate (45V/µs), wide
bandwidth (20MHz), and rail-to-rail outputs. In addition,
the MAX17075 features a high-voltage switch-control
block, a 1.25V reference output, well-defined power-up
and power-down sequences, and thermal-overload
protection. Figure 2 shows the MAX17075 functional
block diagram.
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
12 ______________________________________________________________________________________
MAX17075
POS
LX
PGND
FB
OUT
BGND
FBN
DRVN
COM
REF
VGON
VVCC
DRN
VCC
AGND
SRC
SUP
NEG
SWITCH
CONTROL
SEQUENCE
BOOST
CONTROLLER
NEGATIVE
CHARGE
PUMP
POSITIVE
CHARGE
PUMP
REF
OSC RSTIN
COMP
VVCC
VGOFF
DEL
DRVP
FBP
SUP
CTL
RST
FROM TCON
VAVDD
VVCC
VAVDD
POUT
VAVDD
Figure 2. Functional Diagram
Main Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast-transient response to
pulsed loads that are typical for TFT LCD panel source
drivers. The 1.2MHz switching frequency allows the use
of low-profile inductors and ceramic capacitors to mini-
mize the thickness of LCD panel design. The integrated
high-efficiency MOSFET and the built-in digital soft-start
function reduce the number of external components
required while controlling inrush currents. The output
voltage can be set from VIN to 18V with an external
resistive voltage-divider. The regulator controls the out-
put voltage and the power delivered to the output by
modulating the duty cycle (D) of the internal power
MOSFET in each switching cycle. The duty cycle of the
MOSFET is approximated by:
where VAVDD is the output voltage of the step-up regulator.
Figure 3 shows the functional diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.25V and changes the COMP output. The voltage at
COMP sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
current necessary to service the load. To maintain sta-
bility at high duty cycles, a slope-compensation signal
is summed with the current-sense signal.
DVV
V
AVDD IN
AVDD
≈−
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 13
LOGIC
AND
DRIVER
SOFT-
START ILIMIT
CURRENT-LIMIT
COMPARATOR
PWM
COMPARATOR
ERROR AMP
LX
PGND
FB
CLOCK
SLOPE COMP
TO FAULT LOGIC
FAULT
COMPARATOR
1.0V
1.25V
COMP
CURRENT
SENSE
OSCILLATOR ∑
MAX17075
Figure 3. Step-Up Regulator Functional Diagram
DESIGNATION DESCRIPTION
C1, C2
10µF ±20%, 6.3V X5R ceramic capacitors
(0603)
Murata GRM188R60J106M
TDK C1608X5R0J106M
C3, C4, C7
10µF ±20%, 25V X5R ceramic capacitors
(1206)
Murata GRM31CR61E106M
TDK C3216X5R1E106M
C10, C14
1µF ±10%, 50V X7R ceramic capacitors
(1206)
Murata GRM31MR71H105KA
TDK C3216X7R1H105K
DESIGNATION DESCRIPTION
C11, C15, C16,
C17
0.1µF ±10%, 50V X7R ceramic capacitors
(0603)
Murata GRM188R71H104K
TDK C1608X7R1H104K
D1 3A, 30V Schottky diode (M-Flat)
Toshiba CMS02 (TE12L,Q) (Top mark S2)
D2, D3, D4 220mA, 100V dual diodes (SOT23)
Fairchild MMBD4148SE (Top mark D4)
L1 3.0µH, 3ADC inductor
Sumida CDRH6D28-3R0
Table 1. Component List
SUPPLIER PHONE FAX WEBSITE
Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida 847-545-6700 847-545-6720 www.sumida.com
TDK 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec
Table 2. Component Suppliers
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
14 ______________________________________________________________________________________
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceed the COMP voltage, the controller resets the
flip-flop and turns off the MOSFET. Since the inductor
current is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate-
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to GND with the
midpoint connected to FBP. The number of charge-
pump stages and the setting of the feedback divider
determine the output voltage of the positive charge-
pump regulator. The charge pump includes a high-side
p-channel MOSFET (P1) and a low-side n-channel
MOSFET (N1) to control the power transfer as shown in
Figure 4.
The error amplifier compares the feedback signal (FBP)
with a 1.25V internal reference. If the feedback signal is
below the reference, the charge-pump regulator turns
on P1 and turns off N1 when the rising edge of the
oscillator clock arrives, level shifting C15 and C17 by
VSUP volts. If the voltage across CPOUT plus a diode
drop (VPOUT + VDIODE) is smaller than the level-shifted
flying capacitor voltage (VC17 + VSUP), charge flows
from C17 to CPOUT until diode D3-1 turns off. Similarly,
if the voltage across C16 plus a diode drop (VC16 +
VDIODE) is smaller than the level-shifted flying capacitor
voltage (VC15 + VSUP), charge flows from C15 to C16
until diode D2-1 turns off. The falling edge of the oscil-
lator clock turns off P1 and turns on N1, allowing VSUP
to charge up the flying capacitor C15 through D2-2 and
C16 to charge C17 through diode D3-2. If the feedback
signal is above the reference when the rising edge of
the oscillator comes, the regulator ignores this clock
edge and keeps N1 on and P1 off.
The MAX17075 also monitors the FBP voltage for
undervoltage conditions. If the VFBP is continuously
below 80% of the nominal regulation voltage for
approximately 50ms, the MAX17075 sets a fault latch,
shutting down all outputs except REF. Once the fault
condition is removed, cycle the input voltage (below the
UVLO falling threshold) to clear the fault latch and reac-
tivate the device.
OSC
REF
1.25V
ERROR
AMPLIFIER
POSITIVE CHARGE-PUMP REGULATOR
MAX17075
P1
N1
SUP
INPUT
SUPPLY
POUT
C14
C16
C15
C6
D2-2
D2-1
C17 D3-2
D3-1
DRVP
FBP
Figure 4. Positive Charge-Pump Regulator Block Diagram
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 15
Negative Charge-Pump Regulator
The negative charge-pump regulator is typically used to
generate the negative supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to REF with the
midpoint connected to FBN. The number of charge-
pump stages and the setting of the feedback divider
determine the output of the negative charge-pump regu-
lator. The charge-pump controller includes a high-side p-
channel MOSFET (P2) and a low-side n-channel MOSFET
(N2) to control the power transfer as shown in Figure 5.
The error amplifier compares the feedback signal (FBN)
with a 250mV internal reference. If the feedback signal
is above the reference, the charge-pump regulator
turns on N2 and turns off P2 when the rising edge of the
oscillator clock arrives, level shifting C11. This connects
C11 in parallel with reservoir capacitor C10. If the volt-
age across C10 minus a diode drop (VC10 - VDIODE) is
higher than the level-shifted flying capacitor voltage
(-VC11), charge flows from C10 to C11 until diode D4-2
turns off. The falling edge of the oscillator clock turns
off N2 and turns on P2, allowing VSUP to charge up fly-
ing capacitor C11 through diode D4-1. If the feedback
signal is below the reference when the rising edge of
the oscillator comes, the regulator ignores this clock
edge and keeps P2 on and N2 off.
The MAX17075 also monitors the FBN voltage for
undervoltage conditions. If the VFBN is continuously
below 80% of the nominal regulation voltage (VREF -
VFBN) for approximately 50ms, the MAX17075 sets a
fault latch, shutting down all outputs except REF. Once
the fault condition is removed, cycle the input voltage
(below the UVLO falling threshold) to clear the fault
latch and reactivate the device.
Operational Amplifiers
The MAX17075 has one operational amplifier. The oper-
ational amplifier is typically used to drive the LCD back-
plane (VCOM) or the gamma-correction divider string. It
features ±500mA output short-circuit current, 45V/µs
slew rate, and 20MHz, 3dB bandwidth.
Figure 5. Negative Charge-Pump Regulator Block Diagram
OSC
REF
0.25V
ERROR
AMPLIFIER
NEGATIVE CHARGE-PUMP REGULATOR
MAX17075
P2
N2
SUP
INPUT
SUPPLY
GOFF
REF
C10
C11 D4-1
D4-2
DRVN
FBN
R7
R6
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
16 ______________________________________________________________________________________
Short-Circuit Current Limit and Input Clamp
The operational amplifier limits short-circuit current to
approximately ±500mA if the output is directly shorted
to SUP or to BGND. If the short-circuit condition per-
sists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-
shutdown threshold, an internal thermal sensor immedi-
ately sets the thermal fault latch, shutting off all the IC’s
outputs. The device remains inactive until the input volt-
age is cycled. The operational amplifier has 4V input
clamp structures in series with a 500Ωresistance and a
diode (Figure 6).
Driving Pure Capacitive Load
The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation. As the operational amplifier’s capaci-
tive load increases, the amplifier’s bandwidth decreas-
es and gain peaking increases. A 5Ωto 50Ωsmall
resistor placed between OUT and the capacitive load
reduces peaking, but also reduces the gain. An alterna-
tive method of reducing peaking is to place a series RC
network (snubber) in parallel with the capacitive load.
The RC network does not continuously load the output
or reduce the gain. Typical values of the resistor are
between 100Ωand 200Ω, and the typical value of the
capacitor is 10nF.
High-Voltage Switch Control
The MAX17075’s high-voltage switch control block
(Figure 7) consists of two high-voltage p-channel
MOSFETs: Q1, between SRC and COM; and Q2,
between COM and DRN. At power-up and only at
power up, before the switch control is enabled (a 1.5kΩ
pulldown is present on COM). At switch-off, COM is
high impedance.
The switch control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds UVLO, the soft-start routine of all the
regulators is complete, there is no fault condition
detected, and VDEL exceeds its turn-on threshold.
Once activated and if CTL is logic-high, Q1 turns on
and Q2 turns off, connecting COM to SRC. When CTL
is logic-low, Q1 turns off and Q2 turns on, connecting
COM to DRN.
Figure 6. Op Amp Input Clamp Structure
NEG
POS
±4V
500Ω
OP AMP INPUT CLAMP STRUCTURE
SUP
OUT
BGND
MAX17075
Figure 7. Switch Control
Q3
5µA
Q1
Q2
2.25V
VREF
SWITCH CONTROL
VCC
DEL
CTL
DRN
SRC
COM
FAULT
REF_OK
MAX17075
1.5kΩ
Q4
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 17
Reference Voltage (REF)
The reference voltage is nominally 1.25V, and can
source at least 50µA (see the
Typical Operating
Characteristics
). VCC is the input of the internal refer-
ence block. Bypass REF with a 0.22µF ceramic capaci-
tor connected between REF and AGND.
Power-Up Sequence and Soft-Start
Once the voltage on VCC exceeds the XAO UVLO
threshold of approximately 1.5V, the reference turns on.
With a 0.22µF REF bypass capacitor, the reference
reaches its regulation voltage of 1.25V in approximately
1ms. When the reference voltage exceeds 1V and VCC
exceeds its UVLO threshold of approximately 2.25V,
the IC enables the main step-up regulator, the gate-on
linear-regulator controller, and the gate-off linear-
regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. Each output uses a 7-bit
soft-start DAC. For the step-up and the gate-on linear
regulator, the DAC output is stepped in 128 steps from
zero up to the reference voltage. For the gate-off linear
regulator, the DAC output steps from the reference
down to 250mV in 128 steps. The soft-start duration is
10ms (typ) for step-up regulator and 3ms (typ) for gate-
on and gate-off regulators.
A capacitor (CDEL) from DEL to AGND determines the
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.25V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5mA current source starts
charging CDEL. Once the capacitor voltage exceeds
1.25V (typ), the switch-control block is enabled as
shown in Figure 8. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when VIN is
less than UVLO, DEL is internally connected to AGND
to discharge CDEL. Select CDEL to set the delay time
using the following equation:
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at VCC
with the UVLO threshold (2.25V rising, 2.20V falling, typ)
to ensure the input voltage is high enough for reliable
operation. The 50mV (typ) hysteresis prevents supply
transients from causing a restart. Once the input voltage
exceeds the UVLO rising threshold, startup begins.
When the input voltage falls below the UVLO falling
threshold, the controller turns off the main step-up regu-
lator and disables the switch-control block; the opera-
tional amplifier output is high impedance.
Fault Protection
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs exceed
their respective fault-detection thresholds, the
MAX17075 activates an internal fault timer. If any condi-
tion or combination of conditions indicates a continuous
fault for the fault-timer duration (50ms typ), the
MAX17075 sets the fault latch to shut down all the out-
puts except the reference. Once the fault condition is
removed, cycle the input voltage (below the UVLO
falling threshold) to clear the fault latch and reactivate
the device. The fault-detection circuit is disabled during
the soft-start time.
CDELAYTIME
µA
V
DEL =×_.
5
125
Figure 8. Power-Up Sequence
1.5V
1V
1.25V
INPUT
VOLTAGE
OK
SWITCH
CONTROL
ENABLED
14ms
3ms
SOFT-START
SOFT-START
SOFT-START BEGINS
2.25V VVCC
VREF
VAVDD
VCOM
VPOUT
VGOFF
VDEL
VGON
MAX17075
Thermal-Overload Protection
Thermal-overload protection prevents excessive power
dissipation from overheating the MAX17075. When the
junction temperature exceeds +160°C, a thermal sen-
sor immediately activates the fault protection, which
shuts down all outputs except the reference, allowing
the device to cool down. Once the device cools down
by approximately 15°C, cycle the input voltage (below
the UVLO falling threshold) to clear the fault latch and
reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of +150°C.
XAO Voltage Detector
Based upon the input at the RSTIN and VCC pins, the
XAO controller either pulls the reset pin RST low or sets
it to high impedance. RST is an open-drain output. Pull
it high to system 3.3V through a 10kΩresistor. Connect
RSTIN to VIN through resistor-dividers R11 and R12
(Figure 1) to set the proper XAO threshold.
Once VCC voltage exceeds approximately 2.25V, the
controller initiates a 220ms blanking period during
which the drop on VCC is ignored and RST is set to
high impedance. After this blanking period and if RSTIN
goes below approximately 1.25V, RST is pulled low
indicating low RSTIN input. RST stays low until VCC falls
below approximately 1V. Then RST cannot be held low
any more. The controller gives up and RST is pulled up
by the external resister. A 50mV hysteresis is imple-
mented for XAO threshold.
Design Procedure
Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple, and therefore reduce the peak current, which
decreases core losses in the inductor and conduction
losses in the entire power path. However, large inductor
values also require more energy storage and more turns
of wire, which increase size and can increase conduc-
tion losses in the inductor. Low inductance values
decrease the size, but increase the current ripple and
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant LIR, which
is the ratio of the inductor peak-to-peak ripple current to
the average DC inductor current at the full load current.
The best trade-off between inductor size and circuit
efficiency for step-up regulators generally has an LIR
between 0.3 and 0.6. However, depending on the AC
characteristics of the inductor core material and ratio of
inductor resistance to other power-path resistances, the
best LIR can shift up or down. If the inductor resistance
is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extreme-
ly thin high-resistance inductors are used, as is com-
mon for LCD-panel applications, the best LIR can
increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IMAIN(MAX)), and the expected efficiency (ηTYP) taken
from an appropriate curve in the
Typical Operating
Characteristics
section, and an estimate of LIR based
on the above discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage (VIN(MIN)) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from the appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
II
I
AVDD PEAK IN DC MAX AVDD RIPPLE
_(,)
_
=+
2
IVVV
L
AVDD RIPPLE
IN MIN AVDD IN MIN
AVDD
_
() ()
=×−
()
×××Vf
AVDD SW
IIV
V
IN DC MAX AVDD MAX AVDD
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
If
AVDD IN
AVDD
AVDD IN
AVDD MAX S
=⎛
⎝
⎜⎞
⎠
⎟−
×
2
()WW
TYP
LIR
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
η
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
18 ______________________________________________________________________________________
The inductor’s saturation current rating and the
MAX17075’s LX current limit should exceed IAVDD_PEAK,
and the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor with
less than 0.1Ωseries resistance.
Considering the typical operating circuit, the maximum
load current (IAVDD(MAX)) is 500mA with a 13V output
and a typical input voltage of 5V. Choosing an LIR of 0.5
and estimating efficiency of 85% at this operating point:
Using the circuit’s minimum input voltage (2.5V) and
estimating efficiency of 80% at that operating point:
The ripple current and the peak current are:
Output Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR):
and
where IPEAK is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output voltage ripple is typically dominated by
VAVDD_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be
considered.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. Two 10µF ceramic capacitors are used
in the typical operating circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, CIN can be reduced below the values used in
the typical operating circuit. Ensure a low-noise supply
at VCC by using adequate CIN. Alternately, greater volt-
age variation can be tolerated on CIN if VCC is decou-
pled from CIN using an RC lowpass filter (see R1 and
C5 in Figure 1).
Rectifier Diode
The MAX17075’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
Output Voltage Selection
The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider from
the output (VAVDD) to ground with the center tap con-
nected to FB (see Figure 1). Select R9 in the 10kΩto
50kΩrange. Calculate R8 with the following equation:
where VFB, the step-up regulator’s feedback set point,
is 1.25V. Place R8 and R9 close to the IC.
Loop Compensation
Choose RCOMP (R10 in Figure 1) to set the high-fre-
quency integrator gain for fast-transient response.
Choose CCOMP (C12 in Figure 1) to set the integrator
zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
CVC
IR
COMP AVDD AVDD
AVDD MAX COMP
≈×
×10 ()
RVV C
LI
COMP IN AVDD AVDD
AVDD AVDD MAX
≈×× ×
×
312 5.
()
RR V
V
AVDD
FB
89 1=× −
⎛
⎝
⎜⎞
⎠
⎟
VIR
AVDD RIPPLE ESR PEAK ESR AVDD_() _
≈
VI
C
VV
Vf
AVDD RIPPLE C AVDD
AVDD
AVDD IN
AVDD SW
_()
≈−
⎛⎛
⎝
⎜⎞
⎠
⎟,
VV V
AVDD RIPPLE AVDD RIPPLE C AVDD RIPPLE E__()_(
=+
SSR)
IA
AA
PEAK =+≈325 051
2351...
IVVV
µH V MHz
RIPPLE =×−
()
×× ≈
25 13 25
33 13 12 05
..
..
.11A
IAV
VA
IN DC MAX(, )
.
..
.=×
×≈
05 13
25 08 325
LV
V
VV
AMHz
AVDD =⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟
5
13
13 5
05 12
0
2
..
.885
05 335
..
⎛
⎝
⎜⎞
⎠
⎟≈µH
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 19
MAX17075
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient-response waveforms.
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement.
The number of positive charge-pump stages is given by:
where nPOS is the number of positive charge-pump
stages, VGON is the output of the positive charge-pump
regulator, VSUP is the supply voltage of the charge-
pump regulators, VDis the forward voltage drop of the
charge-pump diode, and VDROPOUT is the dropout
margin for the regulator. Use VDROPOUT = 600mV.
The number of negative charge-pump stages is given by:
where nNEG is the number of negative charge-pump
stages and VGOFF is the output of the negative charge-
pump regulator.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VAVDD and the first stage of the
negative charge pump is connected to ground.
Flying Capacitors
Increasing the flying capacitor CX(connected to DRVN
and DRVP) value lowers the effective source impedance
and increases the output current capability. Increasing
the capacitance indefinitely has a negligible effect on
output current capability because the internal switch
resistance and the diode impedance place a lower limit
on the source impedance. A 0.1µF ceramic capacitor
works well in most low-current applications. The flying
capacitor’s voltage rating must exceed the following:
where n is the stage number in which the flying capaci-
tor appears.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where COUT_CP is the output capacitor of the charge
pump, ILOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple, and fOSC is the switching frequency.
Output Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from the
REG P output to GND with the center tap connected to
FBP (Figure 1). Select the lower resistor of divider R16
in the 10kΩto 30kΩrange. Calculate the upper resistor
R15 with the following equation:
where VFBP = 1.25V (typical).
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R6 in the 35kΩto 68kΩrange.
Calculate R7 with the following equation:
where VFBN = 250mV, VREF = 1.25V. Note that REF can
only source up to 50µA, using a resistor less than 35kΩ
for R6 results in higher bias current than REF can supply.
Set the XAO Threshold Voltage
XAO threshold voltage can be adjusted by connecting
a resistive voltage-divider from input VIN to GND with
the center tap connected to RSTIN (see Figure 1).
Select R12 in the 10kΩto 50kΩrange. Calculate R11
with the following equation:
where VRSTIN, the RSTIN threshold set point, is 1.25V.
VINXAO is the desired XAO threshold voltage. Place
R11 and R12 close to the IC.
RR V
V
INXAO
RSTIN
11 12 1=× −
⎛
⎝
⎜⎞
⎠
⎟
RRVV
VV
FBN GOFF
REF FBN
76=× −
−
RR V
V
GON
FBP
15 16 1=× −
⎛
⎝
⎜⎞
⎠
⎟
CI
fV
OUT CP LOAD CP
OSC RIPPLE CP
__
_
≥2
VnV
CX SUP
>×
ηNEG GOFF DROPOUT
SUP D
VV
VV
=−+
−×2
ηPOS GON DROPOUT AVDD
SUP D
VV V
VV
=+−
−×2
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
20 ______________________________________________________________________________________
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of high-current loops by placing
the inductor, the output diode, and the output
capacitors near the input capacitors and near the
LX and PGND pins. The high-current input loop
goes from the positive terminal of the input capaci-
tor to the inductor, to the IC’s LX pin, out of PGND,
and to the input capacitor’s negative terminal. The
high-current output loop is from the positive terminal
of the input capacitor to the inductor, to the output
diode (D1), and to the positive terminal of the output
capacitors, reconnecting between the output
capacitor and input capacitor ground terminals.
Connect these loop components with short, wide
connections.
• Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to
reduce resistance and inductance.
• Create a power-ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all
these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an ana-
log ground plane (AGND) consisting of the AGND
pin, all the feedback-divider ground connections,
the operational amplifier divider ground connec-
tions, the COMP and DEL capacitor ground con-
nections, and the device’s exposed backside
paddle. Connect the AGND and PGND islands by
connecting the PGND pin directly to the exposed
backside paddle. Make no other connections
between these separate ground planes.
• Place all feedback voltage-divider resistors within
5mm of their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Take care to avoid running any feedback trace near
LX or the switching nodes in the charge pumps, or
provide a ground shield.
• Place the VCC pin and REF pin bypass capacitors
as close as possible to the device. The ground con-
nection of the VCC bypass capacitor should be
connected directly to the AGND pin with a wide
trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes (FB, FBP, and FBN) and analog
ground. Use DC traces to shield if necessary.
Refer to the MAX17075 evaluation kit for an example of
proper PCB layout.
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
______________________________________________________________________________________ 21
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
22 ______________________________________________________________________________________
23
24
22
21
8
7
9
NEG
BGND
SUP
DRVP
10
POS
FB
RSTIN
AGND
PGND
VCC
12
COM
456
1718 16 14 13
SRC
DEL
FBP
RST
CTL
DRVN
MAX17075
OUT COMP
3
15
DRN
20 11 FBN
LX
19 12 REF
PGND
TQFN
TOP VIEW
Pin Configuration Chip Information
PROCESS: S45UR
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
24 TQFN T2444+4 21-0139 90-0022
MAX17075
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
23
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/08 Initial release —
1 5/12 Updated Absolute Maximum Ratings 2
