SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
DSpeed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
DGreater Noise Immunity Than Standard
Inverters
DOperates With Much Slower Than Standard
Input Rise and Fall Slew Rates
DBalanced Propagation Delays
D±24-mA Output Drive Current
− Fanout to 15 F Devices
DSCR Latchup-Resistant CMOS Process and
Circuit Design
DExceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The CD74AC14 contains six independent inverters. This device performs the Boolean function Y = A.
Each circuit functions as an independent inverter, but because of the Schmitt action, the inverters have dif ferent
input threshold levels for positive-going (VT+) and negative-going (VT−) signals.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − E Tube CD74AC14E CD74AC14E
−55°C to 125°C
SOIC − M
Tube CD74AC14M
AC14M
−55 C to 125 C
SOIC − M
Tape and reel CD74AC14M96
AC14M
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
AOUTPUT
Y
H L
L H
logic diagram, each inverter (positive logic)
YA
Copyright 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
E OR M PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C−55°C to
125°C−40°C to
85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
VCC Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
IOH High-level output current VCC = 4.5 V to 5.5 V −24 −24 −24 mA
IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C−55°C to
125°C−40°C to
85°C
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN MAX MIN MAX MIN MAX
UNIT
VT+
Positive-going
threshold 5 V 2.6 3.4 2.6 3.4 2.6 3.4 V
VT−
Negative-going
threshold 5 V 1.6 2.4 1.6 2.4 1.6 2.4 V
∆VT
Hysteresis
(VT+ − VT−)5 V 0.5 0.5 0.5 V
1.5 V 1.4 1.4 1.4
I
OH
= −50 µA3 V 2.9 2.9 2.9
IOH = −50 µA
4.5 V 4.4 4.4 4.4
V
OH
V
I
= V
T+
IOH = −4 mA 3 V 2.58 2.4 2.48 V
VOH
VI = VT+
IOH = −24 mA 4.5 V 3.94 3.7 3.8
V
IOH = −50 mA†5.5 V 3.85
IOH = −75 mA†5.5 V 3.85
1.5 V 0.1 0.1 0.1
I
OL
= 50 µA3 V 0.1 0.1 0.1
IOL = 50 µA
4.5 V 0.1 0.1 0.1
V
OL
V
I
= V
T−
IOL = 12 mA 3 V 0.36 0.5 0.44 V
VOL
VI = VT−
IOL = 24 mA 4.5 V 0.36 0.5 0.44
V
IOL = 50 mA†5.5 V 1.65
IOL = 75 mA†5.5 V 1.65
IIVI = VCC or GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
Ci10 10 10 pF
†Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
−55°C TO
125°C−40°C TO
85°C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
UNIT
tPLH
A
Y
2.6 10.5 2.7 9.5
ns
tPHL A Y 2.6 10.5 2.7 9.5 ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
Cpd Power dissipation capacitance 45 pF
SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
R1 = 500 Ω†Open
GND
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VC
C
0 V
50% VCC 20% VCC
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
80% VCC
VCC
R2 = 500 Ω†
†When VCC = 1.5 V, R1 = R2 = 1 kΩ
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74AC14E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC14EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC14M ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC14M96 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC14ME4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC14MG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC14M96 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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