Supertex inc. MD1811 High Speed Quad MOSFET Driver Features General Description 6.0ns rise and fall time 2.0A peak output source/sink current 1.8 to 5.0V input CMOS compatible 5.0 to 12V total supply voltage Smart logic threshold Low jitter design Quad matched channels Drives two P- and two N-channel MOSFETs Outputs can swing below ground Low inductance quad flat no-lead package High-performance thermally-enhanced QFN The Supertex MD1811 is a high speed, quad MOSFET driver designed to drive high voltage P and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1811 can operate from a 1.8 to 5.0V logic interface with an optimum operating input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1811 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8V, the control logic may be powered by +5.0 and -5.0V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to 2.0A, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Applications Medical ultrasound imaging Piezoelectric transducer drivers Non-Destructive Testing (NDT) PIN diode driver Clock driver/buffer High speed level translator Typical Application Circuit +10V +10V 0.22F ENAB +PLS1 #1 3.3V CMOS Logic Inputs -PLS1 +PLS2 #2 -PLS2 +100V 0.47F VDD OE VH 1.0F To Piezoelectric Transducer #1 10nF OUTA INA OUTB INB 10nF 1.0F Supertex TC6320 OUTC INC -100V +100V OUTD IND GND VSS VL Supertex MD1811 1.0F To Piezoelectric Transducer #2 10nF 10nF -100V Supertex TC6320 Supertex inc. 1.0F 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com MD1811 Ordering Information Device 16-Lead QFN 4.00x4.00mm body 1.00mm height (max) 0.65mm pitch MD1811 MD1811K6-G -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter Value VDD - VSS, Logic supply voltage -0.5V to +13.5V VH, Output high supply voltage VL -0.5V to VDD+0.5V VL, Output low supply voltage VSS -0.5V to VH+0.5V VSS, Low side supply voltage Pin Configuration 16 1 -7.0V to +0.5V VSS -0.5V to GND +7.0V Logic input levels Maximum junction temperature +125C Storage temperature -65C to 150C Operating temperature -20C to +85C Package power dissipation 16-Lead QFN (K6) (top view) Product Marking 2.2W Thermal resistance (JA)* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Package may or may not include the following marks: Si or 16-Lead QFN (K6) * 1.0oz 4-layer 3x4" PCB DC Electrical Characteristics (V H Sym Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = "Green" Packaging 1811 YWLL 45C/W = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25C) Parameter Min Typ Max Units Logic supply voltage 4.5 - 13 V 2.5V VDD 13V VSS Low side supply voltage -5.5 - 0 V -- VH Output high supply voltage VSS +2.0 - VDD V -- VL Output low supply voltage VSS - VDD -2.0 V -- 0.8 - mA 10 A VDD-VSS IDDQ VDD quiescent current - IHQ VH quiescent current - IDD VDD average current - 8.0 - mA IH VH average current - 26 - mA VIH Input logic voltage high VOE -0.3 - 5.0 V VIL Input logic voltage low 0 - 0.3 V IIH Input logic current high - - 1.0 A IIL Input logic current low - - 1.0 A VIH OE Input logic voltage high 1.7 - 5.0 V VIL OE Input logic voltage low 0 - 0.3 V RIN Input logic impedance to GND 10 20 30 K CIN Logic input capacitance - 5.0 10 pF Supertex inc. Conditions No input transitions, OE = 1 One channel on at 5.0Mhz, No load For logic inputs INA, INB, INC, and IND For logic input OE --- 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 MD1811 Outputs (V H = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25C) Sym Parameter Min Typ Max Units Conditions RSINK Output sink resistance - - 12.5 ISINK = 50mA RSOURCE Output source resistance - - 12.5 ISOURCE = 50mA ISINK Peak output sink current - 2.0 - A -- Peak output source current - 2.0 - A -- ISOURCE AC Electrical Characteristics (V H Sym tirf tPLH tPHL Parameter Input or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25C) Min Typ Max Units Conditions Logic input edge speed requirement - - 10 ns - 7.0 - ns - 7.0 - ns CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns tr Output rise time - 6.0 - ns tf Output fall time - 6.0 - ns l tr - tf l Rise and fall time matching - 1.0 - ns l tPLH-tPHL l Propagation low to high and high to low matching - 1.0 - ns tdm Propagation delay matching - 2.0 - ns Device to device delay match tOE Output enable time - 9.0 - ns --- For each channel Logic Truth Table Logic Inputs Output OE INA INB OUTA OUTB H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL OE INC IND OUTC OUTD H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 MD1811 Simplified Block Diagram VDD VH MD1811 OE OUTA INA OUTB INB OUTC INC OUTD IND GND VSS VL Detailed Block Diagram VDD OE Level Shifter INA Level Shifter OUTA VSS VDD INB VL VH OUTC Level Shifter Level Shifter GND Supertex inc. VH OUTB VDD IND VL Level Shifter VSS INC VH VSS VL VDD VH OUTD SUB VSS VL 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 MD1811 Timing Diagram and VTH / VOE Curve VTH vs VOE VTH 3.3V INPUT 50% 0V 1.5 tPHL tPLH 12V 90% VOE/2 2.0 50% 1.0 90% OUTPUT 0V 0.6V 10% 10% tf tr Application Information For proper operation of the MD1811, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND to OE, where OE is 1.8 to 5.0V. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1811 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2.0A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor Supertex inc. 0.5 0 0 1.0 2.0 3.0 4.0 5.0 VOE of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 MD1811 Pin Description Pin # Function 1 INB Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until IC powered up. 2 VL Supply voltage for N-channel output stage. 3 GND 4 VL Supply voltage for N-channel output stage. 5 INC 6 IND Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until IC powered up. 7 VSS Low side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies and powered-up first. 8 OUTD Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTD will swing to VL turning off the external N-channel MOSFET. 9 OUTC Output driver. Swings from VH to VL. Intended to drive the gate of an externel Pchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTC will swing to VH turning off the external P-channel MOSFET. 10, 11 VH 12 OUTB Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. 13 OUTA Output driver. Swings from VH to VL. Intended to drive the gate of an externel Pchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. 14 VDD High side supply voltage. 15 INA Logic input. Input logic low will cause the output to swing to VH. Input logic high will cause the output to swing to VL. Keep all logic inputs low until IC powered up. 16 OE Output-Enable logic input. When OE is high, (VOE+VGND)/2 sets the logic threshold level for inputs, When OE is low, OUTA and OUTC are at VH, OUTB and OUTD are at VL, regardless of the inputs INA, INB, INC or IND. Keep OE low until IC powered up. Substrate Supertex inc. Description Logic input ground reference. Supply voltage for P-channel output stage. The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6 MD1811 16-Lead QFN Package Outline (K6) 4.00x4.00mm body, 1.00mm height (max), 0.65mm pitch D 16 D2 Note 1 (Index Area D/2 x E/2) 16 1 1 e Note 1 (Index Area D/2 x E/2) E E2 b Top View Bottom View View B Note 3 L A A3 A1 Seating Plane L1 Note 2 Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.25 3.85* 2.50 3.85* 2.50 0.30 4.00 2.65 4.00 2.65 0.35 4.15* 2.80 4.15* 2.80 0.65 BSC L L1 0.00 0O 0.40 - - 0.50 0.15 14O 0.30 JEDEC Registration MO-220, Variation VGGC-2, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-16QFNK64X4P065, Version C041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD1811 D011612 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com