PIC32MX575/675/695/775/795 PIC32MX575/675/695/775/795 Family Silicon Errata and Data Sheet Clarification The PIC32MX575/675/695/775/795 family devices that you have received conform functionally to the current Device Data Sheet (DS61156G), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC32MX575/675/695/775/795 silicon. Note: 1. 2. 3. 4. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A3). Data Sheet clarifications and corrections start on page 14, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with the REAL ICETM In-Circuit Emulator: Note: The Device and Revision ID values for the various PIC32MX575/675/695/775/795 silicon revisions are shown in Table 1. Device ID(1) PIC32MX575F256H 0x4317053 PIC32MX675F256H 0x430B053 PIC32MX775F256H 0x4303053 PIC32MX575F512H 0x4309053 PIC32MX675F512H 0x430C053 PIC32MX695F512H 0x4325053 PIC32MX775F512H 0x430D053 PIC32MX795F512H 0x430E053 PIC32MX575F256L 0x4333053 PIC32MX675F256L 0x4305053 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. SILICON DEVREV VALUES Part Number Note 1: Using the appropriate interface, connect the device to the REAL ICE In-Circuit Emulator. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Revision ID for Silicon Revision(2) A0 A1 A3 0x0 0x1 0x3 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "PIC32MX Flash Programming Specification" (DS61145) for detailed information on Device and Revision IDs for your specific device. (c) 2009-2012 Microchip Technology Inc. DS80480J-page 1 PIC32MX575/675/695/775/795 TABLE 1: SILICON DEVREV VALUES (CONTINUED) Device ID(1) Part Number PIC32MX775F256L 0x4312053 PIC32MX575F512L 0x430F053 PIC32MX675F512L 0x4311053 PIC32MX695F512L 0x4341053 PIC32MX775F512L 0x4307053 PIC32MX795F512L 0x4307053 Note 1: 2: TABLE 2: Revision ID for Silicon Revision(2) A0 A1 A3 0x0 0x1 0x3 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "PIC32MX Flash Programming Specification" (DS61145) for detailed information on Device and Revision IDs for your specific device. SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A0 A1 A3 I2CTM -- 1. The SDA line state may not be detected correctly. X X Ethernet RMII 10 MB 2. Pause frames are sent at 10x the normal rate. X X X ADC Interrupt Generation 3. The interrupt generated by the module cannot be cleared when the module is disabled. X X X Parallel Master Port Slave Mode 4. A PMP interrupt used to wake the device will not be reflected in the interrupt flag until the end of the write strobe. X X X Output Compare Electrical Specification 5. OC Fault detection is not asynchronous. X X X SPI -- 6. The SPIBUSY and SRMT bits assert 1 bit time before the end of the transaction. X X X UART -- 7. The TXBF bit deasserts one PB clock after the interrupt is generated. X X X USB USB PLL 8. The USBPLL does not automatically suspend in Idle mode. X X X Output Compare PWM 9. In PWM mode, the output waveform is one PB clock longer than the expected value. X X X Output Compare PWM Fault Input Mode 10. A Fault interrupt will not be generated if firmware clears the Fault while the Fault is still asserted. X X X DMA Pattern Match 11. In Pattern Match mode, the DMA module may not append all of the CRC results to the result buffer. X X X Timers External Clock 12. In Synchronized External Clock mode, the first period of the count is short. X X X SPI Frame Slave Mode 13. Outgoing data corruption occurs when the frame signal is coincident with the clock. X X X CAN -- 14. TXABAT, TXLARB and TXERR may erroneously be cleared by an aborted read of the CiFIFOCONn register. X X X CAN -- 15. Requested aborts to a TX message via setting CxCON.ABAT or clearing CiFIFOCON.TXREQ may not complete. X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80480J-page 2 (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature CAN -- Item Number 16. Issue Summary The CFIFOCONx.FRESET and CFIFOCONx.UINC bits are not settable via a normal SFR write. Affected Revisions(1) A0 A1 A3 X X X CAN DeviceNetTM 17. DeviceNet filtering does not function. X X X Output Compare PWM Fault Input Mode 18. A Fault may be erroneously cleared due to an aborted read. X X X SPI Slave Mode 19. In Slave mode with STXISEL = 00, a TX buffer underrun condition will not assert the TX interrupt flag. X X X USB -- 20. The TOKBUSY bit does not correctly indicate status when a transfer completes within the Start of Frame (SOF) threshold. X X X USB Host Mode 21. In Host mode, the interval between the first two SOF packets may be less than what is specified by the USB specification. X X X WDT -- 22. When code-protect is enabled, the WDT is not held in Reset during the POR RAM Clear Sequence (RCS). X X X Oscillator Clock Switch and Two -Speed Start-Up 23. Clock switching and Two-Speed Start-up may cause a general exception when the reserved bit 8 of the DDPCON register is `0'. X X X Oscillator Clock Switch 24. Clock source switching may cause a general exception or POR when switching from a slow clock to a fast clock. X X X SPI Slave Mode 25. A wake-up interrupt may not be clearable. X X X PORTS -- 26. I/O pins do not tri-state immediately, if previously driven high. X X X SPI -- 27. Byte writes to the SPISTAT register are not decoded correctly. X X X SPI Frame Mode 28. Recovery from an underrun requires multiple SPI clock periods. X X X CAN -- 29. The TXBAT bit status may be incorrect after an abort. X X X UART IrDA(R) 30. The IrDA minimum bit time is not detected at all baud rates. X X X UART IrDA 31. TX data is corrupted when BRG values greater than 0x200 are used. X X X JTAG -- 32. On 64-pin devices, the TMS pin requires an external pull-up. X X X UART -- 33. The TRMT bit is asserted before the transmission is complete. X X X UART UART Receive Buffer Overrun Error Status 34. The OERR bit does not get cleared on a module Reset. The OERR bit retains its value even after the UART module is reinitialized. X X X ADC Conversion Trigger from INT0 Interrupt 35. The ADC module conversion triggers occur on the rising edge of the INT0 signal even when INT0 is configured to generate an interrupt on the falling edge. X X X JTAG Boundary Scan 36. Pin 100 on 100-pin packages and pin A1 on 121-pin packages do not respond to boundary scan commands. X X X DMA Suspend Status 37. The DMABUSY status bit may not reflect the correct status if the DMA module is suspended. X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. (c) 2009-2012 Microchip Technology Inc. DS80480J-page 3 PIC32MX575/675/695/775/795 TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Number Affected Revisions(1) Issue Summary A0 A1 A3 Voltage Regulator BOR 38. Device may not exit BOR state if BOR event occurs. X X Output Compare PWM Mode 39. If the Output Compare module is configured for a 0% duty cycle (OCxRS = 0), a glitch may occur on the next cycle. X X X Oscillator Clock Switch 40. If a Fail-Safe Clock Monitor (FSCM) event occurs when Primary Oscillator (POSC) mode is used, firmware clock switch requests to switch from FRC mode will fail. X X X I2C Slave Mode 41. The I2C module does not respond to address 0x78 when the STRICT and A10M bits are cleared in the I2CxCON register. X X X USB UIDLE Interrupt 42. UIDLE interrupts cease if the UIDLE interrupt flag is cleared. X X X CPU Data Access from Flash 43. A Data Bus Exception (DBE) may occur if an interrupt is encountered by the CPU while it is accessing data from Flash memory. X X X CPU Data Write to a Peripheral 44. A data write operation by the CPU to a peripheral may be repeated if an interrupt occurs during initial write operation. X X X Oscillator Clock Out 45. A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, during a Power-on Reset (POR) condition. X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80480J-page 4 (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A3). 1. Module: I2CTM The I2C modules, with the exception of I2C1 and I2C2, may not detect state of SDA line correctly: - In Master mode, module may encounter a bus collision when performing a Start condition. - In Slave mode, module may not Acknowledge the first packet sent after enabling the I2C module. In this case, it will return a NACK instead of an ACK.OCxRS. Slave Mode: The I2C master device on the bus must either pull the SDA line low, then high again, prior to sending the first packet to the device, or must resend the first packet. Affected Silicon Revisions A0 A1 X X A3 2. Module: Ethernet In 10 MB RMII mode only, pause frames are sent at 10x the normal rate. This reduces the available network bandwidth if the device is connected to the network via a hub. This does not reduce functionality or violate specifications. Work around Work around If bandwidth is a concern, connect the PIC32 device to a network using an Ethernet switch. Master Mode: Affected Silicon Revisions 1. 2. Use another I2C node on the bus to sequence I2C bus transactions such as the Start event. Connect an unused general-purpose I/O pin to the SDAx pin of the I2C module to be used. The user software must perform the following sequence of operations in order to execute a Start condition on the I2C bus: a) With the I2C module disabled, clear the LAT bit of the general-purpose I/O pin that is connected to the SDAx pin. Then, clear the corresponding TRIS bit to make sure the I/O pin is pulled low. b) Enable the I2C module by setting the ON bit (I2CxCON<15>); but do not configure the I2CxBRG register at this time. c) Execute a software delay loop of at least 10 s. d) Set the TRIS bit of the I/O pin connected to the SDAx pin. This will make it an input pin, thereby ensuring that it goes to a high logic state. e) Execute a software delay loop of at least 10 usec. f) Configure the I2CxBRG register with the value required by the application. g) Issue a Start condition by setting the SEN bit (I2CxCON<0>) as needed. I2C communications can now proceed normally. (c) 2009-2012 Microchip Technology Inc. A0 A1 A3 X X X 3. Module: ADC The interrupt generated by the ADC module cannot be cleared when the ADC module is disabled. Work around Ensure the interrupt is serviced and the interrupt flag is cleared before turning off the ADC module. Affected Silicon Revisions A0 A1 A3 X X X DS80480J-page 5 PIC32MX575/675/695/775/795 4. Module: Parallel Master Port In Slave mode, a PMP interrupt will wake the device; however, the interrupt source will not be reflected in the interrupt flag until the end of the write strobe. Work around There are two possible solutions to this issue: 1. If multiple wake-up sources are to be used, firmware can poll all of the configured wakeup source interrupt flags. If none are set, assume the source was the PMP. Firmware can wait for a period exceeding the write strobe length, and then poll the PMP interrupt flag. 2. 7. Module: UART The UxSTA.TXBF bit clears one PB clock cycle after the interrupt is generated. When using a PB bus divisor other than 1:1 and polling the UART transmit interrupt flag with the next instruction reading the UxSTA.TXBF bit, the result may not reflect the actual TXBF status. Work around There are two possible solutions to this issue: 1. 2. Only use a PB bus divisor of 1:1. If firmware is polling the transmit interrupt flag and the TXBF flag, insert a read of the UxSTA register between these operations and discard the result. This read will ensure the status of the TXBF flag is correct when the next read of this register occurs. Affected Silicon Revisions A0 A1 A3 X X X 5. Module: Output Compare The Fault input detection is not asynchronous. There is a 1 to 2 Peripheral Bus (PB) clock delay between the Fault input assertion and the shutdown of the appropriate OCMP output pin. Affected Silicon Revisions A0 A1 A3 X X X 8. Module: USB When U1CNFG1.USBSIDL is set, the USBPLL does not automatically suspend in Idle mode. Work around Work around Ensure that the device driven by the OCMP module can tolerate this shutdown delay. Use firmware to manually suspend the USB clock before entering Sleep mode. Affected Silicon Revisions Affected Silicon Revisions A0 A1 A3 A0 A1 A3 X X X X X X 6. Module: SPI 9. Module: Output Compare The SPIBUSY and SRMT bits assert 1 bit time before the end of the transaction. In PWM mode, the output waveform is one PB clock longer than the expected value. Work around Work around Firmware must provide a 1 bit time delay between the assertion of these bits and performing any operation that requires the transaction to be complete. Load OCRS with a value one less than the number expected to achieve the desired output. Affected Silicon Revisions A0 A1 A3 X X X DS80480J-page 6 Affected Silicon Revisions A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 10. Module: Output Compare In PWM mode, if firmware attempts to clear the OCFLT bit while the Fault still exists, a second interrupt will not be generated for this Fault when firmware exits the Interrupt Service Routine (ISR). The OCFLT bit will remain set while a Fault is detected. Work around In the ISR, clear the OSxFLT bit, and test the OCxFLT bit before exiting the ISR. If the bit is set, set the OCx interrupt to generate a second interrupt. Affected Silicon Revisions A0 A1 A3 X X X 13. Module: SPI Outgoing data will be corrupted when in Frame Slave mode with FRMCNT > 0 and the frame pulse is coincident with the clock. Work around 1. There is no work around for operation when the Frame pulse is coincident with the clock. 2. Provide a frame signal that precedes the clock signal. Affected Silicon Revisions A0 A1 A3 X X X 14. Module: CAN In Pattern Match mode, the DMA module may not append all of the CRC results to the result buffer. TXABAT, TXLARB and TXERR may erroneously be cleared by an aborted read of the CiFIFOCONn register. An aborted read occurs when a load instruction in the CPU pipeline has started execution, but is aborted due to an interrupt. Work around Work around Use firmware to read the CRC result and append it to the result buffer. Disable interrupts before reading the contents of the CiFIFOCONn register, and then re-enable interrupts after reading the register. 11. Module: DMA Affected Silicon Revisions A0 A1 A3 X X X Affected Silicon Revisions A0 A1 A3 X X X 12. Module: Timers When the Timer module is first enabled and the prescaler value is greater than 1, the number of input clocks required to increment the timer from 0 to 1 is one input clock, not the value stated by the prescaler. Work around None. Affected Silicon Revisions A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. DS80480J-page 7 PIC32MX575/675/695/775/795 15. Module: CAN Requested aborts to a TX message via setting CxCON.ABAT or clearing CiFIFOCON.TXREQ may not complete. The CAN bus protocol is not violated. Work around 1. After a general abort request, firmware should poll until CxCON.BUSY = 0 or wait two message times. If CxCON.ABAT remains high, the message was successfully aborted and the module must be reset by clearing and setting bit CxCON.ON. After a FIFO specific abort request, firmware should poll until CxCON.BUSY = 0 or wait two message times. If CFIFOCONx.TXREQ remains high, the message was successfully aborted and the FIFO must be reset by setting CFIFOCONx.FRESET and polling until CFIFOCONx.FRESET = 0. 2. Affected Silicon Revisions A0 A1 A3 X X X 18. Module: Output Compare The Output Compare module may reinitialize or clear a Fault on an aborted read of the OCxCON register. An aborted read occurs when a read instruction in the CPU pipeline has started execution, but is aborted due to an interrupt. Work around Disable interrupts before reading the contents of the OCxCON register, and then re-enable interrupts after reading the register. Affected Silicon Revisions A0 A1 A3 X X X 19. Module: SPI In Slave mode with STXISEL<1:0> = 00, a TX buffer underrun condition will not assert the TX interrupt flag. Work around Use any other legal value of STXISEL<1:0> (i.e., "01", "10", or "11". Affected Silicon Revisions 16. Module: CAN The CFIFOCONx.FRESET and CFIFOCONx.UINC bits are not settable via a normal Special Function Register (SFR) write. Work around A0 A1 A3 X X X 20. Module: USB Use the SET register operations to change the state of these bits. The TOKBUSY bit does not correctly indicate status when a transfer completes within the Start of Frame threshold. Affected Silicon Revisions Work around A0 A1 A3 X X X 17. Module: CAN The DeviceNetTM message filtering does not function. Use a firmware semaphore to track when a token is written to U1TOK. Firmware then clears the semaphore when the transfer is complete. Affected Silicon Revisions A0 A1 A3 X X X Work around Use hardware to filter the Standard Identifier (SID) and use firmware to decode the DeviceNet identifier. Affected Silicon Revisions A0 A1 A3 X X X 21. Module: USB In Host mode, the interval between the first two SOF packets may be less than what is specified by the USB specification. Work around None. Affected Silicon Revisions DS80480J-page 8 A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 22. Module: WDT 25. Module: SPI When code-protect is enabled, the WDT is not held in reset during the POR RAM Clear Sequence (RCS). If the WDT period does not exceed the RCS period, the WDT will reset the part and the RCS sequence will restart. In Slave mode, when entering Sleep mode after a SPI transfer with SPI interrupts enabled, a false interrupt may be generated that wakes the device. This interrupt can be cleared; however, entering Sleep may cause the condition to occur again. Work around Work around Use WDT periods equal to or longer than 128 ms. Since the RCS and WDT run concurrently, firmware will have a reduced period in which to service the WDT for the first time. Do not use SPI in Slave mode as a wake-up source from Sleep. Affected Silicon Revisions A0 A1 A3 X X X 23. Module: Oscillator Clock switching and Two-Speed Start-up may cause a general exception when the reserved bit 8 of the DDPCON register is `0'. Work around Ensure that the reserved bit 8 of the DDPCON register to set to `1'. For example, DDPCON |= 0x100; Affected Silicon Revisions A0 A1 A3 X X X 24. Module: Oscillator Clock source switching may cause a general exception or POR when switching from a slow clock to a fast clock. Work around Clock source switches should be performed by first switching to the FRC, and then switching to the target clock source. Note: If the peripheral library is being used, clock switching is performed automatically through the FRC. Affected Silicon Revisions A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. Affected Silicon Revisions A0 A1 A3 X X X 26. Module: PORTS When an I/O pin is set to output a logic high signal, and is then changed to an input using the TRISx registers, the I/O pin should immediately tri-state and let the pin float. Instead, the pin will continue to partially drive a logic high signal out for a period of time. Work around The pin should be driven low, prior to being tristated, if it is desirable for the pin to tri-state quickly. Affected Silicon Revisions A0 A1 A3 X X X 27. Module: SPI Byte writes to the SPISTAT register are not decoded correctly. A byte write to byte zero of SPISTAT is actually performed on both byte zero and byte one. A byte write to byte one of SPISTAT is ignored. Work around Only perform word operations on the SPISTAT register. Affected Silicon Revisions A0 A1 A3 X X X DS80480J-page 9 PIC32MX575/675/695/775/795 28. Module: SPI In Frame mode the module is not immediately ready for further transfers after clearing the SPITUR bit. The SPITUR bit will be cleared by hardware before the SPI state machine is prepared for the next operation. Work around Firmware must wait at least four bit times before writing to the SPI registers after clearing the SPITUR bit. Affected Silicon Revisions A0 A1 A3 X X X 29. Module: CAN When an abort request occurs concurrently with a successful message transmission, and additional messages remain in the FIFO, these remaining messages are not transmitted and the TXABAT bit does not reflect the abort. Work around The actual FIFO status can be determined by the FIFO pointers CFIFOCI and CFIFOUA. Affected Silicon Revisions A0 A1 A3 X X X 30. Module: UART The UART module is not fully IrDA(R) compliant. The module does not detect the 1.6 s minimum bit width at all baud rates as defined in the IrDA specification. The module does detect the 3/16 bit width at all baud rates. Work around None. 31. Module: UART In IrDA mode with baud clock output enabled, the UART TX data is corrupted when the BRG value is greater than 0x200. Work around Use the Peripheral Bus (PB) divisor to lower the PB frequency such that the required UART BRG value is less than 0x201. Affected Silicon Revisions A0 A1 A3 X X X 32. Module: JTAG On 64-pin devices an external pull-up resistor is required on the TMS pin for proper JTAG. Work around Connect a 100k-200k pull-up to the TMS pin. Affected Silicon Revisions A0 A1 A3 X X X 33. Module: UART The TRMT bit is asserted during the STOP bit generation, not after the STOP bit has been sent. Work around If firmware needs to be aware when the transmission is complete, firmware should add a half bit time delay after the TRMT bit is asserted. Affected Silicon Revisions A0 A1 A3 X X X Affected Silicon Revisions A0 A1 A3 X X X DS80480J-page 10 (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 34. Module: UART The OERR bit does not get cleared on a module Reset. If the OERR bit is set and the module is disabled, the OERR bit retains its status even after the UART module is reinitialized. Work around The user software must check this bit in the UART module initialization routine and clear it if it is set. Affected Silicon Revisions A0 A1 A3 X X X 35. Module: ADC When the ADC module is configured to start conversion on an external interrupt (SSRC<2:0> = 001), the start of conversion always occurs on a rising edge detected at the INT0 pin, even when the INT0 pin has been configured to generate an interrupt on a falling edge (INT0EP = 0). 37. Module: DMA If the DMA module is suspended by setting the DMA Suspend bit (SUSPEND) in the DMA Controller Control register (DMACON), the DMA Module Busy Bit (DMABUSY) in the DMACON register may continue to show a Busy status, when the DMA module completes transaction. Work around Use the Channel Busy bit (CHBUSY) in the DMA Channel Control Register (DCHxCON) to check the status of the DMA channel. Affected Silicon Revisions A0 A1 A3 X X X 38. Module: Voltage Regulator Device may not exit BOR state if BOR event occurs. Work arounds Work around Work around 1: Generate ADC conversion triggers on the rising edge of the INT0 signal. VDD must remain within the published specification (see parameter DC10 of the device data sheet). Alternatively, use external circuitry to invert the signal appearing at the INT0 pin, so that a falling edge of the input signal is detected as a rising edge by the INT0 pin. Work around 2: Affected Silicon Revisions A0 A1 A3 X X X 36. Module: JTAG Pin 100 on 100-pin packages and pin A1 on 121-pin packages do not respond to boundary scan commands. Work around Reset device by providing POR condition. Affected Silicon Revisions A0 A1 X X A3 39. Module: Output Compare If the Output Compare module is configured for a 0% duty cycle (OCxRS = 0), a glitch may occur on the next cycle. Work around None. The Output Compare module should be disabled and then re-enabled to achieve a 0% duty cycle. Affected Silicon Revisions Affected Silicon Revisions A0 A1 A3 A0 A1 A3 X X X X X X (c) 2009-2012 Microchip Technology Inc. DS80480J-page 11 PIC32MX575/675/695/775/795 40. Module: Oscillator If the Primary Oscillator (POSC) mode is implemented and a Fail-Safe Clock Monitor (FSCM) event occurs (failure of the external primary clock), the internal clock source will switch to the FRC oscillator. Subsequent firmware clock switch requests from the FRC oscillator to other clock sources will fail and the device will continue to execute on the FRC oscillator. Upon repair of the external clock source and a power-on state, the device will resume operation with the primary oscillator clock source. 42. Module: USB In the case where the bus has been idle for > 3 ms, and the UIDLE interrupt flag is set, if software clears the interrupt flag, and the bus remains idle, the UIDLE interrupt flag will not be set again. Work around Software can leave the UIDLE bit set until it has received some indication of bus resumption. (Resume, Reset, SOF, or Error). Note: Resume and Reset are the only interrupts that should be gotten following UIDLE assertion. If, at any point in time, the UIDLE bit is set, it should be okay to suspend the USB module (as long as this code is protected by the GUARD and/or ACTPEND logic). Note that this will require software to clear the UIDLE interrupt enable bit to exit the USB ISR (if using interrupt driven code). Work around None. Affected Silicon Revisions A0 A1 A3 X X X 41. Module: I2C Affected Silicon Revisions The slave address, 0x78, is one of a group of reserved addresses. It is used as the upper byte of a 10-bit address when 10-bit addressing is enabled. The I2C module control register allows the programmer to enable both 10-bit addressing and strict enforcement of reserved addressing, with the A10M and STRICT bits, respectively. When both bits are cleared, the device should respond to the reserved address 0x78, but does not. A0 A1 A3 X X X 43. Module: CPU When both prefetch and instruction cache are enabled, a Data Bus Exception (DBE) may occur if an interrupt is encountered by the CPU while it is accessing data from Flash memory. Work around Work around None. To avoid a DBE, use one of the following two solutions: Affected Silicon Revisions A0 A1 A3 X X X 1. Structure application code, such that interrupts are not used while the CPU is accessing data from Flash memory. Disable either the Prefetch module or CPU cache functionality as follows (both are disabled by default on a Power-on Reset (POR)): a) To disable the Prefetch module, set the Predictive Prefetch Enable bits, PREFEN<1:0>, in the Cache Control Register, CHECON<6:5>, to `00'. b) To disable CPU cache, set the Kseg0 bits, K0<2:0>, in the CP0 Configuration Register, Config<2:0>, to `010'. 2. Affected Silicon Revisions DS80480J-page 12 A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. PIC32MX575/675/695/775/795 44. Module: CPU During normal operation, if a CPU write operation is interrupted by an incoming interrupt, it should be aborted (not completed) and resumed after the interrupt is serviced. However, some of these write operations may not be aborted, resulting in a double write to peripherals by the CPU (the first write during the interrupt and the second write after the interrupt is serviced). Work around Most peripherals are not affected by this issue, as a double write will not have a negative impact. However, the following communication peripherals will double-send data if their respective transmit buffers are written twice: SPI, I2C, UART and PMP. To avoid double transmission of data, utilize DMA to transfer data to these peripherals. Affected Silicon Revisions A0 A1 A3 X X X 45. Module: Oscillator A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, OSCIOFNC (DEVCFG1<10>), during a Power-on Reset (POR) condition. Work around Do not connect the CLKO pin to a device that would be adversely affected by rapid pin toggling or a frequency other than that defined by the oscillator configuration. Do not use the CLKO pin as an input if the device connected to the CLKO pin would be adversely affected by the pin driving a signal out. Affected Silicon Revisions A0 A1 A3 X X X (c) 2009-2012 Microchip Technology Inc. DS80480J-page 13 PIC32MX575/675/695/775/795 Data Sheet Clarifications APPENDIX A: The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS61156G): Rev A Document (8/2009) Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Pin Diagrams In all pin diagrams in the current revision of the data sheet, the D- and D+ pins are incorrectly indicated as 5V-tolerant pins through the use of shading. The D- and D+ pins are not 5V-tolerant pins and should not be shaded in the pin diagrams. 2. Module: AC Characteristics: Standard Operating Conditions The Standard Operating conditions in the following table shows the incorrect starting voltage range of 2.3V. The correct starting range is: 2.9V: * Table 31-35: Ethernet Module Specifications The Standard Operating conditions in the following tables show the incorrect starting voltage range of 2.3V. The correct starting range is: 2.5V: * Table 31-36: ADC Module Specifications * Table 31-37: 10-bit ADC Conversion Rate Parameters * Table 31-38: Analog-to-Digital Conversion Timing Requirements REVISION HISTORY Initial release of this document; issued for revision A0 silicon. Includes silicon issues 1 (I2CTM), 2 (Ethernet), 3 (ADC), 4 (Parallel Master Port), 5 (Output Compare), 6 (SPI) and 7 (UART). Rev B Document (11/2009) Added silicon issues 8 (USB), 9-10 (Output Compare), 11 (DMA), 12 (Timers), 13 (SPI), 14-17 (CAN), 18 (Output Compare), 19 (SPI), 20-21 (USB), 22 (WDT), 23 (Oscillator) and 24 (Oscillator). Rev C Document (9/2010) The document title was changed to PIC32MX575/675/ /695/775/795 Family Silicon Errata and Data Sheet Clarification. Added devices to Table 1: Silicon DEVREV Values. Modified silicon issue 1 (I2CTM). Added silicon issues 25 (SPI), 26 (PORTS), 27-28 (SPI), 29 (CAN), 30-31 (UART), 32 (JTAG), 33 (UART) and 34 (UART), and added data sheet clarification issue 1 (Pin Diagrams). Rev D Document (11/2010) Removed data sheet clarification 1. Added silicon issues 35 (ADC), 36 (JTAG) and 37 (DMA). Rev E Document (12/2010) Added silicon issue 38 (Voltage Regulator). Rev F Document (3/2011) Updated the current silicon revision to A1 throughout the document. Added silicon issue 39 (Output Compare) and data sheet clarification 1 (Pin Diagrams). Rev G Document (10/2011) Updated issue 19 (SPI). Added silicon issues 40 (Oscillator), 41 (I2C), and 42 (USB). Added data sheet clarification 2 (AC Characteristics: Standard Operating Conditions). Rev H Document (10/2011) Updated the current silicon revision to A3 throughout the document. Rev J Document (2/2012) Added silicon issues 43 (CPU), 44 (CPU), and 45 (Oscillator). DS80480J-page 14 (c) 2009-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-049-9 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009-2012 Microchip Technology Inc. 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