SLVS367A − MARCH 2001 − REVISED JUNE 2001
1
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FEATURES
DIntegrated Drive Regulator (4 V to 14 V)
DAdjustable/Adaptive Dead-Time Control
D4-A Peak current at VDRV of 14 V
D10-V to 15-V Supply Voltage Range
DTTL-Compatible Inputs
DInternal Schottky Diode Reduces Part Count
DSynchronous or Nonsynchronous Operation
DInverting and Noninverting Options
DTSSOP PowerPad Package for Excellent
Thermal Performance
APPLICATIONS
DSingle or Multiphase Synchronous-Buck
Power Supplies
DHigh-Current DC/DC Power Modules
DESCRIPTION
The TPS2838/39/48/49 devices are MOSFET
drivers designed for high-performance
synchronous power supplies. The drivers can
source and sink up to 4-A peak current at a 14-V
drive voltage. These are ideal devices to use with
power supply controllers that do not have on-chip
drivers. The low-side driver is capable of driving
loads of 3.3 nF in 10-ns rise/fall times and has
40-ns propagation delays at room temperature.
The MOSFET drivers have an integrated 150-mA
regulator, so the gate drive voltage can be
optimized for specific MOSFETs. The TPS2848
and TPS2849 have a fixed 8-V drive regulator,
while the TPS2838/39 allow the drive regulator to
be adjusted from 4 V to 14 V by selection of two
external resistors.
The devices feature VDRV to PGND shoot-
through protection with adaptive/adjustable
deadtime control. The deadtime, for turning on t h e
high-side FET from LOWDR transitioning low, is
adjustable with an external capacitor on the
DELAY pin. This allows compensation for the
effect the gate resistor has on the synchronous
FET turn off. The adaptive deadtime prevents the
turning on o f the low-side FET until the voltage on
the BOOTLO pin falls below a threshold after the
high-side FET stops conducting. The high-side
drive can be configured as a ground referenced
driver or a floating bootstrap driver. The internal
Schottky diode minimizes the size and number of
external components needed for the bootstrap
driver circuit. Only one external ceramic capacitor
is required to configure the bootstrap driver.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ENABLE
IN
PWRRDY
DELAY
NC
DT
AGND
BOOT
HIGHDR
BOOTLO
VCC
VDRV
LOWDR
PGND
Thermal
Pad
TPS2848, TPS2849
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ENABLE
IN
PWRRDY
DELAY
SYNC
ADJ
DT
AGND
BOOT
HIGHDR
BOOTLO
VCC
VDRV
LOWDR
NC
PGND
Thermal
Pad
TPS2838, TPS2839
PWP PACKAGE
(TOP VIEW)
ACTUAL SIZE
(5,1 mm x 6,6 mm)
ACTUAL SIZE
(5,1 mm x 6,6 mm)
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
Copyright 2001, Texas Instruments Incorporated
PowerPAD is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
2www.ti.com
description (continued)
The SYNC pin can be used regardless of load to disable the synchronous FET driver and operate the power
supply nonsynchronously.
A power ready/undervoltage lockout function outputs the status of the VCC-pin voltage and driver regulator
output on the open-drain PWRRDY pin. This feature can be used to enable a controller’s output once the VCC
voltage reaches the threshold and the regulator output is stable. This function ensures both FET drivers are off
when the VCC voltage is below the voltage threshold.
The TPS2838/39/48/49 devices are offered in the thermally enhanced 14-pin and 16-pin PowerPAD TSSOP
package. The PowerPAD package features an exposed leadframe on the bottom that can be soldered to the
printed-circuit board to improve thermal efficiency. The TPS2838/48 are noninverting control logic while the
TPS2839/49 drivers are inverting control logic.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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functional block diagram (TPS2838, TPS2839)
POR
Vr1
PWRRDY THERMAL
SHUTDOWN
SYS_UVLO
VCC
DRIVE
REGULATOR
REFERENCES
VCC
Vr1Vref
0.9 × Vref
VDRVADJ
SHUTDOWN
BOOT
0.9 × Vref
AGND
BOOTLO
HIGHDR
SHUTDOWN
INVERTING OPTION
TPS2839 ONLY
PGND
LOWDR
SYS_UVLO
VDRV
DEADTIME
CONTROL DELAY
SYNC
DT
ENABLE
IN
functional block diagram (TPS2848, TPS2849)
POR
Vr1
PWRRDY THERMAL
SHUTDOWN
SYS_UVLO
VCC
DRIVE
REGULATOR
REFERENCES
VCC
Vr1Vref
0.9 × Vref
VDRV
SHUTDOWN
BOOT
0.9 × Vref
AGND
BOOTLO
HIGHDR
SHUTDOWN
INVERTING OPTION
TPS2849 ONLY
PGND
LOWDR
SYS_UVLO
VDRV
DEADTIME
CONTROL DELAY
DT
ENABLE
IN
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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Terminal Functions
TERMINAL
NAME
NO. DESCRIPTION
NAME
TPS283x TPS284x
DESCRIPTION
ADJ 6 — Adjust. The adjust pin is the feedback pin for the drive regulator (TPS283X only)
AGND 8 7 Analog ground
BOOT 16 14 Bootstrap. A capacitor is connected between the BOOT and BOOTLO pins to develop the floating
bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.
BOOTLO 14 12 Boot low. This pin connects to the junction of the high-side and low-side MOSFETs.
DELAY 4 4 Delay. Connecting a capacitor between this pin and ground adjusts the deadtime for high-side driver
DT 7 6 Deadtime control. Connect DT to the junction of the high-side and low-side MOSFETs
ENABLE 1 1 Enable. If ENABLE is low, both drivers are off.
HIGHDR 15 13 High drive. This pin is the output drive for the high-side power MOSFET.
IN 2 2 Input. This pin is the input signal to the MOSFET drivers.
LOWDR 11 9Low drive. This pin is the output drive for the low-side power MOSFET.
NC 10 5 No internal connection
PGND 9 8 Power ground. This pin is connected to the FET power ground.
PWRRDY 3 3 Power ready. This open-drain pin indicates a power good for VDRV and VCC.
SYNC 5 — Synchronous rectifier enable. If SYNC is low, the low-side driver is always off; if SYNC is high, the
low-side driver provides gate drive to the low-side MOSFET.
VCC 13 11 Input power supply. It is recommended that a capacitor (minimum 1 µF) be connected from VCC to
PGND. Note that VCC must be 2 V higher than VDRV.
VDRV 12 10 Drive regulator output voltage. It is recommended that a capacitor (minimum 1 µF) be connected from
VDRV to PGND. Note that VCC must be 2 V higher than VDRV.
detailed description
low-side driver
The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 4 A,
source and sink.
high-side driver
The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 4 A
minimum, source and sink. The high-side driver can be configured as a GND-reference driver or as a
floating-bootstrap driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum
voltage that can be applied from BOOT to ground is 30 V.
dead-time (DT) control
Dead-time control prevents shoot-through current from flowing through the main power FETs during switching
transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (BOOTLO) is low. The TTL-compatible DT terminal connects to
the junction of the power FETs.
ENABLE
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a
TTL-compatible digital terminal.
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detailed description (continued)
IN
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The
TPS2838/48 have noninverting inputs; the TPS2839/49 have inverting inputs. On the TPS2838 and TPS2848,
a high on IN results in a high on HIGHDR. On the TPS2839 and TPS2849, a high on IN results in a low on
HIGHDR.
SYNC (TPS283x only)
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off. SYNC is a TTL-compatible digital terminal.
PWRRDY
Depicts the status of the VCC pin voltage and the driver regulator output on the open-drain PWRRDY pin.
DELAY
Adjustable high-side turnon delay from from when the low-side FET is turned off.
ADJ (TPS283x only)
Input for adjusting the driver regulator output. See the application information section for the adjustment formula.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range:ADJ −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to PGND (high-side driver ON) −0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOTLO to PGND −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to BOOTLO −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLE, IN, and SYNC −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDRV, PWRRDY, and DELAY −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DT −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ−40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to PGND.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°CDERATING FACTOR TA = 70°C TA = 85°C
14-pin PWP with solder‡2668 26.68 mW/°C 1467 1067
14-pin PWP without solder‡1024 10.24 mW/°C 563 409
16-pin PWP with solder‡2739 27.39 mW/°C 1506 1095
16-pin PWP without solder‡1108 11.08 mW/°C 609 443
JUNCTION-CASE THERMAL RESISTANCE TABLE
14-pin PWP Junction-case thermal resistance 2.07 °C/W
16-pin PWP Junction-case thermal resistance 2.07 °C/W
‡Test Board Conditions:
1. Thickness: 0.062I
2. 3I × 3I (for packages < 27 mm long)
3. 4I × 4I (for packages > 27 mm long)
4. 2-oz copper traces located on the top of the board (0,071 mm thick)
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1-oz copper (0,036 mm thick)
7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief literature number SLMA002.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 10 15 V
Input voltage, VIBOOT to PGND 10 29 V
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC
Quiescent current
V(ENABLE) = Low, VCC = 13 V 425 µA
ICC Quiescent current V(ENABLE) = High, VCC = 13 V 1 mA
NOTE 2: Ensured by design, not production tested.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
dead-time control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH(LOWDR) LOWDR high-level input voltage Over full VDRV range See Note 2 50 %VDRV
VIL(LOWDR) LOWDR low-level input voltage Over full VDRV range See Note 2 1 V
VIH(DT) DT high-level input voltage Over full VCC range 2 V
VIL(DT) DT low-level input voltage Over full VCC range 1 V
Deadtime delay V(VDRV) = 4 V to 14 V See Note 2 0.5 1 1.5 ns/pF
Driver nonoverlap time (DT to LOWDR)
V(VDRV) = 4.5 V, TJ = 25°C, See Note 2 30 150 ns
Driver nonoverlap time (DT to LOWDR
)
V(VDRV) = 14.5 V, TJ = 25°C, See Note 2 30 100 ns
Driver nonoverlap time (LOWDR to
V(VDRV) = 4.5 V, CL(Delay) = 50 pF
TJ = 25°C, See Note 2 75 180
ns
Driver nonoverlap time (LOWDR to
HIGHDR) V(VDRV) = 14.5 V, CL(Delay) = 50 pF
TJ = 25°C, See Note 2 58 125 ns
Driver nonoverlap time (LOWDR to
V(VDRV) = 4.5 V, CL(Delay) = 0 pF
TJ = 25°C, See Note 2 50 125
ns
Driver nonoverlap time (LOWDR to
HIGHDR) V(VDRV) = 14.5 V, CL(Delay) = 0 pF
TJ = 25°C, See Note 2 30 100 ns
NOTE 2: Ensured by design, not production tested.
high-side driver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BOOT) −V(BOOTLO) = 4 V,
V(HIGHDR) = 0.5 V (src) 1 1.3
V(BOOT) −V(BOOTLO) = 4 V,
See Note 2 V(HIGHDR) = 4 V (sink) 2 2.4
Peak output current
V(BOOT) −V(BOOTLO) = 8 V,
V(HIGHDR) = 0.5 V (src) 2 2.4
A
Peak output current
V(BOOT) −V(BOOTLO) = 8 V,
See Note 2 V(HIGHDR) = 8 V (sink) 2 3.3 A
V(BOOT) −V(BOOTLO) = 14 V,
V(HIGHDR) = 0.5 V (src) 2 3.9
V(BOOT) −V(BOOTLO) = 14 V,
See Note 2 V(HIGHDR) = 14 V (sink) 2 4.4
V(BOOT) −V(BOOTLO) = 4.5 V
V(HIGHDR) = 4 V (src) 45
V(BOOT) −V(BOOTLO) = 4.5 V
TJ = 25°CV(HIGHDR) = 0.5 V (sink) 6
ro
Output resistance
V(BOOT) −V(BOOTLO) = 7.5 V,
V(HIGHDR) = 7 V (src) 26
Ω
roOutput resistance
V(BOOT) −V(BOOTLO) = 7.5 V,
TJ = 25°CV(HIGHDR) = 0.5 V (sink) 5Ω
V(BOOT) −V(BOOTLO) = 11.5 V,
V(HIGHDR) = 11 V (src) 20
V(BOOT) −V(BOOTLO) = 11.5 V,
TJ = 25°CV(HIGHDR) = 0.5 V (sink) 4
HIGHDRV-to-BOOTLO resistor 250 kΩ
CL = 3.3 nF, V(BOOTLO) = GND,
V(BOOT)= 4 V 85
CL = 3.3 nF, V(BOOTLO) = GND
,
TJ = 125
°
C
V(BOOT)= 8 V 70
tr/tf
Rise and fall time
TJ = 125°C
V(BOOT)= 14 V 65
ns
tr/tf
Rise and fall time
(see Notes 2 and 3)
CL = 10 nF, V(BOOTLO) = GND,
V(BOOT)= 4 V 170 ns
(see Notes 2 and 3)
CL = 10 nF, V(BOOTLO) = GND,
TJ = 125
°
C
V(BOOT)= 8 V 140
TJ = 125°C
V(BOOT)= 14 V 100
Propagation delay time,
V(BOOTLO) = GND, TJ = 125°C,
V(BOOT) = 4 V 120
t
PHL
Propagation delay time,
HIGHDR going low
(excluding deadtime)
V(BOOTLO) = GND, TJ = 125°C
,
See Notes 2 and 3
V(BOOT)= 8 V 100 ns
tPHL
HIGHDR going low
(excluding deadtime)
See Notes 2 and 3
V(BOOT)= 14 V 80
ns
NOTES: 2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
low-side driver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(VDRV) = 4 V,
V(LOWDR) = 0.5 V (src) 1 1.6
V(VDRV) = 4 V,
TJ = 25°C, See Note 2 V(LOWDR) = 4 V (sink) 2 2.4
Peak output current
V(VDRV) = 8 V,
V(HIGHDR) = 0.5 V (src) 2 2.4
A
Peak output current
V(VDRV) = 8 V,
TJ = 25°C, See Note 2 V(HIGHDR) = 8 V (sink) 2 3.3 A
V(VDRV) = 14 V (src),
V(HIGHDR) = 0.5 V (src) 2 3.9
V(VDRV) = 14 V (src),
TJ = 25°C, See Note 2 V(HIGHDR) = 14 V (sink) 2 4.4
V(VDRV) = 4.5 V,
V(LOWDR) = 4 V (src) 30
V(VDRV) = 4.5 V,
TJ = 25°CV(LOWDR) = 0.5 V (sink) 8
ro
Output resistance
V(VDRV) = 7.5 V,
V(LOWDR) = 7 V (src) 25
Ω
roOutput resistance
V(VDRV) = 7.5 V,
TJ = 25°CV(LOWDR) = 0.5 V (sink) 7Ω
V(VDRV)= 11.5 V,
V(LOWDR) = 11 V (src) 22
V(VDRV)= 11.5 V,
TJ = 25°CV(LOWDR) = 0.5 V (sink) 6
LOWDR-to-PGND resistor 250 kΩ
CL = 3.3 nF, TJ = 125°C,
V(VDRV) = 4 V 60
CL = 3.3 nF, TJ = 125°C,
See Note 2
V(VDRV) = 8 V 50
tr/tf
Rise and fall time
See Note 2
V(VDRV) = 14 V 40
ns
tr/tfRise and fall time
CL = 10 nF, TJ = 125°C,
V(VDRV) = 4 V 110 ns
CL = 10 nF, TJ = 125°C,
See Note 2
V(VDRV) = 8 V 100
See Note 2
V(VDRV) = 14 V 80
Propagation delay time, LOWDR
TJ = 125°C,
V(VDRV) = 4 V 110 ns
t
PLH
Propagation delay time, LOWDR
going high (excluding deadtime)
TJ = 125°C,
See Notes 2 and 3
V(VDRV) = 8 V 90 ns
tPLH
going high (excluding deadtime)
See Notes 2 and 3
V(VDRV) = 14 V 80 ns
NOTES: 2: Ensured by design, not production tested.
3: The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
VCC undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold voltage 10.3 V
Stop threshold voltage 7.5 V
Vhys Hysteresis voltage 1 1.5 V
tpd Propagation delay time 50-mV overdrive, See Note 2 300 1000 ns
tdFalling-edge delay time See Note 2 2 5 us
NOTE 2: Ensured by design, not production tested.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
digital control (IN, ENABLE, SYNC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH
High-level input voltage
IN Over full VCC range 2 V
VIH High-level input voltage ENABLE, SYNC Over full VCC range 2.2 V
VIL
Low-level input voltage
IN Over full VCC range 1 V
VIL Low-level input voltage ENABLE, SYNC Over full VCC range 1 V
ENABLE propagation delay time See Note 2 2 7 µs
NOTE 2: Ensured by design, not production tested.
thermal shutdown
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Thermal shutdown See Note 2 155 170 185 _C
tdFalling edge delay time See Note 2 10 20 µs
NOTE 2: Ensured by design, not production tested.
drive regulator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Recommended output voltage 4 14 V
VOOutput voltage VCC = 10 V to 15 V, IO = 5 mA to 150 mA −2 2 %nom
Vref Reference voltage VCC = 10 V to 15 V 1.235 V
Dropout voltage VCC = 10 V, IO = 150 mA
See Note 2 1000 1100 mV
Line regulation VCC = 10 V to 15 V, IO = 5 mA 0.2 %/V
Load regulation VCC = 10 V, IO = 5 mA to 150 mA 2 %
Current limit VCC = 8 V 0.5 0.6 A
PWRRDY saturation voltage IO = 5 mA 0.8 V
Ilkg Leakage current VI(PWRRDY) = 4.5 V 1µA
drive regulator undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold voltage See Note 2 85 %Vref
Stop threshold voltage See Note 2 80 %Vref
Vhys Hysteresis voltage See Note 2 2.5 5 %Vref
tpd Propagation delay time 50-mV overdrive, See Note 2 300 1000 ns
Falling-edge delay time See Note 2 2 5 µs
Power on reset time See Note 2 100 1000 µs
NOTE 2: Ensured by design, not production tested.
SLVS367A − MARCH 2001 − REVISED JUNE 2001
10 www.ti.com
PARAMETER MEASUREMENT INFORMATION
trtf
90% 90%
10%
10%
50% 50%
50% 50%
VI
(EN, SYNC, IN)
VO
(LOWDRV, HIGHDR)
ton toff
50% 50%
50% 50%
ton toff
VI
(EN, SYNC, IN)
VO
(LOWDRV, HIGHDR)
VO
(LOWDRV, HIGHDR)
Rising Edge Falling Edge
High-Side and Low-Side Drive
Figure 1. Voltage Waveforms
TYPICAL CHARACTERISTICS
Figure 2
046 810
10
RISE TIME
vs
INPUT VOLTAGE (VDRV)
13
VI − Input Voltage (VDRV) − V
50
60
70
20
30
40
tr− Rise Time − ns
5791112
CL = 3.3 nF
TJ = 25°C
1514
High Side
Low Side
Figure 3
FALL TIME
vs
INPUT VOLTAGE (VDRV)
tf− Fall Time − ns
046 810
5
13
VI − Input Voltage (VDRV) − V
25
30
35
10
15
20
5791112 1514
CL = 3.3 nF
TJ = 25°C
High Side
Low Side
SLVS367A − MARCH 2001 − REVISED JUNE 2001
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TYPICAL CHARACTERISTICS
Figure 4
RISE TIME
vs
JUNCTION TEMPERATURE
tr− Rise Time − ns
TJ − Junction Temperature − °C
00 50 100
10
125
50
60
20
30
40
25 75−50 −25
VDRV = 8 V
CL = 3.3 nF
High Side
Low Side
Figure 5
FALL TIME
vs
JUNCTION TEMPERATURE
tf− Fall Time − ns
TJ − Junction Temperature − °C
00 50 100
5
125
25
30
35
10
15
20
25 75
−50 −25
VDRV = 8 V
CL = 3.3 nF
High Side
Low Side
Figure 6
046 810
20
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
INPUT VOLTAGE (VDRV)
13
VI − Input Voltage (VDRV) − V
100
120
140
40
60
80
5791112
200
160
180
tPLH − Low-to-High Propagation Delay Time − ns
1514
CL = 3.3 nF
TJ = 25°C
Low Side
High Side
Figure 7
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
INPUT VOLTAGE (VDRV)
VI − Input Voltage (VDRV) − V
046 810
20
13
100
120
140
40
60
80
5791112
tPHL − High-to-Low Propagation Delay Time − ns
CL = 3.3 nF
TJ = 25°C
1514
High Side
Low Side
SLVS367A − MARCH 2001 − REVISED JUNE 2001
12 www.ti.com
TYPICAL CHARACTERISTICS
Figure 8
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
00 50 100
20
125
100
120
140
40
60
80
25 75
160
180
tPLH − Low-to-High Propagation Delay Time − ns
−25−50
VDRV = 8 V
CL = 3.3 nF
High Side
Low Side
Figure 9
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
00 50 100
10
125
50
60
70
20
30
40
25 75
80
tPHL − High-to-Low Propagation Delay Time − ns
−25−50
VDRV = 8 V
CL = 3.3 nF
High Side
Low Side
Figure 10
DRIVER-OUTPUT RISE TIME
vs
LOAD CAPACITANCE
CL − Load Capacitance − nF
tr− Driver-Output Rise Time − ns
100
10
1
1000
0.01 1 10 1000.1
VDRV = 8 V
TJ = 25°C
Low Side
High Side
Figure 11
DRIVER-OUTPUT FALL TIME
vs
LOAD CAPACITANCE
CL − Load Capacitance − nF
tf− Driver-Output Fall Time − ns
100
10
1
1000
0.01 1 10 1000.1
VDRV = 8 V
TJ = 25°C
Low Side
High Side
SLVS367A − MARCH 2001 − REVISED JUNE 2001
13
www.ti.com
TYPICAL CHARACTERISTICS
Figure 12
SUPPLY CURRENT
vs
INPUT VOLTAGE (VDRV)
VI − Input Voltage (VDRV) − V
0
1
10
7
8
9
2
3
5
CC
I Supply Current − mA−
4
6
46 810 135791112 1514
CL = 50 pF
TJ = 25°C
50 kHz
25 kHz
300 kHz
200 kHz
100 kHz 500 kHz
Figure 13
SUPPLY CURRENT
vs
INPUT VOLTAGE (VDRV)
VI − Input Voltage (VDRV) − V
0
2.5
25
17.5
20
22.5
5
7.5
12.5
CC
I Supply Current − mA−
10
15
46 810 135791112 1514
CL = 50 pF
TJ = 25°C
1 MHz
2 MHz
Figure 14
PEAK SOURCE CURRENT
vs
INPUT VOLTAGE (VDRV)
Peak Source Current − A
VI − Input Voltage (VDRV) − V
0
0.5
4
2.5
3
3.5
1
1.5
2
4.5
46 810 135791112 1514
TJ = 25°C
High Side
Low Side
Figure 15
Peak Sink Current − A
PEAK SINK CURRENT
vs
INPUT VOLTAGE (VDRV)
VI − Input Voltage (VDRV) − V
0
0.5
4
2.5
3
3.5
1
1.5
2
4.5
46 810 135791112 1514
5
TJ = 25°C
High Side
Low Side
SLVS367A − MARCH 2001 − REVISED JUNE 2001
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 16
START/STOP VCC UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
8.2 0 50 100
8.4
125
9.2
9.4
9.6
8.6
8.8
9
25 75
9.8
10
Start/Stop
−25−50
Start
Stop
VCCUndervoltage Lockout − V
Figure 17
VO − Output Voltage − V
0
200
400
600
1000
800
1200
0 0.5 1 1.5
0.25 0.75 1.25 1.75 2
BOOTSTRAP SCHOTTKY DIODE
INPUT CURRENT
vs
OUTPUT VOLTAGE
I
I − Bootstrap Schottky Diode Input Current − mA
TJ = 25°C
Figure 18
046 810
20
DELAY TIME (DEAD TIME)
vs
INPUT VOLTAGE (VDRV)
13
VI − Input Voltage (VDRV) − V
100
120
140
40
60
80
5791112
200
160
180
Dealy Time (Dead Time) − ns
1514
50 pF
20 pF
10 pF
5 pF
1 pF
0 pF
TJ = 25°C
Figure 19
DELAY TIME
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
00 50 100
20
125
100
120
140
40
60
80
25 75
160
180
Delay Time − ns
−25−50
200
50 pF
5 pF
1 pF
0 pF
50 pF
20 pF
10 pF
VDRV = 8 V
VDRV
ADJ
R2
R1
SLVS367A − MARCH 2001 − REVISED JUNE 2001
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 20
VDRV LINE REGULATION
VCC − Supply Voltage − V
8.055
8.056
8.06
8.061
8.062
8.057
8.058
8.059
10 13
11 12 1514
CL(VDRV) = 1 µF
TJ = 25°C
− Output Voltage − V
VO
Figure 21
VDRV LOAD REGULATION
II − Input Current − mA
8.085
8.09
8.11
8.115
8.095
8.1
8.105
−10 50
10 30 9070 110 150130
CL(VDRV) = 1 µF
TJ = 25°C
− Output Voltage − V
VO
APPLICATION INFORMATION
Figure 22 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001ACD
pulse-width-modulation (PWM) controller and a TPS2838 driver. The converter operates over an input range from
4.5 V to 1 2 V and has a 3.3-V output. The circuit can supply 3-A continuous load. The converter achieves an ef ficiency
of 94% for VIN = 5 V, IL=1 A, and 93% for VIN = 5 V, IL = 3 A.
R1
(kΩ)R2
(kΩ)
VDRV
Voltage
(V)
30 67 4
30 91 5
30 165 8
30 261 12
30 322 14.5
To set the regulator voltage (TPS2838/39) use the following equation:
R2+ǒR1
1.235 VDRVǓ*R1
SLVS367A − MARCH 2001 − REVISED JUNE 2001
16 www.ti.com
VIN
GND
ENABLE
PWRRDY
SYNC
BOOT
HIGHDR
BOOTLO
VDRV
LOWDR
NC
PGND
U1
TPS2838
J1
J3 ENABLE
IN
PWRRDY
DELAY
SYNC
ADJ
DT
AGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C2
100 µF++
C4
100 µF
R19
10 kΩ
R20
10 kΩ
R23
10 kΩC6
0.22 µF
Q1
IRF7201
VIN
C3
1 µF
Vphase
See Note A
L2
10 µH
L1
10 µH
BOOST
5 V
3.3 V LOGIC
J3
LOGIC GND
ANALOG GND
3.3 V ANALOG
3.3 V
+C15
10 µF
C13
10 µF
+
C12
220 µF
R2
4.7 Ω
R4
4.7 Ω
C8
1000 pF
C28
1 µF
C1
1 µF
R22
165 kΩ
R21
30 kΩ
R24
10 Ω
VCC
FB
COMP
DTC
GND
OUT
SCP
1
2
5
8
6
3
4
RT 7
C7
0.1 µF
U2
TL5001ACD
R1
1 kΩ
+C5
1 µFR3
13.7 kΩ
fOSC = 400 kHz
R18
0 Ω
R5
27.4 kΩ
C9
0.018 µFR6
3.01 kΩ
R7
1 kΩ
R9
2.32 kΩ
C14
0.018 µF
R8
100 Ω
C11
390 pF
4.5 V − 8 V
1
2
1
2
3
C10
0.1 µF
1
2
3
4
5
6
Vfb
See Note B
NOTES: A. Node Vphase generates RFI. Make this as contained as possible.
B. Node Vphase is very sensitive. Make this as short as possible.
Figure 22. 3.3-V 3-A Synchronous-Buck Converter Circuit
SLVS367A − MARCH 2001 − REVISED JUNE 2001
17
www.ti.com
APPLICATION INFORMATION
Great care should be taken when laying out the PC board. The power-processing section is the most critical
and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across VCC and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very
sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply
will be relatively free of noise.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2838PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2838PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2839PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2839PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2848PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2848PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2849PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2849PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2008
Addendum-Page 1
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