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Micrel, Inc.
KSZ8081MLX
Features (Continued)
• Loopback modes for di agnostics
• Single 3.3V power supply with VDD I/O opt i ons for 1.8V,
2.5V, or 3.3V
• Built-in 1.2V regulato r f or core
• Available in 48-pin 7mm x 7mm LQFP package
Applications
• Game consoles
• IP phones
• IP set-top boxes
• IP TVs
• LOM
• Printers
Ordering I nfor m ati on
For the device marking (second column in the following table), the fifth character of line three indicates whether the device
has gold wire bondin g or silver wire bonding, as fol l ows:
• Gold wire bonding: The L etter “S” is not pre sent as the fifth character of line 3.
• Silver wire bonding: The Letter “S” is present as the fifth char act er of line 3.
For line three, the presence or lack of the letter “S” is preceded by YYWW, indicating the last two digits of the year and the
two digits work week for the chip date code, and is followed by xxx, i ndi cati ng t he chip revision and a ss embly site.
Ordering Part Nu mber Device Marking Temperature
Range
Wire
Bonding
Description
KSZ8081MLXCA KSZ8081
MLXCA
YYWWxxx 0°C to 70°C Gold MII, Comm er cial Temperatur e, Gold Wire Bonding,
48-Pin LQFP, Pb-Free
SPNZ801136(1) KSZ8081
MLXCA
YYWWSxxx 0°C t o 70° C Silver MII , Commercial T emperature, Silver Wire Bonding,
48-Pin LQFP, Pb-Free
KSZ8081MLXIA(1) KSZ8081
MLXIA
YYWWxxx
−40°C to 85°C Gold MII, Industrial Temperature, Gold Wir e B onding,
48-Pin LQFP, Pb-Free
SPNY801136(1) KSZ8081
MLXIA
YYWWSxxx
−40°C to 85°C Silver MII, Industrial Temperature, Silver W ire Bonding,
48-Pin LQFP, Pb-Free
KSZ8081MLX-EVAL KSZ8081MLX Ev al uation Board
(Mounted with KSZ 8081M L X device in c ommercial
temperature)
Note:
1. Contact factory for availability.
December 10, 2014 2 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Revision Hi stor y
Date Summary of Changes Revision
11/5/12 Initial release o f new product datasheet. 1.0
2/6/14
Removed copper-wire bonding part numbers from Ordering Information.
Added note for TXC (Pin 33) and Regist er 16h, Bit [15] r egarding a Reserved Factor y Mode.
Removed TXC and RXC clock c onnections for MII Back-to-Back mode. This is a datasheet correction.
There is no chang e to the silicon.
Added series resistance and load capacit ance for the crystal selection criteria.
1.1
11/25/14 Added silv er-wire bonding part numbers to Order ing Information.
Updated Ordering Information to include Ordering Part Number and Device Marking. 1.2
December 10, 2014 3 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration ..................................................................................................................................................................... 8
Pin Description ........................................................................................................................................................................ 9
Strapping Opti ons ................................................................................................................................................................. 12
Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 14
100Base-TX Transmit ........................................................................................................................................................ 14
100Base-TX Receive ......................................................................................................................................................... 14
Scrambler/De-Scrambler ( 100Base-TX Only) ................................................................................................................... 14
10Base-T Transmit ............................................................................................................................................................ 14
10Base-T Receive ............................................................................................................................................................. 15
SQE and Jabber Fu ncti on (10Base-T Only) ...................................................................................................................... 15
PLL Clock Synthesizer ...................................................................................................................................................... 15
Auto-Negotiation ................................................................................................................................................................ 15
MII Interface .......................................................................................................................................................................... 17
MII Signal Definition ........................................................................................................................................................... 17
Transmit Clock (TXC) .................................................................................................................................................... 17
Transmit Enable (TXEN) ................................................................................................................................................ 17
Transmit Data[3:0] (TXD[3:0]) ........................................................................................................................................ 18
Receive Clock (RXC) ..................................................................................................................................................... 18
Receive Data V al i d (RXDV) ........................................................................................................................................... 18
Receive Data[3:0] (RXD[3:0]) ........................................................................................................................................ 18
Receive Err or (RXER) .................................................................................................................................................... 18
Carrier Sense (CRS) ...................................................................................................................................................... 18
Collision (COL) ............................................................................................................................................................... 18
MII Signal Diagram ............................................................................................................................................................ 18
Back-to-Back Mode – 100Mbps Coppe r Repeater ............................................................................................................... 20
MII Back-to-Back Mode ..................................................................................................................................................... 20
MII Management (MIIM) Interf ace ......................................................................................................................................... 21
Interrupt (INTRP) ................................................................................................................................................................... 21
HP Auto MDI/MDI-X .............................................................................................................................................................. 21
Straight Cable .................................................................................................................................................................... 22
Crossover Cable ................................................................................................................................................................ 22
Loopback Mode ..................................................................................................................................................................... 23
Local (Digital) Loopback .................................................................................................................................................... 23
Remote (Analog) Loopback ............................................................................................................................................... 24
LinkMD® Cable Diagnostic .................................................................................................................................................... 26
NAND Tree Support .............................................................................................................................................................. 26
NAND Tree I/O Testing ..................................................................................................................................................... 27
December 10, 2014 4 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Power Management .............................................................................................................................................................. 28
Power-Saving Mode .......................................................................................................................................................... 28
Energy-Detect Power-Down Mode .................................................................................................................................... 28
Power-Down Mode ............................................................................................................................................................ 28
Slow-Oscillator Mode ......................................................................................................................................................... 28
Reference Circuit for P ower and Ground Connections ......................................................................................................... 29
Typical Current/P ower Consumptio n .................................................................................................................................... 30
Register Map ......................................................................................................................................................................... 32
Register Description .............................................................................................................................................................. 33
Absolute Maximum Ratings .................................................................................................................................................. 43
Operating Rat ings ................................................................................................................................................................. 43
Electrical Characteristics ....................................................................................................................................................... 43
Timing Diagrams ................................................................................................................................................................... 45
MII SQE Timing (10Base-T) .............................................................................................................................................. 45
MII Transmit Timing (10Base-T) ........................................................................................................................................ 46
MII Receive Timing (10Base-T) ......................................................................................................................................... 47
MII Transmit Timi ng (100Base-TX) ................................................................................................................................... 48
MII Receive Timing (100Base-TX) .................................................................................................................................... 49
Auto-Negotiation Timing .................................................................................................................................................... 50
MDC/MDIO Timing ............................................................................................................................................................ 51
Power-Up/Reset Timing .................................................................................................................................................... 52
Reset Circuit .......................................................................................................................................................................... 53
Reference Circuits − LED Strap-In Pins ................................................................................................................................ 54
Reference Clock − Connection and Sele ct i on ...................................................................................................................... 55
Magnetic − Connection and Selection .................................................................................................................................. 56
Package Information and Recommend ed Landing Pattern .................................................................................................. 58
December 10, 2014 5 Revision 1.2
Micrel, Inc.
KSZ8081MLX
List of Figures
Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 16
Figure 2. KSZ8081MLX MII Interface ................................................................................................................................. 19
Figure 3. KSZ8081MLX to KSZ8081MLX Back -to-Back Copper Repeater ........................................................................ 20
Figure 4. Typical Strai ght Cable Connection ...................................................................................................................... 22
Figure 5. Typical Cros sover Cable Connection .................................................................................................................. 23
Figure 6. Local (Digital) Loopback ...................................................................................................................................... 24
Figure 7. Remote (Analo g) Loopback ................................................................................................................................. 25
Figure 8. KSZ8081MLX Power and Ground Conn ect ions .................................................................................................. 29
Figure 9. MII SQE T im i ng (10B ase-T) ................................................................................................................................ 45
Figure 10. MII Trans m it Timing (10Base-T) .......................................................................................................................... 46
Figure 11. MII Receive T iming (10Base-T) ........................................................................................................................... 47
Figure 12. MII Trans m it Timing (100Base-TX) ...................................................................................................................... 48
Figure 13. MII Receive T iming (100Base-TX) ....................................................................................................................... 49
Figure 14. Auto-Negotiation Fast Link P ulse (FLP) Timing .................................................................................................. 50
Figure 15. MDC/MDIO Timing ............................................................................................................................................... 51
Figure 16. Power-Up/ Reset Timing ....................................................................................................................................... 52
Figure 17. Recommended Reset Circuit ............................................................................................................................... 53
Figure 18. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 53
Figure 19. Reference Circuits for LED St rapping Pins ......................................................................................................... 54
Figure 20. 25MHz Crystal/Oscill ator Ref eren ce Clock Conne ction ...................................................................................... 55
Figure 21. Typical Ma gnetic Interface Ci rcuit ........................................................................................................................ 56
December 10, 2014 6 Revision 1.2
Micrel, Inc.
KSZ8081MLX
List of Tables
Table 1. MII Signal Definition .............................................................................................................................................. 17
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) ........................................... 20
Table 3. MII Management Frame Forma t for the KSZ8081MLX ........................................................................................ 21
Table 4. MDI/MDI-X Pin Definition ...................................................................................................................................... 22
Table 5. NAND Tree Test Pin Order for KSZ8081MLX ...................................................................................................... 27
Table 6. KSZ8081 Po wer Pin Description ........................................................................................................................... 29
Table 7. Typical Current/Power Consum ption (VDDA_3.3 = 3.3V , VDDIO = 3.3V) ........................................................... 30
Table 8. Typical Current/Power Consum ption (VDDA_3.3 = 3.3V , VDDIO = 2.5V) ........................................................... 30
Table 9. Typical Current/Power Consum ption (VDDA_3.3 = 3.3V , VDDIO = 1.8V) ........................................................... 31
Table 10. MII SQE T i mi ng (10Base-T) Parameters .............................................................................................................. 45
Table 11. MII Transmit Timing (10Base-T) Parameters ....................................................................................................... 46
Table 12. MII Receive Ti m ing (10Base-T) P arameters ........................................................................................................ 47
Table 13. MII Transmit Timing (100Ba se-TX) Parameters ................................................................................................... 48
Table 14. MII Receive Ti m ing (100Base-TX ) Parameters .................................................................................................... 49
Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 50
Table 16. MDC/MDI O T im ing Parameters ............................................................................................................................ 51
Table 17. Power-Up/Reset Timing Para m eters .................................................................................................................... 52
Table 18. 25MHz Cry stal / Reference Clock Sel ecti on Criteria ............................................................................................ 55
Table 19. Magnetics S el ection Criteria ................................................................................................................................. 57
Table 20. Compatibl e Single-Port 10/100 Magnetics ........................................................................................................... 57
December 10, 2014 7 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Pin Configuration
48-Pin 7mm × 7mm LQFP
December 10, 2014 8 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Pin Description
Pin Number
Pin Name
Type
(2)
Pin Function
1 GND GND Ground.
2 GND GND Ground.
3 GND GND Ground.
4 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8081MLX). Decouple with 2. 2µF and 0.1µF
capacitors to ground, and join with Pin 31 by po wer t race or plane.
5 NC − No Connect. This pin is not bonded and can be left floating.
6 NC − No Connect. This pin is not bonded and can be left floating.
7 VDDA_3.3 P 3.3V Analog VDD.
8 NC − No Connect. This pin is not bonded and can be left floating.
9 RXM I/O Physical Receive or Transmit Signal (− differential).
10 RXP I/O Physical Receive or Transmit Signal (+ dif ferential).
11 TXM I/O Physical Transmit or Receive Signal (− differential).
12 TXP I/O Physical Transmit or Receive Signal (+ dif ferential).
13 GND Gnd Ground.
14 XO O Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or
external clock source is used.
15 XI I Crystal / Oscillator / External Clock Input (25MHz ±50ppm).
16 REXT I Set PHY Transmit Out put Current. Connect a 6.49kΩ resistor to ground on this pin.
17 GND GND Ground.
18 MDIO Ipu/Opu Manageme nt Interface (M II) Data I/O. Thi s pin h as a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resist or.
19 MDC Ipu Management Interface (MII ) C lock Input. This clock pin is synchronous to the MDIO
data pin.
20 RXD3/
PHYAD0 Ipu/O MII Mode: MII Receive Data Output[3]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as PHYADD R[0] at the de-
assertion of reset. See the Strapping Options section for details.
21 RXD2/
PHYAD1 Ipd/O MII Mode: MII Receive Data Output[2](3)
Config. Mode: The pull-up/pull-down value is latched as PHYADD R[1] at the de-
assertion of reset. See the Strapping Options section for details.
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics(9) for value).
Ipd = Input with internal pull-down (see Electrical Characteristics(9) for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics(9) for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics(9) for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics(9) for value) and output with internal pull-up (see Electrical Characteristics(9) for
value).
3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC.
December 10, 2014 9 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Pin Description (Continued)
Pin Number
Pin Name
Type
(2)
Pin Function
22 RXD1/
PHYAD2 Ipd/O MII Mode: MII Receive Data Output[1](3).
Config. Mode: The pull-up/pull-down value is latched as PHYAD DR [2] at the de-
assertion of reset. See the Strapping Options section for details.
23 RXD0/
DUPLEX Ipu/O MII Mode: MII Receive Data Output[0](3)
Config. Mode: The pull-up/pull-down value is l atched as DUPLEX at the de-assertion
of reset. See t he Strapping Options section for details.
24 GND Gnd Ground.
25 VDDIO P 3.3V, 2.5V, or 1.8V Digital VDD.
26 NC - No Connect. Thi s pin is not bonded and can be left floating.
27 RXDV/
CONFIG2 Ipd/O MII Mode: MII Receive Data Valid Output.
Config. Mode: The pull-up/pull-down value is l atched as CONFI G2 at the de-assertion
of reset. See t he Strapping Options section for details.
28 RXC/
B-CAST_OFF Ipd/O MII Mode: MII Receive Clock Output.
Config. Mode: The pull-up/pull-down value is l atched as B-CAST_OFF at the de-
assertion of reset. See the Strapping Options section for details.
29 RXER/
ISO Ipd/O MII Mode: MII Receive Error output
Config. Mode: The pull-up/pull-down value is l atched as ISOLATE at the de-assertion
of reset See the Strapping Options section for details.
30 GND Gnd Ground.
31 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8081MLX). Decouple with 0.1µF capac i tor to
ground, and join with Pin 4 by power trace or plane.
32 INTRP/
NAND_Tree# Ipu/Opu
Interrupt Output: Progr ammable interr upt output.
This pin has a weak pull-up, is open drain, and requires an external 1.0kΩ pull-up
resistor.
Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset. See the Strapping Options section for details.
33 TXC Ipd/O MII Mode: MII Transmit Clock Output.
At the de-asser tion of reset, thi s pi n needs to latch in a pull-down value for normal
operation. If MAC side pulls this pin high, see Register 16h, Bit [15] f or solution.
34 TXEN I MII Mode: MII Transmit Enabl e input.
December 10, 2014 10 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Pin Description (Continued)
Pin Number
Pin Name
Type
(2)
Pin Function
35 TXD0 I MII Mode: MII Transm it Data Input[0](4)
36 TXD1 I MII Mode: MII Transm it Data Input[1](4)
37 GND GND Ground.
38 TXD2 I MII Mode: MII Transm it Data Input[2]
(
4
)
39 TXD3 I MII Mode: MII Transmit Data Input[3]
(
4
)
40 COL/
CONFIG0 Ipd/O MII Mode: MII Collision Detect output
Config. Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset. See t he Strapping Options section for details.
41 CRS/
CONFIG1 Ipd/O MII Mode: MII Carrier Sense Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset. See t he Strapping Options section for details.
42 LED0/
NWAYEN Ipu/O
LED Output: Programmable L ED0 Output
Config. Mode: Latched as auto-negotiation e nable (Register 0h, Bit [12]) at the de-
assertion of reset. See the Strapping Options section for details.
The LED0 pin is programmable using Register 1Fh Bits [5:4], and is defined as
follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED Mode = [10], [11] Reserved
Note:
4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC.
December 10, 2014 11 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Pin Function
43 LED1/
SPEED Ipu/O
LED Output: Pr ogr ammable LED1 output
Config. Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertio n of reset.
See the Strapping Options s ection for details.
The LED1 pin is programmable using Register 1Fh Bits [5:4], and is defined as
follows:
LED Mode = [00]
Speed
Pin State
LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity
Pin State
LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11]
Reserved
44 NC - No Connect. This pin is not b onded and can be left floating.
45 NC - No Connect. This pin is not b onded and can be left floating.
46 NC - No Connect. This pin is not b onded and can be left floating.
47 RST# Ipu Chip Reset (ac tive low)
48 NC - No Connect. This pin is not b onded and can be left floating.
Strapping Options
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure the intended values are strapped-in correctly.
Pin Number
Pin Name
Type
(5)
Pin Function
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY address i s l atched at de-assert ion of reset and is configurable to any value
from 0 to 7. The default PHY address is 00001. PHY address 00000 is en abled only if
the B-CAST_OFF strapping pin is pulled high. PHY address Bits [4:3] are set to 00 by
default.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
000 MII (default)
110 MII back-to-back
001 – 101, 111 Reserved – not us ed
Note:
5. Ipu/O = Input with internal pull-up (see Electrical Characteristics(9) for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics(9) for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics(9) for value) and output with internal pull-up (see Electrical Characteristics(9) for
value).
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Strapping Options (Continued)
Pin Number
Pin Name
Type
(5)
Pin Function
29 ISO Ipd/O
Isolate Mode:
Pull-up = Enabl e
Pull-down (default) = Disable
At the de-asser tion of reset, thi s pi n v alue is latched into Register 0h, Bit [10].
43 SPEED Ipu/O
Speed Mode:
Pull-up (defaul t) = 100Mbps
Pull-down = 10M bps
At the de-asser tion of reset, this pin value is latched into Register 0h, Bit [ 13] as the
speed select , and also is latched into Register 4h (auto-negotiation advertisement) as
the speed capability support.
23 DUPLEX Ipu/O
Duplex Mode:
Pull-up (defaul t) = Half-duplex
Pull-down = Full-duplex
At the de-asser tion of reset, this pin value is latched into Register 0h, Bit [8].
42 NWAYEN Ipu/O
Nway Auto-Negot iation Enable:
Pull-up (defaul t) = Enable auto-negotiation
Pull-down = Di s able auto-negotiation
At the de-asser tion of reset, this pin value is latched into Register 0h, Bit [12].
28 B-CAST_OFF Ipd/O
Broadcast O ff – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-asser tion of reset, thi s pi n v alue is latched by the chip.
32 NAND_Tree# Ipu/Opu
NAND Tree Mode:
Pull-up (defaul t) = Disable
Pull-down = En able
At the de-asser tion of reset, this pin value is latched by the chip.
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Functional Description: 10B ase-T/100Base-TX Transceiver
The KSZ8081MLX is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs an d by integrating the regul ator to supply the 1. 2V core.
On the copper media side, the KSZ8081MLX supports 10Base-T and 100Base-TX for transmission and reception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8081MLX offers the Media Independent Interface (MII) for direct connection with MII
compliant Ethernet MAC processors and switches.
The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status
registers. Additional l y, an interrupt pin el i mi nates the need for the processor to poll for P HY status change.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT 3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data
is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by
an external 6.49kΩ 1% resistor for the 1:1 transformer rati o.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-p arallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This
is an ongoing process and self-adjusts against environment al changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold i s also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally,
the NRZ serial data is converted to MII format and provided a s t he input data to the MA C.
Scrambler/De-Scrambler (100Base-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with typical amplitude of 2.5V
peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when driven
by an all-ones Manchester-encoded signal.
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10Base-T Recei ve
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8081MLX decodes a data frame. The receive clock is kept active during idle
periods between data receptions.
SQE and Jabber Function (10Base -T Only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to
test the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base-T
transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T
transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8081MLX generates all internal clocks and all external c locks for system timing from an external 25MHz crystal,
oscillator, or ref erence clock.
Auto-Negotiation
The KSZ8081MLX co nforms to the auto-negotiation protocol, defined in Clau se 28 of the IEEE 802.3 Specification.
Auto-negotiation allo ws unshielded twisted pair (UTP) li nk partners to select t he highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is s el ected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8081MLX link partner is forced to bypass auto-negotiation, then the
KSZ8081MLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8081MLX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation
advertisemen t protocol.
Auto-negotiation is enabl ed by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex is
set by Register 0h, Bit [8].
The auto-negotiation link-up pro cess is shown in Figure 1.
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Figure 1. Auto-Negotiation Flow Chart
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MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the fol l owing key character i sti cs:
• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10Mbps and 100Mbps d at a rat es are supported at both half- and full -duplex.
• Data transmission and reception are independent and belong to separate sign al groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KS Z8081MLX is configured to MII mode after it is powered up or hardwa re reset with the following:
• A 25MHz crystal connected to XI, XO (Pins 15, 14), or an external 25MHz clo ck source (oscillat or ) connected to XI.
• The CONFIG[2:0] strapping pins (Pins 27, 41, 40) set to 000 (default setting).
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IE EE 802.3 Specification for detailed informat i on.
Table 1. MII Signal Definition
MII Signal Name Direction
(with respect to P H Y ,
KSZ8081MLX signal)
Direction
(with resp ect to MAC) Description
TXC Output Input Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN Input Output Transmit E nable
TXD[3:0] Input Output Transmit Dat a[3:0]
RXC Output Input Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV Output Input Receive D ata Valid
RXD[3:0] Output Input Receive Data[3:0]
RXER Output Input, or (not required) Receive Err or
CRS Output Input Carrier Sense
COL Output Input Collision Detection
Transmit Clock (TXC)
TXC is sourced by t he PHY. It is a continuous cl ock that provides the tim i ng ref erence for TXEN and TX D[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps op erat i on.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated
before the first T XC following the final nibble of a frame.
TXEN transitions sy nchronously with respect to TXC.
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Transmit Data [3:0 ] (TXD [ 3:0 ])
When TXEN is asserted, TXD[3:0] are the data nibbles accepted by the PHY for transmission. TXD[3:0] is 00 to indicate
idle when TXEN is de-asserted.
TXD[3:0] transitions synchronously with respect to TX C.
Receive Clock (RX C)
RXC provides the tim i ng reference for RXDV, RX D[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference
clock when the l ine is idl e or the link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10M bps operation and 25MHz for 100Mbps operation.
Receive Data Val id (RXDV)
RXDV is driven by the PHY to indicate that the P HY i s pre senting recovered and decoded nibbles on RXD[3:0].
In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of t he frame.
In 100Mbps mode, RXDV is asserted from t he first nibble of the pream ble t o t he last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data[3 :0 ] (RX D[3:0 ])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data fro m the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can
detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC.
Carrier Sense (C RS )
CRS is asserted and de-asserted as follows:
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-asserted
when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE
symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has o ccurred during it s t ransmission to the PHY.
COL transitions asy nchronously with res pect to TXC and RXC.
MII Signal Diagram
The KSZ8081MLX MI I pin connections to the MAC are shown in Fi gure 2.
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Figure 2. KSZ8081MLX MII Interface
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KSZ8081MLX
Back-to-Back Mode – 100Mbps Copp e r Repeat e r
Two KSZ8081MLX devices can be con nect ed back-to-back to form a 100Base-TX to 100Base-TX copper repeat er.
Figure 3. KSZ8081MLX to KSZ8081M LX Back-to-Back Copper Repeater
MII Back-to-Back Mode
In MII back-to-back mode, a KSZ8081MLX interfaces with another KSZ8081MLX to provide a complete 100Mbps copper
repeater solution.
The KSZ8081MLX devi ces are configured to MII back-to-bac k m ode after power-up or reset with the following:
Strapping pin CONFIG[2:0] (Pins 27, 41, 40) set to 11 0
A common 25MHz reference clock connected to XI (Pin 15) of both KSZ8081MLX devices
MII signals conne cted as shown in Table 2.
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8081MLX (100Base-TX copper)
[Device 1]
KSZ8081MLX (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
RXDV 27 Output TXEN 34 Input
RXD3 20 Output TXD3 39 Input
RXD2 21 Output TXD2 38 Input
RXD1 22 Output TXD1 36 Input
RXD0 23 Output TXD0 35 Input
TXEN 34 Input RXDV 27 Output
TXD3 39 Input RXD3 20 Output
TXD2 38 Input RXD2 21 Output
TXD1 36 Input RXD1 22 Output
TXD0 35 Input RXD0 23 Output
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MII Management (MIIM) Interface
The KSZ8081MLX supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8081MLX. An external device with MIIM capability is used to read the PHY status and/or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the fol lowing:
• A physical connect ion t hat incorporates the clock line (MDC) and t he data line (MDIO).
• A specific protocol that operates across t he physical connection mentioned earlier, which allows the external controller
to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Supported registers [0:8] are standard registers, and their functions are defined in the
IEEE 802.3 Specification. The additional registers are provided for expanded functionality. See the Register Map
section for details.
As the default, the KSZ8081MLX supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is
defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8081MLX device, or write to
multiple KSZ8081M LX devices simulta neously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, Pin
28) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] st rapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MLX device.
Table 3 shows the M I I management frame format for the KSZ 8081MLX.
Table 3. MII Management Frame Format for the KSZ8081MLX
Preamble Start of
Frame Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data
Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Interrupt (INTRP)
INTRP (Pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8081MLX PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and disable
the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which
interrupt conditions have occurred. T he i nt errupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interr upt level to active high or a ct i ve low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status
registers. Additional l y, an interrupt pin el i mi nates the need for the pro cessor to poll the P HY for status change.
HP Auto MDI/M DI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8081MLX and its link partner. This feature allows the KSZ8081MLX to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner and assigns transmit and receive pairs of the KSZ8081MLX accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, Bit [13]. MDI and MDI-X mode is
selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transfo rmer with symmetrical transmit and receiv e data paths is recommended to support Aut o MDI/MDI-X.
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Table 4 shows how the IEEE 802.3 St andard defines MDI and MDI-X.
Table 4. MDI/MDI-X Pin Definition
MDI
MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2 TX− 2 RX−
3 RX+ 3 TX+
6 RX− 6 TX−
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 4 shows a
typical straight cable connection between a NIC card (MDI devi ce) and a switch or hub (MDI-X device).
Figure 4. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 5
shows a typical cro ssover cable connection between two s witches or hubs (two MDI-X devices).
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Figure 5. Typical Crossover Cable Connection
Loopback Mode
The KSZ8081MLX supports the f oll owing loopback operations to verify analog and/or digital data paths.
• Local (digital) l oopback
• Remote (analog) loopbac k
Local (Digital) Loopback
This loopback mode checks the MII transmit and receive data paths between the KSZ8081MLX and the external MAC,
and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data pat h i s shown in Figure 6.
1. The MII MAC transmits frames t o t he K SZ8081MLX.
2. Frames are wrapped around inside the KSZ8081MLX.
3. The KSZ8081MLX transmits frames back to the MII MAC.
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KSZ8081MLX
Figure 6. Local (Digital) Loopback
The following prog ramm ing action and register settings are used for local loopback mode.
For 10/100Mbps loopback,
Set Register 0h,
Bit [14] = 1 // Enable local loopba ck mode
Bit [13] = 0/1 // Select 10Mbps/100Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
Remote (Analog) Loopback
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive
data paths between the KSZ8081MLX and its link partner. It is supported for 100Base-TX full-duplex mode only.
The loopback data pat h i s shown in Figure 7.
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081MLX.
2. Frames are wrapped around inside the KSZ8081MLX.
3. The KSZ8081MLX transmits frames back to the Fast Ethernet (100Base-TX ) PHY link partner.
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Figure 7. Remote (Analog) Loopback
The following prog ramm ing steps and register settings are used for remote loopback mode:
1. Set Register 0h,
Bits [13] = 1 // Select 100Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
Or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner
2. Set Register 1Fh,
Bit [2] = 1 // Enable remote loopbac k mode
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short cir cuits, and impedance mi smatches.
LinkMD works by sending a puls e of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cabl e distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the
PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differenti al pai r f or t esting.
NAND Tree Support
The KSZ8081MLX provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8081MLX digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested NAND
gates.
The NAND tree test pr ocess includes:
• Enabling NAND tre e m ode
• Pulling all NAND tree input pi ns high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 5 lists the NAN D t ree pin order.
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Table 5. NAND Tree Test Pin Ord er for KSZ8081MLX
Pin Number Pin Name NAND Tree Descrip tion
18 MDIO Input
19 MDC Input
20 RXD3 Input
21 RXD2 Input
22 RXD1 Input
23 RXD0 Input
27 RXDV Input
28 RXC Input
29 RXER Input
32 INTRP Input
33 TXC Input
34 TXEN Input
35 TXD0 Input
36 TXD1 Input
38 TXD2 Input
39 TXD3 Input
42 LED0 Input
43 LED1 Input
40 COL Input
41 CRS Output
NAND Tree I/O Testing
Use the following p rocedure to check for faults on the KSZ8081MLX digital I/O pin connections to t he board:
1. Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 32) or software (Register 16h, Bit
[5]).
2. Use board logic to drive all KSZ8081ML X NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MLX NAND tree pin ord er, as follows:
a. Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to
indicate that the first pin is connected properly.
b. Leave the first pi n (MDI O) low.
c. Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to high to
indicate that the se cond pin is connected properly.
d. Leave the first pin (MDI O) and the second pin (MDC) low.
e. Toggle the third pin (RXD3) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to
indicate that the t hi rd pin is connected properly.
f. Continue with this sequence until all KSZ8081MLX NAND tree input pins have been toggled.
Each KSZ8081MLX NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the CRS pin fails to toggle when the KSZ8081MLX input pin toggles from high to low, the
input pin has a fault.
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Power Management
The KSZ8081MLX incorporates a number of power-management modes and features that provide methods to consume
less energy. These are discussed in the following sections.
Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enable d and the cable is disconnected
(no link).
In this mode, the KSZ8081MLX shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabl ed after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is discon nected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8081MLX tran sceiver blocks, except f or the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same low-
power state, with Auto MDI/MDI-X disabled, can wake up when the cable is c onnected betwee n them.
By default, energy-detect power-do wn mode is disabled af t er power-up.
Power-Down Mode
Power-down mode is used to power down the KSZ8081MLX device when it is not in use after power-up. It is enabled by
writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8081MLX disables all internal functions except the MII management interface. The KSZ8081MLX
exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 15) and select the on-chip slow
oscillator when the KSZ8081MLX devic e i s not i n use after power-up. It is enabled by writing a ‘1’ to Register 11h, Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081MLX device in the lowest power
state with all internal functions disabled except the MII management interface. To properly exit this mode and return to
normal PHY operation, use the following prog ramming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-d own mode by writing a ‘0 ’ to Register 0h, Bit [11].
3. Initiate software reset by writi ng a ‘1’ to Register 0h, Bit [15].
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Micrel, Inc.
KSZ8081MLX
Reference Circuit for Power and Ground Connections
The KSZ8081MLX is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground
connections are shown in Figure 8 and Table 6 for 3.3V VDDIO.
Figure 8. KSZ8081MLX Power and Ground Connections
Table 6. KSZ8081 P ower Pin Description
Power Pin
Pin Number
Description
VDD_1.2 4 Con nect with Pin 31 by power trace or plane. Decouple with 2.2µF and 0.1µF capacitors to ground.
VDDA_3.3 7 Connect to board’s 3.3V supply through a ferrite bead. Decoupl e with 22µF and 0.1µF capacitors t o
ground.
VDDIO 25 Connec t to board’s 3.3V s upply for 3.3V VDDIO. Decouple with 22µF and 0.1µF capacitors to
ground.
VDD_1.2 31 Con nect with Pin 4 by po wer trace or plane. Decouple with 0.1µF capacitor t o ground.
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Micrel, Inc.
KSZ8081MLX
Typical Current/Power Consumption
Table 7, Table 8, and Table 9 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O
(VDDIO) power pins and typical values for power consumption by the KSZ8081MLX device for the indicated nominal
operating voltages. These current and power consumption values include the transmit driver current and on-c hip regulator
current for the 1.2V core.
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Transcei ver (3.3V), Dig ital I/Os (3.3V)
Condition 3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Li nk-up (no traff i c ) 34 12 152
100Base-T X Full-duplex @ 100% uti li z ation 34 13 155
10Base-T Link-up (no traffic) 14 11 82.5
10Base-T Full-duplex @ 100% utilization 30 11 135
Power-saving m ode (Reg. 1Fh, Bit [10] = 1) 14 10 79.2
EDPD mode (Reg. 18h, Bit [11] = 0) 10 10 66.0
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 1 0h, Bit [4] = 1) 3.77 1.54 17.5
Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 1.51 13.5
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.36 0.45 5.97
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Transcei ver (3.3V), Dig ital I/Os (2.5V)
Condition 3.3V Transceiver
(VDDA_3.3)
2.5V Digital I/Os
(VDDIO)
Total Chip Power
mA
mA
mW
100Base-TX Li nk-up (no traff i c ) 34 11 140
100Base-T X Full-duplex @ 100% uti li z ation 34 12 142
10Base-T Link-up (no traffic) 15 10 74.5
10Base-T Full-duplex @ 100% utilization 27 10 114
Power-saving m ode (Reg. 1Fh, Bit [10] = 1) 15 10 74.5
EDPD mode (Reg. 18h, Bit [11] = 0) 11 10 61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 1 0h, Bit [4] = 1) 3.55 1.35 15.1
Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 1.34 10.9
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 0.29 4.52
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Micrel, Inc.
KSZ8081MLX
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Transcei ver (3.3V), Dig ital I/Os (1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Li nk-up (no traff i c ) 34 11 132
100Base-T X Full-duplex @ 100% uti li z ation 34 12 134
10Base-T Link-up (no traffic) 15 9.0 65.7
10Base-T Full-duplex @ 100% ut ilization 27 9.0 105
Power-saving m ode (Reg. 1Fh, Bit [10] = 1) 15 9.0 65.7
EDPD mode (Reg. 18h, Bit [11] = 0) 11 9.0 52.5
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 1 0h, Bit [4] = 1) 4.05 1.21 15.5
Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 1.21 11.4
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 0.19 5.79
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Micrel, Inc.
KSZ8081MLX
Register Ma p
Register Num ber (Hex)
Description
0h Basic Control
1h Basic Status
2h PHY Identif i er 1
3h PHY Identif i er 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Link Partner Ability
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Pag e
8h Link Partn er Next Page Abi li ty
9h – Fh Reserved
10h Digital Reserved Control
11h AFE Contr ol 1
12h – 14h Reserved
15h RXER Count er
16h Operatio n Mode Strap Over r i de
17h Operatio n Mode Strap Stat us
18h Expande d Control
19h – 1Ah Reserved
1Bh Interrupt Control/St atus
1Ch Reserved
1Dh LinkMD Cont rol/Status
1Eh PHY Control 1
1Fh PHY Control 2
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on
Address Name Description
Mode
(6)
Default
Register 0h – Basic Control
0.15 Reset 1 = Software reset
0 = Normal operat i on
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operat i on RW 0
0.13 Speed Select
1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation is e nabled
(Register 0.12 = 1).
RW Set by the SPE ED strapping pin.
See the Strapping Options
section for details.
0.12 Auto-Negotiation
Enable
1 = Enable auto-negotiation p rocess
0 = Disable auto-negotiation process
If enabled, the auto-negotiation result overrides
the settings in Register 0. 13 and 0.8.
RW
Set by the NWAY E N s trapping
pin.
See the Strapping Options
section for details.
0.11 Power-Down
1 = Power-down mode
0 = Normal operat i on
If soft ware reset (Register 0.15) is used to ex i t
power-down mode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write reset s the chip and re-
latches the pin strapping pin values.
RW 0
0.10 Isolate 1 = Electric al i solation of PHY from MII
0 = Normal operat i on RW S et by the ISO s trapping pin.
See the Strapping Options
section for details.
0.9 Restart Auto-
Negotiation
1 = Restart aut o-negotiation process
0 = Normal operat i on.
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW
The inverse of the DUPLEX
strapping pin value.
See the Strapping Options
section for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL t est RW 0
0.6:0 Reserved Reserved RO 000_0000
Note:
6. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100Base-TX Ful l-
Duplex 1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex RO 1
1.13 100Base-TX Half-
Duplex 1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex RO 1
1.12 10Base-T
Full-Duplex 1 = Capable of 10Mb ps full-duplex
0 = Not capable of 10Mbps full-duplex RO 1
1.11 10Base-T
Half-Duplex 1 = Capable of 10Mbps hal f-duplex
0 = Not capable of 10Mbps half-duplex RO 1
1.10:7 Reserved Reserved RO 000_0
1.6 No Pream bl e 1 = Preamble s uppression
0 = Normal pream ble RO 1
1.5 Auto-Negotiation
Complete 1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed RO 0
1.4 Remote Fault 1 = Remote f aul t
0 = No remote fault RO/LH 0
1.3 Auto-Negotiation
Ability 1 = Can perf orm auto-negotiation
0 = Cannot perform auto-negotiation RO 1
1.2 Link Stat us 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not det ected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports e xtended capabil ity registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID Number
Assigned to the 3rd through 18th bits of the
Organizationally Uniq ue Identifier ( OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0022h
Register 3h – PHY Identifier 2
3.15:10 PHY ID Number
Assigned to the 19th through 24th bits of the
Organizationally Uniq ue Identifier ( OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0001_01
3.9:4 Mode l N um ber Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision Number Four-bit manufacturer’s revision number RO Indicates sili c on revision
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability RW 0
4.14 Reserved Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetr i c pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100Base-T4 1 = T4 c apabl e
0 = No T4 capability RO 0
4.8 100Base-TX Full-
Duplex 1 = 100M bps full-duplex capable
0 = No 100Mbps full -duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options
section for details.
4.7 100Base-TX Hal f-
Duplex 1 = 100M bps half-duplex capable
0 = No 100Mbps half -d upl e x capa bili t y RW Set by the SPEED st rapping pin.
See the Strapping Options
section for details.
4.6 10Base-T
Full-Duplex 1 = 10Mbps full-dupl ex capable
0 = No 10Mbps full -duplex capability RW 1
4.5 10Base-T
Half-Duplex 1 = 10Mbps half-duple x capable
0 = No 10Mbps half -duplex capabilit y RW 1
4.4:0 Select or Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetr i c pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100Base-T4 1 = T4 c apabl e
0 = No T4 capability RO 0
5.8 100Base-TX Full-
Duplex 1 = 100M bps full-duplex capable
0 = No 100Mbps full -duplex capability RO 0
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 5h – Auto-Negotiation Link Partner Ability
5.7 100Base-TX Hal f-
Duplex 1 = 100M bps half-duplex capable
0 = No 100Mbps half -d upl e x capa bili t y RO 0
5.6 10Base-T
Full-Duplex 1 = 10Mbps full-dupl ex capable
0 = No 10Mbps full -duplex capability RO 0
5.5 10Base-T
Half-Duplex 1 = 10Mbps half-duple x capable
0 = No 10Mbps half -duplex capab i li ty RO 0
5.4:0 Select or Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4 Parallel Detection
Fault 1 = Fault detected by parallel detection
0 = No fault detected by parall el detection RO/LH 0
6.3 Link Partner Next
Page Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability RO 0
6.2 Next Page Able 1 = Local dev ice has next page capability
0 = Local device does not have next page
capability RO 1
6.1 Page Received 1 = New pag e r eceived
0 = New page not received yet RO/LH 0
6.0 Link Partner Auto-
Negotiation Able
1 = Link partner has auto-negotiation capabili ty
0 = Link partner does not have auto-negotiation
capability RO 0
Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page RW 0
7.14 Reserved Reserved RO 0
7.13 Messag e Page 1 = Mess age page
0 = Unformatt ed page RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0 RO 0
7.10:0 Message Field 11-bit wide field to encode 2048 messa ges RW 000_0000_0001
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 8h – Link Partner Next P age Abili ty
8.15 Next Page 1 = Additional next pages will follow
0 = Last page RO 0
8.14 Acknowledge 1 = Succ es sful receipt of l ink word
0 = No success ful receipt of link word RO 0
8.13 Messag e Page 1 = Mess age page
0 = Unformatt ed page RO 0
8.12 Acknowledge2 1 = Can act on the information
0 = Cannot act on the information RO 0
8.11 Toggle
1 = Previous v alue of transmitted link code word
equal to logic 0
0 = Previous v alue of transmitted link code word
equal to logic 1
RO 0
8.10:0 Message Field 11-bit wide field to encode 2048 messa ges RO 000_0000_0000
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off 1 = Turn PLL off automat i c al ly in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [ 11] for EDPD mode RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
11.5 Slow-Oscillator
Mode Enable
Slow-oscillat or mode is used to dis c onnect the
input reference crystal/c l oc k on the XI pin and
select the on-chi p s low oscillator when the
KSZ8081MLX devi ce is not in use af ter power-
up.
1 = Enable
0 = Disable
This bit automatically set s software po wer-down
to the analog si de when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 15h – RXE R Counter
15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 16h – Operation Mode Strap Override
16.15 Reserved
Factory Mode
If TXC (Pin 33) l atches in a pull-up value at the
de-assertion of reset, write a ‘ 0’ to this bit to
clear Reserved Factory Mode. RW Set by the pull-up / pull-down
value of T XC (P i n 33) .
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9 B-CAST_OFF
Override 1 = Override st rap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0
16.8 Reserved Reserved RW 0
16.7 MII B-to-B
Override 1 = Override strap-in f or MII back-to-back mode
(also set Bit 0 of this register to ‘1’) RW 0
16.6 Reserved Reserved RW 0
16.5 NAND Tree
Override 1 = Override st rap-in for NAND tree mode RW 0
16.4:1 Reserved Reserved RW 0_000
16.0 MII Override 1 = Override strap-in for MI I mode RW 1
Register 17h – Operation Mode Strap Status
17.15:13 PHYAD[2:0] Strap-
In Status
[000] = Strap to PH Y Address 0
[001] = Strap to PH Y Address 1
[010] = Strap to PH Y Address 2
[011] = Strap to PH Y Address 3
[100] = Strap to PH Y Address 4
[101] = Strap to PH Y Address 5
[110] = Strap to PH Y Address 6
[111] = Strap to PH Y Address 7
RO
17.12:10 Reserved Reserved RO
17.9 B-CAST_OFF
Strap-In Status 1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RO
17.8 Reserved Reserved RO
17.7 MII B-to-B Strap-In
Status 1 = St rap to MII back-to-back mode RO
17.6 Reserved Reserved RO
17.5 NAND Tree Strap-
In Status 1 = Strap to NAND tree m ode RO
17.4:1 Reserved Reserved RO
17.0 MII Strap-In Status 1 = Strap to M II mode RO
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [ 4] for PLL off.
RW 1
18.10 100Base-TX
Latency
1 = MII output is r andom latenc y
0 = MII output is fixed latency
For both settings, all bytes of received preamble
are passed to the M II output.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6 10Base-T
Preamble Restore
1 = Restore re c ei v ed preamble t o MII output
0 = Remove all s even bytes of pream ble before
sending frame (starting with SFD) to MII output RW 0
18.5:0 Reserved Reserved RW 00_0000
Register 1Bh – I n terrupt Control/Status
1B.15 Jabber Interrupt
Enable 1 = Enable jabber interrupt
0 = Disable jabber i nterrupt RW 0
1B.14 Receive Error
Interrupt Enable 1 = Enable rec ei v e error interrupt
0 = Disable receive error inter rupt RW 0
1B.13 Page Rec eived
Interrupt Enable 1 = Enable page received int errupt
0 = Disable page r eceived int er rupt RW 0
1B.12 Parallel Detect
Fault Interr upt
Enable
1 = Enable parall el detect fault interrupt
0 = Disable par all el detect fault interrupt RW 0
1B.11 Link Partner
Acknowledge
Interrupt Enable
1 = Enable link partner acknowl edge interru pt
0 = Disable link partner acknowledge interrupt RW 0
1B.10 Link-Down
Interrupt Enable 1= Enable link-down interrupt
0 = Disable link-down interrupt RW 0
1B.9 Remote F ault
Interrupt Enable 1 = Enable remote fault interrupt
0 = Disable re mote fault interrupt RW 0
1B.8 Link-Up Interrupt
Enable 1 = Enable link-up interrupt
0 = Disable link-up interrupt RW 0
1B.7 Jabber Interrupt 1 = Jabber occurred
0 = Jabber did not occur RO/SC 0
1B.6 Receive Error
Interrupt 1 = Receive error oc curred
0 = Receive error did not occur RO/SC 0
1B.5 Page Rec eive
Interrupt 1 = Page receive occ urred
0 = Page receive did not occur RO/SC 0
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 1Bh – I n terrupt Control/Status (Continued)
1B.4 Parallel Detect
Fault Interr upt 1 = Paralle l detect fault oc c urred
0 = Parallel detect fault did n ot occur RO/SC 0
1B.3 Link Partner
Acknowledge
Interrupt
1 = Link partner ac knowledge occurred
0 = Link partner ac knowledge did n ot occur RO/SC 0
1B.2 Link-Down
Interrupt 1 = Link-down occurred
0 = Link-down did not occur RO/SC 0
1B.1 Remote F ault
Interrupt 1 = Remote fault occurred
0 = Remote fault did not occur RO/SC 0
1B.0 Link-Up Interrupt 1 = Link-up occurred
0 = Link-up did not occur RO/SC 0
Register 1Dh – L i n kMD Control/Status
1D.15 Cable Diagnostic
Test Enable
1 = Enable cab le diagnostic test. After t est has
completed, t hi s bit is self-cleared.
0 = Indicates cable diagnosti c test (if enabled)
has complete d and the status inf ormation is
valid for read.
RW/SC 0
1D.14:13 Cable Diagnos tic
Test Result
[00] = Normal condition
[01] = Open condit ion has been detec ted in
cable
[10] = Short c ondi tion has been detected in
cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Indicator 1 = Short cable (<10 meter) has been det ected
by LinkMD RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter Dis tance to faul t RO 0_0000_0000
Register 1Eh – PHY Control 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9 Enable P ause
(Flow Control) 1 = Flow control capable
0 = No flow cont rol capability RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down RO 0
1E.7 Polarity Status 1 = Polarity is reversed
0 = Polarity is not reversed RO
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X State 1 = MDI-X
0 = MDI RO
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description Mode(6) Default
Register 1Eh – PHY Control 1 (Continued)
1E.4 Energ y Detect
1 = Presence of signal on receive differential
pair
0 = No signal detected on recei v e differenti al
pair
RO 0
1E.3 PHY Isolate 1 = P H Y i n isolate mode
0 = PHY in normal operation RW 0
1E.2:0 Oper ation Mode
Indication
[000] = Still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Bas e-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Bas e-TX ful l-duplex
[111] = Reserved
RO 000
Register 1Fh – P HY Control 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode RW 1
1F.14 MDI/MDI-X Select
When Auto MDI /MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM ( Pins 10, 9) and
Receive on TX P, TXM (Pins 12, 11)
0 = MDI mode
Transmit on TXP,TXM (Pins 12, 11) and
Receive on RXP,RXM (Pins 10, 9)
RW 0
1F.13 Pair Swap Disable 1 = Disable Auto M D I/MDI-X
0 = Enable Auto MD I/MDI-X RW 0
1F.12 Reserved Reserved RW 0
1F.11 Forc e Li nk
1 = Force link pass
0 = Normal link oper ation
This bit b ypass es the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving 1 = Enable power saving
0 = Disable power saving RW 0
1F.9 Interrupt Level 1 = Interrupt pin activ e high
0 = Interrupt pi n ac tive low RW 0
1F.8 Enable Jabber 1 = Enable j abber counter
0 = Disable jabber counter RW 1
1F.7:6 Reserved Reserved RW 00
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Micrel, Inc.
KSZ8081MLX
Register De scr ipt i on ( Cont i nued)
Address Name Description
Mode
(6)
Default
Register 1Fh – P HY Control 2 (Continued)
1F.5:4 LED Mod e
[00] = LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
[10], [11] = Reserved
RW 00
1F.3 Disable
Transmitter 1 = Disable trans m i tter
0 = Enable transmitter RW 0
1F.2 Remote Loopback 1 = Remote (analog) lo opback is enabled
0 = Normal mode RW 0
1F.1 Enable SQ E Test 1 = Enable SQE test
0 = Disable SQE test RW 0
1F.0 Disable Data
Scrambling 1 = Disable scrambler
0 = Enable scram bler RW 0
December 10, 2014 42 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Absolute Ma xi mu m Ratings(7)
Supply Voltage (VIN)
(VDD_1.2) .................................................. −0.5V to +1.8V
(VDDIO, VDDA_3.3) ....................................... −0.5V to +5.0V
Input Voltage (all i nputs) .............................. −0.5V to +5.0V
Output Voltage (all out puts) ......................... −0.5V to +5.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (Ts) ......................... –55°C to +150°C
Operating Ratings(8)
Supply Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
(VDDIO_2.5) ........................................ +2.375V to +2.625V
(VDDIO_1.8) ........................................ +1.710V t o +1.890V
Ambient Temperature
(TA , Commercial) ...................................... 0°C to +70°C
(TA , Industrial) ...................................... –40°C to +85°C
Maximum Junction Te m perature (TJ maximum) ........ 125°C
Thermal Resistance (θJA) ......................................... 76°C/W
Thermal Resistance (θJC) ......................................... 15°C/W
Electric al Characteristics (9)
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(10)
IDD1_3.3V 10Base-T Full-duple x t raffic @ 100% utilization 41 mA
IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA
IDD3_3.3V EDPD Mode Ethernet c able disconnected (reg. 18h.11 = 0) 20 mA
IDD4_3.3V Power-Do wn Mode Software power -down (reg. 0h.11 = 1) 4 mA
CMOS Level Inputs
VIH Input High Voltage
VDDIO = 3.3V 2.0
V VDDIO = 2.5V 1.8
VDDIO = 1.8V 1.3
VIL Input Low Voltage
VDDIO = 3.3V 0.8
V VDDIO = 2.5V 0.7
VDDIO = 1.8V 0.5
|IIN| Input Current VIN = GND ~ VDDIO 10 µA
CMOS Level Outputs
VOH Output High Volt age
VDDIO = 3.3V 2.4
V
VDDIO = 2.5V 2.0
VDDIO = 1.8V 1.5
VOL Output Low Voltage
VDDIO = 3.3V 0.4
V VDDIO = 2.5V 0.4
VDDIO = 1.8V 0.3
|Ioz| Output Tri-State Leakage 10 µA
LED Outputs
ILED Output Drive Curr ent Each LED pin (LED0, LED1) 8 mA
Notes:
7. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage
to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not
implied. Maximum conditions for extended periods may affect reliability.
8. The device is not guaranteed to function outside its operating rating.
9. TA = 25°C. Specification is for packaged product only.
10. Current consumption is for the single 3.3V supply KSZ8081MLX device only, and includes the transmit driver current and the 1.2V supply voltage
(VDD_1.2) that are supplied by the KSZ8081MLX.
Electric al Characteristics (9) (Continued)
December 10, 2014 43 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
All Pull-Up/Pull-D own Pins (including strapping pins)
pu Internal Pull-Up Resistance
VDDIO = 3.3V 30 45 73
kΩ VDDIO = 2.5V 39 61 102
VDDIO = 1.8V 48 99 178
pd Internal Pull-Down Resistance
VDDIO = 3.3V 26 43 79
kΩ
VDDIO = 2.5V 34 59 113
VDDIO = 1.8V 53 99 200
100Base-TX T ransmit (measured differentially after 1:1 transformer)
VO Peak Differential Output
Voltage 100Ω t er mination acros s differential output 0.95 1.05 V
VIMB Output Voltage Imbalance 100Ω termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall T i m e Imbalance 0 0.5 ns
Duty Cycle Distortion ±0.25 ns
Overshoot 5 %
Output Jitter Peak-to-peak 0.7 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output
Voltage 100Ω t er mination acros s differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5 ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Thr es hold 5MHz square wave 400 mV
Transmitter – Drive Setting
VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V
100Mbps Mod e – Industrial Applications Parameters
Clock Phase D elay – XI Input
to MII TXC Output
XI (25MHz clock input) to MII TXC (25MHz clock
output) dela y, referenced t o rising edges of both
clocks. 15 20 25 ns
tllr Link Loss Reaction
(Indication) Time
Link loss detected at receive di fferential inputs to
PHY signal indic ation time for eac h of the following:
1. For LED mode 00, S peed LED output changes
from low (100Mbps) to high (10M bps, default state
for link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status change.
4.4 µs
December 10, 2014 44 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 9. MII SQE Timing (10Base-T)
Table 10. MII SQE Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL T XC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs
tSQEP COL (SQE) pulse dur ation 1.0 µs
December 10, 2014 45 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MII Transmit Timing (10Base-T)
Figure 10. MII Transmit Timin g (10Base-T)
Table 11. MII Transmit Ti ming (10Base-T) Par ameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL T XC pulse width low 200 ns
tWH TXC pulse width hi gh 200 ns
tSU1 TXD[3:0] setup to rising edge of TXC 120 ns
tSU2 TXEN setup to r ising edge of TXC 120 ns
tHD1 TXD[3:0] hold from rising edg e of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 600 ns
tCRS2 TXEN low to CRS de-asserted latenc y 1.0 µs
December 10, 2014 46 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MII Receive Tim ing (10Base-T)
Figure 11. MII Receive Timing (10Base-T)
Table 12. MII Receive Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXDV, RXD[3 :0], RXER) output delay from rising edge of RXC 205 ns
tRLAT CRS to (RXDV, RXD[3:0]) latenc y 7.2 µs
December 10, 2014 47 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MII Transmit Timing (100Base-TX)
Figure 12. MII Transmit Timing (100Base-TX)
Table 13. MII Transmit Ti ming (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 40 ns
tWL T XC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edge of TXC 10 ns
tSU2 TXEN setup to r ising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edg e of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 72 ns
tCRS2 TXEN low to CRS de-asserted latenc y 72 ns
December 10, 2014 48 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MII Receive Tim ing (100Base-TX)
Figure 13. MII Receive Timing (100Base-TX)
Table 14. MI I Receive Timin g (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXDV, RXD[3 :0], RXER) output delay from rising edge of RXC 25 ns
tRLAT CRS to (RXDV, RXD[3:0] latency 170 ns
December 10, 2014 49 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Auto-Negotiation Timing
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 15. Auto-Nego tiation Fast Li nk Pulse (FLP) Ti m ing Parameters
Timing Parameter Description Min. Typ. Max. Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/Data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/data pulses per FLP burst 17 33
December 10, 2014 50 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MDC/MDIO Timing
Figure 15. MDC/MDIO Timing
Table 16. MDC/M DIO Timing Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP MDC period 400 ns
tMD1 MDIO (PHY i nput) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY i nput) hold from ris i ng edge of MDC 4 ns
tMD3 MDIO (PHY output) delay fro m rising edge of M DC 5 ns
December 10, 2014 51 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Power-Up/Reset Timing
The KSZ8081MLX re set timing requirement is summarized in Figure 16 and Table 17.
Figure 16. Power-Up/Reset Timing
Table 17. Power-Up/Reset Timing Parameters
Parameter Description Min. Max. Units
tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms
tCS Configuration setup time 5 ns
tCH Configuration hold time 5 ns
tRC Reset to strap-in pin output 6 ns
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset .
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MII M (MDC/MDIO) interface.
December 10, 2014 52 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Reset Circuit
Figure 17 shows a reset circuit recommended for powering up t he KSZ8081MLX if reset is triggered by the power supply.
Figure 17. Recommended Reset Circuit
Figure 18 shows a reset circuit recommended for applications where reset is driven by another device (for example, the
CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8081MLX
device. The RST_O UT_n from the CPU/FPGA provides the warm reset after p ower-up.
Figure 18. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
December 10, 2014 53 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Reference Circuit s − LED Strap-In Pins
The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strapping pins are shown in
Figure 19 for 3.3V and 2.5V VDDIO.
Figure 19. Reference Circuits for LED Strapping Pins
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
SPEED and NWAYEN strapping pins are functional with a 4.7kΩ pull-up to 1.8V VDDIO or float for a value of ‘1’, and with
1.0kΩ pull-do wn t o ground for a value of ‘0’.
December 10, 2014 54 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Reference Clock − Connection and Selecti on
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081MLX. For
the KSZ8081MLX in all operating modes, the reference clock is 25MHz. The reference clock connections to XI (Pin 15)
and XO (Pin 14), and the reference clock sel ect ion criteria, are pro vided in Figure 20 and Table 18.
Figure 20. 25MHz Crystal/Oscillator Refer ence Clock Connection
Table 18. 25MHz Crystal / Refer ence Clock Select ion Criteria
Characteristics Value Units
Frequency 25 MHz
Frequency tol erance (maximum) ±50 ppm
Crystal series resistance (typical) 40 Ω
Crystal load capacitance (typical) 16 pF
December 10, 2014 55 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Magnetic − Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requi rements.
The KSZ8081MLX design incorpo rate s volt age-m ode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8081MLX side should not be connected to any power
supply source on the board; instead, the center tap pins should be separated from one another and connected through
separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage is
different between transmitting and rec ei ving differential pairs.
Figure 21 shows the t ypical magnetic interface circuit f or t he KSZ8081MLX.
Figure 21. Typical Magneti c Interface Circuit
December 10, 2014 56 Revision 1.2
Micrel, Inc.
KSZ8081MLX
Table 19 lists recom m ended magnetic characteristics.
Table 19. Mag netics Selection Criteria
Parameter
Value
Test Condition
Turns rati o 1 CT : 1 CT
Open-circuit inductance (min.) 350µH 100mV, 100kHz, 8mA
Insertion los s (typ.) –1.1dB 100kHz to 100MHz
HIPOT (min.) 1500Vrms
Table 20 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that
can be used with the KSZ8081MLX.
Table 20. Compatible Single-Port 10/100 Magneti cs
Manufacturer
Part Number
Temperatur e Range
Magnetic + RJ -45
Bel Fuse S558-5999-U7 0°C to 70°C No
Bel Fuse SI-46001-F 0°C to 70°C Yes
Bel Fuse SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70° C No
Pulse H1260 0°C to 70° C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C t o 70° C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70° C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
December 10, 2014 57 Revision 1.2
Micrel, Inc.
KSZ8081MLX
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed
-signal, analog & power semiconductors; high-performan
ce communication, clock
management,
MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs.
Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommu
nications, automotive, and computer products.
Corporation headquarters and state
-of-the-
art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the A
mericas, Europe, and Asia.
Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the inf
ormation furnished in this datash
eet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use.
Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice.
No license, whether express, implied, ar
ising by estoppel or otherwise, to any intellectual
property rights
is granted by this document. E
xcept as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
, or other intellectual property right.
Micrel Product
s are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sus tain li fe, and whose failure to perform can b e reasonably expected to result in a si gnificant i njury to the user. A
Purchaser’s use or sale of Micrel Products for use in l ife s upport applia nc es, dev ices or systems is a Purchaser’s own ri sk and Purchas er agrees to full y
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December 10, 2014 59 Revision 1.2
