Document Number: 322371-003
Intel® Xeon® Processor 3400 Series
Datasheet – Volume 1
June 2010
2Datasheet, Volume 1
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certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software
configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your
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Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii) cause the processor
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* Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability . Intel Turbo Boost Technology performance
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operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which
processors support HT Technology, see http://www.intel.com/info/hyperthreading.
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enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for
more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http://
processorfinder.intel.com or contact your Intel representative for more information.
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*Other names and brands may be claimed as the property of others.
Copyright © 2009-2010, Intel Corporation. All rights reserved.
Datasheet, Volume 1 3
Contents
1Introduction..............................................................................................................9
1.1 Processor Feature Details ...................................................................................11
1.1.1 Supported Technologies ..........................................................................11
1.2 Interfaces ........................................................................................................11
1.2.1 System Memory Support.........................................................................11
1.2.2 PCI Express* .........................................................................................12
1.2.3 Direct Media Interface (DMI)....................................................................13
1.2.4 Platform Environment Control Interface (PECI)...........................................14
1.3 Power Management Support ...............................................................................14
1.3.1 Processor Core.......................................................................................14
1.3.2 System.................................................................................................14
1.3.3 Memory Controller.............................................. ... .. .. ..................... .. .. .. ..14
1.3.4 PCI Express* .........................................................................................14
1.4 Thermal Management Support ............................................................................15
1.5 Package...........................................................................................................15
1.6 Terminology .....................................................................................................15
1.7 Related Documents ...........................................................................................17
2Interfaces................................................................................................................19
2.1 System Memory Interface ..................................................................................19
2.1.1 System Memory Technology Supp o rted................. ... .. .. .. ............. .. ............19
2.1.2 System Memory Timing Supp o rt............... .. .. ............. ...............................21
2.1.3 System Memory Organization Modes.........................................................21
2.1.3.1 Single-Channel Mod e........ .. ... .. .......... .. .. ...................... .. .. ..........21
2.1.3.2 D ual-Channel Mode—Intel® Flex Memory Technology Mode............22
2.1.4 Rules for Populating Memory Slots............................................................23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)..........24
2.1.5.1 Just-in-Time Command Scheduling........ .. ... .. .. ............ ... .. ............24
2.1.5.2 Command Overlap....................................................................24
2.1.5.3 Out-of-Order Scheduling............................................................24
2.1.6 System Memory Pre-Charge Power Down Support Details............................24
2.2 PCI Express* Interface.......................................................................................25
2.2.1 PCI Express* Architecture .......................................................................25
2.2.1.1 Transaction Layer .....................................................................26
2.2.1.2 Data Link Layer ........................................................................26
2.2.1.3 Physical Layer ..........................................................................26
2.2.2 PCI Express* Configuration Mechanism .....................................................27
2.2.3 PCI Express* Ports and Bifurcation ...........................................................28
2.2.3.1 PCI Express* Bifurcated Mode ....................................................28
2.3 Direct Media Interface (DMI)...............................................................................28
2.3.1 DMI Error Flow................................ ... .. .. ..................... .. .. .. .....................28
2.3.2 Processor/PCH Compatibility Assumptions..................................................28
2.3.3 DMI Link Down ......................... .. .. ........... .. .. ........... .. .. .......... ... .. .......... ..28
2.4 Platform Environment Control Interface (PECI)......................................................29
2.5 Interface Clocking .............................................................................................29
2.5.1 Internal Clocking Requirements................................................................29
3 Technologies ...........................................................................................................31
3.1 Intel® Virtualization Technology..........................................................................31
3.1.1 Intel® VT-x Objectives............................................................................31
3.1.2 Intel® VT-x Features ..............................................................................31
4Datasheet, Volume 1
3.1.3 Intel® VT-d Obje ctive s ............... .. .. ..................... .. ... ..................... .. .. ......32
3.1.4 Intel® VT-d Features..... ... .. .......... .. .. ........... .. ........... .. .. .......... .. ... .......... ..32
3.1.5 Intel® VT-d Featu r es Not Supp orte d.......... .. ....................... .......................33
3.2 Intel® Trusted Execution Technology (Intel® TXT) ........... .. .. ........... ........... .. ..........33
3.3 Intel® Hyper-Thre ading Te chnolog y ................... .. ............................... .. ... .. ..........34
3.4 Intel® Turbo Boost Technology.................................... .. .. .. ...................... .. .. .. ......34
4 Power Management .................................................................................................35
4.1 ACPI States Supported .......................................................................................35
4.1.1 System States................. .......... .. .. ........... .. .. ........... .. .. .......... .. ... .......... ..35
4.1.2 Processor Core/Package Idle States...........................................................35
4.1.3 Integrated Me mory Controller States............. .. .. ....................... .................35
4.1.4 PCI Express* Link States .........................................................................36
4.1.5 Interfa ce State Combinations .......... .. ..................... ... .. ..................... .. .. .. ..36
4.2 Processor Core Power Management......................................................................36
4.2.1 Enhanced Intel® SpeedStep® Technology ..................................................37
4.2.2 Low-Power Idle States.............................................................................37
4.2.3 Requesting Low -Power Idle States ............................................................39
4.2.4 Core C-states.........................................................................................39
4.2.4.1 Core C0 State...................... ... .. .......... .. .. ........... .. .. ........... .. .. ....40
4.2.4.2 Core C1/C1E State . .......... .. .. ........... .. .. ........... .. .. .. ........... .. .. ......40
4.2.4.3 Core C3 State...................... ... .. .......... .. .. ........... .. .. ........... .. .. ....40
4.2.4.4 Core C6 State...................... ... .. .......... .. .. ........... .. .. ........... .. .. ....40
4.2.4.5 C-State Auto-Demotion..............................................................40
4.2.5 Package C-States ...................................................................................41
4.2.5.1 Package C0 ................... .. .. ........... .. .. ........... .. .. .......... ... .. ..........42
4.2.5.2 Package C1/C1E........... .. ........... .. .. .. ........... .. .. .......... .. ... .. ..........42
4.2.5.3 Package C3 State.......................... .. .. ..................... .. .. ........... .. ..43
4.2.5.4 Package C6 State.......................... .. .. ..................... .. .. ........... .. ..43
4.3 IMC Power Management .....................................................................................43
4.3.1 Disabling Unused System Memory Outputs.................................................43
4.3.2 DRAM Power Management and Initialization ...............................................44
4.3.2.1 Initialization Role of CKE ............................................................44
4.3.2.2 Conditional Self-Refresh.............................................................44
4.3.2.3 Dynamic Power Down Operation................ ... .. .. .. ............. .. ..........44
4.3.2.4 DRAM I/O Power Management ....................................................45
4.4 PCI Express* Power Management ........................................................................45
5 Thermal Management ..............................................................................................47
6 Signal D escription....................................................................................................49
6.1 System Memory Interface.......................................................... .. .. .. ........... .. .. .. ..50
6.2 Memory Reference and Compensation ..................................................................52
6.3 Reset and Miscellaneous Signals ..........................................................................52
6.4 PCI Express* Based Interface Signals...................................................................53
6.5 DMI—Processor to PCH Serial Interface.................................................................53
6.6 PLL Signals ........................... .. ........... .. .. ........... .. .. .......... ... .. .......... .. .. ........... .. ..54
6.7 Intel® Flexible Display Interface Signals ...............................................................54
6.8 JTAG/ITP Signals ...............................................................................................55
6.9 Error and Thermal Protection............................................................................... 56
6.10 Power Sequ e ncing ...................... .. .. .......... .. .. ........... .. .. ........... .. .. ........... .. ..........57
6.11 Processor Core Power Signals..............................................................................57
6.12 Graphics and Memory Core Power Signals.............................................................59
6.13 Ground and NCTF ..............................................................................................60
6.14 Processor Internal Pull Up/Pull Down ....................................................................60
Datasheet, Volume 1 5
7 Electrical Specifications...........................................................................................61
7.1 Power and Ground Lands....................................................................................61
7.2 Decoupling Guidelines........................................................................................61
7.2.1 Voltage Rail Decoupling...........................................................................61
7.3 Processor Clocking (BCLK[0], BCL K # [ 0])....... ............. ............. ............ ............. ....62
7.3.1 PLL Power Supply...................................................................................62
7.4 VCC Voltage Identification (VID) ..........................................................................62
7.5 Reserved or Unused Signals................................................................................66
7.6 Signal Groups................. ........... .. .. .......... .. ... .......... .. .. ........... .. .. ..................... ..66
7.7 Test Access Port (TAP) Connection.......................................................................69
7.8 Absolute Maximum and Minimum Ratings .............................................................69
7.9 DC Specifications ..............................................................................................70
7.9.1 Voltage and Current Specifications............................................................70
7.10 Platform Environmental Control Interface (PECI) DC Specifications..................... .. ....77
7.10.1 DC Characteristics..................................................................................77
7.10.2 Input Device Hysteresis ..........................................................................78
8 Processor Land and Signal Information ...................................................................79
8.1 Processor Land Assignments...............................................................................79
Figures
1-1 Intel® Xeon® Processor 3400 Series Platform Diagram ........................................ .... .... . 10
2-1 Intel® Flex Memory Technology Operation............... ....................................................22
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asy mme tric Mode s .......... .. .. .. ..23
2-3 PCI Express* Layering Diagram .................................................................................25
2-4 Packet Flow through the Layers .................................................................................26
2-5 PCI Express* Related Register Structures in Processor .................................................27
4-1 Idle Power Management Breakdown of the Processor Cores ...........................................37
4-2 Thread and Core C-State Entry and Exit......................................................................38
4-3 Package C-State Entry and Exit..................................................................................42
7-1 VCC Static and Transient Tolerance Loadlines ...............................................................73
7-2 Input Device Hysteresis ............................................................................................78
8-1 Socket Pinmap (Top View, Upper-Left Quadrant)..........................................................80
8-2 Socket Pinmap (Top View, Upper-Right Quadrant)........................................................81
8-3 Socket Pinmap (Top Vie w, Lower-Left Quadrant)......................... ............ ............. ........82
8-4 Socket Pinmap (Top View, Lower-Right Quadrant)........................................................83
Tables
1-1 Intel® Xeon® Processor 3400 Series Supported Memory Summary................................11
1-2 Related Documents.................................................................................................17
2-1 Supported DIMM Module Configurations.....................................................................20
2-2 DDR3 System Memory Timing Support .....................................................................21
2-3 System Memory Pre-Charge Power Down Support.......................................................24
2-4 Processor Reference Clock Requirements ...................................................................29
4-1 Processor Core/Package State Support ......................................................................35
4-2 G, S, and C State Combinations................................................................................36
4-3 Coordination of Thread Power States at the Core Level ................................................38
4-4 P_LVLx to MWAIT Conversion...................................................................................39
4-5 Coordination of Core Power States at the Package Level...............................................41
4-6 Targeted Memory State Conditions............................................................................44
6-1 Signal Description Buffer Types ................................................................................49
6-2 Memory Channel A.................... .. ... .......... .. .. ........... .. .. ........... .. .. .......... .. ... .. .......... ..50
6-3 Memory Channel B.......... .. .......... ... .. .. .......... .. .. ........... .. .. ........... .. .. ........... .. .. ..........51
6-4 Memory Reference and Compensation .......................................................................52
6Datasheet, Volume 1
6-5 Reset and Miscellaneous Signals................................................................................52
6-6 PCI Express* Based Interface Signals ........................................................................53
6-7 DMI—Processor to PCH Serial Interface......................................................................53
6-8 PLL Signals.......... .. .. ........... .. .. ........... .. .. .......... .. ........... .. .. ........... .. .. ........... .. .. ........54
6-9 Intel® Flexible Display Interface................................................................................54
6-10 JTAG/ITP................................................................................................................55
6-11 Error and Thermal Protection ....................................................................................56
6-12 Power Sequencing.................................. .. .. ........... .. .. .......... .. ... .......... .. .. .................57
6-13 Processor Core Power Signals ...................................................................................57
6-14 Graphics and Memory Power Signals..........................................................................59
6-15 Ground and NCTF....................................................................................................60
6-16 Processor Internal Pull Up/Pull Down..........................................................................60
7-1 VRD 11.1/11.0 Voltage Identification Definition...........................................................63
7-2 Market Segment Selection Truth Table for MSID[2:0]...................................................65
7-3 Signal Groups 1 ......................................................................................................67
7-4 Processor Absolute Minimum and Maximum Ratings.....................................................69
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 70
7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications .....................71
7-7 VCC Static and Transient Tolerance ............................................................................72
7-8 DDR3 Signal Group DC Specifications.........................................................................74
7-9 Control Sideband and TAP Signal Group DC Spe cifications.............................................75
7-10 PCI Express* DC Specifications .................................................................................76
7-11 PECI DC Electrical Limits ..........................................................................................77
8-1 Signals Not Used by the Intel® Xeon® Processor 340 0 Se rie s............... .......... ... .. .. ........79
8-2 Processor Pin List by Pin Name..................................................................................84
Datasheet, Volume 1 7
Revision History
§ §
Revision
Number Description Date
001 • Initial release September
2009
002 • Added workstation information January
2010
003 • Added Intel Xeon X3480 processor June 2010
8Datasheet, Volume 1
Datasheet, Volume 1 9
Introduction
1Introduction
The Intel® Xeon® processor 3400 series are the next generation of 64-bit, multi-core
processors built on 45-nanometer process technology. Based on the low-power/high-
performance Intel microarchitecture, the processor is designed for a two-chip platform,
instead of the traditional three-chip platforms (processor, (G)MCH, and ICH). The two-
chip platform consists of a processor and Platform Controller Hub (PCH) and enables
higher performance, easier validation, and improved x-y footprint. The Intel® 3400
Series Chipset components for servers and workst atio ns are the PCH. The Intel®
Xeon® processor 3400 series is intended for UP server and workstation platforms.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
and additional feature information pertinent to the implem entation and operation of the
processor on its respective platform.
Note: Throughout this document, the Intel® Xeon® processor 3400 series may be referred to
as “processor”.
Note: Throughout this document, the Intel® Xeon® processor 3400 series refers to the Intel®
Xeon® X3480, X3470, X3460, X3450, X3440, X3430, and L3 426 processors.
Note: Througout this document, the Intel® 3400 Series Chipset Platform Controller Hub may
be referred to as “PCH”.
Note: Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Included in this family of processors is an integrated memory controller (IMC) and
integrated I/O (IIO) (such as PCI Express* and DMI) on a single silicon die. This single
die solution is known as a monolithic processor. For specific features supported on
individual Intel Xeon processor 3400 series SKUs, refer to the Intel® Xeon® Processor
3400 Series Specification Update. Figure 1-1 shows an example server platform block
diagram.
Introduction
10 Datasheet, Volume 1
Figure 1-1. Intel® Xeon® Processor 3400 Series Platform Diagram
Processor
Discrete Graphics
(PEG)
Gigabit
Network Connection
USB 2.0
Intel®
HD Audio
FWH
TPM 1.2
Super I/ O
PCI
Serial ATA
Intel® 3400 Series Chipset
PCI Express* 1x16
14
Ports
PCI
6 Ports
3 Gb/s
SPI
PCI Express*
SPI Flash
LPC
SMBUS 2.0
GPIO
OR
DMI
Intel®
Management
Engine
PCI Express* 2x 8
PCI Express* 4x4
Quad C ore CPU w ith
Integrated Memory Controller
PECI
8 x1 PCI Express*
2.0 Po rts
(2.5 GT/s)
OR
Note: Supported PCI Express
configurations vary by SKU.
Som e technologies may not be enabled on all processor SKUs. Refer
to the Processor Specification Update for details.
DDR3 DIMMs
DDR3 DIMMs
2 Channels
(2 UDIMM/Channel)
Or
(3 RDIMM/Channel)
Datasheet, Volume 1 11
Introduction
1.1 Processor Feature Details
• Four cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data second-level cache (L2) for each core
• 8-MB shared instruction/data last-level cache (L3), shared among all cores
1.1.1 Supported Technologies
•Intel
® Virtualization Technology for Directed I/O (Intel® VT-d)
•Intel
® Virtualization Technology (Intel® VT-x )
•Intel
® Trusted Execution Technology (Intel® TXT)
• Intel Active Management Technology 6.0 (Intel 3450 Chipset platform only)
•Intel
® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
•Intel
® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
•Intel
® Hyper-Threading Technology
•Intel
® 64 Architecture
• Execute Disable Bit
•Intel
® Turbo Boost Technology
Note: Some technologies may not be enabled on all processor SKUs. Refer to the processor
specification update for details.
Note: Intel® Active Management Technology 6.0 is not supported on the Intel X eon processor
3400 series for Intel 3400 and 3420 Chipset Platforms.
1.2 Interfaces
1.2.1 System Memory Support
Notes:
1. Non-ECC DIMMs are not supported. Mixing of non-ECC and ECC DIMMs is not supported.
2. Mixing of non-ECC and ECC DIMMs is not supported. Registered DIMMs are not supported.
Table 1-1. Intel® Xeon® Processor 3400 Series Supported Memory Summary
Platform Memory Type # of
Channels DIMMs/
Channel
Transfer
Rate
(MT/s) Notes
Intel 3450 Chipset Platform
DDR3:
Non-ECC Unbuffered 1 or 2 1 or 2 1066, 1333 2
DDR3:
ECC Unbuffered 1 or 2 1 or 2 1066, 1333 2
Intel 3400 and 3420 Chipset
Platforms
DDR3:
ECC Registered DIMM 1 or 2 Up to 3 800, 1066,
1333 1
DDR3:
ECC Unbuffered DIMM 1 or 2 1 or 2 1066, 1333 1
Introduction
12 Datasheet, Volume 1
System memory features include:
• Data burst length of eight for all memory organization modes
•64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Maximum memory bandwidth of 10.6 GB/s in single-channel mode or 21 GB/s in
dual-channel mode assuming DDR3 1333 MT/s
• 1-Gb and 2-Gb DD R3 DRAM technologies are supported.
• Using 2-Gb device technologies, the largest memory capacity possible is 16 GB for
UDIMMs (assuming Dual Channel Mode with a four dual rank unbuffered, non-ECC
DIMM memory configuration), and 32 GB for RDIMMs (assuming Dual Channel
Mode with a four quad-rank registere d DIMM memory configuration)
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Command launch modes of 1n/2n
•Intel
® Fast Memory Access (Intel® FMA)
— Just-in-Time Command Scheduling
—Command Overlap
— Out-of-Order Scheduling
1.2.2 PCI Express*
• The processor PCI Express* port(s) are fully-compliant with the PCI Express Base
Specification, Revision 2.0.
•Intel
® Xe on® processor 3400 series with the Intel® 3450 Chipset supports:
— One 16-lane PCI Express port intended for graphics attach.
— Two 8-lane PCI Express ports for graphics or I/O.
•Intel
® Xe on® processor 3400 series with the Intel 3420 Chipset supports:
— One 16-lane PCI Express port intended for graphics or I/O.
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
•Intel
® Xe on® processor 3400 series with the Intel 3400 Chipset supports:
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
• PCI Express port 0 is mapped to PCI Device 3.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x1 widths for a single PCI Express mode.
• 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s for x16.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
Datasheet, Volume 1 13
Introduction
• PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style tr affic (asynchronous non-sno oped, PC I -X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— PCI Express Port 0 -> PCI Express Port 1
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configur ation cycles that ha ve been previously completed with the
Configuration Retry status.
• PCI Express reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MS I-X) messages
• Polarity inversion
1.2.3 Direct Media Interface (DMI)
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
Introduction
14 Datasheet, Volume 1
• Supports the following traffic types to or from the PCH
— DMI -> PCI Express Port 0 write traffic
— DMI -> PCI Express Port 1 write traffic
—DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI, and SERR error indication
• Legacy support for ISA regime protocol (P HOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage” and Full Swing “high-power/high-
voltage” modes
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH.
1.3 Power Management Support
1.3.1 Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6
• Enhanced Intel SpeedStep® Technology
1.3.2 System
• S0, S1, S4, S5
1.3.3 Memory Controller
• Conditional self-refresh
•Dynamic power-down
1.3.4 PCI Express*
• L0s and L1 ASPM power management capability.
— L0s not supported on the Intel Xe on® processor 3400 series when configured
as PCI Express 4x4
Datasheet, Volume 1 15
Introduction
1.4 Thermal Management Support
• Digital Thermal Sensor
•Intel
® Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor
• Fan Speed Control with DTS
1.5 Package
• The processor socket type is noted as LGA 1156. The package is a 37.5 x 37.5 mm
Flip Chip Land Grid Array (FCLGA 1156).
1.6 Terminology
Term Description
DDR3 Third generation Double Data Rate SDRAM memory technology
DP Display Port*
DMA Direct Memory Access
DMI Direct Media Interface
DTS Digital Thermal Sensor
ECC Error Correction Code
Enhanced Intel
SpeedStep® Technology Technology that provides power management capabilities.
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code attempts
to run in non-executable memory, the pr ocessor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit
buffer overrun vulner abilities and can, thus, help improve the overall s ecurity of the
system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals
for more detailed information.
FCLGA Flip Chip Land Grid Array
(G)MCH Legacy component – Graphics Memory Controller Hub. Platforms using LGA 1156
processors do not use a (G)MCH component.
ICH
The legacy I/O Con troller H ub component that contains the main PCI interface, LPC
interface, USB2, Serial ATA, and other I/O functions. It communicates with the
legacy (G)MCH over a proprietary interconnect called DMI. Platforms using LGA
1156 processors do not use an ICH component.
IMC Integrated Memory Controller
Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture.
Intel® Hyper-Threading
Technology The processor supports Intel ® Hyper-Threading Technology (Intel® HT Technology)
that allows an execution core to function as two logical processors.
Intel® Turbo Boost
Technology
Intel® Turbo Boost Technology is a feature that allows the processor core to
opportunistically and automatical ly run faster than its rated ope rating frequency if it
is operating below power, temperature, and current limits.
Intel® TXT Intel® Trusted Execution Technology
Introduction
16 Datasheet, Volume 1
Intel® VT-d
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS) control,
for enabling I/O device virtualization. VT-d also brings robust security by providing
protection from errant DMAs by using DMA remapping, a key feature of Inte l VT-d.
Intel® Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
ITPM Integrated Trusted Platform Module
IOV I/O Virtualization
LCD Liquid Crystal Display
LVDS Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
NCTF Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
PCH Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity, audio
features, power management, manageability, security and storage features.
PECI Platform Environment Control Interface
PEG PCI Express* Graphics. External Graphics using PCI Express Architecture. A high-
speed serial interface whose configuration is software compatible with the existing
PCI specifications.
Processor The 64-bit multi-core component (package)
Processor Core The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray, or
loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages,
have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is,
unsealed packaging or a device removed from packaging material), the processor
must be handled in accordance with moisture sensitivity labeling (MSL) as indicated
on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TLP Transaction Layer Packet
TOM Top of Memory
TTM Time-To-Market
VCC Processor core power rail
VSS Processor ground
VTT L3 shared cache, memory controller, and processor I/O power rail
VDDQ DDR3 power rail
VLD Variable Length Decoding
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
Term Description
Datasheet, Volume 1 17
Introduction
1.7 Related Documents
Refer to the following documents for additional information.
§ §
Table 1-2. Related Documents
Document Document Number/ Location
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2 http://www.intel.com/Assets/PDF
/datasheet/322372.pdf
Intel® Xeon® Processor 3400 Series Specification Update http://www.intel.com/Assets/PDF
/datasheet/322373.pdf
Intel® Xeon® Processor 3400 Series and LGA1156 Socket Thermal and
Mechanical Specifications and Design Guidelines http://www.intel.com/Assets/PDF
/datasheet/322374.pdf
Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet www.intel.com/Assets/PDF/datas
heet/322169
Intel® 5 Series Chipset and Intel® 3400 Series Chipset Thermal and
Mechanical Specifications and Design Guidelines www.intel.com/Assets/PDF/d
esignguide/322171.pdf
Voltage Regulator-Down (VRD) 11.1 Design Guidelines http://download.intel.com/design
/processor/designex/322172.pdf
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/specificati
ons
PCI Express Base Specification, Revision 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
Display Port Specification http://www.vesa.org
Intel® 64 and IA-32 Architectures Software Developer's Manuals
http://www.intel.com/products/pr
ocessor/manuals/
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instr uction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
Introduction
18 Datasheet, Volume 1
Datasheet, Volume 1 19
Interfaces
2Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wid e channels. Refer to Section 1.2.1 for details on the type of
memory supported.
• Supported DIMM Types
— Unbuffered DIMMs—1066 MT/s (PC3-8500), and 1333 MT/s (PC3-10600)
— Registered DIMMs—1066 MT/s (PC3-8500), and 1333 MT/s (PC3-10600)
• Intel 3450 Chipset platforms DDR3 DIMM Modules
— Raw Card A—Single Sided x8 unbuffered non-ECC
— Raw Card B—Double Sided x8 unbuffered non-ECC
— Raw Card C—Single Sided x16 unbuffered non-ECC
— Raw Card D—Single Sided x8 unbuffered ECC
— Raw Card E—Double Sided x8 unbuffered ECC
• Intel 3400 and 3420 Chipset platforms DDR3 DIMM Modules
— Raw Card D—Single Sided x8 unbuffered ECC
— Raw Card E—Double Sided x8 unbuffered ECC
— Raw Card A—Single Sided x8 registered ECC
— Raw Card B—Double Sided x8 registered ECC
— Raw Card G—Quad Rank x8 registered ECC
— Raw Card H—Quad Rank Stacked x8 registered ECC
• DDR3 DRAM Devi ce Technology
— Unbuffered—1-Gb and 2-Gb DDR3 DRAM Device technologies and addressing
are supported (as detailed in Table 2-1).
— Registered—1-Gb and 2-Gb DDR3 DRAM Device technologies and addressing
are supported (as detailed in Table 2-1).
Interfaces
20 Datasheet, Volume 1
Note: DIMM module support is based on availability and is subject to change.
Table 2-1. Supported DIMM Module Configurations
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of
Row/Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
Intel 3450 Chipset Platforms with Intel Xeon® Processor 3400 Series Skus:
Unbuffered/ECC Supported DIMM Module Configurations
A 1 GB 1 Gb 128 M X 8 8 1 14/10 8 8 K
B 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8 K
4 GB 2 Gb 256 M X 8 16 2 15/10 8 8 K
C 512 MB 1 Gb 64 M X 16 4 1 13/10 8 8 K
D 1 GB 1 Gb 128 M X 8 9 1 14/10 8 8 K
E 2 GB 1 Gb 128 M X 8 18 2 14/10 8 8 K
4 GB 2 Gb 256 M X 8 18 2 15/10 8 8 K
Intel 3400 and 3420 Chipset Platforms with Intel Xeon® Processor 3400 Ser ies SKUs:
Registered/ECC Supported RDIMM Module Configurations and
Unbuffered/ECC Supported DIMM Module Configurations (D and E)
D 1 GB 1 Gb 128 M X 8 9 1 14/10 8 8 K
E 2 GB 1 Gb 128 M X 8 18 2 14/10 8 8 K
4 GB 2 Gb 256 M X 8 18 2 15/10 8 8 K
A 1 GB 1 Gb 128 M X 8 9 1 14/10 8 8 K
B 2 GB 1 Gb 128 M X 8 18 2 14/10 8 8 K
G 8 GB 2 Gb 256 M X 8 36 4 15/10 8 8 K
H 4 GB 1 Gb 128 M X 8 36 4 14/10 8 8 K
Datasheet, Volume 1 21
Interfaces
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
•t
CL = CAS Latency
•t
RCD = Activate Command to READ or WRITE Command delay
•t
RP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every clock
and 2N indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer r ate and memory configuration.
Note:
1. Two Un-buffered DIMM M emory Configurations = 2N Command Mode at 1067/1333 MHz
2. One Un-buffered DIMM Memory Configurations = 1N Command Mode at 1067/1333 MHz
3. Both Channel A and B will run at same Command Mode based on the slowest mode enabled relative to the
memory configurations populated in both channels. For example, if Channel A has both DIMM connectors
populated (2N CMD Mode) and Channel B has on ly one DIMM connecto r populated (1N CMD Mod e) then 2N
CMD mode would be enabled for both channels.
4. System Memory timing support is based on availability and is subject to change.
2.1.3 System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated, but not
both.
Table 2-2. DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
tCL
(tCK)tRCD
(tCK)tRP
(tCK)CWL
(tCK)
Unbuffered
DIMM CMD
Mode
Registered
DIMM CMD
Mode Notes
6 6 6 5 N/A 1N Only 4
1066 777
6 See Note 1, 2, 3 1N Only 4
888
1333
888
7 See Note 1, 2, 3 1N Only
4
999 4
10 10 10 4
Interfaces
22 Datasheet, Volume 1
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology mode. This mode combines the
advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The
symmetric zone starts at the lowest address in each channel and is contiguous until the
asymmetric zone begins or until the top address of the channel with the smaller
capacity is reached. In this mode, the system runs with one zone of dual-channel mode
and one zone of single-channel mode, simultaneously, across the whole memory array.
2.1.3.2.1 Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also kn own as interleaved mode, provides maxim um
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note: The DRAM device technology and width may vary from one channel to the other.
Figure 2-1. Intel® Flex Memory Technology Operation
CH BCH A
CH BCH A
B B
C
BB
C
B
B
CNon interleaved
access
D ual channel
interleaved access
Top of Mem ory
B – T he largest physical m em ory am ount of the sm aller size m em ory m odule
C – The rem aining physical m em ory am ount of the larger size m em ory m odule
Datasheet, Volume 1 23
Interfaces
2.1.3.2.2 Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
This mode is used when Intel Flex Memory Technology is disabled and both Channel A
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
2.1.4 Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory mod ules. The system memory controller supports one or two DIMM
connectors per channel for unbuffered DIMMs or up to three DIMM connectors per
channel for registered DIMMs.For dual-channel modes, both channels must have at
least one DIMM connector populated and for single-channel mode only a single-channel
may have one or more DIMM connectors populated.
Note: DIMM0 must always be populated within an y memory configuration. DIMM0 is the
furthest DIMM within a channel and is identified by the CS#[1:0], ODT[1:0], and
CKE[1:0] signals.
Figure 2-2. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
CL
0
Top of
Memory
CL
0
CH. B
CH. A CH.A-top
DRB
Dual Channel Interleaved
(memory sizes must match) Dual Channel Asymmetric
(memory sizes can differ)
Top of
Memory
Interfaces
24 Datasheet, Volume 1
2.1.5 Technology Enhancements of Intel® Fast Memory Access
(Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 C ommand Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and R ead/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 System Memory Pre-Charge Power Down Support Details
The IMC supports and enables the following DDR3 DRAM Device pre-charge power
down DLL controls during a pre-charge power down.
• Slow Exit is where the DRAM device DLL is disabled after entering pre-charge
power down
• Fast Exit is where the DRAM device DLLs are maintained after entering pre-charge
power down
Table 2-3. System Memory Pre-Charge Power Dow n Support
DIMM per Channel
Configuration DIMM Type Precharge Power Down
Slow/Fast Exit
One Unbuffered DIMM Slow Exit
Two Unbuffered DIMM Fast Exit
One Registe red DIMM Raw Car ds A, B, D , or E Slow Exit
Two or Three Registered DIMM Raw Cards A, B, D, or E Fast Exit
One or Two Registered DIMM Raw Cards G or H Fast Exit
Datasheet, Volume 1 25
Interfaces
2.2 PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers available is dependent on the platform:
• Intel Xeon processor 3400 series with the Intel 3450 Chipset: 1 x16 PCI Express
Graphics or 2x8 PCI Express Graphics are supported.
• Intel Xeon processor 3400 series with Intel 3400 and 3420 Chipset: 1 x16 PCI
Express I/O, 2 x8 PCI Express I/O, or 4 x4 PCI Express I/O are supported.
2.2.1 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation. When operating with more than one PCI Express controller, each controller
can be operating at either 2.5 GT/s or 5.0 GT/s.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-3 for the PCI Express Layering Diagram.
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
Figure 2-3. PCI Express* Layering Diagram
Interfaces
26 Datasheet, Volume 1
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer P ackets) to the form th at can be
processed by the Transaction Layer of the receiving device.
2.2.1.1 T ransaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate tran sactions, such as
read and write, as well as certain types of ev ents. The Transaction Layer also manages
flow control of TLPs.
2.2.1.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of the Data Link Layer include link management, error detection, and
error correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to the Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. O n detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3 Physical La yer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
Figure 2-4. Packet Flow through the Layers
Datasheet, Volume 1 27
Interfaces
2.2.2 PCI Express* Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
.
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI -compatible region (consisting of the first 256 B
of a logical device's configuration space) and an extended PCI Express region
(consisting of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using 32-
bit operations (32-bit aligned) only.
See the PCI Express Base Specification for details of both the PCI-compatible and PCI
Express Enhanced configuration mechanisms and transaction rules.
Figure 2-5. PCI Express* Related Register Structures in Processor
PCI-PCI
Bridge
representing
root PCI
Express port
(Device 3)
PCI-PCI
Bridge
representing
root PCI
Express port
(Device 5)
PCI
Compatib le
Host Bridge
Device
(Device 0)
PCI
Express*
Device
PCI
Express*
Device
PCI Express
Port 0
PCI Express
Port 1
DMI
Interfaces
28 Datasheet, Volume 1
2.2.3 PCI Express* Ports and Bifurcation
The PCI Express interface on the processor is a single 16 lane (x16) port that can also
be configured at narrower widths. It may be bifurcated (refer to Table 6-5) and each
port may train to narrower widths. The PCI Express port is designed to be compliant
with the PCI Express Base Specification rev 2.0
2.2.3.1 PCI Express* Bifurcated Mode
When bifurcated, the signals that had previously been assigned to lanes 15:8 of the
single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary port. This
assignment applies whether the lane numbering is reversed or not. The controls for the
Secondary port and the associated virtual PCI- to-PCI bridge can be found in PCI Device
5. Refer to Table 6-5 for port bifurcation configuration settings and supported
configurations.
When the port is not bifurcated, Device 5 is hidden from the discovery mechanism used
in PCI enumeration, such that configuration of the device is neither possible nor
necessary.
2.3 Direct Media Interface (DMI)
DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane
PCI Express supporting up to 1 GB/s of bandwidth in each direction.
Note: Only DMI x4 configuration is supported.
2.3.1 DMI Error Flow
DMI can only generate SERR in response to errors—never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2 Processor/PCH Compatibility Assumptions
The processor is compatible with the PCH and is not compatible with any previous
(G)MCH or ICH products.
2.3.3 DMI Link Down
The DMI link going down is a fatal, unrecover able error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
Datasheet, Volume 1 29
Interfaces
2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH. The processor implements a PECI
interface to:
• Allow communication of processor thermal and other information to the PECI
master.
• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.
2.5 Interface Clocking
2.5.1 Internal Clocking Requirements
§ §
Table 2-4. Processor Reference Clock Requirements
Reference Input Clocks Input Frequency Associated PLL
BCLK[0]/BCLK#[0] 133 MHz Processor/Memory
PEG_CLK/PEG_CLK# 100 MHz PCI Express/DMI
Interfaces
30 Datasheet, Volume 1
Datasheet, Volume 1 31
Technologies
3Technologies
3.1 Intel® Virtualization Technology
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel Virtualization Technology (Intel VT-x) added hardware support in the
processor to improve the virtualization performance and robustness. Intel Virtualization
Technology for Directed I/O (Intel VT-d) adds chipset hardware implementation to
support and improve I/O virtualization performance and robustness.
Intel VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
http://www.intel.com/products/processor/manuals/index.htm.
The Intel VT-d spec and other VT documents can be referenced at:
http://www.intel.com/technology/virtualization/index.htm.
3.1.1 Intel® VT-x Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable
virtualized platforms. By using Intel VT-x, a VMM is:
•Robust—VMMs no longer need to use paravirtualization or binary translation. This
means that they will be able to run off-the-shelf OSs and applications without any
special steps.
•Enhanced—Intel VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.
•More reliable—Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
•More secure—The use of hardware transitions in the VMM strengthens the
isolation of VMs and further prevents corruption of one VM from affecting oth ers on
the same system.
3.1.2 Intel® VT-x Features
The processor core supports the following Intel VT-x features:
• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
Technologies
32 Datasheet, Volume 1
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
3.1.3 Intel® VT-d Objectives
The key Intel VT-d objectives are domain-based isolation and ha rdware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same operating system, or there can be multiple operating system
instances running on the same system—offering benefits such as system consolidation,
legacy migration, activity partitioning, or security.
3.1.4 Intel® VT-d Features
The processor supports the following Intel VT-d features:
• 48-bit maximum guest address width and 36-bit maximum host address width for
non-isoch traffic, in UP profiles
• 39-bit maximum guest address width and 36-bit maximum host address width for
isoch (Intel High Definition Audio isoch) traffic
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
— Support for fault collapsing based on Requester ID
• Support for both leaf and non-le af caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for page-selective IOTLB invalidation
• Support for queue-based invalidation interface
• Support for Intel VT-d read prefetching/snarfing (such as, translations within a
cacheline are stored in an internal buffer for reuse for subsequent transactions)
• Support for ARI (Alternate Requester ID—a PCI SIG ECR for increasing the function
number count in a PCI Express device) to support IOV devices
Datasheet, Volume 1 33
Technologies
3.1.5 Intel® VT-d Features Not Supported
The following features are not supported by the processor with Intel VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for interrupt remapping
• No support for advance fault reporting
• No support for super pages
• No support for 1 or 2 level page walks for isoch remap engine and 1, 2, or 3 level
walks for non-isoch remap engine
• No support for Intel VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
3.2 Intel® Trusted Execution Technology (Intel® TXT)
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust decision.
The Intel TXT platform determines the identity of the controlling environment by
accurately measuring and verifying the controlling software.
Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
• The launching of the Measured Launched Environment (MLE).
• The protection of the MLE from potential corruption.
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:
• Measured/Verified launch of the MLE.
• Mechanisms to ensure the above measurement is protected and stored in a secure
location.
• Protection mechanisms that allow the MLE to control attempts to modify itself.
Technologies
34 Datasheet, Volume 1
3.3 Intel® Hyper-Threading Technology
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology)
that allows an execution core to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled using the BIOS and
requires operating system support.
Intel recommends enabling Hyper-Threading Technology with Microsoft Windows
Vista*, Microsoft Windows* XP Professional/Windows* XP Home, and disabling Hyper-
Threading Technology using the BIOS for all previous versions of Windows operating
systems. For more information on Hyper-Threading Technology, see:
http://www.intel.com/products/ht/hyperthreading_more.htm.
3.4 Intel® Turbo Boost Technology
Intel® Turbo Boost Technology is a feature that allows the processor core to
opportunistically and automatically run faster than its rated operating frequency if it is
operating below power, temperature, and current limits. Maximum frequency is
dependent on the SKU and number of active cores. No special hardware support is
necessary for Intel Turbo Boost Technology. BIOS and the operating system can enable
or disable Intel Turbo Boost Technology.
Note: Intel Turbo Boost Technology may not be available on all SKUs. Refer to the processor
specification update for details.
§ §
Datasheet, Volume 1 35
Power Management
4Power Management
This chapter provides information on the following power management topics:
•ACPI States
• Processor Core
•IMC
• PCI Express*
4.1 ACPI States Supported
The ACPI states supported by the processor are described in this section.
4.1.1 System States
4.1.2 Processor Core/Package Idle States
4.1.3 Integrated Memory Controller States
State Description
G0/S0 Full On
G1 Suspend-to-RAM (STR).
G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
G3 Mechanical off. All power removed from system.
Table 4-1. Processor Core/Package State Support
State Description
C0 Active mode, processor executing code.
C1 AutoHALT state.
C1E AutoHALT state with lowest frequency and voltage operating point.
C3 Execution cores i n C3 flush thei r L1 instruc tion cache , L1 data c ache, and L 2
cache to the L3 shared cache. Clocks are shut off to the core.
C6 Execution cores in this state save their architectural state before removing
core voltage.
State Description
Power up CKE asserted. Active mode.
Pre-charge Power down CKE de-asserted (not self-refresh) with all banks closed.
Active Power down CKE de-asserted (not self-refresh) with minimum one bank active.
Self-Refresh CKE de-asserted using device self-refresh.
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36 Datasheet, Volume 1
4.1.4 PCI Express* Link States
4.1.5 Interface State Combinations
4.2 Processor Core Power Management
While executing code, Enhanced Intel SpeedS tep Technology optimizes the processor’ s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-
states have longer entry and exit latencies.
State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low power state – Low exit latency.
L1 Lowest Active Power Management - Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.
Table 4-2. G, S, and C State Combinations
Global (G)
State Sleep (S)
State
Processor
Core
(C) State
Processor
State System Clocks Description
G0 S0 C0 Full On On Full On
G0 S0 C1/C1E Auto-Halt On Auto-Halt
G0 S0 C3 Deep Sleep On Deep Sleep
G0 S0 C6 Deep Power
Down On Deep Power Down
G1 — Power off Power off Off, except RTC Suspend to RAM
G1 S4 Power off Power off Off, except RTC Suspend to Disk
G2 S5 P ower off Power off Off , except RTC Soft Off
G3 NA Power off Power off Power off Hard off
Datasheet, Volume 1 37
Power Management
4.2.1 Enhanced Intel® SpeedStep® Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps to an optimized voltage. This voltage is signaled by the VID[7:0] pins
to the voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the VID[7:0] pins.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
4.2.2 Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C -states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread level C-states are
available if Intel Hyper-Threading Technology is enabled.
Figure 4-1. Idle Power Management Breakdown of the Processor Cores
Processor Package State
Core 1 S t ate
Thread 1Thread 0
Core 0 S t ate
Thread 1Thread 0
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38 Datasheet, Volume 1
Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.
While individual threads can request low power C-state s, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolv ed
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C - state.
Note:
1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher.
Figure 4-2. Thread and Core C-State Entry and Exit
C1 C1 E C6C3
C0
MWAIT(C1), HLT
C0 MWAIT(C6),
P_LVL3 I/O R ead
MWAIT(C3),
P_LVL2 I/O Read
MWAIT(C1), H LT
(C1E En abled )
Table 4-3. Coordination of Thread Power States at the Core Level
Processor Core
C-State
Thread 1
C0 C1 C3 C6
Thread 0
C0 C0 C0 C0 C0
C1 C0 C11C11C11
C3 C0 C11C3 C3
C6 C0 C11C3 C6
Datasheet, Volume 1 39
Power Management
4.2.3 Requesting Low-Power Idle States
The primary software interfaces for requesting low-power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C -state request. Therefore, P_L VLx reads do not directly resu lt in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows:
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_L VLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MW AIT substate is always zero if I/O MWAIT redirection is used. By default, P_L VLx I/O
redirections enable the MW AIT 'break on EFLAGS .IF' feature that triggers a wakeup on
an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4 Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (such that,
Thread 0 requests C1E while thread1 requests C3, resulting in a core C1E state).
See Table 4-3.
• A core transitions to C0 state when:
— an interrupt occurs.
— there is an access to the monitored address if the state was entered using an
MWAIT instruction.
• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes
only that thread. However, since both threads are no longer at the same core C-
state, the core resolves to C0.
• For core C6, an interrupt coming into either thread wakes both threads into C0
state.
• Any interrupt coming into the processor package may wake any core.
Table 4-4. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes
P_LVL2 MWAIT(C3)
P_LVL3 MWAIT(C6) C6. No sub-states allowed
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40 Datasheet, Volume 1
4.2.4.1 Core C0 State
The normal operating state of a core where code is being executed.
4.2.4.2 Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2.
4.2.4.3 Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
4.2.4.4 Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_L VL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its v oltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
4.2.4.5 C-State Auto-Demotion
In general, deeper C-states, such as C6, have long latencies and have higher energy
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high.
Therefore, inc orrect or inefficient usag e of deeper C-st ates may have a ne gative impact
on power consumption. To increase residency and improve power consumption in
deeper C-states, the processor supports C-state auto-demotion.
There are two C-State auto-demotion options:
•C6 to C3
• C6/C3 To C1
The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s
residency history. Requests to deeper C-states are demoted to shallower C-states when
the original request doesn't make sense from a performance or energy perspective.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
Datasheet, Volume 1 41
Power Management
4.2.5 Package C-States
The processor supports C0, C1/C1E, C3, and C6 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor. The processor will put the DRAM into self-refresh in the package C3
and C6 states.
• For package C-states, the processor is not required to enter C0 before entering any
other C-state.
The processor exits a package C-state when a break event is detected. If DRAM was
allowed to go into self-refresh in package C3 or C6 state, it will be taken out of self-
refresh. Depending on the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Table 4-5 shows an example package C-state resolution for a dual-core processor.
Figure 4-3 summarizes package C-state transitions.
Note:
1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.
Table 4-5. Coordination of Core Power States at the Package Level
Package C-State Core 1
C0 C11C3 C6
Core 0
C0 C0 C0 C0 C0
C11C0 C11C11C11
C3 C0 C11C3 C3
C6 C0 C11C3 C6
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42 Datasheet, Volume 1
4.2.5.1 Package C0
The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 or C1 state or when the platform has
not granted permission to the processor to go into a low power state. Individual cores
may be in lower power idle states while the package is in C0.
4.2.5.2 Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAI T(C 1) and C1E auto-promotion is
enabled in IA32_MISC_ENA B LES.
No notification to the system occurs upon entry to C1/C1E.
Figure 4-3. Package C-State Entry and Exit
C0
C1 C6
C3
Datasheet, Volume 1 43
Power Management
4.2.5.3 Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
granted pe rmission b y the platform.
• The processor has requested the C6 state, but the platform only allowed C3.
In package C3-state, the L3 shared cache is snoopable.
4.2.5.4 Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 state, and the processor has been granted permission
by the platform.
In package C6 state, all cores save their architectural state and have their core
voltages reduced. The L3 shared cache is still powered and snoopable in this state.
4.3 IMC Power Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
4.3.1 Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as, DIMM connector is
unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals
are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and SCKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with a DIMM present,
the DIMM is not ensured to maintain data integrity.
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44 Datasheet, Volume 1
4.3.2 DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
4.3.2.1 Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2 C onditional Self-Refresh
The processor conditionally places memory into self -refresh in the C3 and C6 low power
states.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service. The target usage is shown in Table 4-6.
4.3.2.3 Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.
The processor core controller can be configured to put the devices in active power down
(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with
all pages closed). Precharge power down provides greater power savings but has a
bigger performance impact, since all pages will first be closed before putting the
devices in power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
Table 4-6. Targeted Memory State Conditions
Mode Memory State with External Graphics
C0, C1, C1E Dynamic memory rank power down based on idle conditions.
C3, C6 Dynamic memory rank power down based on idle conditions
If there are no memory requests, then enter self-refresh. Otherwise, use dynamic memory
rank power down based on idle conditions.
S4 Memory power down (contents lost)
Datasheet, Volume 1 45
Power Management
4.3.2.4 DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM
control signals, such as CS#, CKE, and ODT for unpopulated DIMM slots.
The I/O buffer for an unused signal should be tristated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4 PCI Express* Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L3 Ready state.
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46 Datasheet, Volume 1
Thermal Management
48 Datasheet, Volume 1
Datasheet, Volume 1 49
Signal Description
6Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type.
The signal description also includes the type of buffer used for the particular signal.
Notations Signal Type
IInput Pin
OOutput Pin
I/O Bi-directional Input/Output Pin
Table 6-1. Signal Description Buffer Types
Signal Description
PCI Express* PCI Express* interface signals. These signal s are compatible with the PCI Express 2.0
Signaling Environment AC Specifications and are AC Coupled. The buffers are not
3.3 V tolerant. Refer to the PCI Express Specification.
FDI Intel Flexible Display Interface signals. These signals are compatible with PCI Express
2.0 Signaling Environment AC Specificatio ns , but are DC coupled. The buffers are not
3.3 V tolerant.
DMI Direct Media Interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3 V tolerant.
CMOS CMOS buffers. 1.1 V tolerant
DDR3 DDR3 buffers: 1.5 V tolerant
GTL Gunning Transceiver Logic signaling technology
TAP Test Access Port signal
Analog Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Ref Voltage reference signal
Asynch This signal is asynchronous and has no timing relationship with any reference clock.
Signal Description
50 Datasheet, Volume 1
6.1 System Memory Interface
Table 6-2. Memory Channel A
Signal Name Description Direction Type
SA_BS[2:0] Bank Select: These signals define which banks are
selected within each SDRAM rank. O DDR3
SA_CAS# CAS Control Signal: This signal is used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SDRAM
Commands. O DDR3
SA_CK#[1:0] SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement. O DDR3
SA_CK#[3:2] SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement. O DDR3
SA_CK[1:0]
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
O DDR3
SA_CK[3:2]
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
O DDR3
SA_CKE[3:0]
Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
during STR
O DDR3
SA_CS#[3:0] Chip Select: (1 per r ank) Thes e signal s are used to select
particular SDRAM components during the active state.
There is one Chip Select for each SDRAM rank. O DDR3
SA_CS#[7:4]
These signals are only u sed for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SA_CS#[7:6] are used as the on die
termination for the first DIMM.
O DDR3
SA_DM[7:0]
Data Ma sk: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes.
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SA_DM[7:0] for every data byte lane.
Note: These signals are not used by the Intel Xeon
processor 3400 series. They are connected to VSS on the
package.
SA_DQ[63:0] Data Bus: Channel A data signal interface to the SDRAM
data bus. I/O DDR3
SA_DQS[8:0]
SA_DQS#[8:0]
Data Strobes: SA_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SA_DQS[8:0] and its
SA_DQS#[8:0] during read and write transactions. I/O DDR3
SA_ECC_CB[7:0] Data Lines for ECC Check Byte. I/O DDR3
SA_MA[15:0] Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM. O DDR3
SA_ODT[3:0] On Die Termination: Active Termination Control O DDR3
SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands. O DDR3
SA_WE# Write Enable Control Signal: This signal is used with
SA_RAS# and SA_CAS# (alon g with SA_CS#) to define
the SDRAM Commands. O DDR3
Datasheet, Volume 1 51
Signal Description
Table 6-3. Memory Channel B
Signal Name Descriptio n Direction Type
SB_BS[2:0] Bank Select: These signals define which banks are
selected within each SDRAM rank. ODDR3
SB_CAS# CAS Control Signal: This signal is used with SB_RAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands. ODDR3
SB_CK#[1:0] SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement. ODDR3
SB_CK#[3:2] SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement. ODDR3
SB_CK[1:0]
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
ODDR3
SB_CK[3:2]
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
ODDR3
SB_CKE[3:0]
Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
during STR
ODDR3
SB_CS#[3:0] Chip Select: (1 p er rank) Th ese signals are used to sele ct
particular SDRAM components during the active state.
There is one Chip Select for each SDRAM rank. ODDR3
SB_CS#[7:4]
These signals are only used for processors and platfo rms
that have Registered DIMM support. These s i gnals are
used to select particular SDRAM components during the
active state and SB_CS#[7:6] are used as the on die
termination for the first DIMM.
ODDR3
SB_DM[7:0]
Data Mask: These signals ar e used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes. When activated during writes, the
corresp onding data groups in the SDRAM a re masked.
There is one SB_DM[7:0] for every data byte lane.
Note: These signals are not used by the Intel Xeon
processor 3400 series. They are connected to VSS on the
package.
SB_DQ[63:0] Data Bus: Channel B data signal interface to the SDRAM
data bus. I/O DDR3
SB_DQS[8:0]
SB_DQS#[8:0]
Data Strobes: SB_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SB_DQS[8:0] and its
SB_DQS#[8:0] during read and write transactions. I/O DDR3
SB_ECC_CB[7:0] Data Lines for ECC Check Byte. I/O DDR3
SB_MA[15:0] Memory Address: These signals are u sed to provide the
multiplexed row and column address to the SDRAM. ODDR3
SB_ODT[3:0] On-Die Termination: Active Termination Control. ODDR3
SB_RAS# RAS Control Signal: This signal is used with SB_CAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands. ODDR3
SB_WE# Write Enable Control Signal: This signal is used with
SB_RAS# and SB_CAS# (along with SB_CS#) to define
the SDRAM Commands. ODDR3
Signal Description
52 Datasheet, Volume 1
6.2 Memory Reference and Compensation
6.3 Reset and Miscellaneous Signals
Table 6-4. Memory Reference and Compensation
Signal Name Description Direction Type
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ Channel A and B Output DDR3 DIMM DQ Refere nce Voltage. OAnalog
SM_RCOMP[2:0] System Memory Impedance Compensation. IAnalog
Table 6-5. Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name Description Direction Type
CFG[17:0]
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board.
•CFG[1:0]: PCI Express Bifurcation
Intel Xeon® processor 3400 series:
11 = 1 x16 PCI Express
10 = 2 x8 PCI Express
01 = 4 x4 PCI Express (requires Intel 3420 or
3400 Chipset)
00 = Reserved
•CFG[2]: Reserved configuration land. A test point
may be placed on the board for this land.
•CFG[3]: Reserved configuration land.
•CFG[6:4]: Reserved configuration lands. A test
point may be placed on the board for this land.
•CFG[17:7]: Reserved configuration lands. Intel
does not recommend a test point on the board for
this land.
ICMOS
COMP0 Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement. IAnalog
COMP1 Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement. IAnalog
COMP2 Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement. IAnalog
COMP3 Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement. IAnalog
FC_x Future Compatibility (FC) signals are signals that are
available for compatibility with other processors. A test
point may be placed on the board for these lands.
PM_EXT_TS#[1:0]
External Thermal Sensor Input: If the system
temperature reaches a dangerously high value, this
signal can be used to trigger the start of system
memory throttling. ICMOS
PM_SYNC Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor. ICMOS
Datasheet, Volume 1 53
Signal Description
6.4 PCI Express* Based Interface Signals
6.5 DMI—Processor to PCH Serial Interface
RESET_OBS# This signal is an indication of the processor being reset. OAsynch
CMOS
RSTIN# Reset In: When ass erted, this signal will asynchronously
reset the processor logic. This s ignal is connected to the
PLTRST# output of the PCH. ICMOS
RSVD RESERVED. Must be left unconnected on the board.
Intel does not recommend a test point on the board for
this land.
RSVD_NCTF RESERVED/Non-Critical to Function: Pin for package
mechanical reliability. A test point may be placed on the
board for this land.
RSVD_TP RESERVED - Test Point. A test poin t may be placed on the
board for this land.
SM_DRAMRST# DDR3 DRAM Reset: Reset signal from processor to
DRAM devices. One common to all channels. ODDR3
Table 6-6. PCI Express* Based Interface Sign als
Signal Name Description Direction Type
PEG_ICOMPI PCI Express Current Compensation. I Analog
PEG_ICOMPO PCI Express Current Compensation. I Analog
PEG_RBIAS PCI Express Resistor Bias Control. I Analog
PEG_RCOMPO PCI Express Resistance Compensation. I Analog
PEG_RX[15:0]
PEG_RX#[15:0] PCI Express Receive Differential Pair. IPCI
Express
PEG_TX[15:0]
PEG_TX#[15:0] PCI Express Transmit Differential Pair. OPCI
Express
Table 6-7. DMI—Processor to PCH Serial Interface
Signal Name Description Direction Type
DMI_RX[3:0]
DMI_RX#[3:0] DMI input from PCH: Direct Media Interface receive
differential pair. IDMI
DMI_TX[3:0]
DMI_TX#[3:0] DMI output to PCH: Direct Media Interface transmit
differential pair. ODMI
Table 6-5. Reset and Miscellaneous Signals (Sheet 2 of 2)
Signal Name Description Direc tion Type
Signal Description
54 Datasheet, Volume 1
6.6 PLL Signals
6.7 Intel® Flexible Display Interface Signals
Note: The signals noted below as not being used are included for reference to define all LGA
1156 land locations. These signals will be used by future processors that are
compatible with LGA 1156 platforms.
Table 6-8. PLL Signals
Signal Name Description Direction Type
BCLK[0]
BCLK#[0] Differential bus clock input to the processor. I Diff Clk
BCLK[1]
BCLK#[1] Differential bus clock input to the processor. Reserved
for possible future use. I Diff Clk
BCLK_ITP
BCLK_ITP# Buffered differential bus clock pair to ITP.. O Diff Clk
PEG_CLK
PEG_CLK#
Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock.
This clock is used to generate the clocks necessary for
the support of PCI Express. This also is the reference
clock for Intel® Flexible Display Interface.
I Diff Clk
Table 6-9. Intel® Flexible Display Interface
Signal Name Description Direction Type
FDI_FSYNC[0] Intel® Flexible Display Interface Frame Sync—Pipe A.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
FDI_FSYNC[1] Intel® Flexible Display Interface Frame Sync—Pipe B.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
FDI_INT Intel® Flexible Display Interface Hot Plug Interrupt.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
FDI_LSYNC[0] Intel® Flexible Display Interface Line Sync—Pipe A.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
FDI_LSYNC[1] Intel® Flexible Display Interface Line Sync—Pipe B.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
FDI_TX[3:0]
FDI_TX#[3:0]
Intel® Flexible Display Interface Transmit Differential
Pair—Pipe A..
Note: These signals are not used by the processor.
They are connected to VSS on the package.
FDI_TX[7:4]
FDI_TX#[7:4]
Intel® Flexible Display Interface Transmit Differential
Pair—Pipe B.
Note: These signals are not used by the processor.
They are connected to VSS on the package.
Datasheet, Volume 1 55
Signal Description
6.8 JTAG/ITP Signals
Table 6-10. JTAG/ITP
Signal Name Description Direction Type
BPM#[7:0]
Breakpoint and Performance Monitor Signals: Outputs
from the processor that indicate the status of
breakpoints and programmable counters used for
monitoring processor performance.
I/O GTL
DBR#
DBR# is used only in systems where no debug port is
implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can
drive system reset.
O
PRDY# PRDY# is a processor output used by debug tools to
determine processor debug readiness. OAsynch
GTL
PREQ# PREQ# is used by debug tools to request debug
operation of the processor. IAsynch
GTL
TCK TCK (Test Clock) provides the clock input for the
processor Test Bus (also known as the Test Access Port). ITAP
TDI TDI (Test Data In) transfers serial test data into the
processor. TDI provides the serial input needed for JT AG
specification support. ITAP
TDI_M TDI_M (Test Data In) transfers serial test data into the
processor. TDI_M provides the serial input needed for
JTAG specification support. ITAP
TDO TDO (Test Data Out) transfers serial test data out o f th e
processor. TDO provides the serial output needed for
JTAG specification support. OTAP
TDO_M TDO_M (Test Data Out) transfers serial test data out of
the processor. TDO_M provides th e serial output nee ded
for JTAG specification support. OTAP
TMS TMS (Test Mode Select) is a JTAG specification support
signal used b y debug tools . ITAP
TRST# TRST# (Test Reset) resets the Test Access Port (TAP)
logic. TRST# mus t be driven low during power on R eset. ITAP
Signal Description
56 Datasheet, Volume 1
6.9 Error and Thermal Protection
Table 6-11. Error and Thermal Protection
Signal Name Description Direction Type
CATERR#
Catastrophic Error: This signal indicates that the system
has experienced a catastrophic error an d cannot continue
to operate. The proce ss or will set this for n on-recoverable
machine check errors or other unrecoverable internal
errors. Since this is an I/O pin, external agents are allowed
to assert this pin that will cause the processor to take a
machine check exception.
CA TERR# is used for signaling the following types of errors:
• Legacy MCERR: CATERR# is asserted for 16 BCLKs.
• Legacy IERR: CA TERR# remains asserted until w arm or
cold reset.
I/O GTL
PECI PECI (Platform Environmen t Co ntro l Inte rface ) is t he s er ial
sideband interface to the processor and is used primarily
for thermal, power, and error management. I/O Asynch
PROCHOT#
PROCHOT# goes active when the processor temperature
monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit has
been activated, if enabled. This signal can also be driven to
the processor to activate the Thermal Control Circuit. This
signal does not have on-die termination and must be
terminated on the system board.
I/O Asynch
GTL
PSI#
Processor Power Status Indicator: This signal is asserted
when maximum possible processor core current
consumption is less than 15 A. Assertion of this signal is an
indication that the VR control ler doe s not currently ne ed to
be able to provide ICC above 15 A, and the VR controller
can use this information to move to more efficient
operating point. This signal will de-assert at least 3.3 s
before the current consumption will exceed 15 A. The
minimum PSI# assertion and de-assertion time is 1 BCLK.
OAsynch
CMOS
THERMTRIP#
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The
processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is
signaled to the system by the THERMTRIP# pin.
OAsynch
GTL
Datasheet, Volume 1 57
Signal Description
6.10 Power Sequencing
6.11 Processor Core Power Signals
Table 6-12. Power Sequen cing
Signal Name Description Direction Type
SKTOCC#
SKTOCC# (Sock et Occupied): This signal will be pulled to
ground on the p rocess or packag e. T here is no co nnectio n
to the processor silicon for this signal. System board
designers may use this signal to determine if the
processor is present.
O
SM_DRAMPWROK SM_DRAMPWROK processor input: This signal connects to
PCH DRAMPWROK. IAsynch
CMOS
TAPPWRGOOD Power good for ITP. Indicates to the ITP when the TAP can
be accessed. OAsynch
CMOS
VCCPWRGOOD_0
VCCPWRGOOD_1
VCCPWRGOOD_0 and VCCPWRGOOD_1 (Power Good)
Processor Input: The processor requires these signals to
be a clean indication that VCC, VCCPLL, VTT, VAXG supplies
are stable and within their specifications and that BCLK is
stable and has been running for a minimum number of
cycles. These signals must then transition monotonically
to a high state. These signals can be driven inactive at
any time, but BCLK and power must again be stable
before a subsequent ri sing ed ge of VCC PWRGOOD_0 and
VCCPWRGOOD_1. These signals should be tied together
and connected to the CPUPWRGD output signal of the
PCH.
IAsynch
CMOS
VTTPWRGOOD
The processor requires this input signal to be a clean
indication that the VTT power supply is stable and within
specifications. 'Clean' implies that the signal will remain
low (capable of sinking leakage curr ent), without glitche s,
from the time that the power s upplies are tur ned on until
they come within specification. The signal must then
transition mono tonically to a high state. Note that it is not
valid for VTTPWRGOOD to be de-asserted while
VCCPWRGOOD_0 and VCCPWRGOOD_1 are asserted.
IAsynch
CMOS
Table 6-13. Processor Core Power Signals (Sheet 1 of 2)
Signal Name Description Direction Type
ISENSE Current sense from VRD11.1 Compliant Regulator to the
processor core. IAnalog
VCC Processor core power supply. The voltage supplied to
these pins is determined by the VID pins. PWR
VCC_NCTF VCC/Non-Critical to Function: Pin for package
mechanical reliability. PWR
VCC_SENSE
VCC_SENSE and VSS_SENSE provide an isolated, lo w
impedance connection to the processor core voltage
and ground. They can be used to sense or measure
voltage near the silicon.
Analog
Signal Description
58 Datasheet, Volume 1
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
VID[7:0] (Voltage ID) are used to support automatic
selection of power supply voltages (VCC). Refer to the
Voltage Regulator-Down (VRD) 11.1 Design Guidelines
for more information. The voltage supply for these
signals must be valid before the VR can supply VCC to
the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID signals
become valid. The VR must supply the voltage that is
requested by the signals, or disable itself.
VID7 and VID6 should be tied separately to VSS using a
1k resistor (This value is latched on the rising edge of
VTTPWRGOOD).
CSC[2:0]—Current Sense C onfigur ation bits, for ISENSE
gain setting. See Voltage Regulator-Down (VRD) 11.1
Design Guidelines for gain setting information. This
value is latched on the rising edge of VTTPWRGOOD.
MSID[2:0] (Market Segment Identification) are used to
indicate the maximum platform capability to the
processor. A processor will only boot if the MSID[2:0]
pins are strapped to the appropriate setting (or higher)
on the platform (see Table 7-3 for MSID encodings).
MSID is used to help protect the platform by preventing
a higher power processor from booting in a platform
designed for lower power processors. MSID[2:0] are
latched on the rising edge of VTTPWRGOOD.
I/O CMOS
VSS_SENSE
VCC_SENSE and VSS_SENSE provide an isolated, low
impedance connection to the processor core voltage
and ground. They can be used to sense or measure
voltage near the silicon.
Analog
VSS_SENSE_VTT
VTT_SENSE and VSS_SENSE_VTT provide an isolated,
low impedance co nnection to the proces sor VTT voltage
and ground. They can be used to sense or measure
voltage near the silicon.
Analog
VTT Processor power for the memory controlle r, shared cache
and I/O (1.1 V). PWR
VTT_SELECT The VTT_SELECT signal is used to select the correct VTT
voltage level for the processor. The processor will be
configured to drive a low voltage level for VTT_SELECT. OCMOS
VTT_SENSE
VTT_SENSE and VSS_SENSE_VTT provide an isolated,
low impedance co nnection to the proces sor VTT voltage
and ground. They can be used to sense or measure
voltage near the silicon.
Analog
Table 6-13. Processor Co re Power Signals (Sheet 2 of 2)
Signal Name Description Direction Type
Datasheet, Volume 1 59
Signal Description
6.12 Graphics and Memory Core Power Signals
Note: The signals noted below as not being used are included for reference to define all LGA
1156 land locations. These signals will be used by future processors that are
compatible with LGA 1156 platforms.
Table 6-14. Graphics and Memory Power Signals
Signal Name Description Direction Type
GFX_DPRSLPVR
Integrated gr aphics output signal to a VRD11.1 compliant
VR. When asserted this signal indicates that the
integrated graphics is in render suspend mode. This
signal is also used to control render suspend state exit
slew rate.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
GFX_IMON
Current Sense from an VRD11.1 compliant VR to the
integrated graphics.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
GFX_VID[6:0]
GFX_VID[6:0] (Voltage ID) pins are used to support
automatic selection of nominal voltages (V AXG). Thes e are
CMOS signals that are driven by the processor. The VID
code output by VID[6:0] and associated voltages are
given in Chapter 7.
Note: These signals are not used by the processor. They
are connected to VTT on the package.
GFX_VR_EN
Integrated graphics output signal to integrated graphics
VR. This signal is used as an on/off control to
enable/disable the integrated graphics VR.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
VAXG Graphics core power supply.
Note: These signals are not used by the processor. They
are no connect on the package.
VAXG_SENSE
VAXG_SENSE and VSSAXG_SENSE provide an isolated,
low impedance connection to the VAXG voltage and
ground. They can be used to sense or measure voltage
near the silicon.
Note: This signal is not used by the processor. It is a no
connect on the package.
VCCPLL VCCPLL provides isolated power for internal processor
PLLs. PWR
VDDQ Processor I/O supply voltage for DDR3. PWR
VSSAXG_SENSE
VAXG_SENSE and VSSAXG_SENSE provide an isolated,
low impedance connection to the VAXG voltage and
ground. They can be used to sense or measure voltage
near the silicon.
Note: This signal is not used by the processor. It is
connected to VSS on the package.
Signal Description
60 Datasheet, Volume 1
6.13 Ground and NCTF
6.14 Processor Internal Pull Up/Pull Down
§ §
Table 6-15. Ground and NCTF
Signal Name Description Direction Type
VSS VSS are the ground pins for the processor and should be
connected to the system ground plane. GND
CGC_TP_NCTF
Corner Ground Co nnection: This land may be used to tes t
for connection to ground. A test point may be placed on
the board for this land. This land is considered Non-
Critical to Function.
Table 6-16. Processor Internal Pull Up/P ull Down
Signal Name Pull Up/Pull
Down Rail Value
SM_DRAMPWROK Pull Down VSS 10–20 k
VCCPWRGOOD_0
VCCPWRGOOD_1 Pull Down VSS 10–20 k
VTTPWRGOOD Pull Down VSS 10–20 k
BPM#[7:0] Pull Up VTT 44–55
TCK Pull Up VTT 44–55
TDI Pull Up VTT 44–55
TMS Pull Up VTT 44–55
TRST# Pull Up VTT 1–5 k
TDI_M Pull Up VTT 44–55
PREQ# Pull Up VTT 44–55
CFG[17:0] Pull Up VTT 5–14 k
Datasheet, Volume 1 61
Electrical Specifications
7Electrical Specifications
7.1 Power and Ground Lands
The processor has VCC, VTT, VDDQ, VCCPLL, VAXG, and VSS (ground) inputs for on-
chip power distribution. All power lands must be connected to their respective
processor power planes, while all VSS lands must be connected to the system ground
plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
The VCC lands must be supplied with the voltage determined by the processor Voltage
IDentification (VID) signals. Table 7-1 specifies the voltage level for the various VIDs.
7.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors,
supply current during longer lasting changes in current demand (for example, coming
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
Caution: Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in Table 7-5. Failure to do so can result in timing violations or
reduced lifetime of the processor. For further information and design guidelines, refer
to the Voltage Regulator Down (VRD) 11.1 Design Guidelines.
7.2.1 Voltage Rail Decoupling
The voltage regulator solution needs to provide:
• bulk capacitance with low effective series resistance (ESR).
• a low interconnect resistance from the regulator to the socket.
• bulk decoupling to compensate for large current swings generated during power-
on, or low-power idle state entry/exit.
The power delivery solution must ensure that the voltage an d current specifications are
met, as defined in Table 7-5.
Electrical Specifications
62 Datasheet, Volume 1
7.3 P rocessor Clocking (BCLK[0], BCLK#[0])
The processor uses a differential clock to gene rate the processor core(s) operating
frequency, memory controller frequency, and other internal clocks. The processor core
frequency is determined by multiplying the processor core ratio by 133 MHz. Clock
multiplying within the processor is provided by an internal phase locked loop (PLL) that
requires a constant frequency input, with exceptions for Spread Spectrum Clocking
(SSC).
The processor maximum core frequency is configured during power-on reset by using
its manufacturing default value. This value is the highest core multiplier at which the
processor can operate. If lower maximu m speeds are desired, the appropriate ratio can
be configured using the FLEX_RATIO MSR.
7.3.1 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 7-6 for DC
specifications.
7.4 VCC Voltage Identification (VID)
The VID specification for the processor is defined by the Voltage Regulator Down (VRD)
11.1 Design Guidelines. The processor uses eight voltage identification signals,
VID[7:0], to support automatic selection of voltages. Table 7-1 specifies the voltage
level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage
level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0]
= 11111111), or the voltage regulation circuit cannot supply the voltage that is
requested, the voltage regulator must disable itself. See the Voltage Regulator Down
(VRD) 11.1 Design Guidelines for further details. VID signals are CMOS push/pull
drivers. Refer to Table 7-9 for the DC specifications for these signals. The VID codes will
change due to temperature and/or current load changes to minimize the power of the
part. A voltage range is provided in Table 7-5. The specifications are set so that one
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Table 7-5. The processor provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This
will represent a DC shift in the loadline.
Note: A low-to-high or high-to-low voltage state change will result in as many VID tr ansitions
as necessary to reach the target core voltage. Transitions above the maximum
specified VID are not permitted. One VID transition occurs in 1.25 us. Table 7-1
includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be
maintained.
The VR used must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
Table 7-5 and Table 7-7. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines
for further details.
Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dual
purpose and are sampled during reset. Refer to the signal description table in
Chapter 6 and Table 7-3 for further information.
Datasheet, Volume 1 63
Electrical Specifications
Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 1 of 3)
VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX
0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1.04375
0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1.03750
0 0 0 0 0 0 1 0 1.60000 0 1 0 1 1 1 0 1 1.03125
0 0 0 0 0 0 1 1 1.59375 0 1 0 1 1 1 1 0 1.02500
0 0 0 0 0 1 0 0 1.58750 0 1 0 1 1 1 1 1 1.01875
0 0 0 0 0 1 0 1 1.58125 0 1 1 0 0 0 0 0 1.01250
0 0 0 0 0 1 1 0 1.57500 0 1 1 0 0 0 0 1 1.00625
0 0 0 0 0 1 1 1 1.56875 0 1 1 0 0 0 1 0 1.00000
0 0 0 0 1 0 0 0 1.56250 0 1 1 0 0 0 1 1 0.99375
0 0 0 0 1 0 0 1 1.55625 0 1 1 0 0 1 0 0 0.98750
0 0 0 0 1 0 1 0 1.55000 0 1 1 0 0 1 0 1 0.98125
0 0 0 0 1 0 1 1 1.54375 0 1 1 0 0 1 1 0 0.97500
0 0 0 0 1 1 0 0 1.53750 0 1 1 0 0 1 1 1 0.96875
0 0 0 0 1 1 0 1 1.53125 0 1 1 0 1 0 0 0 0.96250
0 0 0 0 1 1 1 0 1.52500 0 1 1 0 1 0 0 1 0.95626
0 0 0 0 1 1 1 1 1.51875 0 1 1 0 1 0 1 0 0.95000
0 0 0 1 0 0 0 0 1.51250 0 1 1 0 1 0 1 1 0.94375
0 0 0 1 0 0 0 1 1.50625 0 1 1 0 1 1 0 0 0.93750
0 0 0 1 0 0 1 0 1.50000 0 1 1 0 1 1 0 1 0.93125
0 0 0 1 0 0 1 1 1.49375 0 1 1 0 1 1 1 0 0.92500
0 0 0 1 0 1 0 0 1.48750 0 1 1 0 1 1 1 1 0.91875
0 0 0 1 0 1 0 1 1.48125 0 1 1 1 0 0 0 0 0.91250
0 0 0 1 0 1 1 0 1.47500 0 1 1 1 0 0 0 1 0.90625
0 0 0 1 0 1 1 1 1.46875 0 1 1 1 0 0 1 0 0.90000
0 0 0 1 1 0 0 0 1.46250 0 1 1 1 0 0 1 1 0.89375
0 0 0 1 1 0 0 1 1.45625 0 1 1 1 0 1 0 0 0.88750
0 0 0 1 1 0 1 0 1.45000 0 1 1 1 0 1 0 1 0.88125
0 0 0 1 1 0 1 1 1.44375 0 1 1 1 0 1 1 0 0.87500
0 0 0 1 1 1 0 0 1.43750 0 1 1 1 0 1 1 1 0.86875
0 0 0 1 1 1 0 1 1.43125 0 1 1 1 1 0 0 0 0.86250
0 0 0 1 1 1 1 0 1.42500 0 1 1 1 1 0 0 1 0.85625
0 0 0 1 1 1 1 1 1.41875 0 1 1 1 1 0 1 0 0.85000
0 0 1 0 0 0 0 0 1.41250 0 1 1 1 1 0 1 1 0.84374
0 0 1 0 0 0 0 1 1.40625 0 1 1 1 1 1 0 0 0.83750
0 0 1 0 0 0 1 0 1.40000 0 1 1 1 1 1 0 1 0.83125
0 0 1 0 0 0 1 1 1.39375 0 1 1 1 1 1 1 0 0.82500
0 0 1 0 0 1 0 0 1.38750 0 1 1 1 1 1 1 1 0.81875
0 0 1 0 0 1 0 1 1.38125 1 0 0 0 0 0 0 0 0.81250
0 0 1 0 0 1 1 0 1.37500 1 0 0 0 0 0 0 1 0.80625
Electrical Specifications
64 Datasheet, Volume 1
0 0 1 0 0 1 1 1 1.36875 1 0 0 0 0 0 1 0 0.80000
0 0 1 0 1 0 0 0 1.36250 1 0 0 0 0 0 1 1 0.79375
0 0 1 0 1 0 0 1 1.35625 1 0 0 0 0 1 0 0 0.78750
0 0 1 0 1 0 1 0 1.35000 1 0 0 0 0 1 0 1 0.78125
0 0 1 0 1 0 1 1 1.34375 1 0 0 0 0 1 1 0 0.77500
0 0 1 0 1 1 0 0 1.33750 1 0 0 0 0 1 1 1 0.76875
0 0 1 0 1 1 0 1 1.33125 1 0 0 0 1 0 0 0 0.76250
0 0 1 0 1 1 1 0 1.32500 1 0 0 0 1 0 0 1 0.75625
0 0 1 0 1 1 1 1 1.31875 1 0 0 0 1 0 1 0 0.75000
0 0 1 1 0 0 0 0 1.31250 1 0 0 0 1 0 1 1 0.74375
0 0 1 1 0 0 0 1 1.30625 1 0 0 0 1 1 0 0 0.73750
0 0 1 1 0 0 1 0 1.30000 1 0 0 0 1 1 0 1 0.73125
0 0 1 1 0 0 1 1 1.29375 1 0 0 0 1 1 1 0 0.72500
0 0 1 1 0 1 0 0 1.28750 1 0 0 0 1 1 1 1 0.71875
0 0 1 1 0 1 0 1 1.28125 1 0 0 1 0 0 0 0 0.71250
0 0 1 1 0 1 1 0 1.27500 1 0 0 1 0 0 0 1 0.70625
0 0 1 1 0 1 1 1 1.26875 1 0 0 1 0 0 1 0 0.70000
0 0 1 1 1 0 0 0 1.26250 1 0 0 1 0 0 1 1 0.69375
0 0 1 1 1 0 0 1 1.25625 1 0 0 1 0 1 0 0 0.68750
0 0 1 1 1 0 1 0 1.25000 1 0 0 1 0 1 0 1 0.68125
0 0 1 1 1 0 1 1 1.24375 1 0 0 1 0 1 1 0 0.67500
0 0 1 1 1 1 0 0 1.23750 1 0 0 1 0 1 1 1 0.66875
0 0 1 1 1 1 0 1 1.23125 1 0 0 1 1 0 0 0 0.66250
0 0 1 1 1 1 1 0 1.22500 1 0 0 1 1 0 0 1 0.65625
0 0 1 1 1 1 1 1 1.21875 1 0 0 1 1 0 1 0 0.65000
0 1 0 0 0 0 0 0 1.21250 1 0 0 1 1 0 1 1 0.64375
0 1 0 0 0 0 0 1 1.20625 1 0 0 1 1 1 0 0 0.63750
0 1 0 0 0 0 1 0 1.20000 1 0 0 1 1 1 0 1 0.63125
0 1 0 0 0 0 1 1 1.19375 1 0 0 1 1 1 1 0 0.62500
0 1 0 0 0 1 0 0 1.18750 1 0 0 1 1 1 1 1 0.61875
0 1 0 0 0 1 0 1 1.18125 1 0 1 0 0 0 0 0 0.61250
0 1 0 0 0 1 1 0 1.17500 1 0 1 0 0 0 0 1 0.60625
0 1 0 0 0 1 1 1 1.16875 1 0 1 0 0 0 1 0 0.60000
0 1 0 0 1 0 0 0 1.16250 1 0 1 0 0 0 1 1 0.59375
0 1 0 0 1 0 0 1 1.15625 1 0 1 0 0 1 0 0 0.58750
0 1 0 0 1 0 1 0 1.15000 1 0 1 0 0 1 0 1 0.58125
0 1 0 0 1 0 1 1 1.14375 1 0 1 0 0 1 1 0 0.57500
0 1 0 0 1 1 0 0 1.13750 1 0 1 0 0 1 1 1 0.56875
0 1 0 0 1 1 0 1 1.13125 1 0 1 0 1 0 0 0 0.56250
0 1 0 0 1 1 1 0 1.12500 1 0 1 0 1 0 0 1 0.55625
Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3)
VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX
Datasheet, Volume 1 65
Electrical Specifications
Notes:
1. The MSID[2:0] signals are provided to indicate the maximum platform capability to the processor.
2. 2009A processors ha ve thermal requirements that are equi valent to those of the Intel ® Core™2 Duo E8000
processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and Design
Guidelines for additional information (see Section 1.7).
3. 2009B processors have thermal requirements that are equivalent to those of the Intel® Core™2 Quad
Q9000 processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and
Design Guidelines for additional information (see Section 1.7).
0 1 0 0 1 1 1 1 1.11875 1 0 1 0 1 0 1 0 0.55000
0 1 0 1 0 0 0 0 1.11250 1 0 1 0 1 0 1 1 0.54375
0 1 0 1 0 0 0 1 1.10625 1 0 1 0 1 1 0 0 0.53750
0 1 0 1 0 0 1 0 1.10000 1 0 1 0 1 1 0 1 0.53125
0 1 0 1 0 0 1 1 1.09375 1 0 1 0 1 1 1 0 0.52500
0 1 0 1 0 1 0 0 1.08750 1 0 1 0 1 1 1 1 0.51875
0 1 0 1 0 1 0 1 1.08125 1 0 1 1 0 0 0 0 0.51250
0 1 0 1 0 1 1 0 1.07500 1 0 1 1 0 0 0 1 0.50625
0 1 0 1 0 1 1 1 1.06875 1 0 1 1 0 0 1 0 0.50000
0 1 0 1 1 0 0 0 1.06250 1 1 1 1 1 1 1 0 OFF
0 1 0 1 1 0 0 1 1.05625 1 1 1 1 1 1 1 1 OFF
0 1 0 1 1 0 1 0 1.05000
Table 7-2. Market Segment Selection Truth Table for MSID[2:0]
MSID2 MSID1 MSID0 Description1
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 2009A processors supported 2
1 1 0 2009B processors supported 3
1 1 1 Reserved
Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 3 of 3)
VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX VID
7VID
6VID
5VID
4VID
3VID
2VID
1VID
0VCC_MAX
Electrical Specifications
66 Datasheet, Volume 1
7.5 Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals sh oul d be ro uted to a test point
• RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to VCC, VTT, VDDQ, VCCPLL, VSS, or to any other
signal (including each other) may result in component malfunction or incompatibility
with future processors. See Chapter 8 for a land listing of the processor and the
location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs may be left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For details, see Table 7-9.
7.6 Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals, have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Datasheet, Volume 1 67
Electrical Specifications
Table 7-3. Signal Groups (Sheet 1 of 2)1
Signal Group Alpha
Group Type Signals
System Reference Clock
Differential (a) CMOS Input BCLK[0], BCLK#[0],
BCLK[1], BCLK#[1],
PEG_CLK, PEG_CLK#
Differential (b) CMOS Output BCLK_ITP, BCLK_ITP#
DDR3 Reference Clocks2
Differential (c) DDR3 Output SA_CK[3:0], SA_CK#[3:0]
SB_CK[3:0], SB_CK#[3:0]
DDR3 Command Signals2
Single Ended (d) DDR3 Output
SA_RAS#, SB_RAS#,
SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
SA_DM[7:0]4, SB_DM[7:0]4
SM_DRAMRST#
SA_CS#[3:0], SB_CS#[3:0]
SA_CS#[7:4], SB_CS#[7:4]
SA_ODT[3:0], SB_ODT[3:0]
SA_CKE[3:0], SB_CKE[3:0]
DDR3 Data Signals2
Single ended (e) DDR3 Bi-directional SA_DQ[63:0], SB_DQ[63:0]
Differential (f) DDR3 Bi-directional
SA_DQS[8:0], SA_DQS#[8:0]
SA_ECC_CB[7:0]3
SB_DQS[8:0], SB_DQS#[8:0]
SB_ECC_CB[7:0]3
TAP (ITP/XDP)
Single Ended (g) CMOS Input TCK, TDI, TMS, TRST#, TDI_M
Single Ended (h) CMOS Open-Drain
Output TDO, TDO_M
Single Ended (i) Asynchronous CMOS
Output TAPPWRGOOD
Control Sideband
Single Ended (ja) Asynchronous CMOS
Input VCCPWRGOOD_0,
VCCPWRGOOD_1, VTTPWRGOOD
Single Ended (jb) Asynchronous CMOS
Input SM_DRAMPWROK
Single Ended (k) Asynchronous Output RESET_OBS#
Single Ended (l) Asynchronous GTL
Output PRDY#, THERMTRIP#
Single Ended (m) Asynchronous GTL Input PREQ#
Single Ended (n) GTL Bi-directional CATERR#, BPM#[7:0]
Single Ended (o) Asynchronous Bi-
directional PECI
Single Ended (p) Asynchronous GTL Bi-
directional PROCHOT#
Single Ended (qa) CMOS Input CFG[17:0], PM_SYNC,
PM_EXT_TS#[1:0]
Electrical Specifications
68 Datasheet, Volume 1
Notes:
1. Refer to Chapter 6 for signal description details.
2. SA and SB refer to DDR3 Channel A and DDR3 Channel B.
3. These signals are only used on processors and platforms that support ECC DIMMs.
4. These signals will not be actively used on the Intel Xeon processor 3400 series.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least eight BCLKs for the processor to recognize the proper signal state. See
Section 7.9 for the DC specifications.
Single Ended (qb) CMOS Input RSTIN#
Single Ended (r) CMOS Output VTT_SELECT
Single Ended (s) CMOS Bi-directional VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
Single Ended (t) Analog Input COMP0, COMP1, COMP2, COMP3,
SM_RCOMP[2:0], ISENSE
Single Ended (ta) Analog Output SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Power/Ground/Other
(u) Power VCC, VCC_NCTF, VTT, VCCPLL,
VDDQ, VAXG
(v) Ground VSS, CGC_TP_NCTF
(w) No Connect RSVD, RSVD_NCTF, RSVD_TP,
FC_x
Single Ended (x) Asynchronous CMOS
Output PSI#
(y) Sense Points VCC_SENSE, VSS_SENSE,
VTT_SENSE, VSS_SENSE_VTT,
VAXG_SENSE, VSSAXG_SENSE
(z) Other SKTOCC#, DBR#
PCI Express*
Differential (ac) PCI Express Input PEG_RX[15:0], PEG_RX#[15:0]
Differential (ad) PCI Express Output PEG_TX[15:0], PEG_TX#[15:0]
Single Ended (ae) Analog Input PEG_ICOMP0, PEG_ICOMPI,
PEG_RCOMP0, PEG_RBIAS
DMI
Differential (af) DMI Input DMI_RX[3:0], DMI_RX#[3:0]
Differential (ag) DMI Output DMI_TX[3:0], DMI_TX#[3:0]
Intel® FDI
Single Ended (ah) FDI Input FDI_FSYNC[1:0]4,
FDI_LSYNC[1:0]4, FDI_INT4
Differential (ai) FDI Output FDI_TX[7:0]4, FDI_TX#[7:0]4
Table 7-3. Signal Groups (Sheet 2 of 2)1
Signal Group Alpha
Group Type Signals
Datasheet, Volume 1 69
Electrical Specifications
7.7 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
7.8 Absolute Maximum and Minimum Ratings
Table 7-4 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits (but within the absolute maximum and minimum
ratings) the device may be functional, but with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute max imum and minimum r atings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time, it will either not function or its reliability will be
severely degraded when returned to conditions within the functional operating
condition limits.
Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.
Notes:
1. F or functional oper ation, all proce ssor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a v o ltage bias . Storage within these limits will not affect
the long-term reliability of the device. For functional operation, refer to the processor case temperature
specifications.
4. This rating applies to the processor and does not include any tray or packaging.
5. Failure to adhe re to this spe cification can affect the long-term reliability of the processor.
6. VCC is a VID based rail.
Table 7-4. Processor Absolute Minimum and Maximum Ratings
Symbol Parameter Min Max Unit Notes1, 2
VCC Processor Core voltage with respect
to VSS -0.3 1.40 V 6
VTT Voltage for the memory controller
and Shared Cache with respect to VSS -0.3 1.40 V
VDDQ Processor I/O supply voltage for
DDR3 with respect to VSS -0.3 1.80 V
VCCPLL Processor PLL voltage with respect to
VSS -0.3 1.98 V
TSTORAGE Storage temperature -40 85 C3, 4, 5
Electrical Specifications
70 Datasheet, Volume 1
7.9 DC Specifications
The processor DC specifications in this section are defined at the processor
pads, unless noted otherwise. See Chapter 8 for the processor land listings and
Chapter 6 for signal definitions. Voltage and current specifications are detailed in
Table 7-5 and Table 7-6. For platform planning, refer to Table 7-7 that provides VCC
static and transient tolerances. This same information is presented graphically in
Figure 7-1.
The DC specifications for the DDR3 signals are listed in Table 7-8 Control Sideband and
Test Access Port (TAP) are listed in Table 7-9.
Table 7-5 through Table 7-6 list the DC specifications for the processor and are valid
only while meeting the thermal specifications (as specified in the processor Thermal
and Mechanical Specifications and Guidelines), clock frequency, and input voltages.
Care should be taken to read all notes associated with each parameter.
7.9.1 Voltage and Current Specifications
Notes:
1. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
2. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
3. R efer to Table 7-7 and Figure 7-1 for the minimum, typical, and maximum VCC allowed for a give n curre nt.
The processo r should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a
given current.
4. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 7-1 for details.
Table 7-5. Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Note
VID VID Range 0.6500 — 1.4000 V
VCC VCC for processor core See Table 7-7 and Figure 7-1 V1, 2, 3
VCC,BOOT Default VCC voltage for initial power up — 1.10 — V
ICC
Processor
Number
X3480
X3470
X3460
X3450
X3440
X3430
For Intel Xeon processor 3400
series with 95 W TDP
3.06 GHz
2.93 GHz
2.80 GHz
2.66 GHz
2.53 GHz
2.40 GHz
——
110
110
110
110
110
110
A4
ICC
Processor
Number
L3426
For Intel Xeon processor 3400
series with 45 W TDP
1.86 GHz
——
55
A4
ICC_TDC Sustained ICC; recommended design target
for Intel Xeon processor 3400 series with
95 W TDP ——90A
ICC_TDC 2009A Sustained ICC; recommended design
target for Intel Xeon processor 3400 series
with 45 W TDP ——45A
Datasheet, Volume 1 71
Electrical Specifications
Notes:
1. VTT must be provided using a separate voltage source and not be connected to VCC. The voltage
specification requirements are defined in the middle of the VT T pinfield at the processor socket vias on the
bottom side of th e baseboard. The voltage specifications are measured with a 20-MHz bandwidth
oscilloscope, 1. 5 pF maximum probe cap acitance, and 1 M min i mum i mpe dan ce. The ma ximu m l engt h of
ground wire o n the p rob e should be less than 5 mm. E n su re extern al noise from the system is not c oup led
into the oscilloscope probe.
2. VTT must be provided using a separate voltage source and not be connected to VCC. The voltage
specification requ irements are defined across VTT_SENSE and VSS_SENSE_VTT lands at the processor
socket vias on the bottom side of the baseboard. The requirements across the SENSE signals ac count for
voltage drops and impedances across the baseboard vias, socket, and processor package up to the
processor Si. The voltage specifications are measured with a 20-MHz bandwidth oscilloscope, 1.5 pF
maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the
probe should be les s than 5 mm. Ensure external noise fro m the system is not coupled into the oscilloscope
probe.
Table 7-6. Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Note
VTT
Voltage for the memory controller
and shared cache defined at the
socket motherboard VTT pinfield
via.
1.045 1.10 1.155 V 1
Voltage for the memory controller
and shared cache defined across
VTT_SENSE and VSS_SENSE_VTT. 1.023 1.10 1.117 V 2
VDDQ Processor I/O supply voltage for
DDR3 1.425 1.5 1.575 V
VCCPLL PLL supply voltage (DC + AC
specification) 1.71 1.8 1.89 V
ITT
Intel Xeon processor 3400 series
with 95 W TDP: Current for the
memory controller and Shared
Cache
——35A
ITT
Intel Xeon processor 3400 series
with 45 W TDP: Current for the
memory controller and Shared
Cache
——27A
ITT_TDC
Intel Xeon processor 3400 series
with 95 W TDP: Sustained current
for the memory controller and
Shared Cache
——30A
ITT_TDC
Intel Xeon processor 3400 series
with 45 W TDP: Sustained current
for the memory controller and
Shared Cache
——22A
IDDQ Processor I/O supply current for
DDR3 —— 6A
IDDQ_TDC Processor I/O supply sustained
current for DDR3 —— 6A
IDDQ_STANDBY Processor I/O supply standby
current for DDR3 — — 0.650 A
ICC_VCCPLL PLL supply current — — 1.1 A
ICC_VCCPLL_TDC PLL susta ined supply current — — 0.7 A
Electrical Specifications
72 Datasheet, Volume 1
Notes:
1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits.
2. This table is intended to aid in reading discrete points on Figure 7-1.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VS S_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands. Re fer to the Voltage Regulator Down (VRD) 11.1 Design Guide lines for socket load line
guidelines and VR implementation.
Table 7-7. VCC Static and Transient Tolerance
ICC (A)
Voltage Deviation from VID Setting 1, 2, 3
VCC_Max (V)
1.40 m
VCC_Typ (V)
1.40 m
VCC_Min (V)
1.40 m
0 0.000 -0.019 -0.038
5 -0.007 -0.026 -0.045
10 -0.014 -0.033 -0.052
15 -0.021 -0.040 -0.059
20 -0.028 -0.047 -0.066
25 -0.035 -0.054 -0.073
30 -0.042 -0.061 -0.080
35 -0.049 -0.068 -0.087
40 -0.056 -0.075 -0.094
45 -0.063 -0.082 -0.101
50 -0.070 -0.089 -0.108
55 -0.077 -0.096 -0.115
60 -0.084 -0.103 -0.122
65 -0.091 -0.110 -0.129
70 -0.098 -0.117 -0.136
75 -0.105 -0.124 -0.143
80 -0.112 -0.131 -0.150
85 -0.119 -0.138 -0.157
90 -0.126 -0.145 -0.164
95 -0.133 -0.152 -0.171
100 -0.140 -0.159 -0.178
110 -0.147 -0.166 -0.185
Datasheet, Volume 1 73
Electrical Specifications
Figure 7-1. VCC Static and Transient Tolerance Loadlines
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
0 102030405060708090100110
Icc [A]
Vcc [V]
Vcc Typical
Vcc Mi nimum
Vcc Maximum
Electrical Specifications
74 Datasheet, Volume 1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality
specifications.
5. This is the pull down driver resistance.
6. RVTT_TERM is the termination on the DIMM and is not controlled by the processor.
7. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VSS.
Table 7-8. DDR3 Signal Group DC Specifications
Symbol Parameter Alpha
Group Min Typ Max Units Notes1
VIL Input Low Voltage (e,f) — — 0.43*VDDQ V2,4
VIH Input High Voltage (e,f) 0.57*VDDQ ——V3
VOL Output Low Voltage (c,d,e,f) — (VDDQ / 2)* (RON /
(RON+RVTT_TERM)) —6
VOH Output High Voltage (c,d,e,f) — VDDQ – ((VDDQ / 2)*
(RON/(RON+RVTT_TERM)) —V4,6
RON DDR3 Clock Buffer On
Resistance —21 — 365
RON DDR3 Command Buffer On
Resistance —20 — 315
RON DDR3 Control Buffer On
Resistance —20 — 315
RON DDR3 Data Buffer On
Resistance —21 — 365
Data ODT On-Die Termination for
Data Signals (d) 93.5 — 126.5
ILI Input Leakage Current — — — ± 1 mA
SM_RCOMP0 COMP Resistance (t) 99 100 101 7
SM_RCOMP1 COMP Resistance (t) 24.7 24.9 25.1 7
SM_RCOMP2 COMP Resistance (t) 128.7 130 131.3 7
Datasheet, Volume 1 75
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VTT referred to in these specifications refers to instantaneous VTT.
3. For VIN between 0 V and VTT. Measured when the driver is tristated.
4. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality
specifications.
5. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VSS.
6. RSYS_TERM is the system termination on the signal.
Table 7-9. Control Sideband and TAP Signal Group DC Specifications
Symbol Alpha Group Parameter Min Typ Max Units Notes1
VIL (m),(n),(p),(qa),(qb),(s) Input Low Voltage — — 0.64 * VTT V2
VIH (m),(n),(p),(qa),(qb),(s) Input High Voltage 0.76 * VTT —— V2,4
VIL (g) Input Low Voltage — — 0.40 * VTT V2
VIH (g) Input High Voltage 0.75 * VTT —— V2,4
VIL (ja) Input Low Voltage — — 0.25 * VTT V2
VIH (ja) Input High Voltage 0.75 * VTT —— V2,4
VIL (jb) Input Low Voltage — — 0.29 V 2
VIH (jb) Input High Voltage 0.87 — — V 2,4
VOL (k),(l),(n),(p),(r),
(s),(h),(i) Output Low Voltage ——
VTT * RON /
(RON +
RSYS_TERM)V2,6
VOH (k),(l),(n),(p),
(r),(s),(i) Output High Voltage VTT —— V2,4
RON (ab) Buffer on Resistance 20 — 45
ILI (ja),(jb),(m),(n),
(p),(qa),(s),(t),(g) Input Leakage Current — — ±200 A3
ILI (qb) Input Leakage Current — — ±100 A3
COMP0 (t) COMP Resistance 49.4 49.9 50.4 5
COMP1 (t) COMP Resistance 49.4 49.9 50.4 5
COMP2 (t) COMP Resistance 19.8 20 20.2 5
COMP3 (t) COMP Resistance 19.8 20 20.2 5
Electrical Specifications
76 Datasheet, Volume 1
Notes:
1. Refer to the PCI Express Base Specification for more details.
2. VTX-AC-CM-PP and VTX-AC-CM-P are defined in the PCI Express Base Specification. Measurement is made over
at least 10^6 UI.
3. As measured with compliance test load. Defined as 2*|VTXD+ – VTXD- |.
4. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VSS.
5. PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor
6. RMS value.
7. Measured at Rx pins into a pair of 50-terminations into ground. Common mode peak v oltage is defined by
the expression: max{|(Vd+ - Vd-) – V-CMDC|}.
8. DC impedance limits are n eeded to guarantee Receiver detect.
9. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 ±20%) must be within the
specified range by the time Detect is entered.
10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
Table 7-10. PCI Express* DC Specifications
Symbol Alpha
Group Parameter Min Typ Max Units Notes1
VTX-DIFF-p-p (ad) Differential peak to peak Tx
voltage swing 0.8 — 1.2 V 3
VTX_CM-AC-p (ad) Tx AC Peak Common Mode
Output Voltage (Gen1 only) — — 20 mV 1,2,6
VTX_CM-AC-p-p (ad) Tx AC Peak -to-P eak Common
Mode Output Voltage (Gen2
only) — — 100 mV 1,2
ZTX-DIFF-DC (ad) DC Differential Tx Impedance
(Gen1 only) 80 — 120 1,10
ZTX-DIFF-DC (ad) DC Differential Tx Impedance
(Gen2 only) — — 120 1,10
ZRX-DC (ac) DC Common Mode Rx
Impedance 40 — 60 1,8,9
ZRX-DIFF-DC (ac) DC Differential Rx Impedance
(Gen1 only) 80 — 120 1
VRX-DIFFp-p (ac) Differential Rx input Peak to
Peak Voltage (Gen1 only) 0.175 — 1.2 V 1
VRX-DIFFp-p (ac) Differential Rx Input Peak to
Peak Voltage (Gen2 only) 0.120 — 1.2 V 1,1
VRX_CM-AC-p (ac) Rx AC peak Common Mode
Input Voltage — — 150 mV 1,7
PEG_ICOMPO (ae) Comp Resistance 49.5 50 50.5 4,5
PEG_ICOMPI (ae) Comp Resistance 49.5 50 50.5 4,5
PEG_RCOMPO (ae) Comp Resistance 49.5 50 50.5 4,5
PEG_RBIAS (ae) Comp Resistance 742.5 750 757.5 4,5
Datasheet, Volume 1 77
Electrical Specifications
7.10 Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. For the
PECI command set supported by the processor, refer to the appropriate processor
Thermal and Mechanical Specifications and Design Guidelines for additional information
(see Section 1.7).
7.10.1 DC Characteristics
The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical
specifications shown in Table 7-11 is used with devices normally operating from a VTT
interface supply. VTT nominal levels will vary between processor families. All PECI
devices will operate at the VTT level determined by the processor installed in the
system. For specific nominal VTT levels, refer to Table 7-6.
Notes:
1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
2. The leakage specification applies to powered devices on the PECI bus.
Table 7-11. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes1
Vin Input Voltage Range -0.150 VTT V
Vhysteresis Hysteresis 0.1 * VTT N/A V
VnNegative-Edge Threshold Voltage 0.275 * VTT 0.500 * VTT V
VpPositive-Edge Threshold Voltage 0.550 * VTT 0.725 * VTT V
Isource High -Level Output Source
(VOH = 0.75 * VTT)-6.0 N/A mA
Isink Low-Level Output Sink
(VOL = 0.25 * VTT)0.5 1.0 mA
Ileak+ High Impedance State Leakage to
VTT (Vleak = VOL) N/A 100 µA 2
Ileak- High Impedance Leakage to GND
(Vleak = VOH)N/A 100 µA 2
Cbus Bus Capacitance per Node N/A 10 pF
Vnoise Signal Noise Immunity above
300 MHz 0.1 * VTT N/A Vp-p
Electrical Specifications
78 Datasheet, Volume 1
7.10.2 Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.
.
§ §
Figure 7-2. Input Device Hy st er esis
Minimum VP
Maximum VP
Minimum VN
Maximum VN
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
VTTD
PECI Ground
Datasheet, Volume 1 79
Processor Land and Signal Information
8Processor Land and Signal
Information
8.1 Processor Land Assignments
The processor land-map quadrants are shown in Figure 8-1 through Figure 8-4.
Table 8-2 provides a listing of all processor lands ordered alphabetically by pin name.
Not all signals are used by the processor. Table 8-1 lists the signals that are not used by
the Intel Xeon processor 3400 series.
Table 8-1. Signals Not Used by the Intel® Xeon® Processor 3400 Series
Interface Signals Not Used
Intel Flexible Display Inte rface
FDI_FSYNC[1:0]
FDI_LSYNC[1:0]
FDI_INT
FDI_TX[7:0]
FDI_TX#[7:0]
Integrated Graphics Core Power
GFX_DPRSLPVR
GFX_IMON
GFX_VID[6:0]
GFX_VR_EN
VAXG
Memory SA_DM[7:0]
SB_DM[7:0]
Processor Land and Signal Information
80 Datasheet, Volume 1
Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
AY RSVD_NCTF VSS SA_DQ[49] SA_DQ[52] VSS SB_CS#[0] VDDQ SB_MA[10] SA_ODT[3] VDDQ
AW RSVD_NCTF SA_DQ[55] SA_DQS[6] SA_DQ[48] SA_DQ[53] SA_DQ[47] SA_DQS#[5] SA_DM[5] SA_DQ[45] SB_CS#[1] SB_MA[13] SB_CAS# SB_RAS# SB_BS[1] SA_CS#[1] SA_ODT[2]
AV RSVD_NCTF VSS SA_DQ[50] SA_DQ[54] SA_DQS#[6] VSS SA_DQ[42] SA_DQS[5] VSS SA_DQ[44] SB_CS#[3] VDDQ SB_ODT[2] SB_CS#[2] VDDQ SA_ODT[1] SA_ODT[0] VDDQ SA_CS#[0]
AU RSVD_NCTF SA_DQ[61] SA_DQ[60] SA_DQ[51] VSS SA_DM[6] SA_DQ[43] SA_DQ[46] VSS SA_DQ[41] SA_DQ[40] SB_ODT[1] SB_ODT[3] SB_ODT[0] SB_WE# SB_BS[0] SA_MA[13] SA_CS#[3] SA_CAS# SA_CS#[2]
AT SA_DQ[57] SA_DQ[56] SA_DM[7] VSS SB_DQ[49] SB_DQ[53] VSS SB_DQ[47] SB_DQ[40] SB_DQ[44] VSS SA_DQS#[4] SA_DQ[33] VSS SB_DQ[39] SB_DQS[4] VSS SB_DQ[36] SA_WE# VDDQ
AR VSS SA_DQS[7] SA_DQS#[7] SB_DQS#[6] SB_DQS[6] SB_DQ[48] SB_DQ[46] SB_DQ[42] SB_DQS#[5] SB_DQ[45] VSS SA_DQ[38] SA_DQS[4] SA_DQ[37] SB_DQ[35] SB_DQ[34] SB_DQS#[4] VSS SA_CK[0] SA_CK#[0]
AP SA_DQ[63] SA_DQ[62] VSS SB_DQ[55] SB_DQ[51] VSS SB_DQ[52] VSS SB_DQS[5] SB_DQ[41] SA_DQ[35] VSS SA_DQ[34] VSS VSS SB_DQ[38] VSS SB_DQ[33] SB_DQ[37] SA_CK#[2]
AN TMS SA_DQ[59] SA_DQ[58] TCK VSS SB_DQ[60] SB_DQ[54] SB_DQ[50] SB_DM[5] VSS SA_DQ[39] SA_DM[4] VSS SA_DQ[32] SA_DQ[36] VSS SB_DM[4] SB_DQ[32] VSS SA_CK[2]
AM VSS TRST# TDO TDI SB_DQS#[7] SB_DQ[57] SB_DQ[61] SB_DM[6] SB_DQ[43] BPM#[4] RSVD RSVD RSVD RSVD RSVD RSVD SB_CS#[5] SB_CS#[4] SA_CS#[5] RSVD
AL DBR# RESET_OBS# VSS SB_DQS[7] SB_DQ[63] SB_DQ[56] VSS BPM#[0] BPM#[1] VSS BPM#[5] RSVD VSS RSVD RSVD VSS SB_CS#[6] SA_CS#[6] VSS VTT
AK BCLK_ITP# BCLK_ITP SKTOCC# PREQ# VSS SB_DM[7] TAPPWRGOOD BPM#[2] BPM#[3] BPM#[7] BPM#[6] RSVD RSVD RSVD RSVD RSVD SB_CS#[7] SA_CS#[7] SA_CS#[4] VTT
AJ VSS RSVD PRDY# SB_DQ[59] SB_DQ[58] SB_DQ[62] VSS VSS VTT VTT VSS VTT VSS VTT VSS VTT VSS VTT VSS VTT
AH RSVD PM_SYNC VSS SM_DRAMPWROK VCCPWRGOOD_1 VCCPWRGOOD_0 PROCHOT# VSS
AG FC_AG40 CATERR# PSI# VTTPWRGOOD VSS PECI VSS VTT
AF VSS VTT_SELECT TDO_M TDI_M COMP0 THERMTRIP# RSTIN# VTT
AE VTT VTT FC_AE38 VSS VSS_SENSE_VTT VTT_SENSE VTT VTT
AD VTT VTT VTT VTT VTT VTT VTT VTT
AC VTT VTT VTT VTT VTT VTT VTT VTT
AB VSS VSS VSS VSS VSS VSS VSS VSS
AA VTTVTTVTTVTTVTTVTT
Datasheet, Volume 1 81
Processor Land and Signal Information
Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant)
2019181716151413121110987654321
SB_MA[4] VDDQ SB_MA[9] SA_MA[1] VDDQ SA_MA[5] SB_MA[14] VDDQ SA_CKE[3] SB_CKE[1] SA_DQ[27] VSS SA_DQS[3] SA_DQ[25] VSS RSVD_NCTF AY
SA_MA[0] SB_MA[6] SB_MA[11] SB_MA[12] SA_MA[4] SA_MA[7] SA_MA[9] SA_MA[12] SA_CKE[1] VDDQ SB_CKE[0] SA_DQ[31] SA_DQS#[3] SA_DQ[24] SA_DQ[19] SA_DQ[18] RSVD_NCTF AW
SA_BS[0] VDDQ SB_MA[2] SB_MA[5] VDDQ SA_MA[2] SA_MA[6] VDDQ SB_BS[2] SB_MA[15] SA_CKE[2] SB_CKE[3] SM_DRAMRST# SA_DQ[30] SA_DM[3] SA_DQ[29] SA_DQ[23] VSS SA_DQ[22] RSVD_NCTF AV
SB_MA[0] SA_BS[1] SB_MA[1] SB_MA[3] SB_MA[7] SA_MA[3] SA_MA[8] SA_MA[11] SA_BS[2] VDDQ SA_CKE[0] SB_CKE[2] SA_DQ[26] VSS VSS SA_DQ[28] SA_DQS[2] SA_DQS#[2] SA_DQ[17] SA_DM[2] AU
SA_RAS# SA_MA[10] VDDQ SB_MA[8] VSS SB_CK[1] VSS SB_ECC_CB[1] VSS SA_MA[14] VDDQ SB_DQ[31] VSS SB_DM[3] SB_DQ[24] VSS SA_DQ[16] SA_DQ[20] VSS SA_DQ[21] AT
VSS SB_CK[3] SB_CK#[3] SB_CK[0] SB_CK#[0] SB_CK#[1] SB_DQS[8] SB_DQS#[8] SB_ECC_CB[0] SA_ECC_CB[2] SA_MA[15] SB_DQ[26] SB_DQS[3] SB_DQ[25] SB_DQ[29] SB_DQ[19] SA_DQ[15] SA_DQ[10] SA_DQ[11] VSS AR
VSS SA_CK[3] SA_CK[1] VSS VSS VSS SB_ECC_CB[3] SB_ECC_CB[7] VSS SA_ECC_CB[3] SA_ECC_CB[0] VSS SB_DQS#[3] VSS SB_DQ[18] SB_DQ[23] VSS SA_DQS#[1] SA_DQS[1] SA_DQ[14] AP
VSS SA_CK#[3] SA_CK#[1] SB_CK[2] SB_CK#[2] SB_ECC_CB[2] SB_ECC_CB[6] VSS SB_ECC_CB[5] RSVD_TP SA_ECC_CB[1] VSS SB_DQ[28] SB_DQ[22] SB_DQS[2] SB_DQ[17] VSS SA_DQ[8] SA_DQ[9] SA_DM[1] AN
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SB_ECC_CB[4] SA_ECC_CB[7] SA_DQS#[8] VSS SB_DQ[27] SB_DM[2] SB_DQS#[2] VSS SB_DQ[21] SA_DQ[12] SA_DQ[13] VSS AM
VTT VSS RSVD RSVD VSS RSVD RSVD VSS RSVD VSS SA_DQS[8] SA_ECC_CB[5] SB_DQ[30] VSS SB_DQ[16] SB_DQ[20] SB_DQ[11] VSS SA_DQ[2] SA_DQ[3] AL
VTT VTT RSVD VSS RSVD RSVD RSVD RSVD RSVD SA_ECC_CB[6] VSS SA_ECC_CB[4] VSS SB_DQ[15] SB_DQ[10] VSS VSS SA_DQS[0] SA_DQ[7] SA_DQ[6] AK
VSS VTT VSS VTT VSS VDDQ VSS VDDQ VSS VDDQ VSS SB_DQ[3] SB_DQ[14] VSS SB_DQS#[1] SA_DQ[1] SA_DQS#[0] SA_DM[0] VSS AJ
SB_DQ[2] SB_DQ[9] SB_DQS[1] VSS SB_DM[1] VSS SA_DQ[5] SA_DQ[0] AH
VCCPLL VSS SB_DQ[12] SB_DQ[8] SB_DQ[13] SB_DIMM_VREFDQ SA_DQ[4] SM_RCOMP[0] AG
VCCPLL VCCPLL VSS SB_DQ[6] SB_DQS[0] SA_DIMM_VREFDQ COMP1 VSS AF
VTT VSS SB_DQ[7] SB_DQS#[0] SB_DM[0] VSS RSVD SM_RCOMP[2] AE
VSS SB_DQ[0] SB_DQ[1] VSS FDI_LSYNC[0] FDI_LSYNC[1] RSVD SM_RCOMP[1] AD
VTT SB_DQ[4] SB_DQ[5] VTT FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT VSS AC
VSS VTT VSS PM_EXT_TS#[0] PM_EXT_TS#[1] VSS AB
BCLK[1] BCLK[0] BCLK#[0] VSS PEG_CLK# PEG_CLK AA
Processor Land and Signal Information
82 Datasheet, Volume 1
Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant)
YVTT VTT VTT VTT VTT VTT
WVSS VSS VSS VSS VSS VSS
VVTT VTT VTT VTT VTT VTT VTT VTT
UVID[0]/MSID[0] VID[1]/MSID[1] VID[2]/MSID[2] VID[3]/CSC[0] VID[4]/CSC[1] VID[5]/CSC[2] VID[6] VID[7]
TISENSE VSS VSS VSS VSS VCC_SENSE VSS_SENSE VSS
RVCC VCC VCC VCC VCC VCC VCC VCC
PVCC VCC VCC VCC VCC VCC VCC VCC
NVSS VCC VCC VSS VCC VCC VSS VCC
MVCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
LVCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
KVSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
JVCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
HVCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
GVSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
FVCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
EVCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
DVSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VAXG
CVCC_NCTF VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VCC VSS VAXG
BCGC_TP_NCTF VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
AVCC_NCTF VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Datasheet, Volume 1 83
Processor Land and Signal Information
Figure 8-4. Socket Pinmap (Top View, Lowe r-R ight Quadrant)
BCLK#[1] VSS FDI_TX[7] FDI_TX#[7] FDI_TX[6] FDI_TX#[6] Y
FDI_TX[3] FDI_TX#[3] VTT FDI_TX[4] FDI_TX#[4] DMI_RX[3] DMI_RX#[3] VTT W
VTT VTT VTT VSS FDI_TX[1] FDI_TX#[1] VTT DMI_RX#[2] V
FDI_TX[2] FDI_TX#[2] FDI_TX[0] FDI_TX#[0] VSS DMI_RX[1] DMI_RX#[1] DMI_RX[2] U
VTT VTT VTT VSS PEG_RX#[15] PEG_RX[15] VTT DMI_RX#[0] T
FDI_TX[5] FDI_TX#[5] PEG_TX#[15] PEG_TX[15] VSS DMI_TX#[3] DMI_TX[3] DMI_RX[0] R
VTT VTT VTT VSS PEG_RX#[14] PEG_RX[14] VSS DMI_TX#[2] P
PEG_TX#[14] VTT PEG_TX[13] PEG_TX#[13] VSS DMI_TX[1] DMI_TX#[1] DMI_TX[2] N
VSS VCC VSS VCC VAXG VAXG VAXG VSS RSVD VTT VTT VTT PEG_TX[14] VSS VSS VSS PEG_TX[11] PEG_TX#[11] VSS DMI_TX#[0] M
VCC VCC VSS VCC VAXG VAXG VAXG VSS RSVD CFG[17] VTT VSS CFG[13] PEG_TX#[12] PEG_TX[10] PEG_TX#[10] VSS PEG_RX#[13] PEG_RX[13] DMI_TX[0] L
VCC VSS VCC VCC VAXG VAXG VAXG VSS CFG[15] VSS CFG[10] CFG[14] CFG[11] PEG_TX[12] VSS VSS PEG_TX#[8] PEG_TX[8] VSS PEG_RX#[12] K
VSS VCC VCC VSS VAXG VAXG VAXG VSS CFG[12] GFX_VID[6] GFX_DPRSLPVR VSS PEG_TX#[9] VSS PEG_TX[7] PEG_TX#[7] VSS PEG_RX[11] PEG_RX#[11] PEG_RX[12] J
VCC VCC VSS VAXG VSS VAXG VAXG VSS CFG[9] VSS CFG[4] CFG[5] PEG_TX[9] CFG[16] VSS VSS PEG_TX[5] PEG_TX#[5] VSS PEG_RX#[10] H
VCC VSS VAXG VAXG VSS VAXG VAXG VSS CFG[8] GFX_VID[5] GFX_VID[0] VSS CFG[1] PEG_TX#[6] PEG_TX[4] PEG_TX#[4] VSS PEG_RX[9] PEG_RX#[9] PEG_RX[10] G
VSS VAXG VAXG VAXG VSS VAXG VAXG VSS GFX_VR_EN VSS CFG[3] CFG[7] VSS PEG_TX[6] GFX_IMON PEG_TX#[2] PEG_TX#[3] PEG_TX[3] VSS PEG_RX#[8] F
VAXG VSS VAXG VAXG VSS VAXG VAXG VSS GFX_VID[2] GFX_VID[3] CFG[2] CFG[6] CFG[0] PEG_TX[1] PEG_TX#[1] PEG_TX[2] VSS VSS PEG_RX#[7] PEG_RX[8] E
VAXG VSS VAXG VAXG VSS VAXG VAXG VSS VSS PEG_ICOMPI VSS PEG_RX#[0] VSS PEG_TX#[0] VSS VSS VSS PEG_RX#[6] PEG_RX[7] RSVD_NCTF D
VAXG VSS VAXG VAXG VSS VAXG VAXG VSS GFX_VID[4] COMP3 PEG_ICOMPO PEG_RX[0] PEG_RX#[1] PEG_TX[0] PEG_RX#[3] VSS PEG_RX#[5] PEG_RX[6] RSVD_NCTF C
VAXG VAXG VSS VAXG VAXG VSSAXG_SENSE GFX_VID[1] COMP2 PEG_RCOMPO VSS PEG_RX[1] VSS PEG_RX[3] PEG_RX#[4] PEG_RX[5] RSVD_NCTF B
VAXG VAXG VSS VAXG VAXG VAXG_SENSE RSVD PEG_RBIAS PEG_RX[2] PEG_RX#[2] PEG_RX[4] RSVD_NCTF A
2019181716151413121110987654321
84 Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
BCLK_ITP AK39 CMOS O
BCLK_ITP# AK40 CMOS O
BCLK[0] AA7 CMOS I
BCLK[1] AA8 Diff Clk I
BCLK#[0] AA6 CMOS I
BCLK#[1] Y8 Diff Clk I
BPM#[0] AL33 GTL I/O
BPM#[1] AL32 GTL I/O
BPM#[2] AK33 GTL I/O
BPM#[3] AK32 GTL I/O
BPM#[4] AM31 GTL I/O
BPM#[5] AL30 GTL I/O
BPM#[6] AK30 GTL I/O
BPM#[7] AK31 GTL I/O
CATERR# AG39 GTL I/O
CFG[0] E8 CMOS I
CFG[1] G8 CMOS I
CFG[10] K10 CMOS I
CFG[11] K8 CMOS I
CFG[12] J12 CMOS I
CFG[13] L8 CMOS I
CFG[14] K9 CMOS I
CFG[15] K12 CMOS I
CFG[16] H7 CMOS I
CFG[17] L11 CMOS I
CFG[2] E10 CMOS I
CFG[3] F10 CMOS I
CFG[4] H10 CMOS I
CFG[5] H9 CMOS I
CFG[6] E9 CMOS I
CFG[7] F9 CMOS I
CFG[8] G12 CMOS I
CFG[9] H12 CMOS I
CGC_TP_NCTF B39
COMP0 AF36 Analog I
COMP1 AF2 Analog I
COMP2 B11 Analog I
COMP3 C11 Analog I
DBR# AL40 O
SA_DIMM_VREFDQ AF3 Analog O
SB_DIMM_VREFDQ AG3 Analog O
DMI_RX[0] R1 DMI I
DMI_RX[1] U3 DMI I
DMI_RX[2] U1 DMI I
DMI_RX[3] W3 DMI I
DMI_RX#[0] T1 DMI I
DMI_RX#[1] U2 DMI I
DMI_RX#[2] V1 DMI I
DMI_RX#[3] W2 DMI I
DMI_TX[0] L1 DMI O
DMI_TX[1] N3 DMI O
DMI_TX[2] N1 DMI O
DMI_TX[3] R2 DMI O
DMI_TX#[0] M1 DMI O
DMI_TX#[1] N2 DMI O
DMI_TX#[2] P1 DMI O
DMI_TX#[3] R3 DMI O
FC_AE38 AE38
FC_AG40 AG40
FDI_FSYNC[0] AC4 CMOS I
FDI_FSYNC[1] AC3 CMOS I
FDI_INT AC2 CMOS I
FDI_LSYNC[0] AD4 CMOS I
FDI_LSYNC[1] AD3 CMOS I
FDI_TX[0] U6 FDI O
FDI_TX[1] V4 FDI O
FDI_TX[2] U8 FDI O
FDI_TX[3] W8 FDI O
FDI_TX[4] W5 FDI O
FDI_TX[5] R8 FDI O
FDI_TX[6] Y4 FDI O
FDI_TX[7] Y6 FDI O
FDI_TX#[0] U5 FDI O
FDI_TX#[1] V3 FDI O
FDI_TX#[2] U7 FDI O
FDI_TX#[3] W7 FDI O
FDI_TX#[4] W4 FDI O
FDI_TX#[5] R7 FDI O
FDI_TX#[6] Y3 FDI O
FDI_TX#[7] Y5 FDI O
GFX_DPRSLPVR J10 CMOS O
GFX_IMON F6 Analog I
GFX_VID[0] G10 CMOS O
GFX_VID[1] B12 CMOS O
GFX_VID[2] E12 CMOS O
GFX_VID[3] E11 CMOS O
GFX_VID[4] C12 CMOS O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 85
Processor Land and Signal Information
GFX_VID[5] G11 CMOS O
GFX_VID[6] J11 CMOS O
GFX_VR_EN F12 CMOS O
ISENSE T40 Analog I
PECI AG35 Asynch I/O
PEG_CLK AA3 Diff Clk I
PEG_CLK# AA4 Diff Clk I
PEG_ICOMPI D11 Analog I
PEG_ICOMPO C10 Analog I
PEG_RBIAS A11 Analog I
PEG_RCOMPO B10 Analog I
PEG_RX[0] C9 PCI Express I
PEG_RX[1] B8 PCI Express I
PEG_RX[10] G1 PCI Express I
PEG_RX[11] J3 PCI Express I
PEG_RX[12] J1 PCI Express I
PEG_RX[13] L2 PCI Express I
PEG_RX[14] P3 PCI Express I
PEG_RX[15] T3 PCI Express I
PEG_RX[2] A7 PCI Express I
PEG_RX[3] B6 PCI Express I
PEG_RX[4] A5 PCI Express I
PEG_RX[5] B4 PCI Express I
PEG_RX[6] C3 PCI Express I
PEG_RX[7] D2 PCI Express I
PEG_RX[8] E1 PCI Express I
PEG_RX[9] G3 PCI Express I
PEG_RX#[0] D9 PCI Express I
PEG_RX#[1] C8 PCI Express I
PEG_RX#[10] H1 PCI Express I
PEG_RX#[11] J2 PCI Express I
PEG_RX#[12] K1 PCI Express I
PEG_RX#[13] L3 PCI Express I
PEG_RX#[14] P4 PCI Express I
PEG_RX#[15] T4 PCI Express I
PEG_RX#[2] A6 PCI Express I
PEG_RX#[3] C6 PCI Express I
PEG_RX#[4] B5 PCI Express I
PEG_RX#[5] C4 PCI Express I
PEG_RX#[6] D3 PCI Express I
PEG_RX#[7] E2 PCI Express I
PEG_RX#[8] F1 PCI Express I
PEG_RX#[9] G2 PCI Express I
PEG_TX[0] C7 PCI Express O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
PEG_TX[1] E7 PCI Express O
PEG_TX[10] L6 PCI Express O
PEG_TX[11] M4 PCI Express O
PEG_TX[12] K7 PCI Express O
PEG_TX[13] N6 PCI Express O
PEG_TX[14] M8 PCI Express O
PEG_TX[15] R5 PCI Express O
PEG_TX[2] E5 PCI Express O
PEG_TX[3] F3 PCI Express O
PEG_TX[4] G6 PCI Express O
PEG_TX[5] H4 PCI Express O
PEG_TX[6] F7 PCI Express O
PEG_TX[7] J6 PCI Express O
PEG_TX[8] K3 PCI Express O
PEG_TX[9] H8 PCI Express O
PEG_TX#[0] D7 PCI Express O
PEG_TX#[1] E6 PCI Express O
PEG_TX#[10] L5 PCI Express O
PEG_TX#[11] M3 PCI Express O
PEG_TX#[12] L7 PCI Express O
PEG_TX#[13] N5 PCI Express O
PEG_TX#[14] N8 PCI Express O
PEG_TX#[15] R6 PCI Express O
PEG_TX#[2] F5 PCI Express O
PEG_TX#[3] F4 PCI Express O
PEG_TX#[4] G5 PCI Express O
PEG_TX#[5] H3 PCI Express O
PEG_TX#[6] G7 PCI Express O
PEG_TX#[7] J5 PCI Express O
PEG_TX#[8] K4 PCI Express O
PEG_TX#[9] J8 PCI Express O
PM_EXT_TS#[0] AB5 CMOS I
PM_EXT_TS#[1] AB4 CMOS I
PM_SYNC AH39 CMOS I
PRDY# AJ38 Asynch GTL O
PREQ# AK37 Asynch GTL I
PROCHOT# AH34 Asynch GTL I/O
PSI# AG38 Asynch CMOS O
RESET_OBS# AL39 Asynch CMOS O
RSTIN# AF34 CMOS I
RSVD A12
RSVD AD2
RSVD AE2
RSVD AH40
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
86 Datasheet, Volume 1
Processor Land and Signal Information
RSVD AJ39
RSVD AK12
RSVD AK13
RSVD AK14
RSVD AK15
RSVD AK16
RSVD AK18
RSVD AK25
RSVD AK26
RSVD AK27
RSVD AK28
RSVD AK29
RSVD AL12
RSVD AL14
RSVD AL15
RSVD AL17
RSVD AL18
RSVD AL26
RSVD AL27
RSVD AL29
RSVD AM13
RSVD AM14
RSVD AM15
RSVD AM16
RSVD AM17
RSVD AM18
RSVD AM19
RSVD AM20
RSVD AM21
RSVD AM25
RSVD AM26
RSVD AM27
RSVD AM28
RSVD AM29
RSVD AM30
RSVD L12
RSVD M12
RSVD_NCTF A4
RSVD_NCTF AU40
RSVD_NCTF AV1
RSVD_NCTF AV39
RSVD_NCTF AW2
RSVD_NCTF AW38
RSVD_NCTF AY3
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
RSVD_NCTF AY37
RSVD_NCTF B3
RSVD_NCTF C2
RSVD_NCTF D1
RSVD_TP AN11
SA_BS[0] AV20 DDR3 O
SA_BS[1] AU19 DDR3 O
SA_BS[2] AU12 DDR3 O
SA_CAS# AU22 DDR3 O
SA_CK[0] AR22 DDR3 O
SA_CK[1] AP18 DDR3 O
SA_CK[2] AN21 DDR3 O
SA_CK[3] AP19 DDR3 O
SA_CK#[0] AR21 DDR3 O
SA_CK#[1] AN18 DDR3 O
SA_CK#[2] AP21 DDR3 O
SA_CK#[3] AN19 DDR3 O
SA_CKE[0] AU10 DDR3 O
SA_CKE[1] AW10 DDR3 O
SA_CKE[2] AV10 DDR3 O
SA_CKE[3] AY10 DDR3 O
SA_CS#[0] AV21 DDR3 O
SA_CS#[1] AW24 DDR3 O
SA_CS#[2] AU21 DDR3 O
SA_CS#[3] AU23 DDR3 O
SA_CS#[4] AK22 DDR3 O
SA_CS#[5] AM22 DDR3 O
SA_CS#[6] AL23 DDR3 O
SA_CS#[7] AK23 DDR3 O
SA_DM[0] AJ2 DDR3 O
SA_DM[1] AN1 DDR3 O
SA_DM[2] AU1 DDR3 O
SA_DM[3] AV6 DDR3 I/O
SA_DM[4] AN29 DDR3 O
SA_DM[5] AW31 DDR3 O
SA_DM[6] AU35 DDR3 O
SA_DM[7] AT38 DDR3 O
SA_DQ[0] AH1 DDR3 I/O
SA_DQ[1] AJ4 DDR3 I/O
SA_DQ[10] AR3 DDR3 I/O
SA_DQ[11] AR2 DDR3 I/O
SA_DQ[12] AM3 DDR3 I/O
SA_DQ[13] AM2 DDR3 I/O
SA_DQ[14] AP1 DDR3 I/O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 87
Processor Land and Signal Information
SA_DQ[15] AR4 DDR3 I/O
SA_DQ[16] AT4 DDR3 I/O
SA_DQ[17] AU2 DDR3 I/O
SA_DQ[18] AW3 DDR3 I/O
SA_DQ[19] AW4 DDR3 I/O
SA_DQ[2] AL2 DDR3 I/O
SA_DQ[20] AT3 DDR3 I/O
SA_DQ[21] AT1 DDR3 I/O
SA_DQ[22] AV2 DDR3 I/O
SA_DQ[23] AV4 DDR3 I/O
SA_DQ[24] AW5 DDR3 I/O
SA_DQ[25] AY5 DDR3 I/O
SA_DQ[26] AU8 DDR3 I/O
SA_DQ[27] AY8 DDR3 I/O
SA_DQ[28] AU5 DDR3 I/O
SA_DQ[29] AV5 DDR3 I/O
SA_DQ[3] AL1 DDR3 I/O
SA_DQ[30] AV7 DDR3 I/O
SA_DQ[31] AW7 DDR3 I/O
SA_DQ[32] AN27 DDR3 I/O
SA_DQ[33] AT28 DDR3 I/O
SA_DQ[34] AP28 DDR3 I/O
SA_DQ[35] AP30 DDR3 I/O
SA_DQ[36] AN26 DDR3 I/O
SA_DQ[37] AR27 DDR3 I/O
SA_DQ[38] AR29 DDR3 I/O
SA_DQ[39] AN30 DDR3 I/O
SA_DQ[4] AG2 DDR3 I/O
SA_DQ[40] AU30 DDR3 I/O
SA_DQ[41] AU31 DDR3 I/O
SA_DQ[42] AV33 DDR3 I/O
SA_DQ[43] AU34 DDR3 I/O
SA_DQ[44] AV30 DDR3 I/O
SA_DQ[45] AW30 DDR3 I/O
SA_DQ[46] AU33 DDR3 I/O
SA_DQ[47] AW33 DDR3 I/O
SA_DQ[48] AW35 DDR3 I/O
SA_DQ[49] AY35 DDR3 I/O
SA_DQ[5] AH2 DDR3 I/O
SA_DQ[50] AV37 DDR3 I/O
SA_DQ[51] AU37 DDR3 I/O
SA_DQ[52] AY34 DDR3 I/O
SA_DQ[53] AW34 DDR3 I/O
SA_DQ[54] AV36 DDR3 I/O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
SA_DQ[55] AW37 DDR3 I/O
SA_DQ[56] AT39 DDR3 I/O
SA_DQ[57] AT40 DDR3 I/O
SA_DQ[58] AN38 DDR3 I/O
SA_DQ[59] AN39 DDR3 I/O
SA_DQ[6] AK1 DDR3 I/O
SA_DQ[60] AU38 DDR3 I/O
SA_DQ[61] AU39 DDR3 I/O
SA_DQ[62] AP39 DDR3 I/O
SA_DQ[63] AP40 DDR3 I/O
SA_DQ[7] AK2 DDR3 I/O
SA_DQ[8] AN3 DDR3 I/O
SA_DQ[9] AN2 DDR3 I/O
SA_DQS[0] AK3 DDR3 I/O
SA_DQS[1] AP2 DDR3 I/O
SA_DQS[2] AU4 DDR3 I/O
SA_DQS[3] AY6 DDR3 I/O
SA_DQS[4] AR28 DDR3 I/O
SA_DQS[5] AV32 DDR3 I/O
SA_DQS[6] AW36 DDR3 I/O
SA_DQS[7] AR39 DDR3 I/O
SA_DQS[8] AL10 DDR3 I/O
SA_DQS#[0] AJ3 DDR3 I/O
SA_DQS#[1] AP3 DDR3 I/O
SA_DQS#[2] AU3 DDR3 I/O
SA_DQS#[3] AW6 DDR3 I/O
SA_DQS#[4] AT29 DDR3 I/O
SA_DQS#[5] AW32 DDR3 I/O
SA_DQS#[6] AV35 DDR3 I/O
SA_DQS#[7] AR38 DDR3 I/O
SA_DQS#[8] AM10 DDR3 I/O
SA_ECC_CB[0] AP10 DDR3 I/O
SA_ECC_CB[1] AN10 DDR3 I/O
SA_ECC_CB[2] AR11 DDR3 I/O
SA_ECC_CB[3] AP11 DDR3 I/O
SA_ECC_CB[4] AK9 DDR3 I/O
SA_ECC_CB[5] AL9 DDR3 I/O
SA_ECC_CB[6] AK11 DDR3 I/O
SA_ECC_CB[7] AM11 DDR3 I/O
SA_MA[0] AW18 DDR3 O
SA_MA[1] AY15 DDR3 O
SA_MA[10] AT19 DDR3 O
SA_MA[11] AU13 DDR3 O
SA_MA[12] AW11 DDR3 O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
88 Datasheet, Volume 1
Processor Land and Signal Information
SA_MA[13] AU24 DDR3 O
SA_MA[14] AT11 DDR3 O
SA_MA[15] AR10 DDR3 O
SA_MA[2] AV15 DDR3 O
SA_MA[3] AU15 DDR3 O
SA_MA[4] AW14 DDR3 O
SA_MA[5] AY13 DDR3 O
SA_MA[6] AV14 DDR3 O
SA_MA[7] AW13 DDR3 O
SA_MA[8] AU14 DDR3 O
SA_MA[9] AW12 DDR3 O
SA_ODT[0] AV23 DDR3 O
SA_ODT[1] AV24 DDR3 O
SA_ODT[2] AW23 DDR3 O
SA_ODT[3] AY24 DDR3 O
SA_RAS# AT20 DDR3 O
SA_WE# AT22 DDR3 O
SB_BS[0] AU25 DDR3 O
SB_BS[1] AW25 DDR3 O
SB_BS[2] AV12 DDR3 O
SB_CAS# AW27 DDR3 O
SB_CK[0] AR17 DDR3 O
SB_CK[1] AT15 DDR3 O
SB_CK[2] AN17 DDR3 O
SB_CK[3] AR19 DDR3 O
SB_CK#[0] AR16 DDR3 O
SB_CK#[1] AR15 DDR3 O
SB_CK#[2] AN16 DDR3 O
SB_CK#[3] AR18 DDR3 O
SB_CKE[0] AW8 DDR3 O
SB_CKE[1] AY9 DDR3 O
SB_CKE[2] AU9 DDR3 O
SB_CKE[3] AV9 DDR3 O
SB_CS#[0] AY27 DDR3 O
SB_CS#[1] AW29 DDR3 O
SB_CS#[2] AV26 DDR3 O
SB_CS#[3] AV29 DDR3 O
SB_CS#[4] AM23 DDR3 O
SB_CS#[5] AM24 DDR3 O
SB_CS#[6] AL24 DDR3 O
SB_CS#[7] AK24 DDR3 O
SB_DM[0] AE4 DDR3 O
SB_DM[1] AH4 DDR3 O
SB_DM[2] AM7 DDR3 O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
SB_DM[3] AT7 DDR3 O
SB_DM[4] AN24 DDR3 O
SB_DM[5] AN32 DDR3 O
SB_DM[6] AM33 DDR3 O
SB_DM[7] AK35 DDR3 O
SB_DQ[0] AD7 DDR3 I/O
SB_DQ[1] AD6 DDR3 I/O
SB_DQ[10] AK6 DDR3 I/O
SB_DQ[11] AL4 DDR3 I/O
SB_DQ[12] AG6 DDR3 I/O
SB_DQ[13] AG4 DDR3 I/O
SB_DQ[14] AJ7 DDR3 I/O
SB_DQ[15] AK7 DDR3 I/O
SB_DQ[16] AL6 DDR3 I/O
SB_DQ[17] AN5 DDR3 I/O
SB_DQ[18] AP6 DDR3 I/O
SB_DQ[19] AR5 DDR3 I/O
SB_DQ[2] AH8 DDR3 I/O
SB_DQ[20] AL5 DDR3 I/O
SB_DQ[21] AM4 DDR3 I/O
SB_DQ[22] AN7 DDR3 I/O
SB_DQ[23] AP5 DDR3 I/O
SB_DQ[24] AT6 DDR3 I/O
SB_DQ[25] AR7 DDR3 I/O
SB_DQ[26] AR9 DDR3 I/O
SB_DQ[27] AM8 DDR3 I/O
SB_DQ[28] AN8 DDR3 I/O
SB_DQ[29] AR6 DDR3 I/O
SB_DQ[3] AJ8 DDR3 I/O
SB_DQ[30] AL8 DDR3 I/O
SB_DQ[31] AT9 DDR3 I/O
SB_DQ[32] AN23 DDR3 I/O
SB_DQ[33] AP23 DDR3 I/O
SB_DQ[34] AR25 DDR3 I/O
SB_DQ[35] AR26 DDR3 I/O
SB_DQ[36] AT23 DDR3 I/O
SB_DQ[37] AP22 DDR3 I/O
SB_DQ[38] AP25 DDR3 I/O
SB_DQ[39] AT26 DDR3 I/O
SB_DQ[4] AC7 DDR3 I/O
SB_DQ[40] AT32 DDR3 I/O
SB_DQ[41] AP31 DDR3 I/O
SB_DQ[42] AR33 DDR3 I/O
SB_DQ[43] AM32 DDR3 I/O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 89
Processor Land and Signal Information
SB_DQ[44] AT31 DDR3 I/O
SB_DQ[45] AR31 DDR3 I/O
SB_DQ[46] AR34 DDR3 I/O
SB_DQ[47] AT33 DDR3 I/O
SB_DQ[48] AR35 DDR3 I/O
SB_DQ[49] AT36 DDR3 I/O
SB_DQ[5] AC6 DDR3 I/O
SB_DQ[50] AN33 DDR3 I/O
SB_DQ[51] AP36 DDR3 I/O
SB_DQ[52] AP34 DDR3 I/O
SB_DQ[53] AT35 DDR3 I/O
SB_DQ[54] AN34 DDR3 I/O
SB_DQ[55] AP37 DDR3 I/O
SB_DQ[56] AL35 DDR3 I/O
SB_DQ[57] AM35 DDR3 I/O
SB_DQ[58] AJ36 DDR3 I/O
SB_DQ[59] AJ37 DDR3 I/O
SB_DQ[6] AF5 DDR3 I/O
SB_DQ[60] AN35 DDR3 I/O
SB_DQ[61] AM34 DDR3 I/O
SB_DQ[62] AJ35 DDR3 I/O
SB_DQ[63] AL36 DDR3 I/O
SB_DQ[7] AE6 DDR3 I/O
SB_DQ[8] AG5 DDR3 I/O
SB_DQ[9] AH7 DDR3 I/O
SB_DQS[0] AF4 DDR3 I/O
SB_DQS[1] AH6 DDR3 I/O
SB_DQS[2] AN6 DDR3 I/O
SB_DQS[3] AR8 DDR3 I/O
SB_DQS[4] AT25 DDR3 I/O
SB_DQS[5] AP32 DDR3 I/O
SB_DQS[6] AR36 DDR3 I/O
SB_DQS[7] AL37 DDR3 I/O
SB_DQS[8] AR14 DDR3 I/O
SB_DQS#[0] AE5 DDR3 I/O
SB_DQS#[1] AJ5 DDR3 I/O
SB_DQS#[2] AM6 DDR3 I/O
SB_DQS#[3] AP8 DDR3 I/O
SB_DQS#[4] AR24 DDR3 I/O
SB_DQS#[5] AR32 DDR3 I/O
SB_DQS#[6] AR37 DDR3 I/O
SB_DQS#[7] AM36 DDR3 I/O
SB_DQS#[8] AR13 DDR3 I/O
SB_ECC_CB[0] AR12 DDR3 I/O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
SB_ECC_CB[1] AT13 DDR3 I/O
SB_ECC_CB[2] AN15 DDR3 I/O
SB_ECC_CB[3] AP14 DDR3 I/O
SB_ECC_CB[4] AM12 DDR3 I/O
SB_ECC_CB[5] AN12 DDR3 I/O
SB_ECC_CB[6] AN14 DDR3 I/O
SB_ECC_CB[7] AP13 DDR3 I/O
SB_MA[0] AU20 DDR3 O
SB_MA[1] AU18 DDR3 O
SB_MA[10] AY25 DDR3 O
SB_MA[11] AW16 DDR3 O
SB_MA[12] AW15 DDR3 O
SB_MA[13] AW28 DDR3 O
SB_MA[14] AY12 DDR3 O
SB_MA[15] AV11 DDR3 O
SB_MA[2] AV18 DDR3 O
SB_MA[3] AU17 DDR3 O
SB_MA[4] AY18 DDR3 O
SB_MA[5] AV17 DDR3 O
SB_MA[6] AW17 DDR3 O
SB_MA[7] AU16 DDR3 O
SB_MA[8] AT17 DDR3 O
SB_MA[9] AY16 DDR3 O
SB_ODT[0] AU27 DDR3 O
SB_ODT[1] AU29 DDR3 O
SB_ODT[2] AV27 DDR3 O
SB_ODT[3] AU28 DDR3 O
SB_RAS# AW26 DDR3 O
SB_WE# AU26 DDR3 O
SKTOCC# AK38 O
SM_DRAMPWROK AH37 Asynch CMOS I
SM_DRAMRST# AV8 DDR3 O
SM_RCOMP[0] AG1 Analog I
SM_RCOMP[1] AD1 Analog I
SM_RCOMP[2] AE1 Analog I
TAPPWRGOOD AK34 Asynch CMOS O
TCK AN37 TAP I
TDI AM37 TAP I
TDI_M AF37 TAP I
TDO AM38 TAP O
TDO_M AF38 TAP O
THERMTRIP# AF35 Asynch GTL O
TMS AN40 TAP I
TRST# AM39 TAP I
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
90 Datasheet, Volume 1
Processor Land and Signal Information
VAXG A14 PWR
VAXG A15 PWR
VAXG A17 PWR
VAXG A18 PWR
VAXG B14 PWR
VAXG B15 PWR
VAXG B17 PWR
VAXG B18 PWR
VAXG C14 PWR
VAXG C15 PWR
VAXG C17 PWR
VAXG C18 PWR
VAXG C20 PWR
VAXG C21 PWR
VAXG D14 PWR
VAXG D15 PWR
VAXG D17 PWR
VAXG D18 PWR
VAXG D20 PWR
VAXG D21 PWR
VAXG E14 PWR
VAXG E15 PWR
VAXG E17 PWR
VAXG E18 PWR
VAXG E20 PWR
VAXG F14 PWR
VAXG F15 PWR
VAXG F17 PWR
VAXG F18 PWR
VAXG F19 PWR
VAXG G14 PWR
VAXG G15 PWR
VAXG G17 PWR
VAXG G18 PWR
VAXG H14 PWR
VAXG H15 PWR
VAXG H17 PWR
VAXG J14 PWR
VAXG J15 PWR
VAXG J16 PWR
VAXG K14 PWR
VAXG K15 PWR
VAXG K16 PWR
VAXG L14 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VAXG L15 PWR
VAXG L16 PWR
VAXG M14 PWR
VAXG M15 PWR
VAXG M16 PWR
VAXG_SENSE A13 Analog
VCC A23 PWR
VCC A24 PWR
VCC A26 PWR
VCC A27 PWR
VCC A33 PWR
VCC A35 PWR
VCC A36 PWR
VCC B23 PWR
VCC B25 PWR
VCC B26 PWR
VCC B28 PWR
VCC B29 PWR
VCC B31 PWR
VCC B32 PWR
VCC B34 PWR
VCC B35 PWR
VCC B37 PWR
VCC B38 PWR
VCC C23 PWR
VCC C24 PWR
VCC C25 PWR
VCC C27 PWR
VCC C28 PWR
VCC C30 PWR
VCC C31 PWR
VCC C33 PWR
VCC C34 PWR
VCC C36 PWR
VCC C37 PWR
VCC C39 PWR
VCC D23 PWR
VCC D24 PWR
VCC D26 PWR
VCC D27 PWR
VCC D29 PWR
VCC D30 PWR
VCC D32 PWR
VCC D33 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 91
Processor Land and Signal Information
VCC D35 PWR
VCC D36 PWR
VCC D38 PWR
VCC D39 PWR
VCC E22 PWR
VCC E23 PWR
VCC E25 PWR
VCC E26 PWR
VCC E28 PWR
VCC E29 PWR
VCC E31 PWR
VCC E32 PWR
VCC E34 PWR
VCC E35 PWR
VCC E37 PWR
VCC E38 PWR
VCC E40 PWR
VCC F21 PWR
VCC F22 PWR
VCC F24 PWR
VCC F25 PWR
VCC F27 PWR
VCC F28 PWR
VCC F30 PWR
VCC F31 PWR
VCC F33 PWR
VCC F34 PWR
VCC F36 PWR
VCC F37 PWR
VCC F39 PWR
VCC F40 PWR
VCC G20 PWR
VCC G21 PWR
VCC G23 PWR
VCC G24 PWR
VCC G26 PWR
VCC G27 PWR
VCC G29 PWR
VCC G30 PWR
VCC G32 PWR
VCC G33 PWR
VCC G35 PWR
VCC G36 PWR
VCC G38 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VCC G39 PWR
VCC H19 PWR
VCC H20 PWR
VCC H22 PWR
VCC H23 PWR
VCC H25 PWR
VCC H26 PWR
VCC H28 PWR
VCC H29 PWR
VCC H31 PWR
VCC H32 PWR
VCC H34 PWR
VCC H35 PWR
VCC H37 PWR
VCC H38 PWR
VCC H40 PWR
VCC J18 PWR
VCC J19 PWR
VCC J21 PWR
VCC J22 PWR
VCC J24 PWR
VCC J25 PWR
VCC J27 PWR
VCC J28 PWR
VCC J30 PWR
VCC J31 PWR
VCC J33 PWR
VCC J34 PWR
VCC J36 PWR
VCC J37 PWR
VCC J39 PWR
VCC J40 PWR
VCC K17 PWR
VCC K18 PWR
VCC K20 PWR
VCC K21 PWR
VCC K23 PWR
VCC K24 PWR
VCC K26 PWR
VCC K27 PWR
VCC K29 PWR
VCC K30 PWR
VCC K32 PWR
VCC K33 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
92 Datasheet, Volume 1
Processor Land and Signal Information
VCC K35 PWR
VCC K36 PWR
VCC K38 PWR
VCC K39 PWR
VCC L17 PWR
VCC L19 PWR
VCC L20 PWR
VCC L22 PWR
VCC L23 PWR
VCC L25 PWR
VCC L26 PWR
VCC L28 PWR
VCC L29 PWR
VCC L31 PWR
VCC L32 PWR
VCC L34 PWR
VCC L35 PWR
VCC L37 PWR
VCC L38 PWR
VCC L40 PWR
VCC M17 PWR
VCC M19 PWR
VCC M21 PWR
VCC M22 PWR
VCC M24 PWR
VCC M25 PWR
VCC M27 PWR
VCC M28 PWR
VCC M30 PWR
VCC M33 PWR
VCC M34 PWR
VCC M36 PWR
VCC M37 PWR
VCC M39 PWR
VCC M40 PWR
VCC N33 PWR
VCC N35 PWR
VCC N36 PWR
VCC N38 PWR
VCC N39 PWR
VCC P33 PWR
VCC P34 PWR
VCC P35 PWR
VCC P36 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VCC P37 PWR
VCC P38 PWR
VCC P39 PWR
VCC P40 PWR
VCC R33 PWR
VCC R34 PWR
VCC R35 PWR
VCC R36 PWR
VCC R37 PWR
VCC R38 PWR
VCC R39 PWR
VCC R40 PWR
VCC_NCTF A38 PWR
VCC_NCTF C40 PWR
VCC_SENSE T35 Analog
VCCPLL AF7 PWR
VCCPLL AF8 PWR
VCCPLL AG8 PWR
VCCPWRGOOD_0 AH35 Asynch I
VCCPWRGOOD_1 AH36 Asynch I
VDDQ AJ11 PWR
VDDQ AJ13 PWR
VDDQ AJ15 PWR
VDDQ AT10 PWR
VDDQ AT18 PWR
VDDQ AT21 PWR
VDDQ AU11 PWR
VDDQ AV13 PWR
VDDQ AV16 PWR
VDDQ AV19 PWR
VDDQ AV22 PWR
VDDQ AV25 PWR
VDDQ AV28 PWR
VDDQ AW9 PWR
VDDQ AY11 PWR
VDDQ AY14 PWR
VDDQ AY17 PWR
VDDQ AY23 PWR
VDDQ AY26 PWR
VID[0]/MSID[0] U40 CMOS I/O
VID[1]/MSID[1] U39 CMOS I/O
VID[2]/MSID[2] U38 CMOS I/O
VID[3]/CSC[0] U37 CMOS I/O
VID[4]/CSC[1] U36 CMOS I/O
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 93
Processor Land and Signal Information
VID[5]/CSC[2] U35 CMOS I/O
VID[6] U34 CMOS I/O
VID[7] U33 CMOS I/O
VSS A16 GND
VSS A25 GND
VSS A28 GND
VSS A34 GND
VSS A37 GND
VSS AA5 GND
VSS AB3 GND
VSS AB33 GND
VSS AB34 GND
VSS AB35 GND
VSS AB36 GND
VSS AB37 GND
VSS AB38 GND
VSS AB39 GND
VSS AB40 GND
VSS AB6 GND
VSS AB8 GND
VSS AC1 GND
VSS AD5 GND
VSS AD8 GND
VSS AE3 GND
VSS AE37 GND
VSS AE7 GND
VSS AF1 GND
VSS AF40 GND
VSS AF6 GND
VSS AG34 GND
VSS AG36 GND
VSS AG7 GND
VSS AH3 GND
VSS AH33 GND
VSS AH38 GND
VSS AH5 GND
VSS AJ1 GND
VSS AJ12 GND
VSS AJ14 GND
VSS AJ16 GND
VSS AJ18 GND
VSS AJ20 GND
VSS AJ22 GND
VSS AJ24 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VSS AJ26 GND
VSS AJ28 GND
VSS AJ30 GND
VSS AJ33 GND
VSS AJ34 GND
VSS AJ40 GND
VSS AJ6 GND
VSS AJ9 GND
VSS AK10 GND
VSS AK17 GND
VSS AK36 GND
VSS AK4 GND
VSS AK5 GND
VSS AK8 GND
VSS AL11 GND
VSS AL13 GND
VSS AL16 GND
VSS AL19 GND
VSS AL22 GND
VSS AL25 GND
VSS AL28 GND
VSS AL3 GND
VSS AL31 GND
VSS AL34 GND
VSS AL38 GND
VSS AL7 GND
VSS AM1 GND
VSS AM40 GND
VSS AM5 GND
VSS AM9 GND
VSS AN13 GND
VSS AN20 GND
VSS AN22 GND
VSS AN25 GND
VSS AN28 GND
VSS AN31 GND
VSS AN36 GND
VSS AN4 GND
VSS AN9 GND
VSS AP12 GND
VSS AP15 GND
VSS AP16 GND
VSS AP17 GND
VSS AP20 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
94 Datasheet, Volume 1
Processor Land and Signal Information
VSS AP24 GND
VSS AP26 GND
VSS AP27 GND
VSS AP29 GND
VSS AP33 GND
VSS AP35 GND
VSS AP38 GND
VSS AP4 GND
VSS AP7 GND
VSS AP9 GND
VSS AR1 GND
VSS AR20 GND
VSS AR23 GND
VSS AR30 GND
VSS AR40 GND
VSS AT12 GND
VSS AT14 GND
VSS AT16 GND
VSS AT2 GND
VSS AT24 GND
VSS AT27 GND
VSS AT30 GND
VSS AT34 GND
VSS AT37 GND
VSS AT5 GND
VSS AT8 GND
VSS AU32 GND
VSS AU36 GND
VSS AU6 GND
VSS AU7 GND
VSS AV3 GND
VSS AV31 GND
VSS AV34 GND
VSS AV38 GND
VSS AY33 GND
VSS AY36 GND
VSS AY4 GND
VSS AY7 GND
VSS B16 GND
VSS B24 GND
VSS B27 GND
VSS B30 GND
VSS B33 GND
VSS B36 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VSS B7 GND
VSS B9 GND
VSS C13 GND
VSS C16 GND
VSS C19 GND
VSS C22 GND
VSS C26 GND
VSS C29 GND
VSS C32 GND
VSS C35 GND
VSS C38 GND
VSS C5 GND
VSS D10 GND
VSS D12 GND
VSS D13 GND
VSS D16 GND
VSS D19 GND
VSS D22 GND
VSS D25 GND
VSS D28 GND
VSS D31 GND
VSS D34 GND
VSS D37 GND
VSS D4 GND
VSS D40 GND
VSS D5 GND
VSS D6 GND
VSS D8 GND
VSS E13 GND
VSS E16 GND
VSS E19 GND
VSS E21 GND
VSS E24 GND
VSS E27 GND
VSS E3 GND
VSS E30 GND
VSS E33 GND
VSS E36 GND
VSS E39 GND
VSS E4 GND
VSS F11 GND
VSS F13 GND
VSS F16 GND
VSS F2 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 95
Processor Land and Signal Information
VSS F20 GND
VSS F23 GND
VSS F26 GND
VSS F29 GND
VSS F32 GND
VSS F35 GND
VSS F38 GND
VSS F8 GND
VSS G13 GND
VSS G16 GND
VSS G19 GND
VSS G22 GND
VSS G25 GND
VSS G28 GND
VSS G31 GND
VSS G34 GND
VSS G37 GND
VSS G4 GND
VSS G40 GND
VSS G9 GND
VSS H11 GND
VSS H13 GND
VSS H16 GND
VSS H18 GND
VSS H2 GND
VSS H21 GND
VSS H24 GND
VSS H27 GND
VSS H30 GND
VSS H33 GND
VSS H36 GND
VSS H39 GND
VSS H5 GND
VSS H6 GND
VSS J13 GND
VSS J17 GND
VSS J20 GND
VSS J23 GND
VSS J26 GND
VSS J29 GND
VSS J32 GND
VSS J35 GND
VSS J38 GND
VSS J4 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VSS J7 GND
VSS J9 GND
VSS K11 GND
VSS K13 GND
VSS K19 GND
VSS K2 GND
VSS K22 GND
VSS K25 GND
VSS K28 GND
VSS K31 GND
VSS K34 GND
VSS K37 GND
VSS K40 GND
VSS K5 GND
VSS K6 GND
VSS L13 GND
VSS L18 GND
VSS L21 GND
VSS L24 GND
VSS L27 GND
VSS L30 GND
VSS L33 GND
VSS L36 GND
VSS L39 GND
VSS L4 GND
VSS L9 GND
VSS M13 GND
VSS M18 GND
VSS M2 GND
VSS M20 GND
VSS M23 GND
VSS M26 GND
VSS M29 GND
VSS M32 GND
VSS M35 GND
VSS M38 GND
VSS M5 GND
VSS M6 GND
VSS M7 GND
VSS N34 GND
VSS N37 GND
VSS N4 GND
VSS N40 GND
VSS P2 GND
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
96 Datasheet, Volume 1
Processor Land and Signal Information
VSS P5 GND
VSS R4 GND
VSS T33 GND
VSS T36 GND
VSS T37 GND
VSS T38 GND
VSS T39 GND
VSS T5 GND
VSS U4 GND
VSS V5 GND
VSS W33 GND
VSS W34 GND
VSS W35 GND
VSS W36 GND
VSS W37 GND
VSS W38 GND
VSS Y7 GND
VSS_SENSE T34 Analog
VSS_SENSE_VTT AE36 Analog
VSSAXG_SENSE B13 Analog
VTT AA33 PWR
VTT AA34 PWR
VTT AA35 PWR
VTT AA36 PWR
VTT AA37 PWR
VTT AA38 PWR
VTT AB7 PWR
VTT AC33 PWR
VTT AC34 PWR
VTT AC35 PWR
VTT AC36 PWR
VTT AC37 PWR
VTT AC38 PWR
VTT AC39 PWR
VTT AC40 PWR
VTT AC5 PWR
VTT AC8 PWR
VTT AD33 PWR
VTT AD34 PWR
VTT AD35 PWR
VTT AD36 PWR
VTT AD37 PWR
VTT AD38 PWR
VTT AD39 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
VTT AD40 PWR
VTT AE33 PWR
VTT AE34 PWR
VTT AE39 PWR
VTT AE40 PWR
VTT AE8 PWR
VTT AF33 PWR
VTT AG33 PWR
VTT AJ17 PWR
VTT AJ19 PWR
VTT AJ21 PWR
VTT AJ23 PWR
VTT AJ25 PWR
VTT AJ27 PWR
VTT AJ29 PWR
VTT AJ31 PWR
VTT AJ32 PWR
VTT AK19 PWR
VTT AK20 PWR
VTT AK21 PWR
VTT AL20 PWR
VTT AL21 PWR
VTT L10 PWR
VTT M10 PWR
VTT M11 PWR
VTT M9 PWR
VTT N7 PWR
VTT P6 PWR
VTT P7 PWR
VTT P8 PWR
VTT T2 PWR
VTT T6 PWR
VTT T7 PWR
VTT T8 PWR
VTT V2 PWR
VTT V33 PWR
VTT V34 PWR
VTT V35 PWR
VTT V36 PWR
VTT V37 PWR
VTT V38 PWR
VTT V39 PWR
VTT V40 PWR
VTT V6 PWR
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
Datasheet, Volume 1 97
Processor Land and Signal Information
§ §
VTT V7 PWR
VTT V8 PWR
VTT W1 PWR
VTT W6 PWR
VTT Y33 PWR
VTT Y34 PWR
VTT Y35 PWR
VTT Y36 PWR
VTT Y37 PWR
VTT Y38 PWR
VTT_SELECT AF39 CMOS O
VTT_SENSE AE35 Analog
VTTPWRGOOD AG37 Asynch CMOS I
Table 8-2. Processor Pin List by Pin
Name
Pin Name Pin # Buffer Type Dir.
98 Datasheet, Volume 1
Processor Land and Signal Information
