MCM63P736•MCM63P818
1
MOTOROLA FAST SRAM
128K x 36 and 256K x 18 Bit
Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P736 and MCM63P818 are 4M–bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC and other high performance microprocessors. The MCM63P736 is
organized as 128K words of 36 bits each, and the MCM63P818 is organized as
256K words of 18 bits each. These devices integrate input registers, an output
register , a 2–bit address counter, and high speed SRAM onto a single monolithic
circuit for reduced parts count in cache data RAM applications. Synchronous
design allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled
through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P736 and MCM63P818
(burst sequence operates in linear or interleaved mode dependent upon the state
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are
asserted with SW . All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply
and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs
are JEDEC standard JESD8–5 compatible.
•MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
•3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
•ADSP, ADSC, and ADV Burst Control Pins
•Selectable Burst Sequencing Order (Linear/Interleaved)
•Two–Cycle Deselect Timing
•Internally Self–T imed W rite Cycle
•Byte Write and Global W rite Control
•Sleep Mode (ZZ)
•JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Order this document
by MCM63P736/D
SEMICONDUCTOR TECHNICAL DATA
MCM63P736
MCM63P818
ZP PACKAGE
PBGA
CASE 999–02
TQ PACKAGE
TQFP
CASE 983A–01
REV 3
3/12/99
Motorola, Inc. 1999
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MCM63P736•MCM63P818
2MOTOROLA FAST SRAM
WRITE
REGISTER
a
WRITE
REGISTER
b
ENABLE
REGISTER
BURST
COUNTER
ADSP
G
CLR
WRITE
REGISTER
c*
WRITE
REGISTER
d*
SBa
SBb
SBc*
SBd*
SE3
15/16
17/18
SGW
DATA–OUT
REGISTER
ENABLE
REGISTER
K2 K
ADDRESS
REGISTER 17/18
DATA–IN
REGISTER
128K x 36 /
256K x 18
ARRAY
SE2
LBO
ADV
K
ADSC
SA
SA1
SA0
SW
SE1
K
4/2
36/18
2
2
K2
DQa – DQd /
DQa – DQb
36/18
FUNCTIONAL BLOCK DIAGRAM
WRITE
REGISTER
K
ZZ
*Valid only for MCM63P736.
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MCM63P736•MCM63P818
3
MOTOROLA FAST SRAM
VSS
VDDQ
37 3834 3536 42 4339 40 41 45 464431 32 33 50494847
94 9397 96 95 89 8892 91 90 86 858710099 98 81828384
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
VDDQ
VSS
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC
SA
SA
SA
SA
SA
SA
SA
LBO
NC
NC
VDDQ
VSS
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
DQa
DQa
VSS
VDDQ
VDDQ
VSS
DQc
DQc
DQc
DQc
VDDQ
VSS
VSS
VDDQ
DQd
DQd
DQc
DQc
NC
VDD
NC
DQd
DQd
DQd
VSS
VDDQ
VDD
VSS
SBd
SBc
SBb
SBa
SE3
G
SE1
SE2
SA
SA
SA
SA
SA
SA
SA
SA
SA1
SA0
VDD
VSS
K
ADV
SW
ADSP
ADSC
SGW
6543217
B
C
V
SS
G
A
D
E
F
H
J
VSS
VSS
SBb
VSS
SA
VSS
VSS
VSS
SA SA SA SA
SA SA SA SA
NC SA SA NC
NC
NC
DQb
SA SA
NC
ZZ
SW
DQa
DQa
VDDQ
VDDQ
DQb
VDDQ
DQb
DQb
DQa
DQa
NCVDD
NC
SA
NCNC
NC
NC
DQd DQd VSS SA0
NC
LBO
DQa
DQaSA1VSS
DQdDQd
VDDQ DQd VSS
NC
DQa
DQaSBa
SBdDQdDQd
DQd DQd VSS KV
SS
DQc
DQa
VDD
NCVDD
NCVDD
VDDQ
DQc VSS SGW DQb
DQb
DQbADV
SBcDQcDQc
VDDQ DQc VSS G
DQbSE1VSS
DQcDQc
DQc DQc VSS NC DQb
VDD
NC
NC SE2 SA ADSC
ADSP
K
L
M
N
P
R
T
U
VDDQ VDDQ
SE3
VDDQ VDDQ
NC
119–BUMP PBGA
TOP VIEW Not to Scale
100–PIN TQFP
TOP VIEW
MCM63P736 PIN ASSIGNMENTS
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MCM63P736•MCM63P818
4MOTOROLA FAST SRAM
MCM63P736 TQFP PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
83 ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86 G Input Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89 K Input Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA1, SA0 Input Synchronous Address Inputs: these pins must be wired to the two LSBs
of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
15, 41, 65, 91 VDD Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90 VSS Supply Ground.
14, 16, 38, 39, 42, 43, 66 NC — No Connection: There is no connection to the chip.
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MCM63P736•MCM63P818
5
MOTOROLA FAST SRAM
MCM63P736 PBGA PIN DESCRIPTIONS
Pin Locations Symbol Type Description
4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
4G ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
4F G Input Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
4K K Input Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 5G, 3G, 3L
(a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
4E SE1 Input Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
2B SE2 Input Synchronous Chip Enable: Active high for depth expansion.
6B SE3 Input Synchronous Chip Enable: Active low for depth expansion.
4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
4M SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground.
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U NC — No Connection: There is no connection to the chip.
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MCM63P736•MCM63P818
6MOTOROLA FAST SRAM
VSS
VDDQ
37 3834 3536 42 4339 40 41 45 464431 32 33 50494847
94 9397 96 95 89 8892 91 90 86 858710099 98 81828384
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SA
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQa
DQa
VDDQ
VSS
NC
NC
NC
VSS
DQb
DQb
DQb
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
LBO
NC
NC
VDDQ
VSS
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
NC
NC
VSS
VDDQ
VDDQ
VSS
NC
NC
DQb
DQb
VDDQ
VSS
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VDD
NC
NC
NC
NC
VSS
VDDQ
VDD
VSS
NC
NC
SBb
SBa
SE3
G
SE1
SE2
SA
SA
SA
SA
SA
SA
SA
SA
SA1
SA0
VDD
VSS
K
ADV
SW
ADSP
ADSC
SGW
6543217
B
C
V
SS
G
A
D
E
F
H
J
VSS
VSS
VSS
VSS
SA
VSS
VSS
VSS
SA SA SA SA
SA SA SA SA
SA SA SA SA
NC
NC
NC
SA SA
NC
ZZ
SW
NC
NC
VDDQ
VDDQ
NC
VDDQ
DQa
DQa
DQa
DQa
NCVDD
NC
NC
NCNC
NC
NC
NC DQb VSS SA0
NC
LBO
NC
DQaSA1VSS
NCDQb
VDDQ DQb VSS
NC
NC
DQaSBa
VSS
NCDQb
NC DQb VSS KV
SS
DQb
NC
VDD
NCVDD
NCVDD
VDDQ
NC VSS SGW DQa
DQa
NCADV
SBbDQbNC
VDDQ NC VSS G
NCSE1VSS
DQbNC
DQb NC VSS NC DQa
VDD
NC
NC SE2 SA ADSC
ADSP
K
L
M
N
P
R
T
U
VDDQ VDDQ
SE3
VDDQ VDDQ
NC
119–BUMP PBGA
TOP VIEW Not to Scale
100–PIN TQFP
TOP VIEW
MCM63P818 PIN ASSIGNMENTS
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MCM63P736•MCM63P818
7
MOTOROLA FAST SRAM
MCM63P818 TQFP PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
83 ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86 G Input Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89 K Input Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46, 47, 48,
49, 50, 80, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94
(a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
15, 41, 65, 91 VDD Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90 VSS Supply Ground.
1, 2, 3, 6, 7, 14, 16, 25, 28, 29,
30, 38, 39, 42, 43, 51, 52, 53,
56, 57, 66, 75, 78, 79, 95, 96
NC — No Connection: There is no connection to the chip.
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MCM63P736•MCM63P818
8MOTOROLA FAST SRAM
MCM63P818 PBGA PIN DESCRIPTIONS
Pin Locations Symbol Type Description
4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
4G ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
4F G Input Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
4K K Input Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
4E SE1 Input Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
2B SE2 Input Synchronous Chip Enable: Active high for depth expansion.
6B SE3 Input Synchronous Chip Enable: Active low for depth expansion.
4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
4M SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground.
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U
NC — No Connection: There is no connection to the chip.
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MCM63P736•MCM63P818
9
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 Through 5)
Next Cycle Address
Used SE1 SE2 SE3 ADSP ADSC ADV G 3DQx Write 2, 4
Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z X
Begin Read External 0 1 0 1 0 X X High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
ASYNCHRONOUS TRUTH TABLE
Operation ZZ G I/O Status
Read L L Data Out (DQx)
Read L H High–Z
Write L X High–Z
Deselected L X High–Z
Sleep H X High–Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
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MCM63P736•MCM63P818
10 MOTOROLA FAST SRAM
WRITE TRUTH TABLE
Cycle Type SGW SW SBa SBb SBc
(See Note 1) SBd
(See Note 1)
Read H H X X X X
Read H L H H H H
Write Byte a H L L H H H
Write Byte b H L H L H H
Write Byte c (See Note 1) H L H H L H
Write Byte d (See Note 1) H L H H H L
Write All Bytes H L L L L L
Write All Bytes L X X X X X
NOTE:
1. Valid only for MCM63P736.
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Symbol Value Unit Notes
Power Supply Voltage VDD VSS – 0.5 to 4.6 V
I/O Supply Voltage VDDQ VSS – 0.5 to VDD V 2
Input Voltage Relative to VSS for
Any Pin Except VDD Vin, Vout VSS – 0.5 to
VDD + 0.5 V 2
Input V oltage (Three–State I/O) VIT VSS – 0.5 to
VDDQ + 0.5 V 2
Output Current (per I/O) Iout ± 20 mA
Package Power Dissipation PD1.6 W 3
Temperature Under Bias Tbias – 10 to 85 °C
Storage Temperature Tstg – 55 to 125 °C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could af fect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS — TQFP
Rating Symbol Max Unit Notes
Junction to Ambient (@ 200 lfm) Single–Layer Board
Four–Layer Board RθJA 40
25 °C/W 1, 2
Junction to Board (Bottom) RθJB 17 °C/W 3
Junction to Case (Top) RθJC 9°C/W 4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
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11
MOTOROLA FAST SRAM
PACKAGE THERMAL CHARACTERISTICS — PBGA
Rating Symbol Max Unit Notes
Junction to Ambient (@ 200 lfm) Single–Layer Board
Four–Layer Board RθJA 38
22 °C/W 1, 2
Junction to Board (Bottom) RθJB 14 °C/W 3
Junction to Case (Top) RθJC 5°C/W 4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 2.5 V I/O SUPPLY
(Voltages Referenced to VSS = 0 V)
Parameter Symbol Min Typ Max Unit
Supply Voltage VDD 3.135 3.3 3.6 V
I/O Supply Voltage VDDQ 2.375 2.5 2.9 V
Input Low Voltage VIL – 0.3 — 0.7 V
Input High Voltage VIH 1.7 — VDD + 0.3 V
Input High Voltage I/O Pins VIH2 1.7 — VDDQ + 0.3 V
Output Low Voltage (IOL = 2 mA) VOL — — 0.7 V
Output High Voltage (IOL = – 2 mA) VOH 1.7 — — V
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 3.3 V I/O SUPPLY
(Voltages Referenced to VSS = 0 V)
Parameter Symbol Min Typ Max Unit
Supply Voltage VDD 3.135 3.3 3.6 V
I/O Supply Voltage VDDQ 3.135 3.3 VDD V
Input Low Voltage VIL – 0.5 — 0.8 V
Input High Voltage VIH 2 — VDD + 0.5 V
Input High Voltage I/O Pins VIH2 2 — VDDQ + 0.5 V
Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V
Output High Voltage (IOL = – 4 mA) VOH 2.4 — — V
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 1. Undershoot Voltage
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12 MOTOROLA FAST SRAM
SUPPLY CURRENTS
Parameter Symbol Min Typ Max Unit Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — — ± 1 µA 1
Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ± 1 µA
AC Supply Current (Device Selected, MCM63P736/818–133
All Outputs Open, Freq = Max) MCM63P736/818–100
Includes VDD Only MCM63P736/818–66
IDDA — — 450/380
410/345
350/285
mA 2, 3, 4
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels) ISB2 — — 15 mA 5, 6
Sleep Mode Standby Current (Device Deselected, Freq = Max,
VDD = Max, All Other Inputs Static at CMOS Levels,
ZZ ≥ VDD – 0.2 V)
IZZ — — 5 mA 1, 5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels) ISB3 — — 35 mA 5, 7
Clock Running (Device Deselected, MCM63P736/818–133
Freq = Max, VDD = Max, All Inputs MCM63P736/818–100
Toggling at CMOS Levels) MCM63P736/818–66
ISB4 — — 160/145
135/120
110/95
mA 5, 6
Static Clock Running (Device Deselected, MCM63P736/818–133
Freq = Max,VDD = Max, All Inputs MCM63P736/818–100
Static at TTL Levels) MCM63P736/818–66
ISB5 — — 65/55
50/40
35/30
mA 5, 6
NOTES:
1. LBO and ZZ pins have an internal pull–up and pull–down, respectively; and will exhibit leakage currents of ± 5 µA.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device is deselected as defined by the Truth Table.
6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
7. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
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13
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 1.0 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 2 Unless Otherwise Noted. . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
P
Sbl
MCM63P736–133
MCM63P818–133 MCM63P736–100
MCM63P818–100 MCM63P737–66
MCM63P819–66
Ui
N
Parameter Symbol Min Max Min Max Min Max Unit Notes
Cycle Time tKHKH 7.5 — 10 — 15 — ns
Clock High Pulse Width tKHKL 3 — 4 — 6 — ns 3
Clock Low Pulse Width tKLKH 3 — 4 — 6 — ns 3
Clock Access Time tKHQV — 4 — 5 — 7 ns
Output Enable to Output Valid tGLQV —3.8 — 4 — 6 ns
Clock High to Output Active tKHQX1 0 — 0 — 0 — ns 4, 5
Clock High to Output Change tKHQX2 1.5 — 1.5 — 1.5 — ns 4
Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 4, 5
Output Disable to Q High–Z tGHQZ —3.8 — 4 — 6 ns 4, 5
Clock High to Q High–Z tKHQZ 1.5 7.5 1.5 10 1.5 15 ns 4, 5
Setup T imes: Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
2 — 2 — 2 — ns
Hold T imes: Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5 — 0.5 — 0.5 — ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low . Chip Enable is defined as SE1 low , SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
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14 MOTOROLA FAST SRAM
OUTPUT
Z0 = 50 ΩRL = 50 Ω
1.5 V
Figure 2. AC Test Load
Figure 3. Lumped Capacitive Load and Typical Derating Curve
2000
1600
1200
800
400
0
LUMPED CAPACITANCE, CL (pF)
100806040200
CL
CLOCK ACCESS TIME DELA Y (ps)
OUTPUT
2400
200
600
1800
1400
1000
2200
2.4
INPUT
WAVEFORM
tr
TEST POINT
OUTPUT
BUFFER
2.4
0.6 0.6
OUTPUT
WAVEFORM
OUTPUT LOAD
tf
UNLOADED RISE AND F ALL TIME MEASUREMENT
NOTES:
1. Input waveform has a slew rate of 1 V/ns.
2. Rise time is measured from 0.6 to 2.4 V unloaded.
3. Fall time is measured from 2.4 to 0.6 V unloaded.
Figure 4. Unloaded Rise and Fall Time Characterization
2.4 2.4
0.6 0.6
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15
MOTOROLA FAST SRAM
(a) Pull–Up for 2.5 V I/O Supply
(c) Pull–Down
VOLTAGE (V)
PULL–UP
I (mA) MIN I (mA) MAX
– 0.5
0
0.8
1.25
1.5
2.3
2.7
2.9
– 38
– 38
– 38
– 26
– 20
0
0
0
– 105
– 105
– 105
– 83
– 70
– 30
– 10
0
VOLTAGE (V)
PULL–DOWN
I (mA) MIN I (mA) MAX
– 0.5
0
0.4
0.8
1.25
1.6
2.8
3.2
3.4
0
0
10
20
31
40
40
40
40
0
0
20
40
63
80
80
80
80
Figure 5. Typical Output Buffer Characteristics
2.9
2.5
2.3
2.1
1.25
0.8
00 – 38 – 105
CURRENT (mA)
VOLTAGE (V)
VDD
1.6
1.25
0.3
0040 80
CURRENT (mA)
VOLTAGE (V)
(b) Pull–Up for 3.3 V I/O Supply
VOLTAGE (V)
PULL–UP
I (mA) MIN I (mA) MAX
– 0.5
0
1.4
1.65
2.0
3.135
3.6
– 50
– 50
– 50
– 46
– 35
0
0
– 150
– 150
– 150
– 130
– 101
– 25
0
3.135
2.8
1.5
1.4
00– 50
CURRENT (mA)
VOLTAGE (V)
3.6
– 150– 100
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16 MOTOROLA FAST SRAM
BURST READSINGLE READ
ADSC
tKHKL
tKHKH
E
K
ADSP
ADV
Q(A)
BURST WRITE
ADSP, SA
SA A B
READ/WRITE CYCLES
tKLKH
CD
SE1
W
Q(B) Q(B+1)
tKHQV BURST WRAPS AROUND
Q(B+2) Q(B+3) Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)
tGLQV
DESELECTED SINGLE READ
SE2, SE3
IGNORED
G
tKHQX2 tGHQZ
NOTE: E low = SE2 high and SE3 low.
W low = SGW low and/or SW and SBx low.
DQx Q(n)
tKHQZ tKHQX1 tGLQX
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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ZZ
E
K
ADS
ADV
SLEEP MODE TIMING
W
G
tZZQZ
ADS high = both ADSC, ADSP high.
NOTE: ADS low = ADSC low or ADSP low.
tZZS tZZREC
E low = SE1 low, SE2 high, SE3 low.
ADDR
DQ
NORMAL OPERATION
NO READS OR
WRITES ALLOWEDIN SLEEP MODE
NO NEW READS OR
WRITES ALLOWEDNORMAL OPERATION
IZZ
I (max) specifications will not be met if inputs toggle.
ZZ
IDD
MCM63P736•MCM63P818
17
MOTOROLA FAST SRAM
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18 MOTOROLA FAST SRAM
APPLICATION INFORMATION
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P736 and MCM63P818. It allows the system
designer to place the RAM in the lowest possible power
condition by asserting ZZ. The sleep mode timing diagram
shows the different modes of operation: Normal Operation,
No READ/WRITE Allowed, and Sleep Mode. Each mode has
its own set of constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
times prior to sleep and tZZREC nanoseconds after re-
covering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to
sleep, initiation of either a read or write operation is not
allowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep
current (IZZ). All inputs are allowed to toggle — the RAM will
not be selected and perform any reads or writes. However, if
inputs toggle, the IZZ (max) specification will not be met.
Note: It is invalid to go from stop clock mode directly into
sleep mode.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and other high end MPU–based systems, these SRAMs can
be used in other high speed L2 cache or memory applica-
tions that do not require the burst address feature. Most L2
caches designed with a synchronous interface can make use
of the MCM63P736 and MCM63P818. The burst counter
feature of the BurstRAMs can be disabled, and the SRAMs
can be configured to act upon a continuous stream of ad-
dresses. See Figure 6.
CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)
Non–Burst ADSP ADSC ADV SE1 SE2 LBO
Sync Non–Burst,
Pipelined SRAM H L H L H X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
WRITESREADS
DQ
K
Q(B)Q(A)
ADDR A B CD EFGH
W
Q(D)Q(C) D(F)D(E) D(H)D(G)
G
Figure 6. Example Configuration as Non–Burst Synchronous SRAM
SE3
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MOTOROLA FAST SRAM
MCM 63P818 XX X X
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM63P736TQ133 MCM63P736TQ100 MCM63P736TQ66
MCM63P736TQ133R MCM63P736TQ100R MCM63P736TQ66R
MCM63P736ZP133 MCM63P736ZP100 MCM63P736ZP66
MCM63P736ZP133R MCM63P736ZP100R MCM63P736ZP66R
MCM63P818TQ133 MCM63P818TQ100 MCM63P818TQ66
MCM63P818TQ133R MCM63P818TQ100R MCM63P818TQ66R
MCM63P818ZP133 MCM63P818ZP100 MCM63P818ZP66
MCM63P818ZP133R MCM63P818ZP100R MCM63P818ZP66R
Package (TQ = TQFP, ZP = PBGA)
Blank = T rays, R = Tape and Reel
Speed (133 = 133 MHz, 100 = 100 MHz,
66 = 66 MHz)
ORDERING INFORMATION
(Order by Full Part Number)
63P736
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20 MOTOROLA FAST SRAM
TQ PACKAGE
TQFP
CASE 983A–01
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057
b0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013
c0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006
D22.00 BSC 0.866 BSC
E16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC
e0.65 BSC 0.026 BSC
L0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF
S0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008
0 7 0 7
0 ––– 0 –––
11 13 11 13
11 13 11 13
1
2
3
D1 20.00 BSC 0.787 BSC
0.020 REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
A–B0.20 (0.008) H e
D
A–B0.20 (0.008) C D
A–B0.20 (0.008) C D
0.10 (0.004) C
0.25 (0.010)
S
0.05 (0.002)
S
A–B
M
0.13 (0.005) D S
C
e/2
D/2
E
E1
D1
D
D1/2
E1/2
E/2
4X
2X 30 TIPS
2X 20 TIPS
–D–
–B–
–A–
–C–
–H–
1
3
2
100
81
80 51
50
31
301
PLATING
SECTION B–B
c1
c
b
b1
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
BASE
METAL
A
SEATING
PLANE VIEW AB
S
VIEW AB
A2
A1 R1 L2
L
L1
R2 GAGE PLANE
–X–
VIEW Y
B
BX=A, B, OR D
PACKAGE DIMENSIONS
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MCM63P736•MCM63P818
21
MOTOROLA FAST SRAM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D2
E2
4X
16X
119X
TOP VIEW BOTTOM VIEW
SIDE VIEW
D
0.20
6X e
e
7654321
b
0.35 A
CE
0.25 A
0.20 A
A
SEATING
PLANE
A
A1
A2
A3
M
0.3 CA B
M
0.15 A
D1
E1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
DIM MIN MAX
MILLIMETERS
A––– 2.40
A1 0.50 0.70
A2 1.30 1.70
A3 0.80 1.00
D22.00 BSC
D1 20.32 BSC
D2 19.40 19.60
E14.00 BSC
E1 7.62 BSC
E2 11.90 12.10
b0.60 0.90
e1.27 BSC
B
ZP PACKAGE
7 x 17 BUMP PBGA
CASE 999–02
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