Datasheet 1 Rev. 1.0
www.infineon.com 2020-01-16
HITFET
TM
+ 24V
BTT3018EJ Smart Low-Side Power Switch
Features
• Single channel device optimized for 24 V applications
• Electrostatic discharge protection (ESD)
• Over current, active clamping and over temperature protection
• Over temperature latch shutdown
• Supply pin undervoltage protection
• Dedicated status signal
• Slew-rate control to adjust switching speed
• PWM switching capability of 20KHz (duty cycle 10%-90%)
• Green Product (RoHS compliant)
• AEC Qualified
Potential applications
• Suitable for resistive and inductive loads
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The BTT3018EJ is a 16 mΩ single channel Smart Low-Side Power Switch within a PG-TDSO-8 package
providing embedded protective functions. The power transistor is built by a N-channel vertical power
MOSFET. The BTT3018EJ is monolithically integrated.
The BTT3018EJ is automotive qualified and is optimized for 24 V automotive applications.
Table 1 Product Summary
Parameter Symbol Values
Operating Voltage Range VOUT 0 … 36 V
Maximum load voltage VBAT(OUT) 63 V
ON-State Resistance RDS(ON)_25 16 mΩ
Nominal Load Current IL(NOM) 7.0 A
Minimum Current Limitation IL(LIM) 30 A
Datasheet 2 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Type Package Marking
BTT3018EJ PG-TDSO-8 T3018EJ
Datasheet 3 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Transient Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Output On-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Resistive Load Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Adjustable switching speed / Slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.1 Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.2 Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Reverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Undervoltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Over Voltage Clamping on Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Overcurrent Limitation / Short Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Reset latch condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Functional Description of the STATUS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Characterisation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.1 Layout recommendations/considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table of Contents
Datasheet 4 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
10.2 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Datasheet 5 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Block Diagram
1 Block Diagram
Figure 1 Block Diagram of the BTT3018EJ
OUT
GND
IN
VDD
STATUS
Over-temperature
Pr ot ecti o n
Over-current
Pr ot ecti o n
Supply
Unit Gate
Driving
Unit
Ove r-voltage
Pr ot ecti o n
St atu s
Feedback
ES D
Prot ecti on
Slewrat e
ad j ustm en t
SRP
ES D
Prot ectio n
ES D
Prot ecti on
ES D
Prot ectio n
Under-voltage
Pr ot ecti o n
La tch
Lo gic
Datasheet 6 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Pin Configuration
2 Pin Configuration
2.1 Pin Assignment
Figure 2 Pin Configuration. PG-TDSO-8
2.2 Pin Definitions and Functions
Pin Symbol I/O Function
1 IN I If IN is high, switches ON the Power DMOS
If IN is low, switches OFF the Power DMOS
2 VDD I Logic supply voltage pin, 3.3V to 5.5V
3 STATUS I/O RESET thermal latch function by microcontroller and pull-up
If STATUS is high, device is in normal operation
If STATUS is low, device is in over temperature condition
4 SRP I Slewrate control with external resistor
5 NC Pin internally not connected
6, 7, 8 GND I/O GND; Source of power DMOS and logic1)
1) All GND pins must be connected together
Cooling Tab OUT I/O Load connection, Drain of power DMOS
GND
GND
GND
IN
VDD
STATUS
SRP NC
1
3
2
8
7
6
45
OUT
Datasheet 7 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Pin Configuration
2.3 Voltage and Current Definition
Figure 3 Naming definition of electrical parameters
V
BA T
GND
IN
V
BA T
V
IN
I
IN
GND
Z
L
I
L
,
I
D
V
OUT,
V
DS
OUT
VDD
I
DD
V
DD
V
DD
STA TUS
I
ST ATU S
R
ST ATU S
V
ST ATU S
SRP
I
SR P
V
SR P
R
SR P
Datasheet 8 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
General Product Characteristics
3 General Product Characteristics
3.1 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) Not subject to production test, specified by design.
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Output Voltages
Output Voltage VOUT -0.3 – 63 V internally clamped P_3.1.1
Battery Voltage for short circuit
protection
(Extended Range)
VBAT(SC) -0.3 – 36 V VIN = 5V P_3.1.2
Power Stage
Load current IL0–IL(LIM) A– P_3.1.3
Logic Pins
IN Pin Voltage VIN -0.3 – 5.5 V – P_3.1.4
STATUS Pin Voltage VSTATUS -0.3 – 5.5 V – P_3.1.5
SRP Pin Voltage VSRP -0.3 – 5.5 V – P_3.1.6
VDD Pin Voltage VDD -0.3 – 6.5 V – P_3.1.7
Energy capability
Energy. Single pulse EAS – – 150 mJ IL(0) = IL(NOM)
VBAT = 28 V
TJ(0) = 150°C
P_3.1.8
Energy. Repetitive pulse
1 M cycles
EAR(1M) ––80mJI
L(0) = IL(NOM)
VBAT = 28V
TJ(0) = 105°C
P_3.1.11
Temperatures
Junction Temperature TJ-40 – 150 °C – P_3.1.13
Storage Temperature TSTG -55 – 150 °C – P_3.1.14
ESD Susceptibility
ESD Susceptibility (all pins
except OUT tab, to GND)
VESD -2 – 2 kV HBM2)
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF.)
P_3.1.15
ESD Susceptibility (OUT tab to
GND)
VESD_OUT -4 – 4 kV HBM2) P_3.1.16
ESD Susceptibility (all pins) VESD_CDMA -500 – 500 V CDM3)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101.
P_3.1.17
ESD Susceptibility (corner pins) VESD_CDMC -750 – 750 V CDM3) P_3.1.18
Datasheet 9 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
General Product Characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
datasheet. Fault conditions are considered as outside normal operating range. Protection functions are not
designed for continuous repetitive operation.
3.2 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
table.
Table 3 Functional Range
1)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Battery Voltage Range for
Nominal Operation
VBAT(NOR) 6–36V– P_3.2.1
Supply Voltage Range for
Nominal Operation
VDD(NOR) 3.3 – 5.5 V – P_3.2.2
Supply Voltage Range for
Extended_1 Operation
VDD(EXT1) 3.0 – 5.5 V 1)
Parameter
deviations
possible
1) Not subject to production test, specified by design.
P_3.2.6
Battery Voltage Range for
Extended_2 Operation
VDD(EXT2) 5.5 – 6.5 V 1)
VBAT < 46V;
Parameter
deviations
possible
P_3.2.7
Junction Temperature TJ-40 – 150 °C – P_3.2.4
External Resistor Range for
Adjustable Slewrate
Operation
RSRP 2.2 – 160 kΩ–P_3.2.5
Datasheet 10 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
General Product Characteristics
3.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
3.4 Transient Thermal Impedance
Figure 4 Typical transient thermal impedance ZthJA = f(tp), Ta = 85°C
Value is according to Jedec JESD51-2, at natural convection on FR4 boards. Where
applicable a thermal via array under the ex posed pad contacted the first inner copper layer.
Device is dissipating 1 W power.
Table 4 Thermal Resistance
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to Case RthJC –0.84–K/W
1) 2)
1) Not subject to production test, specified by design.
2) Specified RthJC value is simulated at natural convection on a cold plate setup. Bottom of the package is fixed to
ambient temperature. TAMB = 85°C. Device loaded with 1 W power
P_3.3.1
Junction to Ambient 2s2p RthJA(2s2p) –30–K/W
1) 3)
3) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The Product (Chip +
Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu).
TAMB = 85°C. Device loaded with 1 W power
P_3.3.2
Datasheet 11 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Power Stage
4 Power Stage
4.1 Output On-state Resistance
The on-state resistance depends on the supply voltage (VDD) and on the junction temperature (TJ). Figure 5
shows these dependencies. The behavior in reverse polarity is described in chapter“Reverse Current
Capability” on Page 15.
Figure 5 Typical On-State Resistance,
RDS(ON) = f(TJ); VDD = VIN = 5 V, 3 V
Datasheet 12 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Power Stage
4.2 Resistive Load Output Timing
Figure 6 shows the typical timing when switching a resistive load.
Both -(ΔV/Δt)ON and (ΔV/Δt)OFF can be calculated using the following formulas:
Turn-on Slew rate: -(ΔV/Δt)ON= (0.6 x VBAT) / tF
Turn-off Slew rate: (ΔV/Δt)OFF= (0.6 x VBAT) / tR
NB: the coefficient 0.6 is based on 20% to 80% of VBAT, this is how the measurement of ΔV is defined.
As shown in Figure 6 tON and tOFF can be calculated from delay time (tDON, tDOFF) and falling/rising time (tF, tR)
using the following formulas:
Turn-on time: tON = tDON + tF
Turn-on time: tOFF = tDOFF + tR
Figure 6 Definition of Power Output Timing for Resistive Load
4.3 Adjustable switching speed / Slew rate
Figure 7 Simplified SRP circuit
Figure 7 shows the slew rate control circuit of the BTT3018EJ. The circuit includes an ESD protection
mechanism via a zener structure.
t
VOUT
V
BA T
t
20 %
80 %
tON
tDON
tOF F
tDOFF
VIN
V
IN ( TH ) L
V
IN ( TH ) H
-(
Δ
V/
Δ
t)ON (
Δ
V/
Δ
t)OF F
tFtR
SRP
GND
RSR P (in t )
ESD
Driver
&
Logic
RSR P
Datasheet 13 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Power Stage
In order to optimize the switching speed of the MOSFET to a specific application, an external resistor can be
connected between SRP pin and GND to select the desired slew rate (see switching timings in Chapter 8.1).
The adjustment of the slew rate also allows to balance between electromagnetic emissions and power
dissipation.
To reduce the number of external components, the SRP pin can be connected directly to GND. This sets the
slew rate at its largest value enabling fast switching timings.
It is not recommanded to connected directly SRP pin to VDD or to leave it floating (open).
The accuracy of the switching speed is dependent on the accuracy of the external resistor used. It is
recommended to use short connections between the SRP pin and either RSRP, GND bias.
Figure 8 show the typical relation between switching speed and the external SRP resistor (RSRP).
Figure 8 Typical diagram representing the relation between RSRP and tON, tOFF; VDD= 3V, 5V
Datasheet 14 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Power Stage
4.3.1 Output Clamping
When switching off inductive loads with low side switches, the drain-source voltage VOUT rises above the
battery potential due to the inductance tendency to continue driving the current. To prevent unwanted high
voltages, the device has a voltage clamping mechanism to keep the voltage at VOUT(CLAMP). During this clamping
operation mode the device heats up as it dissipates the energy from the inductance. Therefore the maximum
allowed load inductance is limited. See Figure 9 and Figure 10 for more details.
Figure 9 Output Clamp Circuitry
Figure 10 Switching an Inductive Load
Note: Repetitive switching of an inductive load by VDD instead of using the input pin is a not recommended
operation and may affect the device reliability and reduce the lifetime.
4.3.2 Maximum Load Inductance
During the demagnetization of inductive loads, energy has to be dissipated by the device.
This energy can be calculated by the following equation:
GND ( DMOS Source)
OUT (DMOS Drain )
I
GND
V
BAT
Z
L
I
L
V
OUT
t
t
V
OUT
V
BAT
t
I
OUT
V
OUT(CLAMP)
V
IN
Datasheet 15 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Power Stage
(4.1)
Following equation is simplified under the assumption of RL = 0
(4.2)
Figure 11 shows the inductance for a given current the device BTT3018EJ can withstand.
For maximum single avalanche energy please also refer to EAS parameter in Chapter 3.1
Figure 11 Maximum load inductance for single pulse
IL= f(L); TJ(0) = 150 °C; VBAT = 28 V
4.4 Reverse Current Capability
A reverse battery situation means that the device drain is pulled below GND potential to -VBAT. In this situation
the load is driven by a current through the intrinsic body diode of the BTT3018EJ and all protections, such as
current limitation, over temperature or over voltage clamping, are not active.
In inverse or reverse operation via the reverse body diode, the device is dissipating a power loss which is
defined by the driven current and the voltage drop on the body diode.
4.5 Characteristics
Please see “Power Stage” on Page 23 for electrical characteristic table.
L
L
CLAMPOUTBAT
LL
L
CLAMPOUTBAT
CLAMPOUT R
L
I
VV
IR
R
VV
V×
+
−
×
−×
−
×=
)(
)(
)( 1lnE
−
−×=
)(
2
1
2
1
CLAMPOUTBAT
BAT
L
VV
V
LIE
Datasheet 16 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Supply and Input Stage
5 Supply and Input Stage
Figure 12 Simplified supply and input circuit
Figure 12 shows the supply and input circuit of the BTT3018EJ. Both terminals include an ESD protection
mechanism via a zener structure.
5.1 Supply Circuit
The device’s supply is not internally regulated but provided by an external supply. Therefore a reverse polarity
protected and buffered (3.3V .. 5.5V) voltage supply is required at VDD pin. To achieve the best RDS(ON) and the
fastest switching speed a 5V supply is required.
5.1.1 Undervoltage Shutdown
In order to ensure a stable device behavior under all allowed conditions, the supply voltage VDD is monitored.
The output switches off if the supply voltage VDD drops below the switch-off threshold VDD(TH)L. If the supply
voltage VDD drops below the supply voltage reset threshold VDD(RESET), a reset of the STATUS signal and the
latch-OFF state will occur. The device functions are only given for supply voltages above the supply voltage
threshold VDD(TH)H.
5.1.2 Supply current consumption
The supply current consumption is determined by the state of the IN pin, being low, with the IDD(OFF) and being
high, with the IDD(ON). After a thermal shutdown, when the device is in OFF latch mode, the current
consumption values matches the normal ON state IDD(ON) as long as input is high.
However in PWM the consumption depends on the switching frequency. The higher the frequency, the higher
the IDD(PWM).
Figure 13 shows the typical relation between the supply current consumption and the switching frequency
considering a duty-cycle of 50%.
IN
VDD
GND
R
DD
R
IN
ESD
ESD
Driver
&
Logic
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HITFETTM+ 24V
BTT3018EJ
Protection Functions
6 Protection Functions
The BTT3018EJ provides embedded protection functions. They are designed to prevent IC destruction under
fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operation.
Protection functions are not to be used for continuous or repetitive operation.
6.1 Over Voltage Clamping on Output
The BTT3018EJ is designed with a voltage clamp circuitry that limits the drain-source voltage VDS at a certain
level VOUT(CLAMP). The over voltage clamping is overruling the other protection functions. Power dissipation has
to be limited to not exceed the maximum allowed junction temperature.
This function is also used in terms of inductive clamping. Please see also “Output Clamping” on Page 14 for
more details.
6.2 Thermal Protection
The device is protected against over temperature due to overload and/or bad cooling conditions by an
integrated static temperature sensor. The thermal protection is available when the device is active. In the
event of over temperature shutdown TJ(SD), the device will remain OFF until the device is reset via STATUS pin.
Please see Figure 14 and Figure 15.
6.3 Overcurrent Limitation / Short Circuit Behavior
This BTT3018EJ provides an overcurrent limitation intended to protect against short circuit or over current
conditions.
When the drain current reaches the current limitation level IL(LIM), the device will limit the current at that level.
While doing so, the power dissipation will heat up the device. Once the device reaches the over temperature
shutdown threshold TJ(SD), it will automatically shutdown and remain OFF until it is reset via STATUS pin.
6.4 Reset latch condition
The reset of the latch OFF mode is done in two steps that need to be performed in the correct sequence. During
the first step, the voltage at the STATUS pin must be below the VSTATUS(RESET)L threshold for a time t >
tSTATUS(RESET)L. In the second step of the reset sequence, the STATUS pin voltage needs to be pulled-up above
the VSTATUS(RESET)H threshold for a time t > tSTATUS(RESET)H. The total reset time is given by the sum of tSTATUS(RESET)L
and tSTATUS(RESET)H.
The following sub-chapters explain in more details the reset functionality in different conditions.
Reset via STATUS pin
If the temperature protection shutdowns the device, it will remain latched OFF independently of the input
signal at IN pin. Simultaneously, the STATUS pin signal will be signalized low VSTATUS(LATCH). In order to reset the
latch condition, the STATUS pin needs to remain below VSTATUS(RESET)L for a minimum time tSTATUS(RESET)L before
being externally pulled-up to VSTATUS(RESET)H for a minimum time tSTATUS(RESET)H. Please refer to Figure 14 and the
application diagram in Figure 33.
This configuration allows the device to be driven with high frequency PWM signal via the IN pin without a risk
of resetting the device in case it goes in protection shut-down mode (latch OFF).
Datasheet 19 Rev. 1.0
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BTT3018EJ
Protection Functions
Figure 14 Mechanism to reset latch condition via STATUS pin
Reset via STATUS pin and IN pin connected together
If STATUS pin and IN pin are connected together (No RSTATUS pull-up external resistor), the voltage provided
through the IN pin will prevent the STATUS low notification. To reset the device under this condition, the
STATUS-IN connection needs to be pulled-down to VSTATUS(RESET)L for a minimum time tSTATUS(RESET)L before
being pulled-up to VSTATUS(RESET)H for a minimum time tSTATUS(RESET)H. Please refer to Figure 15 and the
application diagram in Figure 34.
If no diagnosis of the device is required, this configuration avoids the need of a dedicated I/O from the
microcontroller for the STATUS pin. The maximum frequency to not reset the device allowed in PWM mode is
constrained by the tSTATUS(RESET)L and tSTATUS(RESET)H times.
V
ST AT U S
t
Thermal s hutdown
t
T
j
T
j(SD)
t
STATUS(RESET)L
V
OUT
t
t
I
D
,
I
L
I
L(LIM )
Current l imitation
Ov er c ur r en t e ve nt
t
STATUS(RESET)H
IN
t
No reset via IN
Total RESET time
External pull-up
STATUS pin high
V
STATUS(RESET)H
V
STATUS(RESET)L
V
STAT US(LATCH)
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HITFETTM+ 24V
BTT3018EJ
Protection Functions
Figure 15 Mechanism to reset latch condition with STATUS pin and IN pin connected together
Note: For better understanding, the time scale is not linear. The real timing of this drawing is application
dependant and cannot be described.
6.5 Characteristics
Please see “Protection” on Page 25 for electrical characteristic table.
VIN ,
VST ATU S
t
Ther mal shutdown
t
Tj
Tj(SD)
VOUT
t
t
ID, IL
IL(LIM)
Current limita ti on
Ov er c ur r en t e ve nt
t
STAT US(RESET)L
t
STATUS(RESET)H
Ext erna l pull-up
IN pin hig h
Total RESET time
External pull-down
IN pin low
V
STATUS(RESET)H
V
STATUS(RESET)L
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HITFETTM+ 24V
BTT3018EJ
Diagnostics
7 Diagnostics
The BTT3018EJ provides a latching digital fault feedback signal on the STATUS pin triggered by an over
temperature shutdown.
Figure 16 Simplified diagnosis circuit
Figure 16 shows the diagnosis circuit of the BTT3018EJ. The circuit include an ESD protection mechanism via
a zener structure. Note that RSTATUS(int) + RDIAG(int) = RSTATUS(LATCH) (cf. P_8.5.12).
7.1 Functional Description of the STATUS Pin
The BTT3018EJ provides digital status information via the STATUS pin to give feedback to a connected
microcontroller.
The readout of the diagnosis signal is only possible if the STATUS pin has a dedicated connection to the
microcontroller and the appropriate pull-up resistor RSTATUS is in place. See Figure 33 for recommended
values of the external components.
The device is able to operate with STATUS pin and IN pin connected together, however this condition will
inhibit the readout of the diagnosis signal.
Normal operation mode
In normal operation (no thermal shutdown) the STATUS pin’s logic is set “high”. It is pulled-up via an external
Resistor (RSTATUS) to VDD. Internally it is connected to an open drain MOSFET through an internal resistor.
Fault operation mode
In case of a thermal shutdown (fault) the internal MOSFET connected to the STATUS pin, pulls it’s voltage
down to GND providing a “low” level signal to the microcontroller VSTATUS(LATCH). Fault mode operation remains
active independent from the input pin state until it is reset.
Reset latch fault signal (external pull up)
To reset the latch fault signal of the BTT3018EJ, the STATUS pin has to be externally pulled-up. This behavior
is shown in Figure 14 “Mechanism to reset latch condition via STATUS pin” on Page 19.
For other configurations and how to reset the latch OFF of the DMOS, please see “Reset latch condition” on
Page 18.
STATUS
GND
R
DI AG(int)
ESD
Driver
&
Lo gic
R
ST ATU S
R
ST ATU S(in t )
120Ω
10KΩ
VDD
R
STATU S(int)
+ R
DI AG(int)
= R
ST ATU S(LA T C H)
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HITFETTM+ 24V
BTT3018EJ
Electrical Characteristics
8 Electrical Characteristics
Note: Characteristics show the deviation of parameter at given input voltage and junction temperature.
Typical values show the typical parameters expected from manufacturing and in typical application
condition.
All voltages and currents naming and polarity in accordance to
Figure 2.3 “Voltage and Current Definition” on Page 7.
8.1 Power Stage
Please see Chapter “Power Stage” on Page 11 for parameter description and further details.
Table 5 Electrical Characteristics: Power Stage
Tj = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Stage - Static Characteristics
On-State resistance
at 5 V supply and 25°C
RDS(ON)_5_25 –1620mΩ
VDD =5V;
TJ= 25°C
P_8.1.1
On-State resistance
at 5 V supply and 150°C
RDS(ON)_5_150 –3338mΩ
VDD =5V;
TJ= 150°C
P_8.1.2
On-State resistance
at 3 V supply and 25°C
RDS(ON)_3_25 –2030mΩVDD =3V;
TJ= 25°C
P_8.1.3
On-State resistance
at 3 V supply and 150°C
RDS(ON)_3_150 –3950mΩVDD =3V;
Tj= 150°C
P_8.1.4
Nominal load current IL(NOM) –7.0– A 1)
TJ< 150°C;
TA= 85°C;
VDD =5V;
P_8.1.5
OFF state load current, Output
leakage current
IL(OFF)_85 –03.0µA
2)
TJ≤85°C
VBAT(NOR)
P_8.1.6
OFF state load current, Output
leakage current at 150°C
IL(OFF)_150 –430µATJ= 150°C
VBAT(NOR)
P_8.1.7
Body Diode
Reverse diode forward voltage -VDS –0.61 V VIN =0V P_8.1.8
Switching times. RSRP = short to GND; VBAT = 28 V; VDD = 5 V; RLoad = 4.7 Ω
see Figure 6 for definition details
Turn-on delay time tDON_5(0) 1.6 2.7 6.8 µs - P_8.1.11
Turn-off delay time tDOFF_5(0) 1.5 2.8 5.5 µs - P_8.1.12
Turn-on output fall time tF_5(0) 0.5 1.4 2.5 µs - P_8.1.13
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BTT3018EJ
Electrical Characteristics
Turn-off output rise time tR_5(0) 0.3 0.8 1.7 µs - P_8.1.14
Switching times. RSRP = 5.8 KΩ;VBAT = 28 V; VDD = 5 V; RLoad = 4.7 Ω
see Figure 6 for definition details
Turn-on delay time tDON_5(5K8) 2.0 3.1 6.9 µs - P_8.1.33
Turn-off delay time tDOFF_5(5K8) 2.4 4.5 7.6 µs - P_8.1.34
Turn-on output fall time tF_5(5K8) 1.1 2.1 3.6 µs - P_8.1.35
Turn-off output rise time tR_5(5K8) 1.0 1.7 2.9 µs - P_8.1.36
Switching times. RSRP = 58 KΩ;VBAT = 28 V; VDD = 5 V; RLoad = 4.7 Ω
see Figure 6 for definition details
Turn-on delay time tDON_5(58K) 5.5 10.5 15.3 µs P_8.1.55
Turn-off delay time tDOFF_5(58K) 8 20.4 40.9 µs P_8.1.56
Turn-on output fall time tF_5(58K) 5.7 11.3 18.6 µs P_8.1.57
Turn-off output rise time tR_5(58K) 6.9 12.8 19.3 µs P_8.1.58
Switching times. RSRP = 1 MΩ;VBAT = 28 V; VDD = 5 V; RLoad = 4.7 Ω
see Figure 6 for definition details
Turn-on delay time tDON_5(1M) 9.3 17.0 42.2 µs - P_8.1.77
Turn-off delay time tDOFF_5(1M) 10.4 44.2 139 µs - P_8.1.78
Turn-on output fall time tF_5(1M) 8.9 26.7 64.7 µs - P_8.1.79
Turn-off output rise time tR_5(1M) 8.9 27.1 68.2 µs - P_8.1.80
1) Not subject to production test, calculated by RthJA and RDS(ON).
2) Not subject to production test, specified by design
Table 5 Electrical Characteristics: Power Stage (cont’d)
Tj = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 25 Rev. 1.0
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BTT3018EJ
Electrical Characteristics
8.2 Protection
Please see Chapter “Protection Functions” on Page 18 for parameter description and further details.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation
Table 6 Electrical characteristics: Protection
Tj = -40°C to +150°C, VBAT = 28 V; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal shutdown
Static thermal shutdown
junction temperature
TJ(SD) 150 175 200 °C 1)
1) Not subject to production test, specified by design.
P_8.2.1
Overtemperature shutdown
STATUS delay at 5 V
tTJ(SD)5 –4.5 µs
1)
Delay time to trigger
STATUS signal
VDD = 5 V
TAMB=25°C
P_8.2.4
Overtemperature shutdown
STATUS delay at 3 V
tTJ(SD)3 –4.2 µs
1)
Delay time to trigger
STATUS signal
VDD = 3 V
TAMB = 25°C
P_8.2.7
Overvoltage Protection / Clamping
Drain clamp voltage VOUT(CLAMP) 63 72 83 V
ID>50mA
P_8.2.8
Current limitation
Current limitation level IL(LIM)_5 30 45 60 A 2)
VDD =5V;
2) Parameter tested at VBAT = 5 V; specified up to VBAT =36V.
P_8.2.9
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BTT3018EJ
Electrical Characteristics
8.3 Supply and Input Stage
Please see Chapter “Supply and Input Stage” on Page 16 for description and further details.
Table 7 Electrical Characteristics: Supply and Input
Tj = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply
Supply on threshold voltage high VDD(TH)H 2.4 2.8 3.0 V P_8.3.2
Supply off threshold voltage low VDD(TH)L 2.3 2.7 2.9 V 1)
DMOS switches OFF
below threshold
P_8.3.3
Supply current,
continuous ON operation
IDD(ON) – 150 250 µA ON-state
;
VIN =5V;
IL(0) =IL(NOM)
P_8.3.5
Standby supply current IDD(OFF) –0.33 µAVIN =0V
VDD =5.0V
P_8.3.11
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BTT3018EJ
Electrical Characteristics
Input
Input on threshold voltage;
5.5 V supply
VIN(TH)H_5.5 1.9 2.4 2.8 V VDD =5.5V P_8.3.13
Input off threshold voltage;
5.5 V supply
VIN(TH)L_5.5 1.2 1.5 1.8 V VDD =5.5V P_8.3.14
Input on threshold voltage;
3 V supply
VIN(TH)H_3 1.2 1.5 1.8 V VDD =3.0V P_8.3.19
Input off threshold voltage;
3 V supply
VIN(TH)L_3 0.7 1.0 1.2 V VDD =3.0V P_8.3.20
Input pull down current IIN 20 45 80 µA VIN ≤5.5 V;
VDD ≤5.5 V
P_8.3.22
1) Undervoltage shutdown protection doesn’t reset the OFF Latch mode.
Table 7 Electrical Characteristics: Supply and Input (cont’d)
Tj = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 28 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Electrical Characteristics
8.4 Diagnostics
Please see Chapter “Diagnostics” on Page 21 for description and further details.
Table 8 Electrical Characteristics: Diagnostics
Tj = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min
.
Typ
.
Max
.
Diagnostics
Status pin latch voltage VSTATUS(LATCH) ––1.0V 1) 2)
VDD = 5 V;
RSTATUS = 100 kOhm;
3V≤VIN ≤ 5V;
latched fault signal
1) Not subject to production test. Specified by design.
2) Latch feedback signal voltage drop considering VDD =5 V and RSTATUS = 100 kOhm.
P_8.5.1
Status pin reset threshold low VSTATUS(RESET)L_5 1.0 1.4 1.7 V 3)
VDD = 5 V
3) Voltage threshold needed at the STATUS pin to initialize the reset sequence of the latch OFF mode. If STATUS pin and
IN pin are connected together, same voltage threshold applies.
P_8.5.2
Status pin reset threshold
high
VSTATUS(RESET)H_5 1.7 2.2 2.6 V 4)
VDD = 5 V
4) Voltage threshold needed at the STATUS pin to complete the reset sequence of the latch OFF mode. If STATUS pin
and IN pin are connected together, same voltage range applies.
P_8.5.3
Status reset low time tSTATUS(RESET)L_5 1.0 1.6 2.4 ms 1)5)
VDD = 5 V
5) Time needed to remain below VSTATUS(RESET)L to initialize the reset sequence of the latch OFF mode. See Chapter 6.4
for more information
P_8.5.4
Status reset high time tSTATUS(RESET)H_5 20 35 50 µs 1)6)
VDD = 5 V
P_8.5.5
Status pin reset threshold low VSTATUS(RESET)L_3 0.7 1.0 1.2 V 3)
VDD = 3 V
P_8.5.6
Status pin reset threshold
high
VSTATUS(RESET)H_3 1.2 1.6 1.9 V 4)
VDD = 3 V
P_8.5.7
Status reset low time tSTATUS(RESET)L_3 0.5 1.0 2.3 ms 1)5)
VDD = 3 V
P_8.5.8
Status reset high time tSTATUS(RESET)H_3 81550µs1)6)
VDD = 3 V
P_8.5.9
Status pin leakage current;
(No Latch)
ISTATUS(NOLATCH) ––1 µA
1)
3V≤VDD ≤5.5 V
VSTATUS ≤5.5 V;
0V≤VIN ≤5.5 V
P_8.5.10
Status pin internal resistance,
(Latch active)
RSTATUS(LATCH) 71015KΩ
RSTATUS(LATCH) = RSTATUS(int)
+ RDIAG(int)
P_8.5.12
Datasheet 30 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Characterisation Results
9 Characterisation Results
Typical performance characteristics
9.1 Power Stage
Figure 17 Typical RDS(ON) vs. VDD; IL=IL(NOM); VIN= 3V; VBAT=28V; RSRP= 0Ω
Figure 18 Typical IL(OFF) vs. TJ @ VIN = 0V; VDD= 0, 5V
Datasheet 31 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Characterisation Results
Figure 19 Typical destruction point EAS vs. IL @ TJ(0)=150°C; VBAT=28V; IL= IL(NOM), 2*IL(NOM)
Figure 20 Typical EAR vs. IL @ TJ(0)=105°C, VBAT= 28V; Nr cycles = 10k, 100k, 1Mio cycles; IL = IL(NOM),
2*IL(NOM)
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BTT3018EJ
Characterisation Results
Figure 21 Typical EON & EOFF vs. SRP @ TJ(0)=150°C, VDD=5.5V & VDD=3V; VBAT = 28V; IN= 5V; STATUS=
pulled-up to VDD; IL =IL(NOM)
Dynamic characteristics
Figure 22 Typical tR vs. RSRP @ VIN = 5V; VDD= 3V, 5V; VBAT= 28V; RL=4.7Ω; TJ=[-40 .. 150°C]
Datasheet 33 Rev. 1.0
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BTT3018EJ
Characterisation Results
Figure 23 Typical tF vs. RSRP @ VIN = 5V; VDD= 3V, 5V; VBAT= 28V; RL=4.7Ω; TJ=[-40 .. 150°C]
Figure 24 Typical tDON vs. RSRP @ VIN = 5V; VDD= 3V, 5V; VBAT= 28V; RL=4.7Ω; TJ=[-40 .. 150°C]
Datasheet 34 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Characterisation Results
Figure 25 Typical tDOFF vs. RSRP @ VIN = 5V; VDD= 3V, 5V; VBAT= 28V; RL=4.7Ω; TJ=[-40 .. 150°C]
9.2 Protection
Figure 26 Typical IL(LIM) vs. VDD; VIN= 5V
Datasheet 35 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Characterisation Results
Figure 27 Typical time to shut down tTJ(SD) vs. IL; VBAT= 28V; VDD= 5V; VIN= 5V; RthJA(1s0p + 300mm2)
9.3 Supply and Input Stage
Figure 28 Typical VDD(TH) vs. TJ; VDD(TH)H, VDD(TH)L; VIN = 3V;RSRP= GND; VBAT = 28V
Datasheet 36 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Characterisation Results
Figure 29 Typical IDD(ON) vs. RSRP; IL=IL(NOM); VIN = 3V; VDD= 5V; VBAT=28V
Figure 30 Typical IDD(ON) vs. VDD; IL=IL(NOM); VIN = 3V; VBAT = 28V; RSRP = GND
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BTT3018EJ
Characterisation Results
Figure 31 Typical IDD(LIM) vs. VDD; VIN = 3V; RSRP= GND; VBAT= 5V
Figure 32 Typical VIN(TH) vs. VDD ; VIN(TH)H, VIN(TH)L; RLOAD = 150kΩ; RSRP =GND; VBAT = 28V
Datasheet 38 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Application Information
10 Application Information
10.1 Layout recommendations/considerations
As consequences of the fast switching times for high currents (INOM and above), special care has to be taken for
the PCB layout. Stray inductances have to be minimized. BTT3018EJ has no separate pin for power ground
and logic ground.
It is recommended:
- to ensure that the offset between the ground connection of the SRP resistor and ground pins of the device is
minimized. RSRP should be placed next to the device and directly connected to the GND pins, to avoid any
influence of GND shift to SRP functionality.
- to ensure that the offset between the ground of the VDD suplly and the ground of the pins of the device is
minimized.
The maximum parasitic capacitance between the SRP line and GND (CSRP) has to be less than 10pF to avoid any
influence on SRP functionality (e.g. switching times).
10.2 Application Diagrams
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 33 Application Diagram to use IN pin and STATUS pin independently
Recommended values for VIN = VDD = 5 V:
RSTATUS = 100 kΩ
Datasheet 39 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Application Information
Figure 34 Application Diagram to use IN pin and STATUS pin simultaneously with different supply and
microcontroller voltage class
Example given for VIN = 3.3V; VDD = 5V allows to mantain an optimal RDS(ON) while driving the input with a 3.3V
microcontroller. This configuration makes not possible the readout of the fault signal and will reset the latch
OFF via IN pin (see parameters in Chapter8.4).
For RSRP recommended values, please see Table 9
Note: This are very simplified examples of an application circuit. The function must be verified in the real
application.
Table 9 RSRP switching modes1)
1) For switching timings please refer to Chapter8.1
RSRP min RSRP max Unit Behavior
02.2kΩFast switching mode. SRP pin can be connected to GND
2.2 160 kΩAdjustable switching mode
160 1000 kΩSlow switching mode
Datasheet 40 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Package Outlines
11 Package Outlines
Figure 35 PG-TDSO-8
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Datasheet 41 Rev. 1.0
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HITFETTM+ 24V
BTT3018EJ
Revision History
12 Revision History
Datasheet 42 Rev. 1.0
2020-01-16
HITFETTM+ 24V
BTT3018EJ
Revision History
Revision Date Changes
Rev. 1.0 2020-01-17 Initial release
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.
Trademarks updated November 2015
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Edition 2020-01-16
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG.
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