CML Microcircuits COMMUNICATION SEMICONDUCTORS D/868A/3 CMX868A Low Power V.22 bis Modem May 2008 Features Applications * V.22 bis 2400/2400 bps QAM * Telephone Telemetry Systems * V.22, Bell 212A 1200/1200 or 600/600 bps DPSK * Remote Utility Meter Reading * V.23 1200/75, 1200/1200, 75, 1200 bps FSK * Security Systems * Bell 202 1200/150, 1200/1200, 150, 1200 bps FSK * Industrial Control Systems * V.21 or Bell 103 300/300 bps FSK * Electronic Cash Terminals * DTMF/Tones Transmit and Receive * Pay-Phones * `Powersave' Standby Mode * Set-Top Boxes 1. Brief Description The CMX868A is a multi-standard modem for use in telephone based information and telemetry systems. Control of the device is via a simple high speed serial bus, compatible with most types of C serial interface. The data transmitted and received by the modem is also transferred over the same serial bus. On-chip programmable Tx and Rx USARTs meeting the requirements of V.14 are provided for use with asynchronous data and allow unformatted synchronous data to be received or transmitted as 8-bit words. A high-quality DTMF decoder with excellent immunity to falsing on voice and a standard DTMF encoder are included. Alternatively, these blocks can be used to transmit and detect user-specific, programmed single and dual-tone signals, call progress signals or modem calling and answering tones. Flexible line driver and receive hybrid circuits are integrated on chip, requiring only passive external components to build a 2 or 4-wire line interface. The device also features a hook switch relay drive output and a Ring Detector circuit which continues to function when the device is in the Powersave mode, providing an interrupt which can be used to wake up the host Controller when line voltage reversal or ringing is detected. The CMX868A operates from a single 2.7 to 5.5V supply over a temperature range of -40C to +85C and is available in 24-pin TSSOP, SOIC and DIP packages. (c) 2008 CML Microsystems Plc Low Power V.22 bis Modem CMX868A CONTENTS Page Section 1. Brief Description ..................................................................................... 1 2. Block Diagram ......................................................................................... 3 3. Signal List ................................................................................................ 4 4. External Components............................................................................. 5 4.1 Ring Detector Interface ............................................................. 6 4.2 Line Interface.............................................................................. 7 5. General Description.............................................................................. 10 5.1 Tx USART.................................................................................. 11 5.2 FSK and QAM/DPSK Modulators ........................................... 12 5.3 Tx Filter and Equaliser ............................................................ 13 5.4 DTMF/Tone Generator ............................................................. 13 5.5 Tx Level Control and Output Buffer....................................... 13 5.6 Rx DTMF/Tones Detectors ...................................................... 14 5.7 Rx Modem Filtering and Demodulation ................................. 15 5.8 Rx Modem Pattern Detectors and Descrambler ................... 16 5.9 Rx Data Register and USART ................................................. 16 5.10 C-BUS Interface........................................................................ 18 5.10.1 General Reset Command ........................................... 18 5.10.2 General Control Register ........................................... 20 5.10.3 Transmit Mode Register ............................................. 22 5.10.4 Receive Mode Register............................................... 26 5.10.5 Tx Data Register.......................................................... 28 5.10.6 Rx Data Register ......................................................... 28 5.10.7 Status Register............................................................ 29 5.10.8 Programming Register ............................................... 32 6. Application Notes ................................................................................. 35 6.1 V.22 bis Calling Modem Application ...................................... 35 6.2 V.22 bis Answering Modem Application ............................... 36 6.3 Reference Diagrams ................................................................ 37 7. Performance Specification................................................................... 38 7.1 Electrical Performance ............................................................ 38 7.1.1 Absolute Maximum Ratings....................................... 38 7.1.2 Operating Limits ......................................................... 38 7.1.3 Operating Characteristics.......................................... 39 7.2 Packaging ................................................................................. 46 It is always recommended that you check for the latest product datasheet version from the Datasheets page of the CML website: [www.cmlmicro.com]. (c) 2008 CML Microsystems Plc 2 D/868A/3 Low Power V.22 bis Modem 2. CMX868A Block Diagram Figure 1 Block Diagram (c) 2008 CML Microsystems Plc 3 D/868A/3 Low Power V.22 bis Modem 3. CMX868A Signal List CMX868A D2/E2/P4 Signal Description Pin No. Name Type 1 XTALN O/P The output of the on-chip Xtal oscillator inverter. 2 XTAL/CLOCK I/P 3 RDRVN O/P 4, 8, 12, 17, 21 VSS Power The input to the oscillator inverter from the Xtal circuit or external clock source. Relay drive output, low resistance pull down to VSS when active and medium resistance pull up to VDD when inactive. The negative supply rail (ground). 5 RD I/P 6 RT BI 7, 16, 24 VDD Power 9 RXAFB O/P Schmitt trigger input to the Ring signal detector. Connect to VSS if Ring Detector not used. Open drain output and Schmitt trigger input forming part of the Ring signal detector. Connect to VDD if Ring Detector not used. The positive supply rail. Levels and thresholds within the device are proportional to this voltage. The output of the Rx Input Amplifier. 10 RXAN I/P The inverting input to the Rx Input Amplifier 11 RXA I/P The non-inverting input to the Rx Input Amplifier 13 VBIAS O/P 14 TXAN O/P Internally generated bias voltage of approximately VDD /2, except when the device is in `Powersave' mode when VBIAS will discharge to VSS. Should be decoupled to VSS by a capacitor mounted close to the device pins. The inverted output of the Tx Output Buffer. 15 TXA O/P The non-inverted output of the Tx Output Buffer. 18 CSN I/P The C-BUS chip select input from the C. 19 COMMAND DATA I/P The C-BUS serial data input from the C. 20 SERIAL CLOCK I/P The C-BUS serial clock input from the C. 22 REPLY DATA T/S 23 IRQN O/P A 3-state C-BUS serial data output to the C. This output is high impedance when not sending data to the C. A `wire-ORable' output for connection to a C Interrupt Request input. This output is pulled down to VSS when active and is high impedance when inactive. An external pullup resistor is required ie R1 of Figure 2 (c) 2008 CML Microsystems Plc 4 D/868A/3 Low Power V.22 bis Modem CMX868A Notes: I/P O/P BI T/S NC 4. = = = = = Input Output Bidirectional 3-state Output No Connection External Components R1 X1 C1, C2 C3, C4 C5 100k 11.0592MHz or 12.288MHz 22pF 100nF 10uF Resistors 5%, capacitors 20% unless otherwise stated. Figure 2 Recommended External Components for a Typical Application This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and VBIAS should be decoupled and the receive path protected from extraneous in-band signals. It is recommended that the printed circuit board is laid out with a VSS ground plane in the CMX868A area to provide a low impedance connection between the VSS pins and the VDD and VBIAS decoupling capacitors. The VSS connections to the Xtal oscillator capacitors C1 and C2 should also be low impedance and preferably be part of the VSS ground plane to ensure reliable start up of the oscillator. (c) 2008 CML Microsystems Plc 5 D/868A/3 Low Power V.22 bis Modem 4.1 CMX868A Ring Detector Interface Figure 3 shows how the CMX868A may be used to detect the large amplitude Ringing signal voltage present on the 2-wire line at the start of an incoming telephone call. The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either C20 and R20 or C21 and R21 to appear at the top end of R22 (point X in Figure 3) in a rectified and attenuated form. The signal at point X is further attenuated by the potential divider formed by R22 and R23 before being applied to the CMX868A RD input. If the amplitude of the signal appearing at RD is greater than the input threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the voltage at RT to VSS by discharging the external capacitor C22. The output of the Schmitt trigger 'B' will then go high, setting bit 14 (Ring Detect) of the Status Register. The minimum amplitude ringing signal that is certain to be detected is: ( 0.7 + Vthi x [R20 + R22 + R23] / R23 ) x 0.707 Vrms where Vthi is the high-going threshold voltage of the Schmitt trigger A (see section 7.1). With R20-22 all 470k as Figure 3, then setting R23 to 68k will guarantee detection of ringing signals of 40Vrms and above for VDD over the range 3 to 5V. R20, 21, 22 R23 R24 C20, 21 C22 D1-4 470k See text 470k 0.1F 0.33F 1N4004 Resistors 5%, capacitors 20% Figure 3 Ring Signal Detector Interface Circuit (c) 2008 CML Microsystems Plc 6 D/868A/3 Low Power V.22 bis Modem CMX868A If the time constant of R24 and C22 is large enough, then the voltage on RT will remain below the threshold of the 'B' Schmitt trigger for the duration of a ring cycle. The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula VRT = VDD x [1 - exp(-t/(R24 x C22)) ] As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x VDD, then the Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at RD. The values of R24 and C22 given in Figure 3 (470k and 0.33F) give a minimum RT charge time of 100 msec, which is adequate for ring frequencies of 10Hz or above. Note that the circuit will also respond to a telephone line voltage reversal. If necessary the C can distinguish between a Ring signal and a line voltage reversal by measuring the time that bit 14 of the Status Register (Ring Detect) is high. If the Ring detect function is not used then pin RD should be connected to VSS and RT to VDD. 4.2 Line Interface A line interface circuit is needed to provide dc isolation and to terminate the line. Typical interface circuits are described below. 2-Wire Line Interface Figure 4a shows an interface circuit for use with a 2-wire line. The complex line termination is provided by R13 and C10, high frequency noise is attenuated by C10 and C11, while R11 and R12 set the receive signal level into the modem. For clarity the 2-wire line protection circuits have not been shown. R11 R12 R13,R14,R15 See text 100k See text C10 C11 C12 33nF 100pF 0.1F Figure 4a 2-Wire Line Interface Circuit (c) 2008 CML Microsystems Plc 7 D/868A/3 Low Power V.22 bis Modem CMX868A Resistor R13 is used to match the AC impedance of the interface to the line. With an ideal transformer this resistor would be equal to the desired impedance (e.g. 600); however in practice with a real transformer, R13 should be set such that the interface as a whole presents the desired impedance. Line transformer manufacturers normally provide guidance in this regard. The transmit line signal level is determined by the voltage swing between the TXA and TXAN pins, less 6dB due to the line termination, and less the loss in the line coupling transformer. Allowing for 1dB loss in the transformer, then with the Tx Mode Register set for a Tx Level Control gain of 0dB the nominal transmit line levels will be: QAM, DPSK and FSK Tx modes (no guard tone) Single tone transmit mode DTMF transmit mode VDD = 3.0V -10dBm -10dBm -6 and -8 dBm VDD = 5.0V -5.5dBm -5.5dBm -1.5 and -3.5 dBm For a line impedance of 600, 0dBm = 775mVrms. See also section 7.1.3 In the receive direction, the signal detection thresholds within the CMX868A are proportional to VDD and are affected by the Rx Gain Control gain setting in the Rx Mode Register. The signal level into the CMX868A is affected by the line coupling transformer loss and the values of R11 and R12 of Figure 4a. Assuming 1dB transformer loss, the Rx Gain Control programmed to 0dB and R12 = 100k, then for correct operation (see section 7.1.3) the value of R11 should be equal to 500 / VDD k i.e. 160k at 3.0V, falling to 100k at 5.0V. (c) 2008 CML Microsystems Plc 8 D/868A/3 Low Power V.22 bis Modem CMX868A 4-Wire Line Interface Figure 4b shows a simplified interface for use with a 600 4-wire line. The line terminations are provided by R10 and R13, the values of which are dependent on the choice of transformer; see notes above. High frequency noise is attenuated by C11 while R11 and R12 set the receive signal level into the modem. Transmit and receive line level settings and the value of R11 are as for the 2-wire circuit. R10, 13 R11 R12 See text See text 100k C3 C11 C12 See Figure 2 100pF 33nF Resistors 5%, capacitors 20% Figure 4b 4-Wire Line Interface Circuit (c) 2008 CML Microsystems Plc 9 D/868A/3 Low Power V.22 bis Modem 5. CMX868A General Description The CMX868A transmit and receive operating modes are independently programmable. The transmit mode can be set to any one of the following: V.22 bis modem. 2400bps QAM (Quadrature Amplitude Modulation). V.22 and Bell 212A modem. 1200 or 600 bps DPSK (Differential Phase Shift Keying). V.21 modem. 300bps FSK (Frequency Shift Keying). Bell 103 modem. 300bps FSK. V.23 modem. 1200 or 75 bps FSK. Bell 202 modem. 1200 or 150 bps FSK. DTMF transmit. Single tone transmit (from a range of modem calling, answer and other tone frequencies) User programmed tone or tone pair transmit (programmable frequencies and levels) Disabled. The receive mode can be set to any one of the following: V.22 bis modem. 2400bps QAM. V.22 and Bell 212A modem. 1200 or 600 bps DPSK. V.21 modem. 300bps FSK. Bell 103 modem. 300 bps FSK. V.23 modem. 1200 or 75 bps FSK. Bell 202 modem. 1200 or 150 bps FSK. DTMF detect. 2100Hz and 2225Hz answer tone detect. Call progress signal detect. User programmed tone or tone pair detect. Disabled. The CMX868A may also be set into a Powersave mode which disables all circuitry except for the C-BUS interface and the Ring Detector. (c) 2008 CML Microsystems Plc 10 D/868A/3 Low Power V.22 bis Modem 5.1 CMX868A Tx USART A flexible Tx USART is provided for all modem modes, meeting the requirements of V.14 for QAM and DPSK modems. It can be programmed to transmit continuous patterns, Start-Stop characters or Synchronous Data. In both Synchronous Data and Start-Stop modes the data to be transmitted is written by the C into the 8bit C-BUS Tx Data Register from which it is transferred to the Tx Data Buffer. If Synchronous Data mode has been selected the 8 data bits in the Tx Data Buffer are transmitted serially, b0 being sent first. In Start-Stop mode a single Start bit is transmitted, followed by 5, 6, 7 or 8 data bits from the Tx Data Buffer - b0 first - followed by an optional Parity bit then - normally - one or two Stop bits. The Start, Parity and Stop bits are generated by the USART as determined by the Tx Mode Register settings and are not taken from the Tx Data Register. Figure 5a Tx USART Every time the contents of the C-BUS Tx Data Register are transferred to the Tx Data Buffer the Tx Data Ready flag bit of the Status Register is set to 1 to indicate that a new value should be loaded into the CBUS Tx Data Register. This flag bit is cleared to 0 when a new value is loaded into the Tx Data Register. Figure 5b Tx USART Function (Start-Stop mode, 8 Data Bits + Parity) If a new value is not loaded into the Tx Data Register in time for the next Tx Data Register to Tx Data Buffer transfer then the Status Register Tx Data Underflow bit will be set to 1. In this event the contents of the Tx Data Buffer will be re-transmitted if Synchronous Data mode has been selected, or if the Tx modem is in Start-Stop mode then a continuous Stop signal (1) will be transmitted until a new value is loaded into the Tx Data Register. In all modes the transmitted bit and baud rates are the nominal rates for the selected modem type, with an accuracy determined by the XTAL frequency accuracy, however for QAM and DPSK modes V.14 requires that Start-Stop characters can be transmitted at up to 1% overspeed (basic signalling rate range) or 2.3% (c) 2008 CML Microsystems Plc 11 D/868A/3 Low Power V.22 bis Modem CMX868A overspeed (extended signalling rate range) by deleting a Stop bit from no more than one out of every 8 (basic range) or 4 (extended range) consecutive transmitted characters. To accommodate the V.14 requirement the Tx Data Register has been given two C-BUS addresses, $E3 and $E4. Data should normally be written to $E3. In QAM or DPSK Start-Stop modes if data is written to $E4 then the programmed number of Stop bits will be reduced by one for that character. In this way the C can delete transmitted Stop bits as needed. In FSK Start-Stop modes, data written to $E4 will be transmitted with a 12.5% reduction in the length of the Stop bit at the end of that character. In all Synchronous Data modes data written to $E4 will be treated as though it had been written to $E3. The underspeed transmission requirement of V.14 is automatically met by the CMX868A as in Start-Stop mode it automatically inserts extra Stop bit(s) if it has to wait for new data to be loaded into the C-BUS Tx Data Register. The optional V.22/V.22 bis compatible data scrambler can be programmed to invert the next input bit in the event of 64 consecutive ones appearing at its input. It uses the generating polynomial: 1 + x-14 + x-17 5.2 FSK and QAM/DPSK Modulators Serial data from the USART is fed via the optional scrambler to the FSK modulator if V.21, V.23, Bell 103 or Bell 202 mode has been selected or to the QAM/DPSK modulator for V.22, V.22 bis and Bell 212A modes. The FSK modulator generates one of two frequencies according to the transmit mode and the value of current transmit data bit. The QAM/DPSK modulator generates a carrier of 1200Hz (Low Band, Calling modem) or 2400Hz (High Band, Answering modem) which is modulated at 600 symbols/sec as described below: 600bps V.22 signals are transmitted as a +90 carrier phase change for a `0' bit, +270 for `1'. For V.22 and Bell 212A 1200bps DPSK the transmit data stream is divided into groups of two consecutive bits (dibits) which are encoded as a carrier phase change: Dibit (left-hand bit is the first of the pair) 00 01 11 10 (c) 2008 CML Microsystems Plc Phase change +90 0 +270 +180 12 D/868A/3 Low Power V.22 bis Modem CMX868A For V.22 bis 2400bps QAM the transmit data stream is divided into groups of 4 consecutive data bits. The first two bits of each group are encoded as a phase quadrant change and the last two bits define one of four elements within a quadrant: First two bits of group (left-hand bit is the first of the pair) 00 01 11 10 Phase quadrant change +90 (e.g. quadrant 1 to 2) 0 (no change of quadrant) +270 (e.g. quadrant 1 to 4) +180 (e.g. quadrant 1 to 3) Figure 6 V.22 bis Signal Constellation 5.3 Tx Filter and Equaliser The FSK or QAM/DPSK modulator output signal is fed through the Transmit Filter and Equaliser block which limits the out-of-band signal energy to acceptable limits. In 600, 1200 and 2400 bps FSK, DPSK and QAM modes this block includes a fixed compromise line equaliser which is automatically set for the particular modulation type and frequency band being employed. This fixed compromise line equaliser may be enabled or disabled by bit 10 of the General Control Register. The amount of Tx equalisation provided compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1 over the frequency band used. 5.4 DTMF/Tone Generator In DTMF/Tones mode this block generates DTMF signals or single or dual frequency tones. In QAM/DPSK modem modes it is used to generate the optional 550 or 1800Hz guard tone. 5.5 Tx Level Control and Output Buffer The outputs (if present) of the Transmit Filter and DTMF/Tone Generator are summed then passed through the programmable Tx Level Control and Tx Output Buffer to the pins TXA and TXAN. The Tx Output Buffer has symmetrical outputs to provide sufficient line voltage swing at low values of VDD and to reduce harmonic distortion of the signal. (c) 2008 CML Microsystems Plc 13 D/868A/3 Low Power V.22 bis Modem 5.6 CMX868A Rx DTMF/Tones Detectors In Rx Tones Detect mode the received signal, after passing through the Rx Gain Control block, is fed to the DTMF / Tones / Call Progress / Answer Tone detector. The user may select any of four separate detectors: The DTMF detector detects standard DTMF signals. A valid DTMF signal will set bit 5 of the Status Register to 1 for as long as the signal is detected. The programmable tone pair detector includes two separate tone detectors (see Figure 11). The first detector will set bit 6 of the Status Register for as long as a valid signal is detected, the second detector sets bit 7, and bit 10 of the Status Register will be set when both tones are detected. The Call Progress detector measures the amplitude of the signal at the output of a 275 - 665 Hz bandpass filter and sets bit 10 of the Status Register to 1 when the signal level exceeds the measurement threshold. 10 0 -10 -20 dB -30 -40 -50 -60 0 0.5 1 1.5 2 kHz 2.5 3 3.5 4 Figure 7a Response of Call Progress Filter The Answer Tone detector measures both amplitude and frequency of the received signal and sets bit 6 or bit 7 of the Status Register when a valid 2225Hz or 2100Hz signal is received. (c) 2008 CML Microsystems Plc 14 D/868A/3 Low Power V.22 bis Modem 5.7 CMX868A Rx Modem Filtering and Demodulation When the receive part of the CMX868A is operating as a modem, the received signal is fed to a bandpass filter to attenuate unwanted signals and to provide fixed compromise line equalisation for 600, 1200 and 2400 bps FSK, DPSK and QAM modes. The characteristics of the bandpass filter and equaliser are determined by the chosen receive modem type and frequency band. The line equaliser may be enabled or disabled by bit 10 of the General Control Register and compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1. The responses of these filters, including the line equaliser and the effect of external components used in Figures 4a and 4b, are shown in Figures 7b-e: dB 10 10 0 0 -10 -10 -20 -20 -30 dB -30 -40 -40 -50 -50 -60 -60 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 kHz Figure 7b QAM/DPSK Rx Filters dB 2 2.5 3 3.5 4 kHz Figure 7c V.21 Rx Filters 10 10 0 0 -10 -10 -20 -20 -30 dB -30 -40 -40 -50 -50 -60 -60 0 0.5 1 1.5 2 2.5 3 3.5 4 0 kHz 0.5 1 1.5 2 2.5 3 3.5 4 kHz Figure 7d Bell 103 Rx Filters Figure 7e V.23/Bell 202 Rx Filters The signal level at the output of the Receive Modem Filter and Equaliser is measured in the Modem Energy Detector block, compared to a threshold value, and the result controls bit 10 of the Status Register. The output of the Receive Modem Filter and Equaliser is also fed to the FSK or QAM/DPSK demodulator depending on the selected modem type. The FSK demodulator recognises individual frequencies as representing received `1' or `0' data bits: (c) 2008 CML Microsystems Plc 15 D/868A/3 Low Power V.22 bis Modem CMX868A The QAM/DPSK demodulator decodes QAM or DPSK modulation of a 1200Hz or 2400Hz carrier and is used for V.22, V.22 bis and Bell 212A modes. It includes an adaptive receive signal equaliser (autoequaliser) that will automatically compensate for a wide range of line conditions in both QAM and DPSK modes. It must be enabled when receiving 2400bps QAM. The auto-equaliser can provide a useful improvement in performance in 600 or 1200bps DPSK modes as well as 2400bps QAM, so although it must be disabled at the start of a handshake sequence, it can be enabled as soon as scrambled 1200bps 1s have been detected. Both FSK and QAM/DPSK demodulators produce a serial data bit stream which is fed to the Rx pattern detector, descrambler and USART block, See Figure 8a. In QAM/DPSK modes the demodulator input is also monitored for the V.22 bis handshake `S1' signal. The QAM/DPSK demodulator also estimates the received bit error rate by comparing the actual received signal against an ideal waveform. This estimate is placed in bits 2-0 of the Status Register. 5.8 Rx Modem Pattern Detectors and Descrambler See Figure 8a. The 1010.. pattern detector operates only in FSK modes and will set bit 9 of the Status Register when 32 bits of alternating 1's and 0's have been received. The `Continuous Unscrambled 1's' detector operates in all modem modes and sets bits 8 and 7 of the Status Register to `01' when 32 consecutive 1's have been received. The descrambler operates only in DPSK/QAM modes and is enabled by setting bit 7 of the Rx Mode Register. The `Continuous Scrambled 1's' detector operates only in DPSK/QAM modes when the descrambler is enabled and sets bits 8 and 7 of the Status Register to `11' when 32 consecutive 1's appear at the output of the descrambler. To avoid possible ambiguity, the `Scrambled 1's' detector is disabled when continuous unscrambled 1's are detected. The `Continuous 0's' detector sets bits 8 and 7 of the Status Register to `10' when NX consecutive 0's have been received, NX being 32 except when DPSK/QAM Start-Stop mode has been selected, in which case NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any Parity bits. All of these pattern detectors will hold the `detect' output for 12 bit times after the end of the detected pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset within 2 msec. 5.9 Rx Data Register and USART A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for QAM and DPSK modems. It can be programmed to treat the received data bit stream as Synchronous data or as Start-Stop characters. In Synchronous mode the received data bits are all fed into the Rx Data Buffer which is copied into the C-BUS Rx Data Register after every 8 bits. In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the required number of data bits (not parity) into the Rx Data Buffer. The parity bit (if used) and the presence of a Stop bit are then checked and the data bits in the Rx Data Buffer copied to the C-BUS Rx Data Register. (c) 2008 CML Microsystems Plc 16 D/868A/3 Low Power V.22 bis Modem CMX868A Figure 8a Rx Modem Data Paths Whenever a new character is copied into the C-BUS Rx Data Register, the Rx Data Ready flag bit of the Status Register is set to `1' to prompt the C to read the new data and, in Start-Stop mode, the Even Rx Parity flag bit of the Status Register is updated. In Start-Stop mode, if the Stop bit is missing (received as a `0' instead of a `1') the received character will still be placed into the Rx Data Register and the Rx Data Ready flag bit set, but, unless allowed by the V.14 overspeed option described below, the Status Register Rx Framing Error bit will also be set to `1' and the USART will re-synchronise onto the next `1' - `0' (Stop - Start) transition. The Rx Framing Error bit will remain set until the next character has been received. Figure 8b Rx USART Function (Start-Stop mode, 8 Data Bits + Parity) If the C has not read the previous data from the Rx Data Register by the time that new data is copied to it from the Rx Data Buffer then the Rx Data Overflow flag bit of the Status Register will be set to 1. The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read by the C. For QAM and DPSK Start-Stop modes, V.14 requires that the receive USART be able to cope with missing Stop bits; up to 1 missing Stop bit in every 8 consecutive received characters being allowed for the +1% overspeed (basic signalling rate) V.14 mode and 1 in 4 for the +2.3% overspeed (extended signalling rate) mode. To accommodate the requirements of V.14, the CMX868A Rx Mode Register can be set for 0, +1% or +2.3% overspeed operation in QAM or DPSK Start-Stop modes. Missing Stop bits beyond those allowed by the selected overspeed option will set the Rx Framing Error flag bit of the Status Register. In order that received Break signals can be handled correctly in V.14 Rx overspeed mode, a received character which has all bits `0', including the Stop and any Parity bits, will always cause the Rx Framing Error bit to be set and the USART to re-synchronise onto the next `1' - `0' transition. (c) 2008 CML Microsystems Plc 17 D/868A/3 Low Power V.22 bis Modem CMX868A Additionally the received Continuous 0s detector will respond when more than 2M + 3 consecutive `0's are received, where `M' is the selected total number of bits per character including Stop and any Parity bits. 5.10 C-BUS Interface This block provides for the transfer of data and control or status information between the CMX868A's internal registers and the C over the C-BUS serial bus. Each transaction consists of a single Register Address byte sent from the C which may be followed by a one or more data byte(s) sent from the C to be written into one of the CMX868A's Write Only Registers, or a one or more byte(s) of data read out from one of the CMX868A's Read Only Registers, as illustrated in Figure 9. Data sent from the C on the Command Data line is clocked into the CMX868A on the rising edge of the Serial Clock input. Reply Data sent from the CMX868A to the C is valid when the Serial Clock is high. The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with most common C serial interfaces and may also be easily implemented with general purpose C I/O pins controlled by a simple software routine. Figure 14 gives detailed C-BUS timing requirements. The following C-BUS addresses and registers are used by the CMX868A: General Reset Command (address only, no data). General Control Register, 16-bit write only. Transmit Mode Register, 16-bit write-only. Receive Mode Register, 16-bit write-only. Transmit Data Register, 8-bit write only. Receive Data Register, 8-bit read-only. Status Register, 16-bit read-only. Programming Register, 16-bit write-only. Address $01 Address $E0 Address $E1 Address $E2 Addresses $E3 and $E4 Address $E5 Address $E6 Address $E8 Note: The C-BUS addresses $E9, $EA and $EB are allocated for production testing and should not be accessed in normal operation. 5.10.1 General Reset Command General Reset Command (no data) C-BUS address $01 This command resets the device and clears all bits of the General Control , Transmit Mode and Receive Mode Registers and bits 15 and 13-0 of the Status Register. Whenever power is applied to the CMX868A, a General Reset command should be sent to the device. This action will cause the device to enter a powersave state (General Control Register bit 8 will be cleared to '0'). Note that the CMX868A does not automatically perform a power-on reset when power is first applied. To bring the device out of powersave, please refer to the description of bits 7 and 8 in the General Control Register, section 5.10.2. (c) 2008 CML Microsystems Plc 18 D/868A/3 Low Power V.22 bis Modem CMX868A Figure 9 C-BUS Transactions (c) 2008 CML Microsystems Plc 19 D/868A/3 Low Power V.22 bis Modem 5.10.2 CMX868A General Control Register General Control Register: 16-bit write-only. C-BUS address $E0 This register controls general features of the CMX868A such as the Powersave and Loopback modes, the IRQ mask bits and the Relay Drive output. It also allows the fixed compromise equalisers in the Tx and Rx signal paths to be disabled if desired, and sets the internal clock dividers to use either a 11.0592 or a 12.288 MHz XTAL frequency. All bits of this register are cleared to 0 by a General Reset command. Bit: 15 0 14 13 TXA TXAN off off 12 11 10 9 8 7 6 Xtal freq LB Equ Rly drv Pwr Rst Irqn en 5 4 3 2 1 0 IRQ Mask Bits General Control Register b15: Reserved, set to 0 General Control Register b14: Disconnect TXA Output This bit allows the TXA output to be disconnected and set to high impedance. b14 = 1 b14 = 0 TXA output disconnected. TXA output connected (normal modem operation). General Control Register b13: Disconnect TXAN Output This bit allows the TXAN output to be disconnected and set to high impedance. b13 = 1 b13 = 0 TXAN output disconnected. TXAN output connected (normal modem operation). General Control Register b12: Xtal frequency This bit should be set according to the Xtal frequency. b12 = 1 b12 = 0 11.0592MHz 12.2880MHz General Control Register b11: Analogue Loopback test mode This bit controls the analogue loopback test mode. Note that in loopback test mode both Transmit and Receive Mode Registers should be set to the same modem type and band or bit rate. b11 = 1 b11 = 0 Local analogue loopback mode enabled No loopback (normal modem operation) General Control Register b10: Tx and Rx Fixed Compromise Equalisers This bit allows the Tx and Rx fixed compromise equalisers in the modem transmit and receive filter blocks to be disabled. b10 = 1 b10 = 0 Disable equalisers Enable equalisers (600, 1200 or 2400bps modem modes) General Control Register b9: Relay Drive This bit directly controls the RDRVN output pin. b9 = 1 b9 = 0 (c) 2008 CML Microsystems Plc RDRVN output pin pulled to VSS RDRVN output pin pulled to VDD 20 D/868A/3 Low Power V.22 bis Modem CMX868A General Control Register b8: Powerup This bit controls the internal power supply to most of the internal circuits, including the Xtal oscillator and VBIAS supply. Note that the General Reset command clears this bit, putting the device into Powersave mode. b8 = 1 b8 = 0 Device powered up normally Powersave mode (all circuits except Ring Detect, RDRVN and C-BUS interface disabled) When power is first applied to the device, the following powerup procedure should be followed to ensure correct operation. i. ii. iii. iv. (Power is applied to the device) Issue a General Reset command Write to the General Control Register (address $E0) setting both the Powerup bit (b8) and the Reset bit (b7) to '1' - leave in this state for a minimum of about 20ms - it is required that the crystal initially runs for this time in order to clock the internal logic into a defined state. The device is now powered up, with the crystal and VBIAS supply operating, but is otherwise not running any transmit or receive functions. The device is now ready to be programmed as and when required. Examples: * A General Reset command could be issued to clear all the registers and therefore powersave the device. * The Reset bit in the General Control Register could be set to '0' as part of a routine to program all the relevant registers for setting up a particular operating mode. When the device is switched from Powersave mode to normal operation by setting the Powerup bit to '1', the Reset bit should also be set to '1' and should be held at '1' for about 20ms while the internal circuits, Xtal oscillator and VBIAS stabilise before starting to use the transmitter or receiver. General Control Register b7: Reset Setting this bit to 1 resets the CMX868A's internal circuitry, clearing all bits of the Transmit and Receive Mode Registers and b13-0 of the Status Register. b7 = 1 b7 = 0 Internal circuitry in a reset condition. Normal operation General Control Register b6: IRQNEN (IRQN O/P Enable) Setting this bit to 1 enables the IRQN output pin. b6 = 1 b6 = 0 IRQN pin driven low (to VSS) if the IRQ bit of the Status Register = 1 IRQN pin disabled (high impedance) General Control Register b5-0: IRQ Mask bits These bits affect the operation of the IRQ bit of the Status Register as described in section 5.10.7 (c) 2008 CML Microsystems Plc 21 D/868A/3 Low Power V.22 bis Modem 5.10.3 CMX868A Transmit Mode Register Transmit Mode Register: 16-bit write-only. C-BUS address $E1 This register controls the CMX868A transmit signal type and level. All bits of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit: 15 14 13 12 11 10 Tx mode = modem Tx level Tx mode = DTMF/Tones Tx mode = Disabled Tx level 9 8 7 Guard tone 6 5 4 Scrambler DTMF Twist Set to 0000 0000 0000 3 2 1 0 Start-stop / # data bits / synch data synch data source DTMF or Tone select Tx Mode Register b15-12: Tx mode These 4 bits select the transmit operating mode. b15 b14 b13 b12 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 V.22 bis 2400 bps QAM " V.22/Bell 212A 1200 bps DPSK " V.22 600 bps DPSK " V.21 300 bps FSK " Bell 103 300 bps FSK " V.23 FSK " Bell 202 FSK " DTMF / Tones Transmitter disabled High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) 1200 bps 75 bps 1200 bps 150 bps Tx Mode Register b11-9: Tx level These 3 bits set the gain of the Tx Level Control block. b11 b10 b9 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 (c) 2008 CML Microsystems Plc 0dB -1.5dB -3.0dB -4.5dB -6.0dB -7.5dB -9.0dB -10.5dB 22 D/868A/3 Low Power V.22 bis Modem CMX868A Tx Mode Register b7-5: DTMF Twist (DTMF mode) These 3 bits allow for adjustment of the DTMF twist to compensate for the frequency response of different external circuits. Set b8 to 0. The device varies the twist by making changes to the upper tone group levels. Note that the twist cannot be adjusted mid-tone. b5 b7 b6 0 0 0 +2.0dB twist (normal setting when external response is flat) 0 0 1 +1.0dB twist 0 1 0 +1.5dB twist 0 1 1 +2.5dB twist 1 0 0 +3.0dB twist 1 0 1 +3.5dB twist 1 1 0 +4.0dB twist 1 1 1 +4.5dB twist (do not use in conjunction with the 0dB tx level setting). Tx Mode Register b8-7: Tx Guard tone (QAM, DPSK modes) These 2 bits select the guard tone to be transmitted together with highband QAM or DPSK. Set both bits to 0 in FSK modes. b8 b7 1 1 Tx 550Hz guard tone 1 0 Tx 1800Hz guard tone 0 x No Tx guard tone Tx Mode Register b6-5: Tx Scrambler (QAM, DPSK modes) These 2 bits control the operation of the Tx scrambler used in QAM and DPSK modes. Set both bits to 0 in FSK modes. b6 b5 1 1 Scrambler enabled, 64 ones detect circuit enabled (normal use) 1 0 Scrambler enabled, 64 ones detect circuit disabled 0 x Scrambler disabled Tx Mode Register b4-3: Tx Data Format (QAM, DPSK, FSK modes) These two bits select Synchronous or Start-stop mode and the addition of a parity bit to transmitted characters in Start-stop mode. b4 1 1 0 0 b3 1 0 1 0 (c) 2008 CML Microsystems Plc Synchronous mode Start-stop mode, no parity Start-stop mode, even parity bit added to data bits Start-stop mode, odd parity bit added to data bits 23 D/868A/3 Low Power V.22 bis Modem CMX868A Tx Mode Register b2-0: Tx Data and Stop bits (QAM, DPSK, FSK Start-Stop modes) In Start-stop mode these three bits select the number of Tx data and stop bits. b2 1 1 1 1 0 0 0 0 b1 1 1 0 0 1 1 0 0 b0 1 0 1 0 1 0 1 0 8 data bits, 2 stop bits 8 data bits, 1 stop bit 7 data bits, 2 stop bits 7 data bits, 1 stop bit 6 data bits, 2 stop bits 6 data bits, 1 stop bit 5 data bits, 2 stop bits 5 data bits, 1 stop bit Tx Mode Register b2-0: Tx Data source (QAM, DPSK, FSK Synchronous mode) In Synchronous mode (b4-3 = 11) these three bits select the source of the data fed to the Tx FSK or QAM/DPSK scrambler and modulator. b2 1 0 0 0 b1 x 1 1 0 (c) 2008 CML Microsystems Plc b0 x 1 0 x Data bytes from Tx Data Buffer Continuous 1s Continuous 0s Continuous V.22 bis handshake S1 pattern dibits '00,11' in DPSK and QAM modes, continuous alternating 1s and 0s in all other modes. 24 D/868A/3 Low Power V.22 bis Modem CMX868A Tx Mode Register b8-0: DTMF/Tones mode If DTMF/Tones transmit mode has been selected (Tx Mode Register b15-12 = 0001) then b8-5 should be set to 0000 and b4-0 will select a DTMF signal or a fixed tone or one of four programmed tones or tone pairs for transmission. b4 = 0: Tx fixed tone or programmed tone pair b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Tone frequency (Hz) No tone 697 770 852 941 1209 1336 1477 1633 1300 2100 2225 Tone pair TA Tone pair TB Tone pair TC Tone pair TD (Calling tone) (Answer tone) (Answer tone) Programmed Tx tone or tone pair, see 5.10.8 " " " b4 = 1: Tx DTMF b3 b2 b1 b0 Low frequency (Hz) High frequency (Hz) Keypad symbol 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 D 1 2 3 4 5 6 7 8 9 0 * # A B C (c) 2008 CML Microsystems Plc 25 D/868A/3 Low Power V.22 bis Modem 5.10.4 CMX868A Receive Mode Register Receive Mode Register: 16-bit write-only. C-BUS address $E2 This register controls the CMX868A receive signal type and level. All bits of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit: 15 14 13 12 11 10 Rx mode = modem Rx level Rx mode = Tones detect Rx mode = Disabled Rx level 9 8 7 Eq 6 Descrambl 5 4 3 2 1 0 Start-stop/Synch No. of bits and parity DTMF/Tones/Call Progress select Set to 0000 0000 0000 Rx Mode Register b15-12: Rx mode These 4 bits select the receive operating mode. b15 b14 b13 b12 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 V.22 bis 2400 bps QAM High band (Calling modem) " Low band (Answering modem) V.22/Bell 212A 1200 bps DPSK High band (Calling modem) " Low band (Answering modem) V.22 600 bps DPSK High band (Calling modem) " Low band (Answering modem) V.21 300 bps FSK High band (Calling modem) " Low band (Answering modem) Bell 103 300 bps FSK High band (Calling modem) " Low band (Answering modem) V.23 FSK 1200 bps " 75 bps Bell 202 FSK 1200 bps " 150 bps DTMF, Programmed tone pair, Answer Tone, Call Progress detect Receiver disabled Rx Mode Register b11-9: Rx level These three bits set the gain of the Rx Gain Control block. b11 b10 b9 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 (c) 2008 CML Microsystems Plc 0dB -1.5dB -3.0dB -4.5dB -6.0dB -7.5dB -9.0dB -10.5dB 26 D/868A/3 Low Power V.22 bis Modem CMX868A Rx Mode Register b8: Rx Auto-equalise (DPSK/QAM modem modes) This bit controls the operation of the receive DPSK/QAM auto-equaliser. Set to 0 in FSK modes. Set to 1 in 2400bps QAM mode. b8 = 1 b8 = 0 Enable auto-equaliser DPSK mode: Auto-equaliser disabled QAM mode : Auto-equaliser settings frozen Rx Mode Register b7-6: Rx Scrambler (DPSK/QAM modem modes) These 2 bits control the operation of the Rx descrambler used in QAM and DPSK modes. Set both bits to 0 in FSK modes b7 b6 1 1 Descrambler enabled, 64 ones detect circuit enabled (normal use) 1 0 Descrambler enabled, 64 ones detect circuit disabled 0 x Descrambler disabled Rx Mode Register b5-3: Rx USART Setting (QAM, DPSK, FSK modem modes) These three bits select the Rx USART operating mode. The 1% and 2.3% overspeed options apply to DPSK/QAM modes only. b5 b4 b3 1 1 1 Rx Synchronous mode 1 1 0 Rx Start-stop mode, no overspeed 1 0 1 Rx Start-stop mode, +1% overspeed (1 in 8 missing Stop bits allowed) 1 0 0 Rx Start-stop mode, +2.3% overspeed (1 in 4 missing Stop bits allowed) 0 x x Rx USART function disabled Rx Mode Register b2-0: Rx Data bits and parity (QAM, DPSK, FSK Start-Stop modem modes) In Start-stop mode these three bits select the number of data bits (plus any parity bit) in each received character. These bits are ignored in Synchronous mode. b2 b1 b0 1 1 1 8 data bits + parity 1 1 0 8 data bits 1 0 1 7 data bits + parity 1 0 0 7 data bits 0 1 1 6 data bits + parity 0 1 0 6 data bits 0 0 1 5 data bits + parity 0 0 0 5 data bits Rx Mode Register b2-0: Tones Detect mode In Tones Detect Mode (Rx Mode Register b15-12 = 0001) b8-3 should be set to 000000 Bits 2-0 select the detector type. b2 b1 b0 1 0 0 Programmable Tone Pair Detect 0 1 1 Call Progress Detect 0 1 0 2100, 2225Hz Answer Tone Detect 0 0 1 DTMF Detect 0 0 0 Disabled (c) 2008 CML Microsystems Plc 27 D/868A/3 Low Power V.22 bis Modem CMX868A 5.10.5 Tx Data Register Tx Data Register: 8-bit write-only. Bit: 7 6 5 4 3 C-BUS addresses $E3 and $E4 2 1 0 Data bits to be transmitted In Synchronous Tx data mode this register contains the next 8 data bits to be transmitted. Bit 0 is transmitted first. In Tx Start-Stop mode the specified number of data bits will be transmitted from this register (b0 first). A Start bit, a Parity bit (if required) and Stop bit(s) will be added automatically. This register should only be written to when the Tx Data Ready bit of the Status Register is 1. C-BUS address $E3 should normally be used, $E4 is for implementing the V.14 overspeed transmission requirement in Start-Stop mode, see section 5.1. 5.10.6 Rx Data Register Rx Data Register: 8-bit read-only. Bit: 7 6 5 4 3 C-BUS address $E5 2 1 0 Received data bits In unformatted Rx data mode this register contains 8 received data bits, b0 of the register holding the earliest received bit, b7 the latest. In Rx Start-Stop data mode this register contains the specified number of data bits from a received character, b0 holding the first received bit. (c) 2008 CML Microsystems Plc 28 D/868A/3 Low Power V.22 bis Modem 5.10.7 CMX868A Status Register Status Register: 16-bit read-only. C-BUS address $E6 Bits 13-0 of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit: 15 14 13 IRQ RD PF 12 11 10 9 8 7 6 5 4 3 2 1 0 See below for uses of these bits The meanings of the Status Register bits 12-0 depend on whether the receive circuitry is in Modem or Tones Detect mode. Status Register bits: Rx Modem modes b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rx Tones Detect modes IRQ Set to 1 on Ring Detect Programming Flag bit. See 5.10.8 Set to 1 on Tx data ready. Cleared by write to Tx Data Register Set to 1 on Tx data underflow. Cleared by write to Tx Data Register 1 when energy is detected in Rx 1 when energy is detected in Call modem signal band Progress band or when both programmable tones are detected 1 when S1 pattern (double DPSK 0 dibit 00,11) is detected in DPSK or QAM modes, or when `1010..' pattern is detected in FSK modes See following table 0 See following table 1 when 2100Hz answer tone or the second programmable tone is detected Set to 1 on Rx data ready. 1 when 2225Hz answer tone or the Cleared by read from Rx Data first programmable tone is detected Register Set to 1 on Rx data overflow. 1 when DTMF code is detected Cleared by read from Rx Data Register Set to 1 on Rx framing error 0 Set to 1 on even Rx parity Rx DTMF code b3, see table QAM/DPSK Rx signal quality b2 Rx DTMF code b2 QAM/DPSK Rx signal quality b1 Rx DTMF code b1 QAM/DPSK Rx signal quality b0 Rx DTMF code b0 or FSK frequency demodulator output ** IRQ Mask bit b5 b4 b3 b3 b2 b1 b1 b1 b0 b0 - Notes: ** This column shows the corresponding IRQ Mask bits in the General Control Register. A 0 to 1 transition on any of the Status Register bits 14-5 will cause the IRQ bit b15 to be set to 1 if the corresponding IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status Register or a (c) 2008 CML Microsystems Plc 29 D/868A/3 Low Power V.22 bis Modem CMX868A General Reset command or by setting b7 or b8 of the General Control Register to 1. The operation of the data demodulator and pattern detector circuits within the CMX868A does not depend on the state of the Rx energy detect function. Decoding of Status Register b8,7 in Rx Modem Modes, see also Figure 8a b8 b7 Descrambler disabled 1 1 - 1 0 0 1 Continuous unscrambled 0s Continuous unscrambled 1s 0 0 - Descrambler enabled (DPSK/QAM modes only) Continuous scrambled 1s (see note) Continuous scrambled 0s Continuous unscrambled 1s - When the descrambler is enabled then detection of continuous unscrambled 1s will inhibit the continuous scrambled 1s detector. Figure 10a Operation of Status Register bits 5-10 The IRQN output pin will be pulled low (to VSS) when the IRQ bit of the Status Register and the IRQNEN bit (b6) of the General Control Register are both 1. Changes to Status Register bits caused by a change of Tx or Rx operating mode can take up to 150s to take effect. In Powersave mode or when the Reset bit (b7) of the General Control Register is 1 the Ring Detect bit (b14) continues to operate. The `continuous 0' and `continuous 1' detectors monitor the Rx signal after the QAM/DPSK descrambler, (see Figure 8a) and hence will detect continuous 1s or 0s if the descrambler is disabled, or continuous scrambled 1s or 0s if the descrambler is enabled. In Rx FSK modem modes bits 2 and 1 will be zero and b0 will show the output of the frequency demodulator, updated at 8 times the nominal data rate. (c) 2008 CML Microsystems Plc 30 D/868A/3 Low Power V.22 bis Modem CMX868A Figure 10b Operation of Status Register in DTMF Rx Mode b3 b2 b1 b0 Low frequency (Hz) High frequency (Hz) Keypad symbol 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 D 1 2 3 4 5 6 7 8 9 0 * # A B C Received DTMF Code: b3-0 of Status Register (c) 2008 CML Microsystems Plc 31 D/868A/3 Low Power V.22 bis Modem CMX868A 5.10.8 Programming Register Programming Register : 16-bit write-only. C-BUS address $E8 This register is used to program the transmit and receive programmed tone pairs by writing appropriate values to RAM locations within the CMX868A. Note that these RAM locations are cleared by Powersave or Reset. The Programming Register should only be written to when the Programming Flag bit (b13) of the Status Register is 1. The act of writing to the Programming Register clears the Programming Flag bit. When the programming action has been completed (normally within 150s) the CMX868A will set the bit back to 1. When programming Transmit or Receive Tone Pairs, do not change the Transmit or Receive Mode Registers until programming is complete and the Programming Flag bit has returned to 1. Transmit Tone Pair Programming 4 transmit tone pairs (TA to TD) can be programmed. The frequency (max 3.4kHz) and level must be entered for each tone to be used. Single tones are programmed by setting both level and frequency values to zero for one of the pair. Programming is done by writing a sequence of up to seventeen 16-bit words to the Programming Register. The first word should be 32768 (8000 hex), the following 16-bit words set the frequencies and levels and are in the range 0 to 16383 (0-3FFF hex) Word 1 2 3 4 5 6 7 ----16 17 Tone Pair TA TA TA TA TB TB ----TD TD Value written 32768 Tone 1 frequency Tone 1 level Tone 2 frequency Tone 2 level Tone 1 frequency Tone 1 level ------------------Tone 2 frequency Tone 2 level The Frequency values to be entered are calculated from the formula: Value to be entered = desired frequency (Hz) * 3.414 i.e. for 1kHz the value to be entered is 3414 (or 0D56 in Hex). The Level values to be entered are calculated from the formula: Value to be entered = desired Vrms * 93780 / VDD i.e. for 0.5Vrms at VDD = 3.0V, the value to be entered is 15630 (3D0E in Hex) Note that allowance should be made for the transmit signal filtering in the CMX868A which attenuates the output signal for frequencies above 2kHz by 0.25dB at 2.5kHz, by 1dB at 3kHz and by 2.2dB at 3.4kHz. On powerup or after a reset, the tone pairs TA-TC are set to notone, and TD set to generate 2130Hz + 2750Hz at approximately -20dBm each. (c) 2008 CML Microsystems Plc 32 D/868A/3 Low Power V.22 bis Modem CMX868A Receive Tone Pair Programming The programmable tone pair detector is implemented as shown in Figure 11a. The filters are 4th order IIR sections. The frequency detectors measure the time taken for a programmable number of complete input signal cycles and compare this time against programmable upper and lower limits. Figure 11a Programmable Tone Detectors Figure 11b Filter Implementation Programming is done by writing a sequence of twenty-seven 16-bit words to the Programming Register. The first word should be 32769 (8001 hex), the following twenty-six 16-bit words set the frequencies and levels and are in the range 0 to 32767 (0000-7FFF hex). Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Value written 32769 Filter #1 coefficient b21 Filter #1 coefficient b11 Filter #1 coefficient b01 Filter #1 coefficient a21 Filter #1 coefficient a11 Filter #1 coefficient b22 Filter #1 coefficient b12 Filter #1 coefficient b02 Filter #1 coefficient a22 Filter #1 coefficient a12 Freq measurement #1 ncycles Freq measurement #1 mintime Freq measurement #1 maxtime Word 15 16 17 18 19 20 21 22 23 24 25 26 27 Value written Filter #2 coefficient b21 Filter #2 coefficient b11 Filter #2 coefficient b01 Filter #2 coefficient a21 Filter #2 coefficient a11 Filter #2 coefficient b22 Filter #2 coefficient b12 Filter #2 coefficient b02 Filter #2 coefficient a22 Filter #2 coefficient a12 Freq measurement #2 ncycles Freq measurement #2 mintime Freq measurement #2 maxtime The coefficients are entered as 15-bit signed (two's complement) integer values (the most significant bit of the 16-bit word entered should be zero) calculated as 8192 * coefficient value from the user's filter design program (i.e. this allows for filter design values of -1.9999 to +1.9999). (c) 2008 CML Microsystems Plc 33 D/868A/3 Low Power V.22 bis Modem CMX868A The design of the IIR filters should make allowance for the fixed receive signal filtering in the CMX868A which has a low pass characteristic above 1.5kHz of 0.4dB at 2kHz, 1.2dB at 2.5kHz, 2.6dB at 3kHz and 4.1dB at 3.4kHz. `ncycles' is the number of signal cycles for the frequency measurement. `mintime' is the smallest acceptable time for ncycles of the input signal expressed as the number of 9.6kHz timer clocks. i.e. `mintime' = 9600 * ncycles / high frequency limit `maxtime' is the highest acceptable time for ncycles of the input signal expressed as the number of 9.6kHz timer clocks. i.e. `maxtime' = 9600 * ncycles / low frequency limit The level detectors include hysteresis. The threshold levels - measured at the 2 or 4-wire line with unity gain filters, using the line interface circuits described in section 4.2, 1.0 dB line coupling transformer loss and with the Rx Gain Control block set to 0dB - are nominally: `Off' to `On' -44.5dBm `On' to `Off' -47.0dBm Note that if any changes are made to the programmed values while the CMX868A is running in Programmed Tone Detect mode they will not take effect until the CMX868A is next switched into Programmed Tone Detect mode. On powerup or after a reset, the programmable tone pair detector is set to act as a simple 2130Hz + 2750Hz detector. (c) 2008 CML Microsystems Plc 34 D/868A/3 Low Power V.22 bis Modem 6. Application Notes 6.1 V.22 bis Calling Modem Application CMX868A This section describes how the CMX868A can be used in a V.22 bis Calling modem application, employing V.25 automatic answering and the V.22 bis recommended handshake sequence. This attempts to establish a 2400bps connection but may fall back to 1200bps if the answering modem is not capable of 2400bps operation. 1. Ensure that the CMX868A is powered up. Set the Tx Mode Register to DTMF/Tones mode (set to `No Tone' at this time), and the Rx Mode Register to Call Progress Detect mode. 2. Connect the line (go off hook) then dial the required number using the DTMF generator, monitoring for call progress signals (dial tone, busy, etc). Change to Answer Tone Detect mode. 3. On detection of the 2100Hz answer tone wait for it to end then wait for the 2225Hz answer tone detector to respond. (The `2225Hz' answer tone detector will recognise unscrambled binary 1s at 1200bps High Band as well as 2225Hz). When unscrambled binary 1s or 2225Hz have been received for 155ms set a 456ms timer. 4. When the 456ms timer expires check that the 2225Hz or unscrambled 1s is still being received, then set the Tx Mode Register for V.22 1200bps Low Band transmission of S1 signal and set a 100ms timer. Also set the Rx Mode register to V.22 1200bps High Band receive, descrambler enabled and Rx USART disabled. 5. When the 100ms timer expires set the Tx Mode Register for V.22 1200bps Low Band transmission of scrambled 1s (continuous 1s with the scrambler enabled) and look for received S1 signal. 6. If the S1 signal is not detected within 270ms then go to step 14 as the answering modem is not capable of 2400bps operation. 7. If S1 signal is detected wait for it to end then set a 450ms timer. 8. When the 450ms timer expires set the Rx Mode Register to V.22 bis 2400bps High Band (this will begin 16-way decisions) with the auto-equaliser and descrambler enabled. Start to monitor for Rx scrambled 1s. Set a 150ms timer. 9. Once 32 consecutive bits of received scrambled 1s at 2400bps have been detected, enable the Rx USART. 10. When the 150ms timer expires set the Tx Mode Register for V.22 bis 2400bps scrambled 1s, set a 200ms timer. 11. Load the Tx Data Register with the first data to be transmitted. 12. When the 200ms timer expires set the Tx Mode Register for Start-Stop or Synchronous transmission of data from the Tx Data Buffer. This will start transmission of the data loaded in step 11. 13. A 2400bps data connection has now been established. 14. If the S1 signal had not been detected within 270ms after step 5 then monitor for scrambled 1s at 1200bps. 15. When scrambled 1s (at 1200bps) have been received for 270ms enable the Rx USART, set a 765ms timer and load the Tx Data Register with the first data to be transmitted. 16. When the timer expires set the Tx Mode Register for Start-Stop or Synchronous transmission of data from the Tx Data Buffer. This will start transmission of the data loaded in step 15. (c) 2008 CML Microsystems Plc 35 D/868A/3 Low Power V.22 bis Modem CMX868A 17. A 1200bps data connection has now been established. 6.2 V.22 bis Answering Modem Application This section describes how the CMX868A can be used in a V.22 bis Answering modem application, employing V.25 automatic answering and the V.22 bis recommended handshake sequence. A 1200 or 2400 bps connection will be established depending on the signals received from the calling modem. 1. It is assumed that the CMX868A will be in Powersave mode, with the Ring Detector circuits monitoring the line. 2. When a ring signal is detected connect the line (go off hook), set a 2150ms timer and power up the CMX868A, setting the Tx Mode Register to DTMF/Tones mode (set for `no tone' at this time) and the Rx Mode Register to V.22 1200bps Low Band receive, descrambler enabled, Rx USART disabled. 3. When the 2150ms timer expires set the Tx Mode Register to transmit the 2100Hz answer tone and set a 3300ms timer. 4. When the 3300ms timer expires set the Tx Mode Register to no tone and set a 75ms timer. 5. When the 75ms timer expires set the Tx Mode Register for V.22 High Band 1200bps transmission of unscrambled 1s. Monitor the received signal for the S1 signal or scrambled 1s. 6. If scrambled 1s are detected for 270ms go to step 15. 7. If the S1 signal is received wait for it to end then set the Tx Mode Register for V.22 High Band 1200bps transmission of the S1 signal and set a 100ms timer. 8. When the 100ms timer expires set the Tx Mode Register for V.22 High Band 1200bps transmission of scrambled 1s and set a 350ms timer. 9. When the 350ms timer expires set the Rx Mode Register for V.22 bis Low Band 2400bps receive (this will begin 16-way decisions) with the auto-equaliser and descrambler enabled and the Rx USART disabled, set a 150ms timer and start to monitor for Rx scrambled 1s. 10. When the 150ms timer expires set the Tx Mode Register for V.22 bis High Band 2400bps transmission of scrambled 1s and set a 200ms timer. 11. Load the Tx Data Buffer with the first data to be transmitted. 12. Once 32 consecutive bits of received scrambled 1s at 2400bps have been detected, enable the Rx USART. 13. When the 200ms timer expires set the Tx Mode Register for Start-Stop or Synchronous transmission of data from the Tx Data Buffer. This will start transmission of the data loaded in step 11. 14. A 2400bps data connection has now been established. 15. If scrambled 1s had been detected for 270ms in step 6, set the Tx Mode Register to V.22 High Band 1200bps scrambled 1s transmission and set a 765ms timer and enable the Rx USART. 16. Load the Tx Data Buffer with the first data to be transmitted. (c) 2008 CML Microsystems Plc 36 D/868A/3 Low Power V.22 bis Modem CMX868A 17. When the 765ms timer expires set the Tx Mode Register for Start-Stop or Synchronous transmission of data from the Tx Data Buffer. This will start transmission of the data loaded in step 16. 18. A 1200bps data connection has now been established. 6.3 Reference Diagrams The circuit diagrams in the DE8681 kit should be consulted for examples of a complete telephone line interface. These diagrams are contained in the DE8681 User Manual, which can be downloaded from the CML website. (c) 2008 CML Microsystems Plc 37 D/868A/3 Low Power V.22 bis Modem 7. Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings CMX868A Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -50 Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into RDRVN pin (RDRVN pin low) Current into or out of any other pin -20 D2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. E2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. P4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. 7.1.2 -55 -40 -55 -40 -55 -40 Max. 7.0 VDD + 0.3 +50 +50 +20 Units V V mA mA mA Max. 600 6.0 +125 +85 Units mW mW/C C C Max. 1000 10.0 +125 +85 Units mW mW/C C C Max. 1660 16.6 +125 +85 Units mW mW/C C C Max. 5.5 +85 Units V C Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature (c) 2008 CML Microsystems Plc 38 Min. 2.7 -40 D/868A/3 Low Power V.22 bis Modem 7.1.3 CMX868A Operating Characteristics For the following conditions unless otherwise specified: VDD = 2.7V to 5.5V at Tamb = -40 to +85C, Xtal Frequency = 11.0592 or 12.288MHz 0.01% (100ppm) 0dBm corresponds to 775mVrms. DC Parameters IDD (Powersave mode) (Reset but not powersave, VDD = 3.0V) (Reset but not powersave, VDD = 5.0V) (Running, VDD = 3.0V) (Running, VDD = 5.0V) Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (Vin = 0 to VDD), (excluding XTAL/CLOCK input) Output Logic '1' Level (lOH = 2 mA) Output Logic '0' Level (lOL = -3 mA) IRQN O/P 'Off' State Current (Vout = VDD) RD and RT pin Schmitt trigger input high-going threshold (Vthi) (see Figure 12) RD and RT pin Schmitt trigger input low-going threshold (Vtlo) (see Figure 12) RDRVN `ON' resistance to VSS (VDD= 3.0V) RDRVN `OFF' resistance to VDD (VDD= 3.0V) Notes: Notes 1, 2 1, 3 1, 3 1 1 4 4 Min. - - - - - 70% - -1.0 Typ. 2.0 1.7 2.5 3.0 5.5 - - - Max. - 3.5 5.0 6.0 11.0 - 30% +1.0 Units A mA mA mA mA VDD VDD A 80% - - 0.56VDD - - - - VDD V A V 0.44VDD - 0.6V - - - - 0.4 1.0 0.56VDD + 0.6V 0.44VDD 50 1300 70 3000 V 1. At 25C, not including any current drawn from the CMX868A pins by external circuitry other than X1, C1 and C2. 2. All logic inputs at VSS except for RT and CSN inputs which are at VDD. 3. General Mode Register b8 and b7 both set to 1. 4. Excluding RD and RT pins. 3.5 3 2.5 2 Vin 1.5 1 Vthi 0.5 Vtlo 0 2.5 3 3.5 4 4.5 5 5.5 Vdd Figure 12 Typical Schmitt Trigger Input Voltage Thresholds vs. VDD (c) 2008 CML Microsystems Plc 39 D/868A/3 Low Power V.22 bis Modem CMX868A XTAL/CLOCK Input (timings for an external clock input) 'High' Pulse Width 'Low' Pulse Width Notes Min. Typ. Max. Units 30 30 - - - - ns ns Transmit QAM and DPSK Modes (V.22, Bell 212A, V.22 bis) Carrier frequency, high band Carrier frequency, low band Baud rate Bit rate (V.22, Bell 212A) Bit rate (V.22 bis) 550Hz guard tone frequency 550Hz guard tone level wrt data signal 1800Hz guard tone frequency 1800Hz guard tone level wrt data signal Notes Min. Typ. Max. Units 5 5 6 6 6 - - - - - 548 -4.0 1797 -7.0 2400 1200 600 1200/600 2400 550 -3.0 1800 -6.0 - - - - - 552 -2.0 1803 -5.0 Hz Hz Baud bps bps Hz dB Hz dB Transmit V.21 FSK Mode Baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Notes 6 Min. - 1647 1847 978 1178 Typ. 300 1650 1850 980 1180 Max. - 1653 1853 982 1182 Units Baud Hz Hz Hz Hz Transmit Bell 103 FSK Mode Baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Notes 6 Min. - 2222 2022 1268 1068 Typ. 300 2225 2025 1270 1070 Max. - 2228 2028 1272 1072 Units Baud Hz Hz Hz Hz Transmit V.23 FSK Mode Baud rate Mark (logical 1) frequency, 1200 baud Space (logical 0) frequency, 1200 baud Mark (logical 1) frequency, 75 baud Space (logical 0) frequency, 75 baud Notes 6 Min. - 1298 2097 389 449 Typ. 1200/75 1300 2100 390 450 Max. - 1302 2103 391 451 Units Baud Hz Hz Hz Hz Transmit Bell 202 FSK Mode Baud rate Mark (logical 1) frequency, 1200 baud Space (logical 0) frequency, 1200 baud Mark (logical 1) frequency, 150 baud Space (logical 0) frequency, 150 baud Notes 6 Min. - 1198 2197 386 486 Typ. 1200/150 1200 2200 387 487 Max. - 1202 2203 388 488 Units Baud Hz Hz Hz Hz DTMF/Single Tone Transmit Tone frequency accuracy Distortion Notes Min. -0.2 - Typ. - 1.0 Max. +0.2 2.0 Units % % (c) 2008 CML Microsystems Plc 7 40 D/868A/3 Low Power V.22 bis Modem CMX868A Transmit Output Level Modem and Single Tone modes DTMF mode, Low Group tones DTMF twist (level of high group tones wrt low group) setting accuracy Tx output buffer gain control accuracy Notes: Notes 7 7 Min. -4.0 -2.0 Typ. -3.0 -1.0 Max. -2.0 0.0 Units dBm dBm 7 7 -1.0 -0.25 - +1.0 +0.25 dB dB 5. % carrier frequency accuracy is the same as XTAL/CLOCK % frequency accuracy. 6 Tx signal % baud or bit rate accuracy is the same as XTAL/CLOCK % frequency accuracy. 7. Measured between TXA and TXAN pins with Tx Level Control gain set to 0dB, 1k2 load between TXA and TXAN, at VDD = 3.0V (levels are proportional to VDD - see section 4.2). Level measurements for all modem modes are performed with random transmitted data and without any guard tone. 0dBm = 775mVrms. 0 -10 Bell 202 -20 -30 dBm -40 -50 -60 -70 10 100 1000 10000 100000 Hz Figure 13 Maximum Out of Band Tx Line Energy Limits (see note 8) Notes: 8. Measured on the 2 or 4-wire line using the line interface circuits described in section 4.2 with the Tx line signal level set to -10dBm for QAM, DPSK, FSK or single tones, -6dBm and -8dBm for DTMF tones. Excludes any distortion due to external components such as the line coupling transformer. (c) 2008 CML Microsystems Plc 41 D/868A/3 Low Power V.22 bis Modem CMX868A Receive QAM and DPSK Modes (V.22, Bell 212A, V.22 bis) Carrier frequency (high band) Carrier frequency (low band) Baud rate Bit rate (V.22, Bell 212A) Bit rate (V.22 bis) Notes: Notes Min. Typ. Max. Units 9 9 9 2392 1192 - - - 2400 1200 600 1200/600 2400 2408 1208 - - - Hz Hz Baud bps bps 9. These are the bit and baud rates of the line signal, the acceptable tolerance is 0.01%. Receive V.21 FSK Mode Acceptable baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Notes Min. 297 1638 1838 968 1168 Typ. 300 1650 1850 980 1180 Max. 303 1662 1862 992 1192 Units Baud Hz Hz Hz Hz Receive Bell 103 FSK Mode Acceptable baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Notes Min. 297 2213 2013 1258 1058 Typ. 300 2225 2025 1270 1070 Max. 303 2237 2037 1282 1082 Units Baud Hz Hz Hz Hz Receive V.23 FSK Mode 1200 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency 75 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency Notes Min. Typ. Max. Units 1188 1280 2080 1200 1300 2100 1212 1320 2120 Baud Hz Hz 74 382 442 75 390 450 76 398 458 Baud Hz Hz Receive Bell 202 FSK Mode 1200 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency 150 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency Notes Min. Typ. Max. Units 1188 1180 2180 1200 1200 2200 1212 1220 2220 Baud Hz Hz 148 377 477 150 387 487 152 397 497 Baud Hz Hz Rx Modem Signal (FSK, DPSK and QAM Modes) Signal level Signal to Noise Ratio (noise flat 300-3400Hz) Notes Min. Typ. Max. Units 10 -45 20 - - -9 - dBm dB (c) 2008 CML Microsystems Plc 42 D/868A/3 Low Power V.22 bis Modem CMX868A Rx Modem S1 Pattern Detector (DPSK and QAM modes) Will detect S1 pattern lasting for Will not detect S1 pattern lasting for Hold time (minimum detector `On' time) Notes Min. Typ. Max. Units 90.0 - 5.0 - - - - 72.0 - ms Rx Modem Energy Detector Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Hysteresis Detect (`Off' to `On') response time QAM and DPSK modes 300 and 1200 baud FSK modes 150 and 75 baud FSK modes Undetect (`On' to `Off') response time QAM and DPSK modes 300 and 1200 baud FSK modes 150 and 75 baud FSK modes Notes 10,11 10,11 10,11 Min. - -48.0 2.0 Typ. - - - Max. -43.0 - - Units dBm dBm dB 10,11 10,11 10,11 10.0 8.0 16.0 - - - 35.0 30.0 60.0 ms ms ms 10,11 10,11 10,11 10.0 10.0 20.0 - - - 55.0 40.0 80.0 ms ms ms Rx Answer Tone Detectors Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Hysteresis Detect (`Off' to `On') response time Undetect (`On' to `Off') response time 2100Hz detector `Will detect' frequency `Will not detect' frequency 2225Hz detector `Will detect' frequency `Will not detect' frequency Notes 10,12 10,12 10,12 10,12 10,12 Min. - -48.0 2.0 30.0 7.0 Typ. - - - 33.0 18.0 Max. -43.0 - - 45.0 25.0 Units dBm dBm dB ms ms 2050 - - - 2160 2000 Hz Hz 2160 2335 - - 2285 - Hz Hz Rx Call Progress Energy Detector Bandwidth (-3dB points) See Figure 7a Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Detect (`Off' to `On') response time Undetect (`On' to `Off') response time Notes Min. 275 - -42.0 30.0 6.0 Typ. - - - 36.0 8.0 Max. 665 -37.0 - 45.0 50.0 Units Hz dBm dBm ms ms Notes: 10,13 10,13 10,13 10,13 ms 10. Rx 2 or 4-wire line signal level assuming 1dB loss in line coupling transformer with Rx Gain Control block set to 0dB and external components as section 4.2. 11.Thresholds and times measured with random data for QAM and DPSK modes, continuous binary `1' for all FSK modes. Fixed compromise line equaliser enabled. Signal switched between off and -33dBm. 12. `Typical' value refers to 2100Hz or 2225Hz signal switched between off and -33dBm. Times measured wrt. received line signal. 13. `Typical' value refers to 400Hz signal switched between off and -33dBm. (c) 2008 CML Microsystems Plc 43 D/868A/3 Low Power V.22 bis Modem CMX868A DTMF Decoder Valid input signal levels (each tone of composite signal) Not decode level (either tone of composite signal) Twist = High Tone/Low Tone Frequency Detect Bandwidth Frequency Not Detect Bandwidth Max level of low frequency noise (i.e dial tone) Interfering signal frequency <= 550Hz Interfering signal frequency <= 450Hz Interfering signal frequency <= 200Hz Max. noise level wrt. signal DTMF detect response time DTMF de-response time Status Register b5 high time `Will Detect' DTMF signal duration `Will Not Detect' DTMF signal duration Pause length detected Pause length ignored Falsing performance Notes: Notes Min. Typ. Max. Unit 10 -31.0 - 2.0 dBm 10 - -10.0 2.2 - - - - - -37.0 10.0 - 3.5 dBm dB % % 14 14 14 14,15 17 - - - - - - 14.0 40.0 30.0 - - - - - - 40.0 - - - 25.0 - - 13 0 10.0 20.0 -10.0 - 30.0 - - - - 15.0 - dB dB dB dB ms ms ms ms ms ms ms falses/ 30mins 16 14. Referenced to DTMF tone of lower amplitude. 15. Flat Gaussian Noise in 300-3400Hz band. 16. Mitel CM7291 test tape, 1kHz reference tone set to 775mVrms. 17. See Figure 10b. The decode time is directly affected by signal quality but, for good signals, will always be much less than the 100ms required for PSTN use. Receive Input Amplifier Input impedance (at 100Hz) Notes Open loop gain (at 100Hz) Rx Gain Control Block accuracy (c) 2008 CML Microsystems Plc 44 Min. 10.0 Typ. - Max. - - -0.25 10000 - - +0.25 Units Moh m V/V dB D/868A/3 Low Power V.22 bis Modem CMX868A C-BUS Timings (See Figure 14) tCSE CSN-Enable to Clock-High time tCSH Last Clock-High to CSN-High time tLOZ Clock-Low to Reply Output enable time CSN-High to Reply Output 3-state time tHIZ tCSOFF CSN-High Time between transactions tNXT Inter-Byte Time tCK Clock-Cycle time tCH Serial Clock-High time tCL Serial Clock-Low time tCDS Command Data Set-Up time tCDH Command Data Hold time tRDS Reply Data Set-Up time tRDH Reply Data Hold time Notes Min. 100 100 0.0 Typ. - - - Max. - - - Units ns ns ns - 1.0 200 200 100 100 75.0 25.0 50.0 0.0 - - - - - - - - - - 1.0 - - - - - - - - - s s ns ns ns ns ns ns ns ns Maximum 30pF load on each C-BUS interface line. Note: These timings are for the latest version of the C-BUS as embodied in the CMX868A. Figure 14 C-BUS Timing (c) 2008 CML Microsystems Plc 45 D/868A/3 Low Power V.22 bis Modem 7.2 CMX868A Packaging Figure 15a 24-pin SOIC (D2) Mechanical Outline: Order as part no. CMX868AD2 Figure 15b 24-pin TSSOP (E2) Mechanical Outline: Order as part no. CMX868AE2 (c) 2008 CML Microsystems Plc 46 D/868A/3 Low Power V.22 bis Modem CMX868A Figure 15c 24-pin DIL (P4) Mechanical Outline: Order as part no. CMX868AP4 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.