19-5335; Rev 1; 6/11 EVALUATION KIT AVAILABLE MAX98088 Stereo Audio Codec with FlexSound Technology General Description Features The MAX98088 is a full-featured audio codec whose high performance and low power consumption make it ideal for portable applications. S S S S Class D speaker amplifiers provide efficient amplification for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches optionally connect an external amplifier to the transducer when the Class D amplifiers are disabled. S S S The IC features a stereo Class H headphone amplifier that utilizes a dual-mode charge pump to maximize efficiency while outputting a ground referenced signal that does not require output coupling capacitors. S S The IC also features a mono differential amplifier that can also be configured as a stereo line output. Two differential analog microphone inputs are available as well as support for two PDM digital microphones. Integrated switches allow for an additional microphone input as well as microphone signals to be routed out to external devices. Two flexible single-ended or differential line inputs may be connected to an FM radio or other sources. S S S Integrated FlexSoundK technology improves loudspeaker performance by optimizing the signal level and frequency response while limiting the maximum distortion and power at the output to prevent speaker damage. Automatic gain control (AGC) and a noise gate optimize the signal level of microphone input signals to make best use of the ADC dynamic range. S S S 5.6mW Power Comsumption (DAC to HP at 97dB DR) 101dB DR Stereo DAC (8kHz < fS < 96kHz) 93dB DR Stereo ADC (8kHz < fS < 96kHz) Stereo Low EMI Class D Amplifiers 950mW/Channel (8I, VSPKVDD_ = 4.2V) Efficient Class H Headphone Amplifier Differential Receiver Amplifier/Stereo Line Outputs 2 Stereo Single-Ended/Mono Differential Line Inputs 3 Differential Microphone Inputs FlexSound Technology 5-Band Parametric EQ Automatic Level Control (ALC) Excursion Limiter Speaker Power Limiter Speaker Distortion Limiter Microphone Automatic Gain Control and Noise Gate Dual I2S/PCM/TDM Digital Audio Interfaces Asynchronous Digital Mixing Supports Master Clock Frequencies from 10MHz to 60MHz RF Immune Analog Inputs and Outputs Extensive Click-and-Pop Reduction Circuitry Available in 63-Bump WLP Package (3.80mm x 3.30mm, 0.4mm Pitch) Ordering Information appears at end of data sheet. The device is fully specified over the -40NC to +85NC extended temperature range. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX98088.related. FlexSound is a trademark of Maxim Integrated Products, Inc. Simplified Block Diagram I2C I2S/PCM I2S/PCM RECEIVER/LINEOUT AMPS DIGITAL AUDIO INTERFACE CONTROL DIGITAL MICROPHONE INPUT FlexSound TECHNOLOGY ADC MIX LINEIN A1 ADC LINEIN A2 + * 5-BAND PARAMETRIC EQ * AUTOMATIC LEVEL CONTROL * LOUDSPEAKER PROCESSING * EXCURSION LIMITER * THD LIMITER * POWER LIMITER * MICROPHONE PROCESSING * AUTOMATIC GAIN CONTROL * NOISE GATE * ASYNCHRONOUS DIGITAL MIXING SPEAKER AMP DAC SPEAKER AMP MIX DAC HEADPHONE AMP MAX98088 LINEIN B1 LINEIN B2 DIGITAL AUDIO INTERFACE + HEADPHONE AMP Maxim Integrated Products1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX98088 Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Digital Microphone Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Microphone to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Line to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Line-In Pin Direct to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DAC to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Line to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DAC to Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Line to Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DAC to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Line to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DAC to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Line to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Speaker Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Maxim Integrated Products2 MAX98088 Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS (continued) Record Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Digital Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Passband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Playback Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Automatic Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Playback Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DAC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Receiver Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Receiver Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Speaker Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Speaker Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Speaker Amplifier Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Excursion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Speaker Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DirectDrive Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Headphone Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Headphone Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Output Bypass Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Jack Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Jack Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Maxim Integrated Products3 MAX98088 Stereo Audio Codec with FlexSound Technology TABLE OF CONTENTS (CONTINUED) I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Device Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Maxim Integrated Products4 D8 INB2 E7 INB1 E9 INA2/EXTMICN F9 INA1/EXTMICP G8 MIC2N G9 MIC2P MIC2BYP MIC1N/ F8 DIGMICCLK MIC1P/ E8 DIGMICDATA F7 MICBIAS E6 JACKSNS INABYP MBEN JDETEN JACK DETECTION I2C REG + + EXTMIC EXTMIC PGAINB: +20dB TO -6dB INBDIFF PGAINB: +20dB TO -6dB PGAINA: +20dB TO -6dB INADIFF PGAINA: +20dB TO -6dB PA2EN: 0/20/30dB PGAM2: +20dB TO 0dB PA1EN: 0/20/30dB PGAM1: +20dB TO 0dB CLOCK CONTROL E2 MCLK MIXADR MIX MIXADL MIX D1 MAS1 DAI1 SEL1 ADREN ADCR ADCL ADLEN BCLKS1 D4 LRCLKS1 D2 LBEN2 MODE1 AVFLT MIX MUX DATA OUTPUT + G7 PORT S2 EQ2EN DV1: 0dB TO -15dB HIZOFF2 MODE1 DVFLT AUDIO/ VOICE FILTERS DCB2 MIXDAR MIX MIXDAL MIX DAREN DACR DALEN DACL C6, C7, D5, D6, D7, E3 N.C. DATA INPUT SDIEN2 G4 DVDD G2 DVDDS2 FlexSoundTM TECHNOLOGY AUDIO FILTERS DVEQ2: 0dB TO -15dB G3 SDINS2 DATA OUTPUT MAS2 LBEN1 DV2: 0dB TO -15dB EXCURSION LIMITER EQ1EN G1 SDOUTS2 FRAME CLOCK LRCLK2 5-BAND PARAMETRIC EQ DVEQ1: 0dB TO -15dB MULTI BAND ALC F1 AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB F3 LRCLKS2 BIT CLOCK BCLK2 DV1G: 0/6/12/18dB 5-BAND PARAMETRIC EQ LTEN1 + MAS2 AGND SAMPLE RATE CONVERTER AUDIO/ VOICE FILTERS DATA INPUT SDIEN1 DVST: 0dB TO -60dB HIZOFF1 DAI2 SEL2 F2 BCLKS2 E1 DVDDS1 DGND SRMIX_ MODE E4 SDINS1 NOISE GATE DSTS SIDETONE SDOUT1 MAS1 PORT S1 SDOUTS1 FRAME CLOCK LRCLK1 AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB AUTOMATIC GAIN CONTROL BIT CLOCK BCLK1 E5 SDIN1 F5 SDOUT2 F4 SDIN2 SDA SCL IRQ G5 AVDD MIXHPR MIX MIXHPL MIX MIXSPR MIX MIXSPL MIX MIXRECR MIX MIXRECL MIX MIXHPR_ PATH SEL MIXHPL_ PATH SEL CHARGE PUMP HPREN HPVOR: +3dB TO -67dB HPLEN B9 A8 SPKBYP POWER/ DISTORTION LIMITER RECREN 0dB RECBYP RECLEN 0dB HPVOLL: +3dB TO -67dB SPREN +6dB SPLEN +6dB RECVOLR: +8dB TO -62dB RECVOLL: +8dB TO -62dB B8 B7 HPVDD HPVSS C1N C1P SPVOLR: +8dB TO -62dB SPVOLL: +8dB TO -62dB LINEMODE MAX98088 BIAS REF A7 A9 PVDD D9 C8 C9 A2, B2 A1, B1 C1, C2 C3, D3 C4, C5 A5, B5 A4, B4 A3, B3 B6 A6 F6 G6 HPGND HPR HPSNS HPL SPKRGND SPKRN SPKRP SPKRVDD SPKLGND SPKLN SPKLP SPKLVDD RECN/ LOUTR/ RXINN RECP/ LOUTL/ RXINP REG MAX98088 Stereo Audio Codec with FlexSound Technology Functional Diagram Maxim Integrated Products5 MAX98088 Stereo Audio Codec with FlexSound Technology ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, PVDD, HPVDD...............................-0.3V to +2.2V SPKLVDD, SPKRVDD, DVDDS1, DVDDS2...........-0.3V to +6.0V DGND, HPGND, SPKLGND, SPKRGND...............-0.1V to +0.1V HPVSS................................ (HPGND - 2.2V) to (HPGND + 0.3V) C1N..................................... (HPVSS - 0.3V) to (HPGND + 0.3V) C1P......................................(HPGND - 0.3V) to (HPVDD + 0.3V) REF, MICBIAS.................................. -0.3V to (SPKLVDD + 0.3V) MCLK, SDINS1, SDINS2, JACKSNS, SDA, SCL, IRQ..................................................-0.3V to +6.0V LRCLKS1, BCLKS1, SDOUTS1.......... -0.3V to (DVDDS1 + 0.3V) LRCLKS2, BCLKS2, SDOUTS2.......... -0.3V to (DVDDS2 + 0.3V) REG, INA1/EXTMICP, INA2/EXTMICN, INB1, INB2, MIC1P/DIGMICDATA, MIC1N/DIGMICCLK, MIC2P, MIC2N...................................................-0.3V to +2.2V HPSNS................................ (HPGND - 0.3V) to (HPGND + 0.3V) HPL, HPR............................. (HPVSS - 0.3V) to (HPVDD + 0.3V) RECP/LOUTL/RXINP, RECN/LOUTR/ RXINN......................(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKLP, SPKLN............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKRP, SPKRN..........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V) Continuous Power Dissipation (TA = +70NC) 63-Bump WLP (derate 25.6mW/NC above +70NC).........2.05W Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Supply Voltage Range Guaranteed by PSRR VSPKLVDD, VSPKRVDD 2.8 VDVDD, VAVDD, VPVDD 1.65 VDVDDS1, VDVDDS2 1.65 Analog Full-duplex 8kHz mono, Speaker receiver output, MAS = 1 Digital Total Supply Current (Notes 2 and 3) Shutdown Supply Current (Note 2) IVDD 5.5 1.8 2 4.5 8 1.6 2.3 1.3 2 DAC playback 48kHz stereo, headphone outputs, MAS = 1 Analog 1.9 3 Speaker 0.001 0.0058 Digital 2.47 3.5 DAC playback 48kHz stereo, speaker outputs, MAS = 1 Analog 3.6 6.5 Speaker 6.41 8.5 Digital 2.49 3.5 Analog 0.2 2 Speaker 0.01 1 1 5 TA = +25NC Digital V 3.6 mA FA REF Voltage 2.5 V REG Voltage 0.79 V Shutdown to Full Operation VSEN = 0 30 VSEN = 1 17 ms Maxim Integrated Products6 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP DR fS = 8kHz, MODE = 0 (IIR voice), AVMICPRE_ = 0dB (Note 4) 88 VIN = 0.1VP-P, fS = 8kHz, f = 1kHz -78 AVMICPRE_ = 0dB, VIN = 1VP-P, f = 1kHz AVMICPRE_ = +30dB, VIN = 32mVP-P, f = 1kHz -85 VIN = 100mVP-P, f = 217Hz 74 MAX UNITS MICROPHONE TO ADC PATH Dynamic Range Total Harmonic Distortion + Noise THD+N Common-Mode Rejection Ratio CMRR VAVDD = 1.65V to 1.95V, input referred, MIC inputs floating Power-Supply Rejection Ratio PSRR Path Phase Delay dB -71 50 dB 62 f = 217Hz, VRIPPLE = 200mVP-P, input referred 62 f = 1kHz, VRIPPLE = 200mVP-P, input referred 62 f = 10kHz, VRIPPLE = 200mVP-P, input referred 53 1kHz, 0dB input, highpass filter disabled measured from analog input to digital output dB MODE = 0 (IIR voice) 8kHz 2.2 MODE = 0 (IIR voice) 16kHz 1.1 MODE = 1 (FIR audio) 8kHz 4.5 MODE = 1 (FIR audio) 48kHz 0.76 dB ms MICROPHONE PREAMP Full-Scale Input AVMICPRE_ = 0dB 1.05 PA1EN/PA2EN = 01 Preamplifier Gain AVMICPRE_ (Note 5) PGA Gain AVMICPGA_ (Note 5) MIC Input Resistance RIN_MIC VP-P 0 PA1EN/PA2EN = 10 19.5 20 20.5 PA1EN/PA2EN = 11 29.5 30 30.5 19 20 21 PGAM1/PGAM2 = 0x00 PGAM1/PGAM2 = 0x14 All gain settings, measured at MIC1P/ MIC1N/MIC2P/MIC2N 0 50 dB dB kI Maxim Integrated Products7 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.15 UNITS MICROPHONE BIAS MICBIAS Output Voltage 2.2 2.25 V Load Regulation VMICBIAS ILOAD = 1mA to 2mA 0.5 4.5 mV Line Regulation VSPKLVDD = 2.8V to 5.5V 110 f = 217Hz, VRIPPLE (SPKLVDD) = 100mVP-P 92 f = 10kHz, VRIPPLE (SPKLVDD) = 100mVP-P 83 A-weighted, f = 20Hz to 20kHz 3.9 P-weighted, f = 20Hz to 4kHz 2.1 f = 1kHz 50 IMIC1_ = 100mA, INABYP = MIC2BYP = 1, VMIC2_ = VINA_ = 0V, AVDD, TA = +25NC 5 Ripple Rejection Noise Voltage ILOAD = 1mA FV dB FVRMS nV/Hz MICROPHONE BYPASS SWITCH On-Resistance RON Total Harmonic Distortion + Noise 30 I VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz, INABYP = MIC2BYP = 1 -80 dB Off-Isolation VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz 60 dB Off-Leakage Current VMIC1_ = [0V, AVDD], VMIC2_/VINA_ = [AVDD, 0V] THD+N -1 +1 FA LINE INPUT TO ADC PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR THD+N Gain Error INA pin direct, fS = 48kHz, MODE = 1 (FIR audio) 93 VIN = 1VP-P, f = 1kHz -82 DC accuracy VAVDD = 1.65V to 1.95V, input referred, line inputs floating, TA = +25NC Power-Supply Rejection Ratio PSRR 1 57 dB -74 dB % 68 f = 217Hz, VRIPPLE = 200mVP-P, AVADC = 0dB, input referred 63 f = 1kHz, VRIPPLE = 200mVP-P, AVADC = 0dB, input referred 63 f = 10kHz, VRIPPLE = 200mVP-P, AVADC = 0dB, input referred 57 dB Maxim Integrated Products8 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LINE INPUT PREAMP Full-Scale Input VIN AVPGAIN_ = 0dB 1 AVPGAIN_ = -6dB 1.4 TA = +25NC AVPGAIN_ (Note 5) Level Adjust Gain PGAINA/PGAINB = 0x0 19 20 21 PGAINA/PGAINB = 0x1 13 14 15 PGAINA/PGAINB = 0x2 2 3 4 PGAINA/PGAINB = 0x4 -4 -3 -2 PGAINA/PGAINB = 0x5, 0x6, 0x7 -7 -6 -5 14.5 21 28 PGAINA/PGAINB = 0x3 AVPGAIN_ = +20dB 0 AVPGAIN_ = +14dB Input Resistance RIN AVPGAIN_ = +3dB 20 AVPGAIN_ = 0dB 7.5 INAEXT/INBEXT = 1 10 14 kI 20 AVPGAIN_ = -6dB RIN_FB dB 20 AVPGAIN_ = -3dB Feedback Resistance VP-P 20 TA = +25NC 18 TA = TMIN to TMAX 16 20 22 24 kI ADC LEVEL CONTROL ADC Level Adjust Range AVADCLVL AVL/AVR = 0xF to 0x0 (Note 5) -12 ADC Level Step Size ADC Gain Adjust Range +3 1 AVADCGAIN AVLG/AVRG = 00 to 11 (Note 5) 0 ADC Gain Adjust Step Size dB dB 18 6 dB dB ADC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff fPLP Passband Ripple Ripple limit cutoff 0.441 x fs -3dB cutoff 0.449 x fs f < fPLP Stopband Cutoff -0.1 fSLP Stopband Attenuation (Note 6) Hz +0.1 0.47 x fS f > fSLP 74 dB Hz dB Maxim Integrated Products9 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0) Passband Cutoff (-3dB from Peak) fAHPPB Stopband Cutoff (-30dB from Peak) fAHPSB DC Attenuation DCATTEN AVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) 0.0161 x fS AVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) 0.0319 x fS AVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) 0.0321 x fS AVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) 0.0632 x fS AVFLT = 0x5 (fS/240 Butterworth) 0.0043 x fS AVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) 0.0139 x fS AVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) 0.0156 x fS AVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) 0.0279 x fS AVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) 0.0312 x fS AVFLT = 0x5 (fS/240 Butterworth) 0.0018 x fS Hz 90 AVFLT 000 Hz dB STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz) Ripple limit cutoff Passband Cutoff fPLP Passband Ripple -3dB cutoff 0.43 x fS 0.48 x fS -6.02dB cutoff 0.5 x fS f < fPLP Stopband Cutoff -0.1 fSLP Stopband Attenuation (Note 6) Hz +0.1 0.58 x fS f < fSLP 60 dB Hz dB ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz) Passband Cutoff fPLP Passband Ripple Ripple limit cutoff 0.208 x fS -3dB cutoff 0.28 x fS -0.1 f < fPLP Stopband Cutoff fSLP Stopband Attenuation Hz +0.1 0.417 x fS f < fSLP 60 dB Hz dB Maxim Integrated Products10 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER (MODE1 = 1) Passband Cutoff (-3dB from Peak) fAHPPB AVFLT 000 DC Attenuation DCAtten AVFLT 000 0.000125 x fS 90 Hz dB MICROPHONE AUTOMATIC GAIN CONTROL AGC Hold Duration AGC Attack Time AGC Release Time AGC Threshold Level AGCHLD = 01 50 AGCHLD = 11 400 AGCATK = 00 2 AGCATK = 11 123 AGCRLS = 000 0.078 AGCRLS = 111 10 AGCTH = 0x0 to 0xF -3 AGC Threshold Step Size ms ms s +18 1 AGC Gain (Note 5) dB dB 0 20 dB -64 -16 dB 0 12 dB ADC NOISE GATE NG Threshold Level ANTH = 0x3 to 0xF, referred to 0dBFS NG Attenuation (Note 5) ADC-TO-DAC DIGITAL SIDETONE (MODE = 0) Sidetone Gain Adjust Range AVSTGA DVST = 0x01 -0.5 DVST = 0x1F -60.5 Sidetone Gain Adjust Step Size dB 2 1kHz, 0dB input, highpass filter disabled Sidetone Path Phase Delay 8kHz 2.2 16kHz 1.1 dB ms ADC-TO-DAC DIGITAL LOOP-THROUGH PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR THD+N fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio), MIC to HP output, TA = +25NC 83 f = 1kHz, fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio), MIC to HP output 93 dB 81 dB DAC LEVEL CONTROL DAC Attenuation Range AVDACATTN DV_ = 0xF to 0x0 (Note 5) -15 AVDACGAIN DV1G = 00 to 11 (Note 5) 0 DAC Attenuation Step Size DAC Gain Adjust Range DAC Gain Adjust Step Size 0 1 dB 18 6 dB dB dB Maxim Integrated Products11 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff 0.448 x fS -3dB cutoff 0.451 x fS f < fPLP -0.1 f > fSLP 75 Hz +0.1 fSLP Stopband Attenuation (Note 6) 0.476 x fS dB Hz dB VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0) Passband Cutoff (-3dB from Peak) fDHPPB Stopband Cutoff (-30dB from Peak) fDHPSB DC Attenuation DVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) 0.0161 x fS DVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) 0.0312 x fS DVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) 0.0321 x fS DVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) 0.0625 x fS DVFLT = 0x5 (fs/240 Butterworth) 0.0042 x fS DVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) 0.0139 x fS DVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) 0.0156 x fS DVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) 0.0279 x fS DVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) 0.0312 x fS DVFLT = 0x5 (fS/240 Butterworth) 0.0021 x fS DCATTEN DVFLT 000 Hz Hz 85 dB STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz) Ripple limit cutoff Passband Cutoff fPLP Passband Ripple -3dB cutoff 0.43 x fS 0.47 x fS -6.02dB cutoff 0.5 x fS f < fPLP Stopband Cutoff -0.1 fSLP Stopband Attenuation (Note 6) Hz +0.1 0.58 x fS f > fSLP 60 dB Hz dB Maxim Integrated Products12 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz) Passband Cutoff fPLP Passband Ripple Ripple limit cutoff 0.24 x fS -3dB cutoff 0.31 x fS f < fPLP Stopband Cutoff Hz -0.1 +0.1 fSLP Stopband Attenuation (Note 6) 0.477 x fS f < fSLP 60 dB Hz dB STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER Passband Cutoff (-3dB from Peak) 0.000104 x fS fDHPPB DVFLT 000 (DAI1), DCB2 = 1 (DAI2) DCATTEN DVFLT 000 (DAI1), DCB2 = 1 (DAI2) 90 dB Dual Band Lowpass Corner Frequency ALCMB = 1 5 kHz Dual Band Highpass Corner Frequency ALCMB = 1 5 kHz DC Attenuation Hz AUTOMATIC LEVEL CONTROL Gain Range Low-Signal Threshold ALCTH = 111 to 001 Release Time 0 12 dB -48 -12 dBFS ALCRLS = 101 0.25 ALCRLS = 000 8 s PARAMETRIC EQUALIZER Number of Bands 5 Per Band Gain Range Preattenuator Gain Range (Note 5) Bands -12 +12 dB -15 0 dB Preattenuator Step Size 1 dB fS = 48kHz, f = 1kHz (Note 4) 96 dB f = 1kHz, POUT = 15mW, RREC = 32I -70 DAC TO RECEIVER AMPLIFIER PATH Dynamic Range DR Total Harmonic Distortion + Noise THD+N VSPKLVDD = 2.8V to 5.5V, TA = +25NC Power-Supply Rejection Ratio Click-and-Pop Level PSRR KCP 64 dB 75 f = 217Hz, VRIPPLE = 200mVP-P f = 1kHz, VRIPPLE = 200mVP-P -59 f = 10kHz, VRIPPLE = 200mVP-P -59 Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB -63 -59 Into shutdown -68 Out of shutdown -72 dB dBV Maxim Integrated Products13 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LINE INPUT TO RECEIVER AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Click-and-Pop Level DR Referenced to full-scale output level THD+N 94 dB -64 dB KCP Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB POUT RREC = 32I, f = 1kHz, THD = 1% 83 mW (Note 7) 1 VRMS Into shutdown -51 Out of shutdown -49 dBV RECEIVER AMPLIFIER Output Power Full-Scale Output Volume Control (Note 5) AVREC Volume Control Step Size Mute Attenuation Capacitive Drive Capability RECVOL = 0x00 -62 RECVOL = 0x1F 8 +8dB to +6dB 0.5 +6dB to +0dB 1 0dB to -14dB 2 -14dB to -38dB 3 -38dB to -62dB 4 f = 1kHz 88 No sustained oscillations RREC = 32I 500 RREC = J 100 dB dB dB pF DAC TO LINE OUT AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR THD+N fS = 48kHz, f = 1kHz f = 1kHz, RL = 1kI 83 96 -78 dB -72 dB LINE INPUT TO LINE OUT AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR THD+N Referenced to full-scale output level 92 dB f = 1kHz, RL = 10kI 76 dB VP-P Full-Scale Output (Note 7) 2 Mute Attenuation f = 1kHz 85 Output Offset Voltage Capacitive Drive Capability VOS AVREC_ = -62dB Q3.0 No sustained oscillations, RL = 1kI 500 dB Q4 mV pF Maxim Integrated Products14 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC TO SPEAKER AMPLIFIER PATH Total Harmonic Distortion + Noise THD+N Crosstalk f = 1kHz, POUT = 200mW, ZSPK = 8I + 68FH -68 dB SPKL to SPKR and SPKR to SPKL, POUT = 640mW, f = 1kHz -88 dB 53 FVRMS Output Noise Click-and-Pop Level KCP Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB Into shutdown 65 Out of shutdown 66 dBV MIC INPUT TO SPEAKER AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Click-and-Pop Level DR Referenced to full-scale output level, AVSPK_ = 0dB 82 dB f = 1kHz, POUT = 200mW, RL = 8I + 68FH 71 dB KCP Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB Into shutdown 55 Out of shutdown 52 POUT f = 1kHz, THD = 1%, ZSPK = 8I + 68FH THD+N dBV SPEAKER AMPLIFIER Output Power Full-Scale Output VSPKLVDD = VSPKRVDD = 5.0V 1323 VSPKLVDD = VSPKRVDD = 4.2V VSPKLVDD = VSPKRVDD = 3.7V 914 VSPKLVDD = VSPKRVDD = 3.2V 514 (Note 7) Volume Control AVSPK_ Volume Control Step Size Mute Attenuation Output Offset Voltage VOS (Note 5) mW 700 2 SPVOLL/SPVOLR = 0x00 -62 SPVOLL/SPVOLR = 0x1F +8 +8dB to +6dB 0.5 +6dB to +0dB 1 0dB to -14dB 2 -14dB to -38dB 3 -38dB to -64dB 4 f = 1kHz 86 AVSPK_ = -61dB, TA = +25NC Q0.5 VRMS dB dB dB Q3 mV Maxim Integrated Products15 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1000 Hz EXCURSION LIMITER Upper Corner Frequency Range DHPUCF = 001 to 100 Lower Corner Frequency DHPLCF = 01 to 10 400 DHPUCF = 000 (fixed mode) 100 DHPUCF = 001 200 DHPUCF = 010 300 DHPUCF = 011 400 Biquad Minimum Corner Frequency 400 DHPUCF = 100 ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = 8dB Threshold Voltage Release Time Hz Hz 500 DHPTH = 000 0.34 DHPTH = 111 0.95 ALCRLS = 101 0.25 ALCRLS = 000 4 VP s POWER LIMITER Attenuation -64 ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = 8dB Threshold Time Constant 1 tPWR1 Time Constant 2 tPWR2 Weighting Factor kPWR PWRTH = 0x1 0.08 PWRTH = 0xF 1.23 PWRT1 = 0x1 0.5 PWRT1 = 0xF 8.7 PWRT2 = 0x1 to 0xF 0.5 PWRT2 = 0xF 8.7 PWRK = 000 to 111 12.5 dB W s min 100 % DISTORTION LIMITER Distortion Limit Release Time Constant THDCLP = 0x1 <1 THDCLP = 0xF 24 THDT1 = 000 0.76 THDT1 = 111 6.2 % s Maxim Integrated Products16 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC TO HEADPHONE AMPLIFIER PATH Master or slave mode Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR THD+N fS = 48kHz f = 1kHz, POUT = 20mW 101 Slave mode 97 Low power mode, TA = +25NC 95 -85 RHP = 32I -92 VAVDD = VPVDD = 1.65V to 2.0V Power-Supply Rejection Ratio PSRR 46 72 f = 1kHz, VRIPPLE = 200mVP-P, AVHP_ = 0dB 63 f = 10kHz, VRIPPLE = 200mVP-P, AVHP_ = 0dB 43 MODE = 0 (voice) 8kHz 2.2 MODE = 0 (voice) 16kHz 1.1 MODE = 1 (music) 8kHz 4.5 MODE = 1 (music) 48kHz 0.76 1 1 Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB dB dB ms Channel Gain Mismatch KCP dB 54 Gain Error Click-and-Pop Level -64 79.5 f = 217Hz, VRIPPLE = 200mVP-P, AVHP_ = 0dB 1kHz, 0dB input, highpass filter disabled measured from digital input to analog output DAC Path Phase Delay 97 RHP = 16I HPL to HPR and HPR to HPL, POUT = 5mW, f = 1kHz, RHP = 32I Crosstalk dB Into shutdown -62 Out of shutdown -63 5 % % dBV LINE INPUT TO HEADPHONE AMPLIFIER PATH Total Harmonic Distortion + Noise THD+N VIN = 1VP-P, f =1kHz, RHP = 32I Dynamic Range (Note 4) Click-and-Pop Level KCP Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB 81 dB 92.5 dB Into shutdown -62 Out of shutdown -63 dBV Maxim Integrated Products17 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HEADPHONE AMPLIFIER Output Power POUT Positive Charge-Pump Output Voltage HPVDD Negative Charge-Pump Output Voltage HPVSS Output Voltage Threshold (Output Voltage at which the Charge Pump Switches Modes; VOUT Rising; Transition from Split to Invert Mode) VTH Full-Scale Output Volume Control AVHP_ Volume Control Step Size f = 1kHz, THD = 1% RHP = 32I 30 RHP = 16I 38 VOUT VPVDD x 0.25V, RHP = J VOUT > VPVDD x 0.25V, RHP = J PVDD/2 VOUT VPVDD x 0.25V, RHP = J -PVDD/2 VOUT > VPVDD x 0.25V, RHP = J -PVDD RL = J QPVDD x 0.25 V (Note 7) 1 VRMS (Note 5) HPVOL_ = 0x00 -67 HPVOL_ = 0x1F +3 +3dB to +1dB 0.5 +1dB to -5dB 1 -5dB to -19dB 2 -19dB to -43dB 3 VOS Capacitive Drive Capability AVHP_ = -67dB No sustained oscillations V dB dB 4 f = 1kHz Output Offset Voltage V PVDD -43dB to -67dB Mute Attenuation mW 100 TA = +25NC Q0.5 TA = TMIN to TMAX dB Q1 Q3 RHP = 32I 500 RHP = J 100 mV pF SPEAKER BYPASS SWITCH On-Resistance RON Total Harmonic Distortion + Noise THD+N ISPKL_ = 100mA, SPKBYP = 1, VRXIN_ = [0V, VSPKLVDD] 2.8 VIN = 2VP-P, VCM = VSPKLVDD/2, RS = 10I ZSPK = 8I + 68FH, f = 1kHz, RS = 0I SPKBYP = 1 Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2, ZSPK = 8I + 68FH, f = 1kHz Off-Leakage Current VRXIN_ = [0V, VSPKLVDD], VSPKL_ = [VSPKLVDD, 0V] I 60 dB 60 96 -20 dB +20 FA Maxim Integrated Products18 MAX98088 Stereo Audio Codec with FlexSound Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL or LOUTR to SPKLGND. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RECEIVER BYPASS SWITCH IRECP = 100mA, RECBYP = 1, VRECN = [0V, VSPKLVDD] 2 I VIN = 2VP-P, VCM = VSPKLVDD/2, ZSPK = 8I + 68FH, f = 1kHz, RECBYP = 1, RS = 0I 60 dB Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2, ZSPK = 8I + 68FH, f = 1kHz 84 dB Off-Leakage Current VRECP = [0V, VSPKLVDD], VRECN = [VSPKLVDD, 0V] On-Resistance RON Total Harmonic Distortion + Noise THD+N -15 +15 FA JACK DETECTION SHDN = 1, JACKSNS rising JACKSNS Threshold 0.92 x 0.95 x 0.98 x VMICBIAS VMICBIAS VMICBIAS SPKLVDD - 0.7 SHDN = 0, JKSNS JACKSNS Sense Voltage SPKLVDD SHDN = 0 VJACKSNS = 0V JACKSNS Sense Current V 4 V 10 FA 5.6 V BATTERY ADC Input Voltage Range 2.6 LSB Size 0.1 V DIGITAL INPUT/OUTPUT CHARACTERISTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MCLK Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIH, IIL 1.2 VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25C V -1 Input Capacitance 0.6 V +1 FA 10 pF SDINS1, BCLKS1, LRCLKS1--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDDS1 0.29 x DVDDS1 Input Hysteresis 200 Input Leakage Current Input Capacitance V IIH, IIL VDVDDS1 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 mV +1 10 V FA pF Maxim Integrated Products19 MAX98088 Stereo Audio Codec with FlexSound Technology DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V BCLKS1, LRCLKS1, SDOUTS1--OUTPUT Output Low Voltage Output High Voltage Input Leakage Current VOL VOH IIH, IIL VDVDDS1 = 1.65V, IOL = 3mA VDVDDS1 = 1.65V, IOH = 3mA VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25C, high-impedance state DVDDS1 - 0.4 V -1 +1 FA SDINS2, BCLKS2, LRCLKS2--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDDS2 V 0.29 x DVDDS2 Input Hysteresis 200 Input Leakage Current IIH, IIL VDVDDS2 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 Input Capacitance V mV +1 10 FA pF BCLKS2, LRCLKS2, SDOUTS2--OUTPUT Output Low Voltage VOL VDVDDS2 = 1.65V, IOL = 3mA Output High Voltage VOH VDVDDS2 = 1.65V, IOH = 3mA Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC, high-impedance state 0.4 DVDDS2 - 0.4 V V -1 +1 FA SDA, SCL--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDD V 0.3 x DVDD Input Hysteresis 210 Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC -1 Input Capacitance mV +1 10 SDA, IRQ--OUTPUT Output High Current Output Low Voltage IOH VOL VOUT = 5.5V, TA = +25C VDVDD = 1.65V, IOL = 3mA V FA pF 1 mA 0.2 x DVDD V DIGMICDATA--INPUT Input High Voltage VIH Input Low Voltage VIL 0.65 x DVDD 0.35 x DVDD Input Hysteresis 125 Input Leakage Current Input Capacitance V IIH, IIL VDVDD = 2.0V, VIN = 0V, 2.0V; TA = +25C -25 mV +25 10 V FA pF Maxim Integrated Products20 MAX98088 Stereo Audio Codec with FlexSound Technology DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V DIGMICCLK--OUTPUT Output Low Voltage VOL VDVDD = 1.65V, IOL = 1mA Output High Voltage VOH VDVDD = 1.65V, IOH = 1mA DVDD 0.4 V INPUT CLOCK CHARACTERISTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER MCLK Input Frequency MCLK Input Duty Cycle SYMBOL CONDITIONS fMCLK MIN DAI1 LRCLK Average Frequency Error (Note 9) MHz PSCLK = 10 or 11 30 60 DHF_ = 0 8 48 DHF_ = 1 48 96 70 100 FREQ1 = 0x8 to 0xF FREQ1 = 0x0 0 0 +0.025 -0.025 +0.025 Rapid lock mode 2 7 Nonrapid lock mode 12 25 100 10 % psRMS -0.025 Maximum LRCLK Jitter to Maintain PLL Lock Soft-Start/Stop Time UNITS 60 40 DAI2 LRCLK Average Frequency Error (Note 9) PLL Lock Time 50 MAX PSCLK = 01 Maximum MCLK Input Jitter LRCLK Sample Rate (Note 8) TYP 10 kHz % % ms ns ms Maxim Integrated Products21 MAX98088 Stereo Audio Codec with FlexSound Technology AUDIO INTERFACE TIMING CHARACTERISTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BCLK Cycle Time tBCLK Slave mode 90 ns BCLK High Time tBCLKH Slave mode 20 ns BCLK Low Time tBCLKL Slave mode 20 BCLK or LRCLK Rise and Fall Time SDIN to BCLK Setup Time tR, tF 5 tSETUP LRCLK to BCLK Setup Time tSYNCSET SDIN to BCLK Hold Time Slave mode tHOLD LRCLK to BCLK Hold Time tSYNCHOLD Slave mode Minimum Delay Time from LSB BCLK Falling Edge to High-Impedance State tHIZOUT Master mode, TDM_ = 1 LRCLK Rising Edge to SDOUT MSB Delay tSYNCTX CL = 30pF, TDM_ = 1, FSW_ = 1 BCLK to SDOUT Delay tCLKTX Delay Time from BCLK to LRCLK Delay Time from LRCLK to BCLK After LSB CL = 30pF tCLKSYNC tENDSYNC Master mode Master mode ns 20 ns 20 ns 20 ns 20 ns 42 ns 50 TDM_ = 1, BCLK rising edge 50 TDM_ = 0 50 TDM_ = 1 -15 ns ns +15 0.8 x TDM_ = 0 ns tBCLKL TDM_ = 1, FSW_ = 1 20 ns tBCLK tF t BCLK R (OUTPUT) ns Master mode, CL = 15pF tBCLKH BCLK (INPUT) tCLKSYNC tBCLKL tSYNCSET LRCLK (INPUT) LRCLK (OUTPUT) tCLKTX tHIZOUT SDOUT (OUTPUT) LSB SDIN (INPUT) LSB tCLKTX tHIZOUT HI-Z tSETUP MSB tHOLD MSB MASTER MODE SDOUT (OUTPUT) LSB SDIN (INPUT) LSB HI-Z tSETUP MSB tHOLD MSB SLAVE MODE Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0) Maxim Integrated Products22 MAX98088 Stereo Audio Codec with FlexSound Technology tBCLK tF tR tBCLKH BCLK (OUTPUT) tBCLKL BCLK (INPUT) tCLKSYNC tSYNCSET tCLKSYNC LRCLK (OUTPUT) tSYNCHOLD LRCLK (INPUT) tCLKTX tHIZOUT SDOUT (OUTPUT) LSB SDOUT (OUTPUT) MSB HI-Z tCLKTX tHIZOUT LSB HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB tSETUP tHOLD SDIN (INPUT) MSB LSB MSB MASTER MODE SLAVE MODE Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0) tBCLK tF tR tBCLKH BCLK (OUTPUT) tENDSYNC tCLKSYNC LRCLK (OUTPUT) LRCLK (INPUT) tHIZOUT SDOUT (OUTPUT) tBCLKL BCLK (INPUT) LSB tSYNCTX tCLKTX HI-Z MSB tHIZOUT SDOUT (OUTPUT) LSB tSYNCTX tCLKTX HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB tSETUP tHOLD SDIN (INPUT) MSB MASTER MODE LSB MSB SLAVE MODE Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1) DIGITAL MICROPHONE TIMING CHARACTERSTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MICCLK = 00 MCLK/8 MICCLK = 01 MCLK/6 MAX UNITS DIGMICCLK Frequency fMICCLK MHz DIGMICDATA to DIGMICCLK Setup Time tSU,MIC Either clock edge 20 ns DIGMICDATA to DIGMICCLK Hold Time tHD,MIC Either clock edge 0 ns Maxim Integrated Products23 MAX98088 Stereo Audio Codec with FlexSound Technology 1/fMICCLK tHD,MIC tSU,MIC tHD,MIC tSU,MIC LEFT RIGHT LEFT RIGHT Figure 4. Digital Microphone Timing Diagram I2C TIMING CHARACTERSTICS (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS Guaranteed by SCL pulse-width low and high MIN MAX UNITS 400 kHz Serial-Clock Frequency fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs tHD,STA 0.6 Fs SCL Pulse-Width Low tLOW 1.3 Fs SCL Pulse-Width High Hold Time (Repeated) START Condition 0 TYP tHIGH 0.6 Fs Setup Time for a Repeated START Condition tSU,STA 0.6 Fs Data Hold Time Data Setup Time tHD,DAT tSU,DAT RPU = 475I, CB = 100pF, 400pF 0 100 900 ns ns SDA and SCL Receiving Rise Time tR (Note 10) 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF (Note 10) 20 + 0.1CB 300 ns SDA Transmitting Fall Time tF RPU = 475I, CB = 100pF, 400pF (Note 10) 20 + 0.05CB 250 ns 400 pF 50 ns Setup Time for STOP Condition tSU,STO Bus Capacitance CB Pulse Width of Suppressed Spike tSP 0.6 Guaranteed by SDA transmitting fall time 0 Fs Maxim Integrated Products24 MAX98088 Stereo Audio Codec with FlexSound Technology I2C TIMING CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. TA = +25NC, unless otherwise noted.) (Note 1) SDA tBUF tSU,STA tSU,DAT tLOW tHD,STA tHD,DAT tSP tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. I2C Interface Timing Diagram Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Note 2: Analog supply current = IAVDD + IHPVDD. Speaker supply current = ISPKLVDD + ISPKRVDD. Digital supply current = IDVDD + IDVDDS1 + IDVDDS2. Note 3: Clocking all zeros into the DAC. Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS. f = 20Hz to 20kHz. Note 5: Gain measured relative to the 0dB setting. Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000. Note 7: 0dBFS for DAC input. 1VP-P for INA/INB inputs. Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some fullscale performance degradation compared to synchronous integer related MCLK/LRCLK ratios. Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate. Note 10: CB is in pF. Power Consumption (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (mW) DYNAMIC RANGE (dB) DAC Playback 48kHz Stereo HP DAC HP Low power mode, 24-bit, music filters, 256Fs 1.25 0.47 0.00 1.35 0.01 5.55 97 DAC Playback 48kHz Stereo HP DAC HP Low power mode, 24-bit, music filters, 256Fs, 0.1mW/channel, RHP = 32I 1.25 1.81 0.00 1.56 0.01 8.32 97 MODE PLAYBACK TO HEADPHONE ONLY Maxim Integrated Products25 MAX98088 Stereo Audio Codec with FlexSound Technology Power Consumption (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (mW) DYNAMIC RANGE (dB) DAC Playback 48kHz Stereo HP DAC HP 24-bit, music filters, 256Fs 2.04 1.27 0.00 1.53 0.01 8.72 101 DAC Playback 48kHz Stereo HP DAC HP 24-bit, music filters, 256Fs, 0.1mW/ channel, RHP = 32I 2.04 2.11 0.00 1.74 0.01 10.63 101 DAC Playback 44.1kHz Stereo HP DAC HP 24-bit, music filters 2.03 1.27 0.00 1.41 0.01 8.46 100 DAC Playback 44.1kHz Stereo HP DAC HP Low power mode, 24-bit, music filters 1.25 0.47 0.00 1.25 0.01 5.34 97 DAC Playback 8kHz Stereo HP DAC HP 16-bit, voice filters 2.04 1.27 0.00 1.07 0.00 7.89 95 DAC Playback 8kHz Stereo HP DAC HP 16-bit, low power mode, voice filters 1.26 0.47 0.00 0.90 0.00 4.72 94 DAC Playback 8kHz Mono HP DAC HP 16-bit, low power mode, voice filters 0.77 0.29 0.00 0.79 0.00 3.33 93.7 Line Playback Stereo HP INA HP Single-ended inputs 2.40 1.27 0.00 0.02 0.00 6.67 95 0.00 6.33 2.14 0.01 31.44 86 MODE DAC PLAYBACK TO CLASS D SPEAKER DAC Playback 48kHz Stereo SPK DAC SPK 24-bit, music filters 2.31 Maxim Integrated Products26 MAX98088 Stereo Audio Codec with FlexSound Technology Power Consumption (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (mW) DYNAMIC RANGE (dB) DAC Playback 48kHz Mono SPK DAC SPK 24-bit, music filters 1.35 0.00 3.23 1.84 0.01 17.69 86 Line Playback Mono SPK INA SPKL Differential inputs 1.01 0.00 3.24 0.03 0.00 13.83 83 Full-Duplex 8kHz Mono RCV MIC1 ADC DAC REC 16-bit, voice filters 6.32 0.00 1.54 1.24 0.01 19.33 Record = 87 Playback = 94 Full-Duplex 8kHz Stereo HP MIC1/2 ADC DAC HP 16-bit, mixer, voice filters 11.19 1.27 0.48 1.28 0.01 26.43 Record = 87 Playback = 96 Full-Duplex 8kHz Stereo HP MIC1/2 ADC DAC HP 16-bit, low power mode, voice filters 7.12 0.47 0.48 1.10 0.02 17.44 Record = 87 Playback = 94 Line Stereo Record 48kHz INA ADC 24-bit, low power, music filters 6.19 0.00 0.20 1.31 0.15 14.47 91 Line Stereo Record 48kHz INA ADC Direct pin input, 24bit, low power, music filters 5.69 0.00 0.20 1.31 0.12 13.53 93 MODE FULL DUPLEX LINE RECORD Maxim Integrated Products27 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Microphone to ADC TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) -50 -60 -70 MAX98088 toc02 -40 -50 -60 -30 -40 -50 -60 -70 -80 -70 -90 -80 -90 -100 -90 -100 10 100 1000 1000 10,000 100,000 10 1000 10,000 100,000 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) -60 -70 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.1VP-P AVMICPRE_ = 0dB -10 -20 -30 -40 0 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.032VP-P AVMICPRE_ = 0dB -10 -80 100 MAX98088 toc06 0 MAX98088 toc04 -50 10 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) THD+N RATIO (dB) -40 100 FREQUENCY (Hz) THD+N RATIO (dB) -30 10 FREQUENCY (Hz) MCLK = 12.288MHz LRCLK = 96kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB -20 10,000 -80 FREQUENCY (Hz) 0 -10 THD+N RATIO (dB) -30 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB -20 THD+N RATIO (dB) -40 -20 0 -10 MAX98088 toc05 THD+N RATIO (dB) -30 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE VIN = 1VP-P AVMICPRE_ = 0dB -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB -20 0 MAX98088 toc01 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) MAX98088 toc03 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) -80 10 100 1000 FREQUENCY (Hz) 10,000 10 100 1000 10,000 FREQUENCY (Hz) Maxim Integrated Products28 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) MODE = 0 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB -60 -70 -80 40 MICPRE = 0dB 30 0 10 100 1000 10 10k -40 1000 10,000 -60 -80 -100 -120 -40 -100 -120 -160 -160 500 1000 1500 2000 2500 3000 3500 4000 1000 10,000 100,000 20 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB 0 -20 -40 -60 -80 -100 -120 -140 -180 -180 FREQUENCY (Hz) 100 FFT, 0dBFS (MIC TO ADC) -80 -140 0 10 FREQUENCY (Hz) -60 -140 MAX98088 toc09 -90 100,000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 0 MAX98088 toc10 MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB 100 RIPPLE ON SPKLVDD, SPKRVDD -80 FFT, -60dBFS (MIC TO ADC) FFT, 0dBFS (MIC TO ADC) 0 RIPPLE ON AVDD, DVDD, HPVDD -50 FREQUENCY (Hz) FREQUENCY (Hz) 20 -40 -70 MCLK = 12.288MHz LRCLK = 48kHz FREQ MODE 10 -90 -30 -60 20 AMPLITUDE (dBFS) -50 -20 MAX98088 toc11 -40 -10 MAX98088 toc12 -30 INPUTS AC GROUNDED VRIPPLE = 200mVP-P 0 MICPRE = 20dB 50 -20 10 PSRR (dB) MODE = 1 60 CMRR (dB) NORMALIZED GAIN (dB) -10 MICPRE = 30dB MAX98088 toc08 0 70 MAX98088 toc07 10 POWER-SUPPLY RECTION RATIO vs. FREQUENCY (MIC TO ADC) COMMON-MODE REJECTION RATIO vs. FREQUENCY (MIC TO ADC) GAIN vs. FREQUENCY (MIC TO ADC) 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz) 0 5000 10,000 15,000 20,000 FREQUENCY (Hz) Maxim Integrated Products29 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -60 -80 MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB 0 -20 AMPLITUDE (dBFS) -100 -40 -60 -80 -100 -120 -120 -140 -140 0 5 10 15 20 0 5 FREQUENCY (kHz) FFT, -60dBFS (MIC TO ADC) AMPLITUDE (dBFS) 20 FFT, 0dBFS (MIC TO ADC) -60 -80 -100 MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB 0 -20 AMPLITUDE (dBFS) MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB -40 15 20 MAX98088 toc15 0 -20 1 FREQUENCY (kHz) MAX98088 toc16 AMPLITUDE (dBFS) -40 MAX98088 toc13 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB -20 FFT, 0dBFS (MIC TO ADC) 20 MAX98088 toc14 FFT, -60dBFS (MIC TO ADC) 0 -40 -60 -80 -100 -120 -120 -140 -140 0 5 10 FREQUENCY (kHz) 15 20 0 5 10 15 20 FREQUENCY (kHz) Maxim Integrated Products30 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) ADC ENABLE/DISABLE RESPONSE (MIC TO ADC) FFT, -60dBFS (MIC TO ADC) MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB AMPLITUDE (dBFS) -20 -40 MAX98088 toc18 MAX98088 toc17 0 SCL 1V/div -60 -80 ADC OUTPUT 0.5V/div -100 -120 -140 0 5 10 15 10ms/div 20 FREQUENCY (kHz) SOFTWARE TURN-ON/OFF RESPONSE (MIC TO ADC) MAX98088 toc19 SCL 1V/div ADC OUTPUT 0.5V/div 10ms/div Maxim Integrated Products31 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to ADC TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) -40 -50 -60 -70 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -80 -90 -80 -90 -100 -90 100 1000 10,000 10 100,000 100 FREQUENCY (Hz) 1000 MCLK = 12.288MHz LRCLK = 48kHz VIN = 1VRMS EXTERNAL GAIN MODE RIN = 56kI CIN = 1F -20 -30 -40 -50 -60 10,000 100,000 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN TO ADC) 10 VRIPPLE = 200mVP-P 0 -10 -20 PSRR (dB) 0 1000 FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO ADC) -10 100 10 100,000 10,000 FREQUENCY (Hz) MAX98088 toc23 10 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 0.1VP-P AVPGAIN_ = +20dB CIN = 1F -10 MAX98088 toc22 -20 0 MAX98088 toc24 -30 THD+N (dB) THD+N RATIO (dB) -20 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P AVPGAIN_ = 0dB CIN = 1F THD+N RATIO (dB) -10 0 -10 THD+N RATIO (dB) MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1.4VP-P AVPGAIN_ = -6dB CIN = 1F MAX98088 toc20 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) MAX98088 toc21 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) -30 -40 RIPPLE ON AVDD, DVDD, HPVDD -50 -60 -70 -70 -80 -80 RIPPLE ON SPKLVDD, SPKRVDD -90 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products32 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line-In Pin Direct to ADC TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN DIRECT TO ADC) -30 VRIPPLE = 200mVP-P -20 -30 -40 PSRR (dB) THD+N RATIO (dB) -20 0 -10 MAX98088 toc26 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P CIN = 1F MAX98088 toc25 0 -10 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN DIRECT TO ADC) -50 -60 RIPPLE ON AVDD, DVDD, HPVDD -40 -50 -60 -70 -80 -70 -90 -80 -100 -90 10 100 1000 10,000 100,000 RIPPLE ON SPKLVDD, SPKRVDD 10 100 FREQUENCY (Hz) 1000 10,000 100,000 FREQUENCY (Hz) Digital Loopback MCLK = 12.288MHz LRCLK = 48kHz NI MODE -20 -60 -80 -100 -120 -140 MCLK = 12.288MHz LRCLK = 48kHz NI MODE -20 -40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 0 MAX98088 toc27 0 FFT, -60dBFS (SDINS1 TO SDINS2 DIGITAL LOOPBACK) MAX98088 toc28 FFT, 0dBFS (SDINS1 TO SDINS2 DIGITAL LOOPBACK) -60 -80 -100 -120 -140 -160 -160 -180 -180 0 5 10 FREQUENCY (kHz) 15 20 0 5 10 15 20 FREQUENCY (kHz) Maxim Integrated Products33 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Analog Loopback TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE) -50 POUT = 0.020W -70 -20 POUT = 0.020W POUT = 0.01W 100 1000 100,000 -80 -120 10 100 -140 1000 10,000 0 100,000 5 10 15 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (kHz) FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE) FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE) FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE) -40 -60 -80 -100 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F 0 -20 -40 -60 -80 -140 5 10 FREQUENCY (kHz) 15 20 -40 -60 -80 -120 -120 -140 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F -20 20 -100 -100 -120 0 AMPLITUDE (dBV) -20 20 MAX98088 toc33 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F 0 -60 -100 POUT = 0.01W -80 10,000 AMPLITUDE (dBV) 10 -40 MAX98088 toc31 MAX98088 toc30 -50 -60 0 AMPLITUDE (dBV) -40 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F 0 -70 -80 -90 -30 20 AMPLITUDE (dBV) -40 -60 -20 MAX98088 toc32 THD+N RATIO (dB) -30 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F -20 0 MAX98088 toc29 0 -10 FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE) MAX98088 toc34 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE) -140 0 5 10 FREQUENCY (kHz) 15 20 0 5 10 15 20 FREQUENCY (kHz) Maxim Integrated Products34 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Receiver f = 3000Hz f = 1000Hz -50 -60 -70 -70 0.04 0.06 0.08 2 140 100 THD+N = 1% 80 10 100 2.5 10,000 1000 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) GAIN vs. FREQUENCY (DAC TO RECEIVER) POWER CONSUMPTION vs. OUTPUT POWER (DAC TO RECEIVER) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO RECEIVER) MAX98088 toc38 1 0 -1 -2 -3 250 MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVREC = +8dB RREC = 32I 200 150 0 INPUTS AC GROUNDED VRIPPLE = 200mVP-P -10 -20 -30 100 -40 RIPPLE ON AVDD, DVDD, HPVDD -50 -60 -70 50 RIPPLE ON SPKLVDD, SPKRVDD -80 -4 -90 -5 10 MAX98088 toc37 THD+N = 10% 120 FREQUENCY (Hz) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I 3 160 60 -90 0.12 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB 180 OUTPUT POWER (W) 5 4 0.10 PSRR (dB) 0.02 POUT = 0.08W 200 MAX98088 toc39 0 POUT = 0.02W -80 f = 100Hz -90 NORMALIZED GAIN (dB) -40 -60 -80 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO RECEIVER) OUTPUT POWER PER CHANNEL (mW) -30 -40 -50 -20 POWER CONSUMPTION (mW) THD+N (dB) -30 THD+N (dB) -20 -10 MAX98088 toc36 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB -10 0 MAX98088 toc35 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO RECEIVER) 100 1000 FREQUENCY (Hz) 10,000 MAX98088 toc40 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO RECEIVER) 0 -100 0 20 40 60 80 100 OUTPUT POWER PER CHANNEL (mW) 120 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products35 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 1) FFT, 0dBFS (DAC TO RECEIVER) MAX98088 toc42 MAX98088 toc41 20 -20 AMPLITUDE (dBV) RECEIVER OUTPUT 1V/div RECEIVER OUTPUT 1V/div MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I 0 SCL 1V/div SCL 1V/div -40 MAX16067 toc43 SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 0) -60 -80 -100 -120 -140 -160 0 10ms/div 10ms/div 5 10 20 15 FREQUENCY (kHz) -40 -60 -80 -100 -20 -40 -60 -80 -100 -120 0 5 10 FREQUENCY (kHz) 15 20 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I -20 -40 -60 -80 -100 -120 -140 0 MAX98088 toc45 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AMPLITUDE (dBm) AMPLITUDE (dBV) -20 0 MAX98088 toc44 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AMPLITUDE (dBm) 0 WIDEBAND FFT, 0dBFS (DAC TO RECEIVER) MAX98088 toc46 WIDEBAND FFT, 0dBFS (DAC TO RECEIVER) FFT, -60dBFS (DAC TO RECEIVER) -120 0 1 10 100 FREQUENCY (kHz) 1000 10,000 0 1 10 100 1000 10,000 FREQUENCY (kHz) Maxim Integrated Products36 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Receiver TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO RECEIVER) -30 -40 f = 1000Hz f = 6000Hz -30 -40 POUT = 0.02W -50 -60 -70 -60 POUT = 0.08W -80 -70 0 0.02 0.04 0.06 0.08 10 100 1000 10,000 100,000 FREQUENCY (Hz) GAIN vs. FREQUENCY (LINE TO RECEIVER) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN DIRECT TO RECEIVER) 0 MAX98088 toc49 RREC = 32I CIN = 1F 3 -90 0.10 OUTPUT POWER (W) 5 4 INPUTS AC GROUNDED VRIPPLE = 200mVP-P -10 -20 2 -30 1 PSRR (dB) NORMALIZED GAIN (dB) RREC = 32I AVREC = +8dB CIN = 1F 0 -1 RIPPLE ON SPKLVDD, SPKRVDD -40 RIPPLE ON AVDD, DVDD, HPVDD -50 -60 -2 MAX98088 toc50 f = 100Hz -50 -20 THD+N RATIO (dB) THD+N RATIO (dB) -20 -10 MAX98088 toc48 RREC = 32I AVREC = +8dB CIN = 1F -10 0 MAX98088 toc47 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO RECEIVER) -70 -3 -4 -80 -5 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products37 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Line Output FFT, 0dBFS (DAC TO LINE OUT) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RLOAD = 10kI -20 AMPLITUDE (dBV) AMPLITUDE (dBV) -20 MAX98088 toc51 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RLOAD = 10kI 0 0 -40 -60 -80 -40 MAX98088 toc52 FFT, -60dBFS (DAC TO LINE OUT) 20 -60 -80 -100 -100 -120 -120 -140 0 5 10 15 -140 20 0 5 FREQUENCY (kHz) 10 15 20 FREQUENCY (kHz) Line to Line Output TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO LINE-OUT) -20 -20 -50 f = 6kHz -60 -40 -50 -70 -80 -80 f = 1kHz -90 0 0.2 0.4 0.6 VOUT = 0.2VRMS -60 -70 f = 100Hz 0.8 1.0 OUTPUT LEVEL (VRMS) 1.4 -40 -50 -60 -70 -80 -90 VOUT = 0.8VRMS -100 -90 1.2 VIN = 1VRMS, 1kHz RLOAD = 10kI EXTERNAL GAIN MODE REXT = 56kI -20 THD+N (dB) THD+N (dB) -40 0 -10 -30 -30 -30 THD+N (dB) RLOAD = 10kI -10 MAX98088 toc55 RLOAD = 10kI -10 0 MAX98088 toc53 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO LINE-OUT) MAX98088 toc54 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT LEVEL (LINE-IN TO LINE-OUT) 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products38 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Speaker -40 -20 f = 6000Hz -50 -60 f = 1000Hz -70 -30 -40 -50 f = 1000Hz -60 -70 -80 0 0.2 0.4 0.6 0.8 1.0 f = 100Hz -80 f = 100Hz -90 1.2 -90 1.4 0 0.2 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) 1 0 -1 -2 -20 -30 -40 -50 -70 -4 -80 -5 -90 100 1k FREQUENCY (Hz) 10k 100k f = 6000Hz -60 -3 10 VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB 0 1.0 VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB -10 -20 THD+N RATIO (dB) 2 0 -10 THD+N RATIO (dB) NORMALIZED GAIN (dBrA) 3 0.8 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) MAX98088 toc59 MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H 4 0.6 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) MAX98088 toc58 5 0.4 OUTPUT POWER (W) -30 f = 6000Hz -40 -50 f = 1000Hz -60 -70 f = 100Hz f = 1000Hz 0 0.5 1.0 MAX98088 toc60 THD+N RATIO (dB) -30 VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB f = 6000Hz -10 THD+N RATIO (dB) VSPKVDD_ = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H AVSPK_ = +8dB -20 0 MAX98088 toc56 0 -10 MAX98088 toc57 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) f = 100Hz -80 1.5 OUTPUT POWER (W) 2.0 2.5 0 0.5 1.0 1.5 2.0 OUTPUT POWER (W) Maxim Integrated Products39 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) f = 6000Hz -40 -50 MAX98088 toc62 -40 -50 POUT = 0.55W f = 100Hz -20 -70 0 0.2 0.4 0.6 1.0 20 1.2 -40 -50 POUT = 0.55W -70 POUT = 0.25W -80 0.8 -30 -60 -70 f = 1000Hz VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB -10 -60 -60 200 2000 POUT = 0.25W -80 20,000 20 200 2000 20,000 OUTPUT POWER (W) FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER) -30 -40 POUT = 1W -50 -60 -70 -20 -30 -40 POUT = 1W -50 -60 POUT = 0.5W -80 -90 100 1000 10,000 FREQUENCY (Hz) 100,000 2200 MAX98088 toc66 -10 -70 POUT = 0.5W -80 VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB OUTPUT POWER PER CHANNEL (mW) -20 0 THD+N RATIO (dB) VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB MAX98088 toc64 0 -10 THD+N RATIO (dB) -30 0 THD+N RATIO (dB) -30 -20 MAX98088 toc65 THD+N RATIO (dB) -20 VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB -10 THD+N RATIO (dB) VSPK_VDD = 3V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB -10 0 MAX98088 toc61 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) MAX98088 toc63 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H AVSPK_ = +8dB 2000 1800 1600 1400 THD+N = 10% 1200 1000 800 THD+N = 1% 600 400 -90 100 1000 10,000 FREQUENCY (Hz) 100,000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Maxim Integrated Products40 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) GAIN vs. FREQUENCY (DAC TO SPEAKER) THD+N = 10% 2000 1500 THD+N = 1% 1000 MAX98088 toc68 80 1 0 -1 70 60 40 -2 30 -3 20 -4 10 0 -5 3.5 4.0 4.5 5.0 1k 10k 0.5 1.0 1.5 2.5 2.0 OUTPUT POWER (W) EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER) SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC TO SPEAKER) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO SPEAKER) 60 ZSPK = 4I + 33H 40 VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVSKP_ = +8dB 30 20 10 MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H SPKVOL_ = +8dB ALL ZEROS AT INPUT 15 12 9 0.4 0.6 0.8 1.0 OUTPUT POWER (W) 1.2 1.4 1.6 -20 -30 RIPPLE ON AVDD, DVDD, HPVDD -40 -60 RIPPLE ON SPKLVDD, SPKRVDD -70 0 0.2 VRIPPLE = 200mVP-P -10 -50 6 3 0 0 MAX98088 toc71 18 PSRR (dB) 70 0 0 100k FREQUENCY (Hz) 80 50 100 SUPPLY VOLTAGE (V) ZSPK = 8I + 68H 90 VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVSKP_ = +8dB 0 10 5.5 SUPPLY CURRENT (mA) 100 3.0 ZSPK = 4I + 33H 50 500 2.5 EFFICIENCY (%) 2 ZSPK = 8I + 68H 90 MAX98088 toc72 2500 3 100 EFFICIENCY (%) 3000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H 4 NORMALIZED GAIN (dB) 3500 5 MAX98088 toc67 MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 4I + 33H AVSPK_ = +8dB MAX98088 toc70 OUTPUT POWER PER CHANNEL (mW) 4000 EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER) MAX98088 toc69 OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER) -80 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products41 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 0) CROSSTALK vs. FREQUENCY (DAC TO SPEAKER) MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H -20 CROSSTALK (dB) MAX98088 toc73 0 -10 SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 1) MAX98088 toc74 MAX98088 toc75 SCL 1V/div SCL 1V/div SPEAKER OUTPUT 1V/div SPEAKER OUTPUT 1V/div -30 -40 -50 -60 -70 -80 10 100 1000 10,000 10ms/div 100,000 10ms/div FREQUENCY (Hz) FFT, -60dBFS (DAC TO SPEAKERS) -60 -80 -40 WIDEBAND FFT (DAC TO SPEAKER) MAX98088 toc77 -60 -80 -100 -100 0 5000 10,000 FREQUENCY (kHz) 15,000 20,000 -20 -30 -40 -50 -60 -70 -90 -140 -140 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE ZSPK_ = 8I + 68H -10 -80 -120 -120 0 AMPLITUDE (dBm) -40 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE ZSPK_ = 8I + 68H -20 AMPLITUDE (dBV) -20 AMPLITUDE (dBV) MAX98088 toc76 MCLK = 12.2888MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H 0 0 MAX98088 toc78 FFT, -60dBFS (DAC TO SPEAKERS) 20 0 5000 10,000 FREQUENCY (kHz) 15,000 20,000 -100 1 10 100 FREQUENCY (MHz) Maxim Integrated Products42 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Speaker f = 1000Hz -50 -40 -70 -70 -80 0.2 0.4 MAX98088 toc80 POUT = 0.5W 0.8 1.0 100 1000 -2 10 100,000 10,000 100 FREQUENCY (Hz) 10 INPUTS AC GROUNDED VRIPPLE = 200mVP-P 1000 0 ZFN = 8I + 68H CIN = 1F -10 -20 CROSSTALK (dB) RIPPLE ON SPKLVDD, SPKRVDD -40 -50 -60 -80 100 1000 FREQUENCY (Hz) 10,000 -40 -50 RIGHT TO LEFT -70 -90 10 -30 -60 RIPPLE ON AVDD, DVDD, HPVDD -70 100,000 CROSSTALK vs. FREQUENCY (LINE TO SPEAKER) -20 -30 10,000 FREQUENCY (Hz) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN TO SPEAKER) -10 0 -1 -5 10 OUTPUT POWER (W) 0 1 -4 -80 0.6 2 -3 POUT = 0.25W MAX98088 toc82 0 3 -50 -60 ZFN = 8I + 68H CIN = 1F 4 -30 -60 f = 100Hz 5 MAX98088 toc83 f = 6000Hz -20 GAIN vs. FREQUENCY (LINE TO SPEAKER) NORMALIZED GAIN (dB) -40 PSRR (dB) THD+N RATIO (dB) -30 ZSPK = 8I + 68H AVSPK_ = +8dB CIN = 1F -10 THD+N RATIO (dB) ZSPK = 8I + 68H AVSPK_ = +8dB CIN = 1F -20 0 MAX98088 toc79 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO SPEAKER) MAX98088 toc81 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO SPEAKER) 100,000 LEFT TO RIGHT -80 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products43 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Headphone TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) -40 -50 f = 3000Hz -60 -70 0 0.01 -40 f = 6000Hz -50 -60 f = 1000Hz f = 100Hz -80 f = 100Hz -90 -30 -70 f = 1000Hz -80 -90 0.02 0.03 0.04 0 0.05 0.01 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) -40 -50 -60 f = 6000Hz -70 f = 1000Hz -30 -50 -60 0.02 0.03 OUTPUT POWER (W) 0.04 0.05 f = 6000Hz 0.04 0.05 -20 -30 -40 -50 -60 f = 6000Hz f = 1000Hz -80 f = 100Hz -90 0.01 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I AVHP_ = +3dB -10 -70 f = 1000Hz 0 0 MAX98088 toc87 -40 -80 f = 100Hz -90 0.01 -20 -70 -80 0 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB THD+N RATIO (dB) -30 0 -10 THD+N RATIO (dB) THD+N RATIO (dB) -20 0.03 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) MAX98088 toc86 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB -10 0.02 OUTPUT POWER (W) OUTPUT POWER (W) 0 MAX98088 toc85 -20 0.02 0.03 OUTPUT POWER (W) f = 100Hz -90 0.04 0.05 MAX98088 toc88 THD+N RATIO (dB) -30 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB -20 0 MAX98088 toc84 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 OUTPUT POWER (W) Maxim Integrated Products44 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) -40 -50 f = 6000Hz -60 -70 f = 1000Hz -80 f = 100Hz MAX98088 toc90 -40 -50 -60 -80 0.01 0.02 0.03 0.04 10 0.05 100 -30 -40 -50 -60 POUT = 0.01W -70 -80 POUT = 0.02W -90 0 -20 POUT = 0.01W -70 -90 1000 POUT = 0.02W -90 10 10,000 100 1000 10,000 100,000 FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) -30 -40 -50 -60 POUT = 0.02W -70 -20 -30 -40 -50 -60 POUT = 0.02W -70 -80 POUT = 0.01W 10 100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I AVHP_ = +3dB -10 -20 -30 -40 -50 -60 POUT = 0.01W -70 -80 -90 0 THD+N RATIO (dB) -20 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) -10 0 MAX98088 toc92 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB -90 MAX98088 toc94 OUTPUT POWER (W) 0 THD+N RATIO (dB) -30 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) -30 -20 0 MAX98088 toc93 THD+N RATIO (dB) -20 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) MCLK = 12.288MHz LRCLK = 48kHz 256 Fs MODE LOW POWER MODE RHP = 16I AVHP_ = +3dB -10 0 MAX98088 toc89 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) MAX98088 toc91 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) -80 POUT = 0.01W POUT = 0.02W -90 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products45 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) PVDD CURRENT vs. OUTPUT POWER (DAC TO HEADPHONE) GAIN vs. FREQUENCY (DAC TO HEADPHONE) -10 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I 120 100 -20 MODE = 0 -30 -40 -50 -80 100 10 60 RPH = 16I 20 RPH = 32I 0 1000 10,000 0.01 100,000 PVDD CURRENT vs. OUTPUT POWER (DAC TO HEADPHONE) 50 RPH = 16I 30 RIPPLE ON AVDD, DVDD, HPVDD -50 -60 RIPPLE ON SPKLVDD, SPKRVDD -80 10 RPH = 32I 0 0.01 0.1 1 10 OUTPUT POWER PER CHANNEL (mW) 100 VRIPPLE = 200mVP-P LOW POWER MODE -20 -30 -40 -70 20 100 0 -10 -30 60 40 VRIPPLE = 200mVP-P -20 PSRR (dB) IPVDD (mA) 70 0 -10 PSRR (dB) 80 MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE AVHP_ = +3dB 10 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE) MAX98088 toc98 90 1 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE) MAX98088 toc97 100 0.1 OUTPUT POWER PER CHANNEL (mW) FREQUENCY (Hz) MAX98088 toc99 -70 80 40 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I -60 MAX98088 toc96 MODE = 1 IPVDD (mA) NORMALIZED GAIN (dBrA) 0 140 MAX98088 toc95 10 -40 RIPPLE ON AVDD, DVDD, HPVDD -50 -60 RIPPLE ON SPKLVDD, SPKRVDD -70 -80 -90 -90 -100 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products46 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) CROSSTALK vs. FREQUENCY (DAC TO HEADPHONE) MAX98088 toc101 MAX98088 toc100 0 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -10 -20 CROSSTALK (dB) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 0) -30 SCL 1V/div -40 -50 -60 RIGHT TO LEFT -70 HEADPHONE OUTPUT 1V/div -80 -90 LEFT TO RIGHT -100 10 100 1000 10,000 100,000 10ms/div FREQUENCY (Hz) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 1) MAX98088 toc102 SCL 1V/div HEADPHONE OUTPUT 1V/div 10ms/div Maxim Integrated Products47 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -80 -100 -120 -120 -140 5 10 15 20 -40 -60 -80 -100 -120 -140 0 5 FREQUENCY (kHz) 10 15 -140 20 0 5 FREQUENCY (kHz) -40 15 20 FFT, 0dBFS (DAC TO HEADPHONE) 20 -60 -80 -100 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I 0 -20 AMPLITUDE (dBV) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I -20 10 FREQUENCY (kHz) FFT, -60dBFS (DAC TO HEADPHONE) 0 MAX98088 toc106 0 MAX98088 toc105 -20 -60 -100 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I 0 MAX98088 toc107 -80 -40 FFT, 0dBFS (DAC TO HEADPHONE) 20 AMPLITUDE (dBV) -60 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I -20 AMPLITUDE (dBV) -40 AMPLITUDE (dBV) AMPLITUDE (dBV) -20 MAX98088 toc103 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I 0 FFT, -60dBFS (DAC TO HEADPHONE) 0 MAX98088 toc104 FFT, 0dBFS (DAC TO HEADPHONE) 20 -40 -60 -80 -120 -100 -140 -120 -140 -160 0 5 10 FREQUENCY (kHz) 15 20 0 5 10 15 20 FREQUENCY (kHz) Maxim Integrated Products48 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) FFT, -60dBFS (DAC TO HEADPHONE) -60 -80 -100 -40 -60 -80 -120 -100 -140 -120 -160 0 5 10 15 -140 20 0 5 FREQUENCY (kHz) FFT, -60dBFS (DAC TO HEADPHONE) -100 -40 -60 -80 -100 -120 -120 -140 -140 -160 10 FREQUENCY (kHz) 15 20 MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE RHP = 32I -20 AMPLITUDE (dBV) AMPLITUDE (dBV) -80 5 20 FFT, -60dBFS (DAC TO HEADPHONE) -60 0 15 0 MAX98088 toc110 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I -40 10 FREQUENCY (kHz) 0 -20 MAX98088 toc109 -20 MAX98088 toc111 AMPLITUDE (dBV) -40 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I 0 AMPLITUDE (dBV) MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -20 FFT, 0dBFS (DAC TO HEADPHONE) 20 MAX98088 toc108 0 -160 0 5 10 15 20 FREQUENCY (kHz) Maxim Integrated Products49 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -40 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I -20 -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 5 10 15 0 20 1 -80 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I LOW POWER MODE -20 -40 -60 -80 -100 -100 0.1 1 10 100 FREQUENCY (kHz) 1000 10,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I LOW POWER MODE -20 -40 -60 -80 -100 -120 -120 0 MAX98088 toc115 OUTPUT AMPLITUDE (dBV) -60 10,000 1000 WIDEBAND FFT -60dBFS (DAC TO HEADPHONE) 0 OUTPUT AMPLITUDE (dBV) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I MAX98088 toc114 0 -40 100 WIDEBAND FFT 0BFS (DAC TO HEADPHONE) WIDEBAND FFT -60dBFS (DAC TO HEADPHONE) -20 10 FREQUENCY (kHz) FREQUENCY (kHz) MAX98088 toc116 0 OFF-ISOLATION (dB) AMPLITUDE (dBV) -20 0 OUTPUT AMPLITUDE (dBV) MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE RHP = 32I MAX98088 toc112 0 MAX98088 toc113 WIDEBAND FFT 0BFS (DAC TO HEADPHONE) FFT, -60dBFS (DAC TO HEADPHONE) 0 1 10 100 FREQUENCY (kHz) 1000 10,000 -120 0.1 1 10 100 1000 10,000 FREQUENCY (kHz) Maxim Integrated Products50 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Headphone TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO HEADPHONE) -20 -30 -40 -50 f = 100Hz f = 6000Hz -70 -80 -90 0.01 0.02 -40 -50 -60 POUT = 0.020W -70 -80 f = 1000Hz 0 -30 -90 0.03 0.05 0.04 POUT = 0.01W 10 100 GAIN vs. FREQUENCY (LINE TO HEADPHONE) 1 -40 -60 -70 -3 -80 -4 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 RIPPLE ON AVDD, DVDD, HPVDD -50 -2 -5 100,000 0 RIPPLE ON SPKLVDD, SPKRVDD RHP = 32I -10 -20 CROSSTALK (dB) -30 0 VRIPPLE = 200mVP-P -20 PSRR (dB) NORMALIZED GAIN (dB) 0 -10 2 -1 10,000 CROSSTALK vs. FREQUENCY (LINE TO HEADPHONES) MAX98088 toc120 RHP = 32I CIN = 1F 3 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONE) MAX98088 toc119 5 4 1000 FREQUENCY (Hz) OUTPUT POWER (W) MAX98088 toc121 -60 RHP = 32I AVHP_ = +3dB CIN = 1F -10 THD+N RATIO (dB) THD+N RATIO (dB) -20 MAX98088 toc118 RHP = 32I AVHP_ = +3dB CIN = 1F -10 0 MAX98088 toc117 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO HEADPHONE) -30 -40 -50 -60 -70 -80 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products51 MAX98088 Stereo Audio Codec with FlexSound Technology Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Speaker Bypass Switch 90 AVPREGAIN = 20dB 80 0 MAX98088 toc122 100 -20 THD+N (dB) AVPREGAIN = 0dB 50 40 30 10 f = 6000Hz f = 1000kHz -50 f = 100Hz -70 -80 0 10 100 1000 0.05 0.10 0.15 0.20 OUTPUT POWER (W) ON-RESISTANCE vs. VCOM (SPEAKER BYPASS SWITCH) OFF-ISOLATION vs. FREQUENCY (SPEAKER BYPASS SWITCH) 2.5 VSPK_VDD = 3.7V 1.5 VSPK_VDD = 5.0V VSPK_VDD = 4.2V 1.0 0 SPEAKER AMP DRIVING LOUDSPEAKER SPEAKER BYPASS SWITCH OPEN MEASURED AT RXIN_ -20 OFF-ISOLATION (dB) VSPK_VDD = 3.0V 3.0 2.0 0 100,000 FREQUENCY (Hz) ISW = 20mA 3.5 10,000 MAX98088 toc124 4.0 RON (I) -40 -60 VOUT = -6dBV CIN = 1F RHP = 32I 20 -30 0.25 MAX98088 toc125 CMRR (dB) 60 RECEIVER AMPLIFIER DRIVING LOUDSPEAKER ZSPK = 8I + 68H -10 70 MAX98088 toc123 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER BYPASS SWITCH) COMMON-MODE REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONES) -40 -60 50I LOAD ON RXIN_ -80 RECEIVER AMP DRIVING RXIN_ -100 0.5 0 0 1 2 3 VCOM (V) 4 5 6 -120 10 100 1000 10,000 100,000 FREQUENCY (Hz) Maxim Integrated Products52 MAX98088 Stereo Audio Codec with FlexSound Technology Pin Configuration TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 7 8 9 A SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECP/ LOUTL/ RXINP PVDD HPVSS HPGND B SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECN/ LOUTR/ RXINN C1P C1N HPVDD C SPKRP SPKRP SPKRVDD SPKLGND SPKLGND N.C N.C. HPSNS HPL MAX98088 D BCLKS1 SDOUTS1 SPKRVDD LRCLKS1 N.C. N.C. N.C. INB2 HPR E DVDDS1 MCLK N.C. SDINS1 IRQ JACKSNS INB1 MIC1P/ DIGMICDATA INA2/ EXTMICN F DGND BCLKS2 LRCLKS2 SDA SCL REG MICBIAS DIGMICCLK INA1/ EXTMICP G SDOUTS2 DVDDS2 SDINS2 DVDD AVDD REF AGND MIC2N MIC2P MIC1N/ Maxim Integrated Products53 MAX98088 Stereo Audio Codec with FlexSound Technology Pin Description PIN NAME FUNCTION A1, B1 SPKRN A2, B2 SPKRGND Negative Right-Channel Class D Speaker Output Right-Speaker Ground A3, B3 SPKLVDD Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF and a 10FF capacitor. A4, B4 SPKLP Positive Left-Channel Class D Speaker Output A5, B5 SPKLN Negative Left-Channel Class D Speaker Output A6 RECP/LOUTL/ RXINP Positive Receiver Amplifier Output or Left Line Output. Can be positive bypass switch input when receiver amp is shut down. A7 PVDD Headphone Power Supply. Bypass to HPGND with 1FF and 10FF capacitors. A8 HPVSS Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor. A9 HPGND Headphone Ground B6 RECN/LOUTR/ RXINN B7 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. B8 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. Negative Receiver Amplifier Output or Right Line Output. Can be negative bypass switch input when receiver amp is shut down. B9 HPVDD Noninverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor. C1, C2 SPKRP Positive Right-Channel Class D Speaker Output C3, D3 SPKRVDD Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor. C4, C5 SPKLGND Left-Speaker Ground C6, C7, D5, D6, D7, E3 N.C. C8 HPSNS C9 HPL D1 BCLKS1 D2 SDOUTS1 S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1. D4 LRCLKS1 S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the IC is in slave mode and an output when in master mode. D8 INB2 Single-Ended Line Input B2. Also positive differential line input B. D9 HPR Right-Channel Headphone Output E1 DVDDS1 E2 MCLK E4 SDINS1 No Connection Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to ground. Left-Channel Headphone Output S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS1. S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz. S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to DVDDS1. Maxim Integrated Products54 MAX98088 Stereo Audio Codec with FlexSound Technology Pin Description (continued) PIN NAME FUNCTION E5 IRQ Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing. E6 JACKSNS E7 INB1 E8 MIC1P/ DIGMICDATA E9 INA2/ EXTMICN F1 DGND F2 BCLKS2 S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. F3 LRCLKS2 S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. F4 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing. F5 SCL I2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing. F6 REG Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor. F7 MICBIAS Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external 2.2kI resistor should be placed between MICBIAS and the microphone output. F8 MIC1N/ DIGMICCLK Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can be retasked as a digital microphone clock output. F9 INA1/ EXTMICP Single-Ended Line Input A1. Also negative differential line input A or positive differential external microphone input. G1 SDOUTS2 S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2. G2 DVDDS2 S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. G3 SDINS2 S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2. G4 DVDD Jack Sense. Detects the insertion of a jack. See the Jack Detection section. Single-Ended Line Input B1. Also negative differential line input B. Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can be retasked as a digital microphone data input. Single-Ended Line Input A2. Also positive differential line input A or negative differential external microphone input. Digital Ground Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a 1FF capacitor. G5 AVDD Analog Power Supply. Bypass to AGND with a 1FF capacitor. G6 REF Converter Reference. Bypass to AGND with a 2.2FF capacitor. G7 AGND Analog Ground G8 MIC2N Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor. G9 MIC2P Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor. Maxim Integrated Products55 MAX98088 Stereo Audio Codec with FlexSound Technology Detailed Description The MAX98088 is a fully integrated stereo audio codec with FlexSound technology and integrated amplifiers. Two differential microphone amplifiers can accept signals from three analog inputs. One input can be retasked to support two digital microphones. Any combination of two microphones (analog or digital) can be recorded simultaneously. The analog signals are amplified up to 50dB and recorded by the stereo ADC. The digital record path supports voice filtering with selectable preset highpass filters and high stopband attenuation at fS/2. An automatic gain control (AGC) circuit monitors the digitized signal and automatically adjusts the analog microphone gain to make best use of the ADC's dynamic range. A noise gate attenuates signals below the user-defined threshold to minimize the noise output by the ADC. The IC includes two analog line inputs. One of the line inputs can be optionally retasked as a third analog microphone input. Both line inputs support either stereo singleended input signals or mono differential signals. The line inputs are preamplified and then routed to the ADC for recording and/or to the output amplifiers for playback. The single-ended line input signals from INA1 and INA2 can bypass the PGAs, and be connected directly to the ADC input to provide the best dynamic range. Integrated analog switches allow two differential microphone signals to be routed out the third microphone input to an external device. This eliminates the need for an external analog switch in systems that have two devices recording signals from the same microphone. Through two digital audio interfaces, the device can transmit one stereo audio signal and receive two stereo audio signals in a wide range of formats including I2S, PCM, and up to four mono slots in TDM. Each interface can be connected to either of two audio ports (S1 and S2) for communication with external devices. Both audio interfaces support 8kHz to 96kHz sample rates. Each input signal is independently equalized using 5-band parametric equalizers. A multiband automatic level control (ALC) boosts signals by up to 12dB. One signal path additionally supports the same voiceband filtering as the ADC path. The IC includes a stereo Class D speaker amplifier, a high-efficiency Class H stereo headphone amplifier, and a differential receiver amplifier that can be configured as a stereo single-ended line output. When the receiver amplifier is disabled, analog switches allow RECP/RXINP and RECN/RXINN to be reused for signal routing. In systems where a single transducer is used for both the loudspeaker and receiver, an external receiver amplifier can be routed to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier, to connect to the loudspeaker. If the internal receiver amplifier is used, then leave RECP/ RXINP and RECN/RXINN unconnected. In systems where an external amplifier drives both the receiver and the MAX98088's line input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN. The stereo Class D amplifier provides efficient amplification for two speakers. The amplifier includes active emissions limiting to minimize the radiated emissions (EMI) traditionally associated with Class D. In most systems, no output filtering is required to meet standard EMI limits. To optimize speaker sound quality, the IC includes an excursion limiter, a distortion limiter, and a power limiter. The excursion limiter is a dynamic highpass filter with variable corner frequency that increases in response to high signal levels. Low-frequency energy typically causes more distortion than useful sound at high signal levels, so attenuating low frequencies allows the speaker to play louder without distortion or damage. At lower signal levels, the filter corner frequency reduces to pass more low frequency energy when the speaker can handle it. The distortion limiter reduces the volume when the output signal exceeds a preset distortion level. This ensures that regardless of input signal and battery voltage, excessive distortion is never heard by the user. The power limiter monitors the continuous power into the loudspeaker and lowers the signal level if the speaker is at risk of overheating. The stereo Class H headphone amplifier uses a dualmode charge pump to maximize efficiency while outputting a ground-referenced signal. This eliminates the need for DC-blocking capacitors or a midrail bias for the headphone jack ground return. Ground sense reduces output noise caused by ground return current. The IC integrates jack detection allowing the detection of insertion and removal of accessories. Maxim Integrated Products56 MAX98088 Stereo Audio Codec with FlexSound Technology I2C Slave Address Configure the MAX98088 using the I2C control bus. The IC uses a slave address of 0x20 or 00100000 for write operations and 0x21 or 00100001 for read operations. See the I2C Serial Interface section for a complete interface description. Registers Table 1 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00 to 0x03 and 0xFF are read-only while all of the other registers are read/ write. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Table 1. Register Map REGISTER STATUS Status B7 B6 B5 B4 B3 B2 B1 B0 CLD SLD ULK -- -- -- JDET -- Microphone AGC/NG NG AGC Jack Status -- JKSNS -- -- Battery Voltage -- -- -- Interrupt Enable ICLD ISLD IULK -- -- -- -- VBAT 0 ADDRESS DEFAULT R/W PAGE 0x00 -- R 111 0x01 -- R 70 0x02 -- R 110 0x03 -- R/W 110 0 0 IJDET 0 0x0F 0x00 R/W 111 0 0 0 0 0x10 0x00 R/W 81 0x11 0x00 R/W 81, 82 0x12 0x00 R/W 82 NI1[0] 0x13 0x00 R/W 82 WS1 0x14 0x00 R/W 76 0x15 0x00 R/W 77 DMONO1 HIZOFF1 SDOEN1 SDIEN1 0x16 0x00 R/W 77, 78 SLOTDLY1 0x17 0x00 R/W 78 0x18 0x00 R/W 86 MASTER CLOCK CONTROL Master Clock 0 0 PSCLK DAI1 CLOCK CONTROL Clock Mode Any Clock Control SR1 FREQ1 PLL1 NI1[14:8] NI1[7:1] DAI1 CONFIGURATION Format BCI1 DLY1 0 ADC_OSR1 DAC_ORS1 0 0 I/O Configuration SEL1 LTEN1 LBEN1 Time-Division Multiplex SLOTL1 Clock Filters MAS1 WCI1 SLOTR1 MODE1 AVFLT1 TDM1 FSW1 BSEL1 DHF1 DVFLT1 DAI2 CLOCK CONTROL Clock Mode Any Clock Control SR2 0 PLL2 0 0 0 0x19 0x00 R/W 81 0x1A 0x00 R/W 82 NI2[0] 0x1B 0x00 R/W 82 WS2 0x1C 0x00 R/W 76 0x1D 0x00 R/W 77 0x1E 0x00 R/W 77, 78 NI2[14:8] NI2[7:1] DAI2 CONFIGURATION Format Clock I/O Configuration MAS2 WCI2 BCI2 DLY2 0 0 DAC_ ORS2 0 0 0 LBEN2 0 SEL2 TDM2 FSW2 BSEL2 DMONO2 HIZOFF2 SDOEN2 SDIEN2 Maxim Integrated Products57 MAX98088 Stereo Audio Codec with FlexSound Technology Table 1. Register Map (continued) REGISTER Time-Division Multiplex Filters SRC Sample Rate Converter B7 B6 B5 SLOTL2 B4 B3 SLOTR2 B2 B1 B0 SLOTDLY2 ADDRESS DEFAULT R/W PAGE 0x1F 0x00 R/W 78 0 0 0 0 DHF2 0 0 DCB2 0x20 0x00 R/W 86 0 0 0 SRMIX_ MODE SRMIX_ ENL SRMIX_ ENR SRC_ ENL SRC_ ENR 0x21 0x00 R/W 85 0x22 0x00 R/W 92 MIXERS DAC Mixer MIXDAL MIXDAR Left ADC Mixer MIXADL 0x23 0x00 R/W 69 Right ADC Mixer MIXADR 0x24 0x00 R/W 69 Left Headphone Amplifier Mixer MIXHPL 0x25 0x00 R/W 105 Right Headphone Amplifier Mixer MIXHPR 0x26 0x00 R/W 105 0x27 0x00 R/W 105 Headphone Amplifier Mixer Control 0 0 MIXHPR_ MIXHPL_ PATHSEL PATHSEL MIXHPR_GAIN MIXHPL_GAIN Left Receiver Amplifier Mixer MIXRECL 0x28 0x00 R/W 94 Right Receiver Amplifier Mixer MIXRECR 0x29 0x00 R/W 94 0x2A 0x00 R/W 94 Receiver Amplifier Mixer Control LINE_ MODE 0 0 0 MIXRECR_GAIN MIXRECL_GAIN Left Speaker Amplifier Mixer MIXSPL 0x2B 0x00 R/W 97 Right Speaker Amplifier Mixer MIXSPR 0x2C 0x00 R/W 97 0x2D 0x00 R/W 97 Speaker Amplifier Mixer Control 0 0 0 0 MIXSPR_GAIN MIXSPL_GAIN Maxim Integrated Products58 MAX98088 Stereo Audio Codec with FlexSound Technology Table 1. Register Map (continued) REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE LEVEL CONTROL Sidetone DAI1 Playback Level DAI1 Playback Level DAI2 Playback Level DAI2 Playback Level Left ADC Level Right ADC Level Microphone 1 Input Level Microphone 2 Input Level INA Input Level INB Input Level DSTS 0 DVST DV1G 0x2E 0x00 R/W 74 DV1 0x2F 0x00 R/W 91 DV1M 0 0 0 0 EQCLP1 DVEQ1 0x30 0x00 R/W 90 DV2M 0 0 0 DV2 0x31 0x00 R/W 91 0 0 0 EQCLP2 DVEQ2 0x32 0x00 R/W 90 0 0 AVLG AVL 0x33 0x00 R/W 73 0 0 AVRG AVR 0x34 0x00 R/W 73 0 PA1EN PGAM1 0x35 0x00 R/W 66 0 PA2EN PGAM2 0x36 0x00 R/W 66 0 INAEXT 0 0 0 PGAINA 0x37 0x00 R/W 68 0 INBEXT 0 0 0 PGAINB 0x38 0x00 R/W 68 Left Headphone Amplifier Volume Control HPLM 0 0 HPVOLL 0x39 0x00 R/W 106 Right Headphone Amplifier Volume Control HPRM 0 0 HPVOLR 0x3A 0x00 R/W 106 Left Receiver Amplifier RECLM Volume Control 0 0 RECVOLL 0x3B 0x00 R/W 95 Right Receiver Amplifier Volume Control 0 0 RECVOLR 0x3C 0x00 R/W 95 RECRM Maxim Integrated Products59 MAX98088 Stereo Audio Codec with FlexSound Technology Table 1. Register Map (continued) REGISTER B7 B6 B5 0 0 SPVOLL 0x3D 0x00 R/W 98 0 0 SPVOLR 0x3E 0x00 R/W 98 0x3F 0x00 R/W 70, 71 0x40 0x00 R/W 71 0x41 0x00 R/W 100 100 Left Speaker Amplifier SPLM Volume Control Right Speaker Amplifier SPRM Volume Control MICROPHONE AGC Configuration AGCSRC B3 AGCRLS Threshold PWRTH Power Limiter Distortion Limiter CONFIGURATION PWRT2 0 0 INADIFF INBDIFF MICCLK Level Control VS2EN Bypass INABYP Switches B0 AGCHLD 0 0 DHPLCF DHPTH 0x42 0x00 R/W ALCMB ALCTH 0x43 0x00 R/W 89, 100 PWRK 0x44 0x00 R/W 101 0x45 0x00 R/W 102 PWRT1 0 DIGMICL DIGMICR ADDRESS DEFAULT R/W PAGE 0 0 THDCLP Microphone B1 AGCTH Power Limiter Audio Input B2 AGCATK ANTH SPEAKER SIGNAL PROCESSING Excursion 0 DHPUCF Limiter Filter Excursion Limiter 0 0 0 Threshold ALC ALCEN ALCRLS Jack Detection B4 0 0 0 THDT1 0x46 0x00 R/W 103 0 0 0 0 0x47 0x00 R/W 68 0 0 0x48 0x00 R/W 66 EQ1EN 0x49 0x00 R/W 90, 108 EXTMIC VSEN ZDEN 0 0 0 0 0 MIC2BYP 0 0 RECBYP SPKBYP 0x4A 0x00 R/W 67, 107 0 0 0 0 0 JDEB 0x4B 0x00 R/W 110 INAEN INBEN 0 0 MBEN 0 HPLEN HPREN SPLEN SPREN BGEN SPREGEN VCMEN BIASEN JDETEN EQ2EN POWER MANAGEMENT Input Enable Output Enable Top-Level Bias Control DAC Low Power Mode 1 DAC Low Power Mode 2 System Shutdown DAI2_DAC_LP ADLEN ADREN 0x4C 0x00 R/W 63 RECLEN RECREN DALEN DAREN 0x4D 0x00 R/W 64 0 0x4E 0xF0 R/W 64 DAI1_DAC_LP 0x4F 0x00 R/W 83 0 0 0 0 0 0 0 DAC2_IP_ DAC1_IP_ CGM2_ CGM1_ DITH_EN DITH_EN EN EN 0x50 0x0F R/W 83 SHDN VBATEN 0 0 PERFMODE HPPLYBACK PWRSV8K PWRSV 0x51 0x00 R/W 63, 100 Maxim Integrated Products60 MAX98088 Stereo Audio Codec with FlexSound Technology Table 1. Register Map (continued) REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE DSP COEFFICIENTS EQ Band 1 (DAI1/DAI2) EQ Band 2 (DAI1/DAI2) EQ Band 3 (DAI1/DAI2) EQ Band 4 (DAI1/DAI2) K_1[15:8] 0x52/0x84 0xXX R/W 89 K_1[7:0] 0x53/0x85 0xXX R/W 89 K1_1[15:8] 0x54/0x86 0xXX R/W 89 K1_1[7:0] 0x55/0x87 0xXX R/W 89 K2_1[15:8] 0x56/0x88 0xXX R/W 89 K2_1[7:0] 0x57/0x89 0xXX R/W 89 c1_1[15:8] 0x58/0x8A 0xXX R/W 89 c1_1[7:0] 0x59/0x8B 0xXX R/W 89 c2_1[15:8] 0x5A/0x8C 0xXX R/W 89 c2_1[7:0] 0x5B/0x8D 0xXX R/W 89 K_2[15:8] 0x5C/0x8E 0xXX R/W 89 K_2[7:0] 0x5D/0x8F 0xXX R/W 89 K1_2[15:8] 0x5E/0x90 0xXX R/W 89 K1_2[7:0] 0x5F/0x91 0xXX R/W 89 K2_2[15:8] 0x60/0x92 0xXX R/W 89 K2_2[7:0] 0x61/0x93 0xXX R/W 89 c1_2[15:8] 0x62/0x94 0xXX R/W 89 c1_2[7:0] 0x63/0x95 0xXX R/W 89 c2_2[15:8] 0x64/0x96 0xXX R/W 89 c2_2[7:0] 0x65/0x97 0xXX R/W 89 K_3[15:8] 0x66/0x98 0xXX R/W 89 K_3[7:0] 0x67/0x99 0xXX R/W 89 K1_3[15:8] 0x68/0x9A 0xXX R/W 89 K1_3[7:0] 0x69/0x9B 0xXX R/W 89 K2_3[15:8] 0x6A/0x9C 0xXX R/W 89 K2_3[7:0] 0x6B/0x9D 0xXX R/W 89 c1_3[15:8] 0x6C/0x9E 0xXX R/W 89 c1_3[7:0] 0x6D/0x9F 0xXX R/W 89 c2_3[15:8] 0x6E/0xAE 0xXX R/W 89 c2_3[7:0] 0x6F/0xA1 0xXX R/W 89 K_4[15:8] 0x70/0xA2 0xXX R/W 89 K_4[7:0] 0x71/0xA3 0xXX R/W 89 K1_4[15:8] 0x72/0xA4 0xXX R/W 89 K1_4[7:0] 0x73/0xA5 0xXX R/W 89 K2_4[15:8] 0x74/0xA6 0xXX R/W 89 K2_4[7:0] 0x75/0xA7 0xXX R/W 89 c1_4[15:8] 0x76/0xA8 0xXX R/W 89 c1_4[7:0] 0x77/0xA9 0xXX R/W 89 c2_4[15:8] 0x78/0xAA 0xXX R/W 89 c2_4[7:0] 0x79/0xAB 0xXX R/W 89 Maxim Integrated Products61 MAX98088 Stereo Audio Codec with FlexSound Technology Table 1. Register Map (continued) REGISTER EQ Band 5 (DAI1/DAI2) Excursion Limiter Biquad (DAI1/DAI2) B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE K_5[15:8] 0x7A/0xAC 0xXX R/W 89 K_5[7:0] 0x7B/0xAD 0xXX R/W 89 K1_5[15:8] 0x7C/0xAE 0xXX R/W 89 K1_5[7:0] 0x7D/0xAF 0xXX R/W 89 K2_5[15:8] 0x7E/0xB0 0xXX R/W 89 K2_5[7:0] 0x7F/0xB1 0xXX R/W 89 c1_5[15:8] 0x80/0xB2 0xXX R/W 89 c1_5[7:0] 0x81/0xB3 0xXX R/W 89 c2_5[15:8] 0x82/0xB4 0xXX R/W 89 c2_5[7:0] 0x83/0xB5 0xXX R/W 89 a1[15:8] 0xB6/0xC0 0xXX R/W 89 a1[7:0] 0xB7/0xC1 0xXX R/W 89 a2[15:8] 0xB8/0xC2 0xXX R/W 89 a2[7:0] 0xB9/0xC3 0xXX R/W 89 b0[15:8] 0xBA/0xC4 0xXX R/W 89 b0[7:0] 0xBB/0xC5 0xXX R/W 89 b1[15:8] 0xBC/0xC6 0xXX R/W 89 b1[7:0] 0xBD/0xC7 0xXX R/W 89 b2[15:8] 0xBE/0xC8 0xXX R/W 89 b2[7:0] 0xBF/0xC9 0xXX R/W 89 REV 0xFF 0x40 R 112 REVISION ID Rev ID Maxim Integrated Products62 MAX98088 Stereo Audio Codec with FlexSound Technology Power Management The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply current. Table 2. Power Management Registers REGISTER 0x51 BIT NAME DESCRIPTION 7 SHDN Global Shutdown. Disables everything except the headset detection circuitry, which is controlled separately. 0 = Device shutdown 1 = Device enabled 6 VBATEN 3 PERFMODE Performance Mode. Selects DAC to headphone playback performance mode. 0 = High performance playback mode. 1 = Low power playback mode. HPPLYBCK Headphone Only Playback Mode. Configures System Bias Control register bits for low power playback when using DAC to headphone playback path only. When enabled, this bit overrides the System Bias Control register settings. When disabled, the System Bias Control register is used to enable system bias blocks. Set both HPPLYBCK and PERFMODE for lowest power consumption when using DAC to headphone playback path only. 0 = Disabled 1 = Enabled PWRSV8K 8kHz Power Save Mode. PWRSV8K configures the ADC for reduced power consumption when fS = 8kHz. PWRSV8K can be used in conjunction with PWRSV when fS = 8kHz for more power savings. 0 = Normal, high-performance mode. 1 = Low power mode. 0 PWRSV Power Save Mode. PWRSV configures the ADC for reduced power consumption for all sample rates. PWRSV can be used in conjunction with PWRSV8K for more power savings. 0 = Normal, high-performance mode. 1 = Low power mode. 7 INAEN Line Input A Enable 0 = Disabled 1 = Enabled 6 INBEN Line Input B Enable 0 = Disabled 1 = Enabled 3 MBEN Microphone Bias Enable 0 = Disabled 1 = Enabled 1 ADLEN Left ADC Enable 0 = Disabled 1 = Enabled 0 ADREN Right ADC Enable 0 = Disabled 1 = Enabled 2 1 0x4C See the Battery Measurement section. Maxim Integrated Products63 MAX98088 Stereo Audio Codec with FlexSound Technology Table 2. Power Management Registers (continued) REGISTER BIT NAME 7 HPLEN Left Headphone Enable 0 = Disabled 1 = Enabled 6 HPREN Right Headphone Enable 0 = Disabled 1 = Enabled 5 SPLEN Left Speaker Enable 0 = Disabled 1 = Enabled 4 SPREN Right Speaker Enable 0 = Disabled 1 = Enabled 0x4D DESCRIPTION 3 RECLEN Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output or left line output. 0 = Disabled 1 = Enabled 2 RECREN Right Line Output Enable. Use this bit to enable the right line output. 0 = Disabled 1 = Enabled 1 DALEN Left DAC Enable 0 = Disabled 1 = Enabled 0 DAREN Right DAC Enable 0 = Disabled 1 = Enabled 7 6 BGEN SPREGEN 0x4E Bandgap Enable. Must be enabled for proper operation of 2.5V regulator and associated circuitry. 0 = Disabled 1 = Enabled 2.5V Regulator Enable. SPREGEN enables a 2.5V internal regulator required for the ADC, speaker and receiver/line out amplifier. The 2.5V regulator is powered by SPKLVDD. 0 = Disabled 1 = Enabled 5 VCMEN Common-Mode Voltage Resistor String Enable. VCMEN enables the common mode voltage for the input and output amplifiers in the codec. 0 = Disabled 1 = Enabled 4 BIASEN Chip Bias Enable. BIASEN needs to be set for the codec amplifiers to be enabled. 0 = Disabled 1 = Enabled Maxim Integrated Products64 MAX98088 Stereo Audio Codec with FlexSound Technology Microphone Inputs In systems where the codec is not the only device recording microphone signals, connect microphones to MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N then become outputs that route the microphone signals to an external device as needed. Two devices can then record microphone signals without needing external analog switches. In the typical application, one microphone input is used for the handset microphone and the other is used as an accessory microphone. In systems using a background noise microphone, INA can be retasked as another microphone input. Analog microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable-gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. To maximize the signalto-noise ratio, use the gain in the first stage whenever possible. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes. The device includes three differential microphone inputs and a low-noise microphone bias for powering the microphones (Figure 6). One microphone input can also be configured as a digital microphone input accepting signals from up to two digital microphones. Any two microphones, analog or digital, can be recorded simultaneously. MCLK MICBIAS REG MBEN CLOCK CONTROL MIC1P/ DIGMICDATA PGAM1: +20dB TO 0dB MIC1N/ DIGMICCLK AGC CONTROL EXTMIC PA1EN: 0/20/30dB MIC2BYP MIC2P MIX ADLEN ADCL MIC2N EXTMIC PA2EN: 0/20/30dB PGAM1: +20dB TO 0dB MIXADL INABYP MIX PGAINA: +20dB TO -6dB INA1/EXTMICP ADCR INADIFF ADREN MIXADR INA2/EXTMICN PGAINA: +20dB TO -6dB Figure 6. Microphone Input Block Diagram Maxim Integrated Products65 MAX98088 Stereo Audio Codec with FlexSound Technology Table 3. Microphone Input Registers REGISTER BIT NAME 6 PA1EN/PA2EN 5 3 0x35/0x36 PGAM1/PGAM2 1 0 7 MICCLK 6 5 GAIN (dB) VALUE GAIN (dB) 0x00 0x01 +20 0x0B +9 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1F 0 0x0A +10 Digital Microphone Clock Frequency Select a frequency that is within the digital microphone's clock frequency range. Set OSR1 = 1 when using a digital microphone. 00 = PCLK/8 01 = PCLK/6 10 = 64 x LRCLK 11 = Reserved DIGMICL DIGMICR Right Digital Microphone Enable Set PA1EN = 00 for proper operation. 0 = Disabled 1 = Enabled 1 EXTMIC 0 VALUE Left Digital Microphone Enable Set PA1EN = 00 for proper operation. 0 = Disabled 1 = Enabled 0x48 4 MIC1/MIC2 Preamplifier Gain Course microphone gain adjustment. 00 = Preamplifier disabled 01 = 0dB 10 = 20dB 11 = 30dB MIC1/MIC2 PGA Fine microphone gain adjustment. 4 2 DESCRIPTION External Microphone Connection Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using INA_/EXTMIC_ as a microphone input. 00 = Disabled 01 = MIC1 input 10 = MIC2 input 11 = Reserved Maxim Integrated Products66 MAX98088 Stereo Audio Codec with FlexSound Technology Table 3. Microphone Input Registers (continued) REGISTER BIT NAME 7 INABYP 4 MIC2BYP 1 RECBYP 0x4A DESCRIPTION INA_/EXTMIC_ to MIC1_ Bypass Switch 0 = Disabled 1 = Enabled MIC1_ to MIC2_ Bypass Switch 0 = Disabled 1 = Enabled See the Output Bypass Switches section. 0 SPKBYP Line Inputs The device includes two sets of line inputs (Figure 7). Each set can be configured as a stereo single-ended input or as a mono differential input. Each input includes adjustable gain to match a wide range of input signal levels. If a custom gain is needed, the external gain mode provides a trimmed feedback resistor. Set the gain by choosing the appropriate input resistor and using the following formula: AVPGAIN = 20 x log (20kI/RIN) The external gain mode also allows summing multiple signals into a single input, by connecting multiple input resistors as show in Figure 8, and/or inputting signals larger than 1VP-P by adjusting the ratio of the 20kI/RIN less than 1. INABYP INA1/ EXTMICP PGAINA: +20dB TO -6dB INADIFF INA2/ EXTMICN PGAINA: +20dB TO -6dB LEFT INPUT 1 LEFT INPUT 2 PGAINB: +20dB TO -6dB 20kI VCM RIGHT INPUT 1 INB1 INBDIFF RIGHT INPUT 2 1VP-P(max) INA1/EXTMICP 20kI INA2/EXTMICN 1VP-P(max) VCM PGAINB: +20dB TO -6dB INB2 Figure 7. Line Input Block Diagram Figure 8. Summing Multiple Input Signals into INA/INB Maxim Integrated Products67 MAX98088 Stereo Audio Codec with FlexSound Technology Table 4. Line Input Registers REGISTER BIT 6 0x37/0x38 NAME DESCRIPTION INAEXT/INBEXT 2 1 PGAINA/PGAINB 0 7 INADIFF 6 INBDIFF 0x47 Line Input A/B External Gain Switches out the internal input resistor and selects a trimmed 20kI feedback resistor. Use an external input resistor to set the gain of the line input. 0 = Disabled 1 = Enabled Line Input A/B Internal Gain Settings 000 = +20dB 001 = +14dB 010 = +3dB 011 = 0dB 100 = -3dB 101 = -6dB 110 = -6dB 111 = -6dB Line Input A Differential Enable 0 = Stereo single-ended input 1 = Mono differential input Line Input B Differential Enable 0 = Stereo single-ended input 1 = Mono differential input ADC Input Mixers The IC's stereo ADC accepts input from the microphone amplifiers, line inputs amplifiers, and directly from the INA1 and INA2. The ADC mixer routes any combination of the eight audio inputs to the left and right ADCs (Figure 9). PGAM1: +20dB TO 0dB PA1EN: 0/20/30dB PGAM2: +20dB TO 0dB MIX ADCL MIXADL PA2EN: 0/20/30dB MIX INADIFF ADCR ADREN PGAINA: +20dB TO -6dB + ADLEN MIXADR PGAINA: +20dB TO -6dB PGAINB: +20dB TO -6dB INBDIFF + PGAINB: +20dB TO -6dB Figure 9. ADC Input Mixer Block Diagram Maxim Integrated Products68 MAX98088 Stereo Audio Codec with FlexSound Technology Table 5. ADC Input Mixer Register REGISTER BIT NAME DESCRIPTION 7 Left/Right ADC Input Mixer Selects which analog inputs are recorded by the left/right ADC. 1xxxxxxx = MIC1 x1xxxxxx = MIC2 xx1xxxxx = INA1 pin direct xxx1xxxx = INA2 pin direct xxxx1xxx = INA1 xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) 6 5 0x23/0x24 4 3 MIXADL/MIXADR 2 1 0 Record Path Signal Processing The device's record signal path includes both automatic gain control (AGC) for the microphone inputs and a digital noise gate at the output of the ADC (Figure 10). Microphone AGC The IC's AGC monitors the signal level at the output of the ADC and then adjusts the MIC1 and MIC2 analog PGA settings automatically. When the signal level is below the predefined threshold, the gain is increased up to its maximum (20dB). If the signal exceeds the threshold, the gain is reduced to prevent the output signal level exceeding the threshold. When AGC is enabled, the microphone PGA is not user programmable. The AGC provides a more constant signal level and improves the available ADC dynamic range. Noise Gate Since the AGC increases the levels of all signals below a user-defined threshold, the noise floor is effectively increased by 20dB. To counteract this, the noise gate reduces the gain at low signal levels. Unlike typical noise gates that completely silence the output below a defined level, the noise gate in the IC applies downward expansion. The noise gate attenuates the output at a rate of 1dB for each 2dB the signal is below the threshold with a maximum attenuation of 12dB. The noise gate can be used in conjunction with the AGC or on its own. When the AGC is enabled, the noise gate reduces the output level only when the AGC has set the gain to the maximum setting. Figure 11 shows the gain response resulting from using the AGC and noise gate. AGC AND NOISE GATE AMPLITUDE RESPONSE 0 PGAM1: +20dB TO -6dB AUTOMATIC GAIN CONTROL PA2EN: 0/20/30dB PGAM2: +20dB TO 0dB AGC ONLY NOISE GATE MIX ADCL ADLEN MIXADL -20 MODE1 AVFLT AUDIO/ VOICE FILTERS AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB SAMPLE RATE CONVERTER OUTPUT AMPLITUDE (dBFS) PA1EN: 0/20/30dB AGC AND NOISE GATE -40 -60 AGC AND NOISE GATE DISABLED -80 NOISE GATE ONLY MIX ADCR ADREN MIXADR -100 -120 -120 -100 -80 -60 -40 -20 0 INPUT AMPLITUDE (dBFS) Figure 10. Record Path Signal Processing Block Diagram Figure 11. AGC and Noise Gate Input vs. Output Gain Maxim Integrated Products69 MAX98088 Stereo Audio Codec with FlexSound Technology Table 6. Record Path Signal Processing Registers REGISTER BIT NAME 7 6 NG 5 AGC Gain Reports the current AGC gain setting. 4 0x01 3 2 AGC 1 0 7 GAIN (dB) VALUE GAIN (dB) 0x00 +20 0x0B +9 0x01 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1F 0 0x0A +10 AGCSRC AGCRLS AGC Release Time Defined as the duration from start to finish of gain increase in the region shown in Figure 12. 000 = 78ms 001 = 156ms 010 = 312ms 011 = 625ms 100 = 1.25s 101 = 2.5s 110 = 5s 111 = 10s 0x3F 4 VALUE AGC/Noise Gate Signal Source Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on both channels regardless of the AGCSRC setting. 0 = Left ADC output 1 = Maximum of either the left or right ADC output 6 5 DESCRIPTION Noise Gate Attenuation Reports the current noise gate attenuation. 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB to 5dB 100 = 6dB to 7dB 101 = 8dB to 9dB 110 = 10dB to 11dB 111 = 12dB Maxim Integrated Products70 MAX98088 Stereo Audio Codec with FlexSound Technology Table 6. Record Path Signal Processing Registers (continued) REGISTER BIT NAME DESCRIPTION AGCATK AGC Attack Time Defined as the time required to reduce gain by 63% of the total gain reduction (one time constant of the exponential response). Attack times are longer for low AGC threshold levels. See Figure 12 for details. 00 = 2ms 01 = 7.2ms 10 = 31ms 11 = 123ms 3 2 0x3F 1 AGCHLD 0 Noise Gate Threshold Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative to the ADC's full-scale output voltage. 7 6 ANTH 5 4 0x40 2 AGCTH 0 VALUE THRESHOLD (dBFS) VALUE THRESHOLD (dBFS) 0x0 Noise gate disabled 0x8 -45 0x1 Reserved 0x9 -41 0x2 Reserved 0xA -38 0x3 -64 0xB -34 0x4 -62 0xC -30 0x5 -58 0xD -27 0x6 -53 0xE -22 0x7 -50 0xF -16 AGC Threshold Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds are relative to the ADC's full-scale voltage. 3 1 AGC Hold Time The delay before the AGC release begins. The hold time counter starts whenever the signal drops below the AGC threshold and is reset by any signal that exceeds the threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details. 00 = AGC disabled 01 = 50ms 10 = 100ms 11 = 400ms VALUE THRESHOLD (dBFS) VALUE THRESHOLD (dBFS) 0x0 -3 0x8 -11 0x1 -4 0x9 -12 0x2 -5 0xA -13 0x3 -6 0xB -14 0x4 -7 0xC -15 0x5 -8 0xD -16 0x6 -9 0xE -17 0x7 -10 0xF -18 Maxim Integrated Products71 MAX98088 Stereo Audio Codec with FlexSound Technology ATTACK TIME HOLD TIME RELEASE TIME Figure 12. AGC Timing ADC Record Level Control the digital level control to 0dB whenever possible. Digital level control is primarily used when adjusting the record level for digital microphones. The IC includes separate digital level control for the left and right ADC outputs (Figure 13). To optimize dynamic range, use analog gain to adjust the signal level and set NOISE GATE AUTOMATIC GAIN CONTROL ADCL ADLEN MODE1 AVFLT AUDIO/ VOICE FILTERS AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB SAMPLE RATE CONVERTER ADCR ADREN Figure 13. ADC Record Level Control Block Diagram Maxim Integrated Products72 MAX98088 Stereo Audio Codec with FlexSound Technology Table 7. ADC Record Level Control Register REGISTER BIT NAME DESCRIPTION Left/Right ADC Gain 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB 5 AVLG/AVRG 4 Left/Right ADC Level 3 0x33/0x34 VALUE GAIN (dB) VALUE GAIN (dB) 0x0 +3 0x8 -5 0x1 +2 0x9 -6 0x2 +1 0xA -7 -8 2 AVL/AVR 1 0 0x3 0 0xB 0x4 -1 0xC -9 0x5 -2 0xD -10 0x6 -3 0xE -11 0x7 -4 0xF -12 speak, providing a more natural user experience. The IC implements sidetone digitally. Doing so helps prevent unwanted feedback into the playback signal path and better matches the playback audio signal. Sidetone Enable sidetone during full-duplex operation to add a low-level copy of the recorded audio signal to the playback audio signal (Figure 14). Sidetone is commonly used in telephony to allow the speaker to hear himself DV1G: 0/6/12/18dB DVST: 0dB TO -60dB SIDETONE + MIX DSTS MULTI BAND ALC DVEQ1: 0dB TO -15dB AUTOMATIC GAIN CONTROL NOISE GATE MODE1 AVFLT ADLEN ADCL ADCR ADREN 5-BAND PARAMETRIC EQ EQ1EN AUDIO/ VOICE FILTERS AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB EQ2EN EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB DV2: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 SAMPLE RATE CONVERTER DV1: 0dB TO -15dB AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 14. Sidetone Block Diagram Maxim Integrated Products73 MAX98088 Stereo Audio Codec with FlexSound Technology Table 8. Sidetone Register REGISTER BIT NAME 7 DSTS 6 Sidetone Level Adjusts the sidetone signal level. All levels are referenced to the ADC's full-scale output. 4 3 0x2E 2 1 0 DESCRIPTION Sidetone Source Selects which ADC output is fed back as sidetone. When mixing the left and right ADC outputs, each is attenuated by 6dB to prevent full-scale signals from clipping. 00 = Sidetone disabled 01 = Left ADC 10 = Right ADC 11 = Left + Right ADC DVST VALUE LEVEL (dB) VALUE LEVEL (dB) 0x00 Sidetone disabled 0x10 -30.5 0x01 -0.5 0x11 -32.5 0x02 -2.5 0x12 -34.5 0x03 -4.5 0x13 -36.5 0x04 -6.5 0x14 -38.5 0x05 -8.5 0x15 -40.5 0x06 -10.5 0x16 -42.5 0x07 -12.5 0x17 -44.5 0x08 -14.5 0x18 -46.5 0x09 -16.5 0x19 -48.5 0x0A -18.5 0x1A -50.5 0x0B -20.5 0x1B -52.5 0x0C -22.5 0x1C -54.5 0x0D -24.5 0x1D -56.6 0x0E -26.5 0x1E -58.5 0x0F -28.5 0x1F -60.5 Digital Audio Interfaces The IC includes two separate playback signal paths and one record signal path. Digital audio interface 1 (DAI1) is used to transmit the recorded stereo audio signal and receive a stereo audio signal for playback. Digital audio interface 2 (DAI2) is used to receive a second stereo audio signal. Use DAI1 for all full-duplex operations and for all voice signals. Use DAI2 for music and to mix two playback audio signals. The digital audio interfaces are separate from the audio ports to enable either interface to communicate with any external device connected to either audio port. Each audio interface can be configured in a variety of formats including left justified, I2S, PCM, and time division multiplexed (TDM). TDM mode supports up to 4 mono audio slots in each frame. The IC can use up to 2 mono slots per interface, leaving the remaining two slots available for another device. Table 9 shows how to configure the device for common digital audio formats. Figures 16 and 17 show examples of common audio formats. By default, SDOUTS1 and SDOUTS2 are set high impedance when the IC is not outputting data to facilitate sharing the bus. Configure the interface in TDM mode using only slot 1 to transmit and receive mono PCM voice data. The IC's digital audio interfaces support both ADC to DAC loop-through and digital loopback. Loop-through allows the signal converted by the ADC to be routed to the DAC for playback. The signal is routed from the record path to the playback path in the digital audio interface to allow the IC's full complement of digital signal processing to be used. Loopback allows digital data input to either SDINS1 or SDINS2 to be routed from one interface to the Maxim Integrated Products74 MAX98088 Stereo Audio Codec with FlexSound Technology other for output on SDOUTS2 or SDOUTS1. Both interfaces must be configured for the same sample rate, but the interface format need not be the same. This allows LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 SDOUTS2 SDINS2 DVDDS2 DAI1 SDIN2 SDOUT2 BCLK2 SDIN1 SDOUT1 LRCLK1 SEL2 BCLK1 SEL1 LRCLKS2 LRCLK2 BCLKS1 the IC to route audio data from one device to another, converting the data format as needed. Figure 15 shows the available digital signal routing options. DAI2 MAS1 MAS1 BIT CLOCK FRAME CLOCK HIZOFF1 SDOEN1 DATA OUTPUT SDIEN1 MAS2 DATA INPUT HIZOFF2 SDOEN2 MAS2 BIT CLOCK FRAME CLOCK DATA OUTPUT SDIEN2 DATA INPUT LBEN1 LBEN2 MUX + LTEN1 DAI1 RECORD PATH DAI1 PLAYBACK PATH DAI2 PLAYBACK PATH Figure 15. Digital Audio Signal Routing Table 9. Common Digital Audio Formats MODE WCI1/WCI2 BCI1/BCI2 DLY1/DLY2 TDM1/TDM2 Left Justified 1 0 0 0 SLOTL1/SLOTL2 SLOTR1/SLOTR2 X X I2S 0 0 1 0 X X PCM X 1 X 1 0 0 TDM X 1 X 1 Set as desired Maxim Integrated Products75 MAX98088 Stereo Audio Codec with FlexSound Technology Table 10. Digital Audio Interface Registers REGISTER BIT 7 6 5 NAME MAS1/MAS2 DAI1/DAI2 Master Mode In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2 accept LRCLK and BCLK as inputs. 0 = Slave mode 1 = Master mode WCI1/WCI2 DAI1/DAI2 Word Clock Invert TDM1/TDM2 = 0: 0 = Left-channel data is transmitted while LRCLK is low. 1 = Right-channel data is transmitted while LRCLK is low. TDM1/TDM2 = 1: Always set WCI = 0. BCI1/BCI2 DAI1/DAI2 Bit Clock Invert BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1. 0 = SDIN is accepted on the rising edge of BCLK. SDOUT is valid on the rising edge of BCLK. 1 = SDIN is accepted on the falling edge of BCLK. SDOUT is valid on the falling edge of BCLK. Master Mode: 0 = LRCLK transitions on the falling edge of BCLK. 1 = LRCLK transitions on the rising edge of BCLK. DLY1/DLY2 DAI1/DAI2 Data Delay DLY1/DLY2 has no effect when TDM1/TDM2 = 1. 0 = The most significant data bit is clocked on the first active BCLK edge after an LRCLK transition. 1 = The most significant data bit is clocked on the second active BCLK edge after an LRCLK transition. TDM1/TDM2 DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode) Set TDM1/TDM2 when communicating with devices that use a frame synchronization pulse on LRCLK instead of a square wave. 0 = Disabled 1 = Enabled (BCI1/BCI2 must be set to 1) FSW1/FSW2 DAI1/DAI2 Wide Frame Sync Pulse Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 = 1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0. 0 = Disabled 1 = Enabled 0x14/0x1C 4 2 1 0 DESCRIPTION WS1/WS2 DAI1/DAI2 Audio Data Bit Depth Determines the maximum bit depth of audio being transmitted and received. Data is always 16 bit when TDM1/TMD2 = 0. 0 = 16 bits 1 = 24 bits Maxim Integrated Products76 MAX98088 Stereo Audio Codec with FlexSound Technology Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME 7 OSR1 6 5 DAC_OSR1/ DAC_OSR2 DAC Oversample Clock. Select PCLK/2 for higher performance. Select PCLK/4 for lower consumption. 1 = DAC input clock = PCLK/2 0 = DAC input clock = PCLK/4 BSEL1/ BSEL2 DAI1/DAI2 BCLK Output Frequency When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK frequency that clocks all data input to the DAC and output by the ADC. 000 = BCLK disabled 001 = 64 x LRCLK 010 = 48 x LRCLK 011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1) 100 = PCLK/2 101 = PCLK/4 110 = PCLK/8 111 = PCLK/16 0x15/0x1D 2 1 0 7 SEL1/SEL2 6 5 3 DAI1/DAI2 Audio Port Selector Selects which port is used by DAI1/DAI2. 00 = None 01 = Port S1 10 = Port S2 11 = Reserved LTEN1 DAI1 Digital Loopthrough Connects the output of the record signal path to the input of the playback path. Data input to DAI1 from an external device is mixed with the recorded audio signal. 0 = Disabled 1 = Enabled LBEN1/ LBEN2 DAI1/DAI2 Digital Audio Interface Loopback LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC output data. 0 = Disabled 1 = Enabled DMONO1/ DMONO2 DAI1/DAI2 DAC Mono Mix Mixes the left and right digital input to mono and routes the combined signal to the left and right playback paths. The left and right input data is attenuated by 6dB prior to the mono mix. 0 = Disabled 1 = Enabled 0x16/0x1E 4 DESCRIPTION ADC Oversampling Ratio Use the higher setting for maximum performance. Use the lower setting for reduced power consumption at the expense of performance. 00 = 96x 01 = 64x 10 = Reserved 11 = Reserved Maxim Integrated Products77 MAX98088 Stereo Audio Codec with FlexSound Technology Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME DESCRIPTION 2 HIZOFF1/ HIZOFF2 Disable DA1/DAI2 Output High-Impedance Mode Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to force a level on SDOUT at all times. 0 = Disabled 1 = Enabled 1 SDOEN1/ SDOEN2 DAI1/DAI2 Record Path Output Enable DAI2 outputs data only if LBEN1 = 1. 0 = Disabled 1 = Enabled 0 SDIEN1/ SDIEN2 DAI1/DAI2 Playback Path Input Enable 0 = Disabled 1 = Enabled 0x16/0x1E 7 SLOTL1/ SLOTL2 6 5 SLOTR1/ SLOTR2 0x17/0x1F 4 3 2 1 0 SLOTDLY1/ SLOTDLY2 TDM Left Time Slot Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Right Time Slot Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Slot Delay Adds 1 BCLK cycle delay to the data in the specified TDM slot. 1xxx = Slot 4 delayed x1xx = Slot 3 delayed xx1x = Slot 2 delayed xxx1 = Slot 1 delayed Maxim Integrated Products78 MAX98088 Stereo Audio Codec with FlexSound Technology WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT RIGHT LEFT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT LEFT RIGHT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT RIGHT LEFT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT LEFT RIGHT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN Figure 16. Non-TDM Data Format Examples Maxim Integrated Products79 MAX98088 Stereo Audio Codec with FlexSound Technology WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 BCLK SDIN WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3 LRCLK HI-Z SDOUT 32 CYCLES L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK 16 CYCLES SDOUT 16 CYCLES 16 CYCLES HI-Z L L L L L L L L R R R R R R R R HI-Z L L L L L L L L R R R R R R R R 16 CYCLES HI-Z BCLK SDIN Figure 17. TDM Mode Data Format Examples Maxim Integrated Products80 MAX98088 Stereo Audio Codec with FlexSound Technology Clock Control The digital signal paths in the IC require a master clock (MCLK) between 10MHz and 60MHz to function. The MAX98088 requires an internal clock between 10MHz and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to create the internal clock (PCLK). PCLK is used to clock all portions of the IC. The MAX98088 includes two digital audio signal paths, both capable of supporting any sample rate from 8kHz to 96kHz. Each path is independently configured to allow different sample rates. To accommodate a wide range of system architectures, four main clocking modes are supported: U PLL Mode: When operating in slave mode, enable the PLL to lock onto any LRCLK input. This mode requires the least configuration, but provides the lowest performance. Use this mode to simplify initial setup or when normal mode and exact integer mode cannot be used. U Normal Mode: This mode uses a 15-bit clock divider to set the sample rate relative to PCLK. This allows high flexibility in both the PCLK and LRCLK frequencies and can be used in either master or slave mode. U Exact Integer Mode (DAI1 only): In both master and slave modes, common MCLK frequencies (12MHz, 13MHz, 16MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates. In these modes, the MCLK and LRCLK rates are selected by using the FREQ1 bits instead of the NI, and PLL control bits. U DAC Low-Power Mode: This mode bypasses the PLL for reduce power consumptions and uses fixed counters to generate the clocks. The DAI__DAC_LP bits override the other clock settings. Table 11. Clock Control Registers REGISTER BIT NAME 5 0x10 PSCLK 4 6 SR1/SR2 5 4 MCLK Prescaler Generates PCLK, which is used by all 00 = PCLK disabled 01 = 10MHz P MCLK P 20MHz (PCLK 10 = 20MHz P MCLK P 40MHz (PCLK 11 = 40MHz P MCLK P 60MHz (PCLK internal circuitry. = MCLK) = MCLK/2) = MCLK/4) DAI1/DAI2 Sample Rate Used by the ALC to correctly set the dual-band crossover frequency and the excursion limiter to set the predefined corner frequencies. 7 0x11/0x19 DESCRIPTION VALUE SAMPLE RATE (kHz) VALUE SAMPLE RATE (kHz) 0x0 Reserved 0x8 48 88.2 0x1 8 0x9 0x2 11.025 0xA 96 0x3 16 0xB Reserved 0x4 22.05 0xC Reserved 0x5 24 0xD Reserved 0x6 32 0xE Reserved 0x7 44.1 0xF Reserved Maxim Integrated Products81 MAX98088 Stereo Audio Codec with FlexSound Technology Table 11. Clock Control Registers (continued) REGISTER BIT NAME DESCRIPTION Exact Integer Mode Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio. 3 0x11 2 FREQ1 1 7 0x12/0x1A PLL1/PLL2 6 4 3 2 1 7 SAMPLE RATE VALUE 0x0 Disabled 0x8 0x1 Reserved 0x9 0x2 Reserved 0xA 0x3 Reserved 0xB 0x4 Reserved 0xC 0x5 Reserved 0xD 0x6 Reserved 0xE 0x7 Reserved 0xF SAMPLE RATE PCLK = 12MHz, LRCLK = 8kHz PCLK = 12MHz, LRCLK = 16kHz PCLK = 13MHz, LRCLK = 8kHz PCLK = 13MHz, LRCLK = 16kHz PCLK = 16MHz, LRCLK = 8kHz PCLK = 16MHz, LRCLK = 16kHz PCLK = 19.2MHz, LRCLK = 8kHz PCLK = 19.2MHz, LRCLK = 16kHz PLL Mode Enable (Slave Mode Only) PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK frequency and automatically sets the LRCLK divider (NI1/NI2). 0 = Disabled 1 = Enabled Normal Mode LRCLK Divider When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12 for common NI values. 5 0 VALUE NI1/ NI2 6 5 SAMPLE RATE DHF1/DHF2 8kHz P LRCLK P 48kHz 0 48kHz < LRCLK P 96kHz 1 NI1/NI2 FORMULA 4 3 0x13/0x1B fLRCLK = LRCLK frequency fPCLK = Prescaled MCLK frequency (PCLK) 2 1 0 NI1[0]/NI2[0] Rapid Lock Mode Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1 to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is much closer to the correct value, thus speeding up lock time. Wait one LRCLK period after programming NI1/NI2 before setting PLL1/PLL2 = 1. Maxim Integrated Products82 MAX98088 Stereo Audio Codec with FlexSound Technology Table 11. Clock Control Registers (continued) REGISTER BIT NAME DESCRIPTION DAI_ DAC Low Power Select. These bits setup the clocks to be generated from fixed counters that bypass the PLL for DAC low power mode. 7 VALUE SETTING FILTER SELECT VALUE SETTING FILTER SELECT 0x0 PLL derived clock -- 0x8 PCLK = 2304 x LRCLK Voice 5 0x1 PCLK = 128 x LRCLK Audio 96kHz 0x9 Reserved -- 4 0x2 PCLK = 192 x LRCLK Audio 96kHz 0xA Reserved -- 0x3 PCLK = 256 x LRCLK Audio 48kHz 0xB Reserved -- 0x4 PCLK = 384 x LRCLK Audio 48kHz 0xC Reserved -- 0x5 PCLK = 768 x LRCLK Voice 0xD Reserved -- 1 0x6 PCLK = 1152 x LRCLK Voice 0xE Reserved -- 0 0x7 PCLK = 1536 x LRCLK Voice 0xF Reserved -- 6 DAI2_DAC_LP 0x4F 3 2 DAI1_DAC_LP 3 2 DAC2DITHEN DAI2 DAC Input Dither Enable DAC2DITHEN is recommended to be set when DAI2_DAC_LP = 0000. 0 = Disabled 1 = Enabled DAC1DITHEN DAI1 DAC Input Dither 1 Enable DAC1DITHEN is recommended to be set when DAI1_DAC_LP = 0000. 0 = Disabled 1 = Enabled CGM2_EN DAI2 Clock Gen Module Enable CGM1_EN has to be set along with CGM2_EN to enable the clock generation for the DAI2 DAC playback path. 0 = Disabled 1 = Enabled CGM1_EN DAI1/Device Clock Gen Module Enable CGM1_EN enables the device clock generation, and needs to be set for DAC playback or ADC record. 0 = Disabled 1 = Enabled 0x50 1 0 Maxim Integrated Products83 MAX98088 Stereo Audio Codec with FlexSound Technology Table 12. Common NI1/NI2 Values LRCLK (kHz) PCLK (MHz) DHF1/2 = 0 8 11.025 12 10 13A9 1B18 11 11E0 18A2 11.2896 116A 1800 1A1F 12 1062 1694 1893 12.288 1000 160D 13 0F20 14D8 DHF1/2 = 1 16 22.05 24 32 44.1 48 64 88.2 1D7E 2752 3631 3AFB 4EA5 1ACF 23BF 3144 359F 477E 22D4 3000 343F 20C5 2D29 3127 1800 2000 2C1A 16AF 1E3F 29AF 96 6C61 75F7 4EA5 6C61 75F7 6287 6B3E 477E 6287 6B3E 45A9 6000 687D 45A9 6000 687D 4189 5A51 624E 4189 5A51 624E 3000 4000 5833 6000 4000 5833 6000 2D5F 3C7F 535F 5ABE 3C7F 535F 5ABE 16 0C4A 10EF 126F 1893 21DE 24DD 3127 43BD 49BA 3127 43BD 49BA 16.9344 0B9C 1000 116A 1738 2000 22D4 2E71 4000 45A9 2E71 4000 45A9 18.432 0AAB 0EB3 1000 1555 1D66 2000 2AAB 3ACD 4000 2AAB 3ACD 4000 20 09D5 0D8C 0EBF 13A9 1B18 1D7E 2752 3631 3AFB 2752 3631 3AFB Note: Values in bold are exact integers that provide maximum full-scale performance. interfaces (SDIN1/SDIN2), and for the resulting mixed audio to output on either audio interface through SDOUT1 or SDOUT2. Sample Rate Converter The sample rate conversion scheme enables the mixing of asynchronous audio data from the digital audio DV1G: 0/6/12/18dB DVST: 0dB TO -60dB SIDETONE + MIX DSTS MULTI BAND ALC DVEQ1: 0dB TO -15dB AUTOMATIC GAIN CONTROL NOISE GATE MODE1 AVFLT ADLEN ADCL ADCR ADREN 5-BAND PARAMETRIC EQ EQ1EN AUDIO/ VOICE FILTERS AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB EQ2EN EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB DV2: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 SAMPLE RATE CONVERTER DV1: 0dB TO -15dB AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 18. Sample Rate Converter Maxim Integrated Products84 MAX98088 Stereo Audio Codec with FlexSound Technology Table 13. Sample Rate Converter REGISTER 0x21 BIT NAME DESCRIPTION 4 SRMIX_MODE 3 SRMIX_ENL 2 SRMIX_ENR 1 SRC_ENL 0 SRC_ENR Sample Rate Mix Mode. Sets mixing configuration applied to the sample rate converted channel(s). 0 = (DAI1 + DAI2) 1 = (DAI1 + DAI2)/2 Sample Rate Mix Enable. If enabled, mixes data on DAI1 and DAI2. If cleared, SCR data source is DAI2 only. 0 = SRC mix disable 1 = SRC mix enable Sample Rate Converter Enable. Select if the SRC is enabled on per channel basis. 0 = Sample rate converter disable 1 = Sample rate converter enable Use music mode when processing high-fidelity audio content. The music FIR filters reduce power consumption and are linear phase to maintain stereo imaging. An optional DC-blocking filter is available to eliminate unwanted DC offset. Passband Filtering Each digital signal path in the IC includes options for defining the path bandwidth (Figure 19). The playback and record paths connected to DAI1 support both voice and music filtering while the playback path connected to DAI2 supports music filtering only. In music mode, a second set of FIR filters are available to support sample rates greater than 50kHz. The filters can be independently selected for DAI1 and DAI2 and support both the playback and record audio paths. The voice IIR filters provide greater than 70dB stopband attenuation at frequencies above fS/2 to reduce aliasing. Three selectable highpass filters eliminate unwanted lowfrequency signals. DV1G: 0/6/12/18dB DVST: 0dB TO -60dB SIDETONE + MIX DSTS MULTI BAND ALC DVEQ1: 0dB TO -15dB AUTOMATIC GAIN CONTROL NOISE GATE MODE1 AVFLT ADLEN ADCL 5-BAND PARAMETRIC EQ EQ1EN AUDIO/ VOICE FILTERS AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB EQ2EN EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB DV2: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 SAMPLE RATE CONVERTER ADCR ADREN DV1: 0dB TO -15dB AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 19. Digital Passband Filtering Block Diagram Maxim Integrated Products85 MAX98088 Stereo Audio Codec with FlexSound Technology Table 14. Passband Filtering Registers REGISTER BIT NAME 7 MODE1 6 AVFLT1 4 0x18 DHF1 2 DVFLT1 0 AVFLT1 0 See Table 15 1 Select a nonzero value to enable the DC-blocking filter. DAI1 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz P LRCLK P 96kHz MODE1 DVFLT1 0 See Table 15 1 Select a nonzero value to enable the DC-blocking filter. DHF2 DAI2 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz < LRCLK P 96kHz DCB2 DAI2 DC Blocking Filter Enables a DC-blocking filter on the DAI2 playback audio path. 0 = Disabled 1 = Enabled 0x20 0 MODE1 DAI1 DAC Highpass Filter Mode 1 3 DAI1 Passband Filtering Mode 0 = Voice filters 1 = Music filters (recommended for fS > 24kHz) DAI1 ADC Highpass Filter Mode 5 3 DESCRIPTION Maxim Integrated Products86 MAX98088 Stereo Audio Codec with FlexSound Technology Table 15. Voice Highpass Filters AVFTL/DVFLT VALUE INTENDED SAMPLE RATE FILTER RESPONSE 000 N/A Disabled 0 001/011 16kHz/8kHz AMPLITUDE (dB) -10 -20 -30 -40 -50 -60 0 200 400 600 800 1000 800 1000 FREQUENCY (Hz) 0 010/100 16kHz/8kHz AMPLITUDE (dB) -10 -20 -30 -40 -50 -60 0 200 400 600 FREQUENCY (Hz) 0 101 8kHz to 48kHz AMPLITUDE (dB) -10 -20 -30 -40 -50 LRCLK = 48kHz -60 0 200 400 600 800 1000 FREQUENCY (Hz) 110/111 N/A Reserved Maxim Integrated Products87 MAX98088 Stereo Audio Codec with FlexSound Technology Playback Path Signal Processing The IC playback signal path includes automatic level control (ALC) and a 5-band parametric equalizer (EQ) (Figure 20). The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers. Two completely separate parametric EQs are included for the DAI1 and DAI2 playback paths. Automatic Level Control The automatic level control (ALC) circuit ensures maximum signal amplitude without producing audible clipping. This is accomplished by a variable gain stage that works on a sample by sample basis to increase the gain up to 12dB. A look-ahead circuit determines if the next sample exceeds full scale and reduces the gain so that the sample is exactly full scale. A programmable low signal threshold determines the minimum signal amplitude that is amplified. Select a threshold that prevents the amplification of background noise. When the signal level drops below the low signal threshold, the ALC reduces the gain to 0dB until the signal increases above the threshold. Figure 21 shows an example of ALC input vs. output curves. The ALC can optionally be configured in dual-band mode. In this mode, the input signal is filtered into two bands with a 5kHz center frequency. Each band is routed through independent ALCs and then summed together. In multiband mode, both bands use the same parameters. OUTPUT SIGNAL (dBFS) 0 LOW-LEVEL -12 0 THRESHOLD ALC WITH ALCTH 000 INPUT SIGNAL (dBFS) OUTPUT SIGNAL (dBFS) 0 DV1G: 0/6/12/18dB + 0 INPUT SIGNAL (dBFS) 0 INPUT SIGNAL (dBFS) MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ LOW-LEVEL THRESHOLD DVEQ2: 0dB TO -15dB ALC WITH ALCTH = 000 5-BAND PARAMETRIC EQ EQ1EN -12 OUTPUT SIGNAL (dBFS) EQ2EN EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL 0 DALEN DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 20. Playback Path Signal Processing Block Diagram LOW-LEVEL THRESHOLD -12 ALC DISABLED Figure 21. ALC Input vs. Output Examples Maxim Integrated Products88 MAX98088 Stereo Audio Codec with FlexSound Technology Table 16. Automatic Level Control Registers BIT 7 NAME ALCEN 0x43 ALCRLS 4 3 0 VALUE 000 001 010 011 100 101 110 111 ALC RELEASE TIME (s) 8 4 2 1 0.5 0.25 Reserved Reserved ALCMB Multiband Enable Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be configured properly to achieve the correct center frequency for each playback path. 0 = Single-band ALC 1 = Dual-band ALC ALCTH Low Signal Threshold Selects the minimum signal level to be boosted by the ALC. 000 = -JdB (low-signal threshold disabled) 001 = -12dB 010 = -18dB 011 = -24dB 100 = -30dB 101 = -36dB 110 = -42dB 111 = -48dB 2 1 ALC Enable Enables ALC on both the DAI1 and DAI2 playback paths. 0 = Disabled 1 = Enabled ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Excursion Limiter section for Excursion Limiter release times. ALC release time is defined as the time required to adjust the gain from 12dB to 0dB. 6 5 DESCRIPTION Parametric Equalizer The parametric EQ contains five independent biquad filters with programmable gain, center frequency, and bandwidth. Each biquad filter has a gain range of Q12dB and a center frequency range from 20Hz to 20kHz. Use a filter Q less than that shown in Figure 22 to achieve ideal frequency responses. Setting a higher Q results in nonideal frequency response. The biquad filters are series connected, allowing a total gain of Q60dB. 1000 MAXIMUM RECOMMENDED FILTER Q REGISTER fs = 8kHz 100 fs = 48kHz 10 fs = 96kHz 1 0.1 100 1000 10,000 100,000 CENTER FREQUENCY (Hz) Figure 22. Maximum Recommended Filter Q vs. Frequency Maxim Integrated Products89 MAX98088 Stereo Audio Codec with FlexSound Technology Use the attenuator at the EQ's input to avoid clipping the signal. The attenuator can be programmed for fixed attenuation or dynamic attenuation based on signal level. If the dynamic EQ clip detection is enabled, the signal level from the EQ is fed back to the attenuator circuit to determine the amount of gain reduction necessary to avoid clipping. The MAX98088 EV kit software includes a graphical interface for generating the EQ coefficients. The coefficients are sample rate dependent and stored in registers 0x52 through 0xB5. Table 17. EQ Registers REGISTER BIT NAME 4 EQCLP1/ EQCLP2 2 DVEQ1/DVEQ2 1 0 7 0x49 DAI1/DAI2 EQ Clip Detection Automatically controls the EQ attenuator to prevent clipping in the EQ. 0 = Enabled 1 = Disabled DAI1/DAI2 EQ Attenuator Provides attenuation to prevent clipping in the EQ when full-scale signals are boosted. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2 = 1. 3 0x30/0x32 DESCRIPTION VALUE GAIN (dB) VALUE GAIN (dB) 0x0 0 0x8 -8 0x1 -1 0x9 -9 0x2 -2 0xA -10 0x3 -3 0xB -11 0x4 -4 0xC -12 0x5 -5 0xD -13 0x6 -6 0xE -14 0x7 -7 0xF -15 VS2EN See the Click-and-Pop Reduction section. 6 VSEN 5 ZDEN 1 EQ2EN DAI2 EQ Enable 0 = Disabled 1 = Enabled 0 EQ1EN DAI1 EQ Enable 0 = Disabled 1 = Enabled Maxim Integrated Products90 MAX98088 Stereo Audio Codec with FlexSound Technology Playback Level Control allows boost when MODE1 = 0 and attenuation in any mode. The DAI2 signal path allows attenuation only. The IC includes separate digital level control for the DAI1 and DAI2 playback audio paths. The DAI1 signal path DV1G: 0/6/12/18dB + MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EQ2EN EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 AUDIO/ VOICE FILTERS MIX MODE1 DVFLT MIXDAR DACR DAREN Figure 23. Playback Level Control Block Diagram Table 18. DAC Playback Level Control Register REGISTER BIT NAME 7 DV1M/DV2M 5 DV1G 4 0x2F/0x31 2 DV1/DV2 0 DAI1/DAI2 Mute 0 = Disabled 1 = Enabled DAI1 Voice Mode Gain DV1G only applies when MODE1 = 0. 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB DAI1/DAI2 Attenuation 3 1 DESCRIPTION VALUE GAIN (dB) VALUE 0x0 0 0x8 GAIN (dB) -8 0x1 -1 0x9 -9 0x2 -2 0xA -10 0x3 -3 0xB -11 0x4 -4 0xC -12 0x5 -5 0xD -13 0x6 -6 0xE -14 0x7 -7 0xF -15 Maxim Integrated Products91 MAX98088 Stereo Audio Codec with FlexSound Technology DAC Input Mixers The IC's stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and right DACs (Figure 24). DV1G: 0/6/12/18dB + MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EQ2EN EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 24. DAC Input Mixer Block Diagram Table 19. DAC Input Mixer Register REGISTER BIT NAME 7 6 5 0x22 MIXDAL Left DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel MIXDAR Right DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel 4 3 2 1 0 DESCRIPTION Maxim Integrated Products92 MAX98088 Stereo Audio Codec with FlexSound Technology Receiver Amplifier The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive a 32I earpiece speaker. In cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver amplifier output to the left speaker outputs. The receiver amplifier can also be configured as stereo singleended line outputs using the I2C interface. RECVOLL: +8dB TO -62dB RECP/ LOUTL/ RXINP 0dB MIX RECLEN MIXRECL RECBYP RECVOLR: +8dB TO -62dB MIX 0dB LINEMODE RECREN MIXRECR RECN/ LOUTR/ RXINN SPKBYP SPKLP +6dB SPKLN SPLEN DACL DALEN DACR DAREN Figure 25. Receiver Amplifier Block Diagram Maxim Integrated Products93 MAX98088 Stereo Audio Codec with FlexSound Technology Receiver Output Mixer The IC's receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal can be configured to attenuate 6dB, 9dB, or 12dB. Table 20. Receiver Output Mixer Register REGISTER BIT NAME 7 MIXRECL MIXRECR Right Receiver Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Right DAC 6 5 0x28 4 3 2 1 0 7 6 5 0x29 4 3 2 1 0 7 3 0x2A 2 LINE_MODE 0 Receiver Output Mode. Configures receive path output mode between BTL and stereo line output. 0 = BTL 1 = Stereo line output MIXRECR _GAIN Right Receiver Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB MIXRECL _GAIN Left Receiver Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB 1 0 DESCRIPTION Left Receiver Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Left DAC Maxim Integrated Products94 MAX98088 Stereo Audio Codec with FlexSound Technology Receiver Output Volume Table 21. Receiver Output Level Register REGISTER BIT NAME 7 RECLM/ RECRM 3 2 1 0 Receiver Output Mute 0 = Disabled 1 = Enabled Receiver Output Volume Level 4 0x3B/0x3C DESCRIPTION RECVOLL/ RECVOLR VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -62 0x10 -10 0x01 -58 0x11 -8 0x02 -54 0x12 -6 0x03 -50 0x13 -4 0x04 -46 0x14 -2 0x05 -42 0x15 0 0x06 -38 0x16 +1 0x07 -35 0x17 +2 0x08 -32 0x18 +3 0x09 -29 0x19 +4 0x0A -26 0x1A +5 0x0B -23 0x1B +6 0x0C -20 0x1C +6.5 0x0D -17 0x1D +7 0x0E -14 0x1E +7.5 0x0F -12 0x1F +8 Maxim Integrated Products95 MAX98088 Stereo Audio Codec with FlexSound Technology Speaker Amplifiers The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as current steering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the IC's Class D amplifier still exhibits 80% efficiency under the same conditions. Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC electromagnetic-interference (EMI) regulation standards. Maxim's patented active emissions limiting edge-rate control circuitry reduces EMI emissions, allowing operation without any output filtering in typical applications. SPKLVDD SPVOLL: +8dB TO -62dB MIX SPKLN SPLEN DACL DALEN SPKLP +6dB SPKLGND POWER/ DISTORTION LIMITER MIXSPL SPKRVDD SPKRP DACR +6dB MIX DAREN MIXSPR SPVOLR: +8dB TO -62dB SPKRN SPREN SPKRGND Figure 26. Speaker Amplifier Path Block Diagram Maxim Integrated Products96 MAX98088 Stereo Audio Codec with FlexSound Technology Speaker Output Mixers The IC's speaker amplifiers accept input from the stereo DAC, the line inputs (single-ended ore differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB or 12dB. Table 22. Speaker Output Mixer Register REGISTER BIT NAME 7 MIXSPL MIXSPR Right Speaker Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Right DAC MIXSPR _GAIN Right Speaker Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB MIXSPL _GAIN Left Speaker Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB 6 5 0x2B 4 3 2 1 0 7 6 5 0x2C 4 3 2 1 0 3 2 0x2D 1 0 DESCRIPTION Left Speaker Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Left DAC Maxim Integrated Products97 MAX98088 Stereo Audio Codec with FlexSound Technology Speaker Output Volume Table 23. Speaker Output Level Register REGISTER BIT 7 NAME SPLM/SPRM DESCRIPTION Left/Right Speaker Output Mute 0 = Disabled 1 = Enabled Left/Right Speaker Output Volume Level 4 0x3D/0x3E 3 SPVOLL/SPVOLR 2 1 VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -62 0x10 -10 0x01 -58 0x11 -8 0x02 -54 0x12 -6 0x03 -50 0x13 -4 0x04 -46 0x14 -2 0x05 -42 0x15 0 0x06 -38 0x16 +1 0x07 -35 0x17 +2 0x08 -32 0x18 +3 0x09 -29 0x19 +4 0x0A -26 0x1A +5 0x0B -23 0x1B +6 0x0C -20 0x1C +6.5 0x0D -17 0x1D +7 0x0E -14 0x1E +7.5 0x0F -12 0x1F +8 Speaker Amplifier Signal Processing The IC includes signal processing to improve the sound quality of the speaker output and protect transducers from damage. An excursion limiter dynamically adjusts the highpass corner frequency, while a power limiter and distortion limiter prevent the amplifier from outputting too much distortion or power. The excursion limiter is located in the DSP while the distortion limiter and power limiter control the analog volume control (Figure 28). All three limiters analyze the speaker amplifier's output signal to determine when to take action. Excursion Limiter The excursion limiter is a dynamic highpass filter that monitors the speaker outputs and increases the highpass corner frequency when the speaker amplifier's output exceeds a predefined threshold. The filter smoothly transitions between the high and low corner frequency to prevent unwanted artifacts. The filter can operate in four different modes: U Fixed-Frequency Preset Mode. The highpass corner frequency is fixed at the upper corner frequency and does not change with signal level. U Fixed-Frequency Programmable Mode. The highpass corner frequency is fixed to that specified by the programmable biquad filter. U Preset Dynamic Mode. The highpass filter automatically slides between a preset upper and lower corner frequency based on output signal level. U User-Programmable Dynamic Mode. The highpass filter slides between a user-programmed biquad filter on the low side to a predefined corner frequency on the high side. Maxim Integrated Products98 MAX98088 Stereo Audio Codec with FlexSound Technology The transfer function for the user-programmable biquad is: b + b1z -1 + b 2z -2 H(z) = 0 1 + a 1z -1 + a 2z -2 The MAX98088 EV kit software includes a graphic interface for generating the user-programmable biquad coefficients. Note: Only change the excursion limiter settings when the signal path is disabled to prevent undesired artifacts. The coefficients b0, b1, b2, a1, and a2 are sample rate dependent and stored in registers 0xB4 through 0xC7. Store b0, b1, and b2 as positive numbers. Store a1 and a2 as negated two's complement numbers. Separate filters can be stored for the DAI1 and DAI2 playback paths. DV1G: 0/6/12/18dB + MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB SPVOLL: +8dB TO -62dB 5-BAND PARAMETRIC EQ EQ1EN MIX SPKLN SPKLGND MIXSPL EXCURSION LIMITER MIX AUDIO/ FILTERS MIXDAL POWER/ DISTORTION LIMITER DACL SPKRVDD DALEN SPKRP DCB2 MIX SPVOLR: MIXSPR +8dB TO -62dB DV1: 0dB TO -15dB SPKLP +6dB SPLEN EQ2EN DV2: 0dB TO -15dB SPKLVDD +6dB SPKRN SPREN SPKRGND AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN Figure 27. Speaker Amplifier Signal Processing Block Diagram Maxim Integrated Products99 MAX98088 Stereo Audio Codec with FlexSound Technology Table 24. Excursion Limiter Registers REGISTER BIT NAME 6 5 DHPUCF 4 0x41 1 DHPLCF 0 6 0x43 5 ALCRLS 4 3 2 0x42 DHPTH 1 0 DESCRIPTION Excursion Limiter Corner Frequency The excursion limiter has limited sliding range and minimum corner frequencies. Listed below are all the valid filter combinations. LOWER CORNER UPPER CORNER MINIMUM BIQUAD DHPUCF DHPLCF FREQUENCY FREQUENCY CORNER FREQUENCY Excursion limiter disabled -- 000 00 400Hz -- 001 00 600Hz -- 010 00 800Hz -- 011 00 1kHz -- 100 00 Programmable using biquad 100Hz 000 11 200Hz 400Hz -- 001 01 400Hz 600Hz -- 010 10 400Hz 800Hz -- 011 10 Programmable 400Hz 200Hz 001 11 using biquad Programmable using biquad 600Hz 300Hz 010 11 Programmable using biquad 800Hz 400Hz 011 11 Programmable using biquad 1kHz 500Hz 100 11 ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control section for ALC release times. Excursion limiter release time is defined as the time required to slide from the high corner frequency to the low corner frequency. VALUE EXCURSION LIMITER RELEASE TIME (s) 000 4 001 2 010 1 011 0.5 100 0.25 101 0.25 110 Reserved 111 Reserved Excursion Limiter Threshold Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper corner frequency. Signals below the threshold use the lower corner frequency. VBAT must correctly reflect the voltage of SPKLVDD to achieve accurate thresholds. 000 = 0.34VP 001 = 0.71VP 010 = 1.30VP 011 = 1.77VP 100 = 2.33VP 101 = 3.25VP 110 = 4.25VP 111 = 4.95VP Maxim Integrated Products100 MAX98088 Stereo Audio Codec with FlexSound Technology Power Limiter The IC's power limiter tracks the continuous power delivered to the loudspeaker and briefly mutes the speaker amplifier output if the speaker is at risk of sustaining permanent damage. Loudspeakers are typically damaged when the voice coil overheats due to extended operation above the rated power. During normal operation, heat generated in the voice coil is transferred to the speaker's magnet, which transfers heat to the surrounding air. For the voice coil to overheat, both the voice coil and the magnet must overheat. The result is that a loudspeaker can operate above its rated power for a significant time before it heats sufficiently to cause damage. The IC's power limiter includes user-programmable time constants and power thresholds to match a wide range of loudspeakers. Program the power limiter's threshold to match the loudspeaker's rated power handling. This can be determined through measurement or the loudspeaker's specification. Program time constant 1 to match the voice coil's thermal time constant. Program time constant 2 to match the magnet's thermal time constant. The time constants can be determined by plotting the voice coil's resistance vs. time as power is applied to the speaker. Table 25. Power Limiter Registers REGISTER BIT NAME DESCRIPTION Power Limiter Threshold If the continuous output power from the speaker amplifiers exceeds this threshold, the output is briefly muted to protect the speaker. The threshold is measured in watts assuming an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/ SPKRVDD to achieve accurate thresholds. 7 VALUE THRESHOLD (W) VALUE THRESHOLD (W) 0x0 Power limiter disabled 0x8 0.27 0x1 0.05 0x9 0.35 0x2 0.06 0xA 0.48 0x3 0.09 0xB 0.72 0x4 0.11 0xC 1.00 0x5 0.13 0xD 1.43 0x6 0.18 0xE 1.57 0x7 0.22 0xF 1.80 6 PWRTH 5 0x44 4 Power Limiter Weighting Factor Determines the balance between time constant 1 and 2 to match the dominance of each time constant in the loudspeaker. 2 1 0 PWRK VALUE T1 (%) 000 50 T2 (%) 50 001 62.5 37.5 010 75 25 011 87.5 12.5 100 100 0 101 12.5 87.5 110 25 75 111 37.5 62.5 Maxim Integrated Products101 MAX98088 Stereo Audio Codec with FlexSound Technology Table 25. Power Limiter Registers (continued) REGISTER BIT NAME 7 6 PWRT2 5 4 0x45 2 PWRT1 0 VALUE TIME CONSTANT (min) VALUE TIME CONSTANT (min) 0x0 Disabled 0x8 3.75 0x1 0.50 0x9 5.00 0x2 0.67 0xA 6.66 0x3 0.89 0xB 8.88 0x4 1.19 0xC Reserved 0x5 1.58 0xD Reserved 0x6 2.11 0xE Reserved 0x7 2.81 0xF Reserved Power Limiter Time Constant 1 Select a value that matches the thermal time constant of the loudspeaker's voice coil. 3 1 DESCRIPTION Power Limiter Time Constant 2 Select a value that matches the thermal time constant of the loudspeaker's magnet. VALUE TIME CONSTANT (s) VALUE TIME CONSTANT (s) 0x0 Disabled 0x8 3.75 0x1 0.50 0x9 5.00 0x2 0.67 0xA 6.66 0x3 0.89 0xB 8.88 0x4 1.19 0xC Reserved 0x5 1.58 0xD Reserved 0x6 2.11 0xE Reserved 0x7 2.81 0xF Reserved Distortion Limiter The IC's distortion limiter ensures that the speaker amplifier's output does not exceed the programmed THD+N limit. The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is clipped. If the distortion exceeds the programmed threshold, the output gain is reduced. Maxim Integrated Products102 MAX98088 Stereo Audio Codec with FlexSound Technology Table 26. Distortion Limiter Registers REGISTER BIT NAME 7 6 5 THDCLP 0x46 4 0 DESCRIPTION Distortion Limit Measured in % THD+N. THDT1 VALUE THD+N LIMIT (%) VALUE THD+N LIMIT (%) 0x0 Limiter disabled 0x8 12 0x1 <1 0x9 14 0x2 1 0xA 16 0x3 2 0xB 18 0x4 4 0xC 20 0x5 6 0xD 21 0x6 8 0xE 22 0x7 10 0xF 24 Distortion Limiter Release Time Constant Duration of time required for the speaker amplifier's output gain to adjust back to the nominal level after a large signal has passed. 0 = 1.4s 1 = 2.8s Headphone DirectDrive Headphone Amplifier Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's second-generation DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the ICs to be biased at GND while operating from a single supply (Figure 28). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220F typ) capacitors, the IC's charge pump requires 3 small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. Charge Pump The dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize efficiency, both the charge pump's switching frequency and output voltage change based on signal level. When the input signal level is less than 10% of PVDD, the switching frequency is reduced to a low rate. This minimizes switching losses in the charge pump. When the input signal exceeds 10% of PVDD, the switching fre quency increases to support the load current. For input signals below 25% of PVDD, the charge pump generates Q(PVDD/2) to minimize the voltage drop across the amplifier's power stage and thus improve efficiency. Input signals that exceed 25% of PVDD cause the charge pump to output QPVDD. The higher output voltage allows for full output power from the headphone amplifier. To prevent audible gliches when transitioning from the Q(PVDD/2) output mode to the QPVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from PVDD for the duration of the transition. The bypass capacitor on PVDD supplies the required current and prevents droop on PVDD. The charge pump's dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(PVDD/2) or QPVDD regardless of input signal level. Maxim Integrated Products103 MAX98088 Stereo Audio Codec with FlexSound Technology VDD VDD/2 Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the ICs, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 29 shows the operation of the output-voltage-dependent power supply GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD 1.8V 0.9V 32ms HPVDD VTH_H OUTPUT VOLTAGE GND VTH_L -0.9V HPVSS 32ms -1.8V -VDD (VSS) DirectDrive AMPLIFIER BIASING SCHEME Figure 28. Traditional Amplifier Output vs. DirectDrive Output Figure 29. Class H Operation DACL DALEN DACR DAREN MIXHPL_ PATH SEL HPVOLL: +3dB TO -67dB MIX HPLEN MIXHPL MIX MIXHPR HPL HPSNS MIXHPR_ PATH SEL HPVOLR: +3dB TO -67dB HPR HPREN Figure 30. Headphone Amplifier Block Diagram Maxim Integrated Products104 MAX98088 Stereo Audio Codec with FlexSound Technology Headphone Output Mixers The headphone amplifier mixer accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB, or 12dB. The stereo DAC can bypass the headphone mixers, and be connected directly to the headphone amplifiers to provide lower power consumption. Table 27. Headphone Output Mixer Register REGISTER BIT NAME 7 6 5 0x25 4 3 MIXHPL 2 1 0 7 6 5 0x26 4 3 MIXHPR 2 1 0 0x27 5 MIXHPR_ PATH SEL 4 MIXHPL_ PATH SEL 3 2 MIXHPR _GAIN 1 0 MIXHPL _GAIN DESCRIPTION Left Headphone Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INB1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Left DAC Right Headphone Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC2 xx1xxxxx = MIC1 xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxx1xxx = INB1 xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxxxx1x = INA1 xxxxxxx1 = Right DAC Right Headphone Mixer Path Select 0 = Directly connect to the right DAC (bypass right headphone output mixer) 1 = Right headphone output mixer Left Headphone Mixer Path Select 0 = Directly connect to the left DAC (bypass left headphone output mixer) 1 = Left headphone output mixer Right Headphone Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB Left Headphone Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB Maxim Integrated Products105 MAX98088 Stereo Audio Codec with FlexSound Technology Headphone Output Volume Table 28. Headphone Output Level Register REGISTER BIT NAME 7 HPLM/HPRM DESCRIPTION Headphone Output Mute 0 = Disabled 1 = Enabled Left/Right Headphone Output Volume Level 4 0x39/0x3A 3 HPVOLL/HPVOLR 2 1 0 VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -67 0x10 -15 0x01 -63 0x11 -13 0x02 -59 0x12 -11 0x03 -55 0x13 -9 0x04 -51 0x14 -7 0x05 -47 0x15 -5 0x06 -43 0x16 -4 0x07 -40 0x17 -3 0x08 -37 0x18 -2 0x09 -34 0x19 -1 0x0A -31 0x1A 0 0x0B -28 0x1B +1 0x0C -25 0x1C +1.5 0x0D -22 0x1D +2 0x0E -19 0x1E +2.5 0x0F -17 0x1F +3 Maxim Integrated Products106 MAX98088 Stereo Audio Codec with FlexSound Technology Output Bypass Switches an external receiver amplifier is used, route its output to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier. In systems where an external amplifier drives both the receiver and the IC's line input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN. The IC includes two output bypass switches that solve common applications problems. When a single transducer is used for the loudspeaker and receiver, the need exists for two amplifiers to power the same transducer. Bypass switches connect the IC's receiver amplifier output to the speaker amplifier's output, allowing either amplifier to power the same transducer. In systems where RECP/RXINP 0dB 10I* RECLEN RECN/RXINN 0dB RECREN RECP/RXINP 0dB 10I* EXTERNAL RECEIVER AMP RECLEN RECLEN RECN/RXINN 0dB RECBYP RECREN SPKBYP SPLEN RECREN SPKBYP RECBYP SPKBYP SPKLVDD SPKLP SPKLVDD SPKLP SPKLN +6dB SPKLN +6dB SPKLGND SPLEN SPKLGND SPLEN POWER/DISTORTION LIMITER EXTERNAL RECEIVER AMP RECN/RXINN 0dB RECBYP SPKLVDD SPKLP +6dB RECP/RXINP 0dB POWER/DISTORTION LIMITER SPKLN SPKLGND POWER/DISTORTION LIMITER *OPTIONAL 10I RESISTORS IMPROVE DISTORTION THROUGH THE ANALOG SWITCH. SPEAKER AMPLIFIER BYPASS USING AN EXTERNAL RECEIVER AMPLIFIER SPEAKER AMPLIFIER BYPASS USING THE INTERNAL RECEIVER AMPLIFIER CONTROLLING AN EXTERNAL RECEIVE AMPLIFIER AND SPEAKER Figure 31. Output Bypass Switch Block Diagrams Table 29. Output Bypass Switches Register REGISTER BIT NAME 7 INABYP 4 MIC2BYP 1 See the Microphone Inputs section. RECBYP RXINP to RXINN Bypass Switch Shorts RXINP to RXINN allowing a signal to pass through the ICs. Disable the receiver amplifier when RECBYP = 1. 0 = Disabled 1 = Enabled SPKBYP RXIN to SPKL Bypass Switch Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external receiver amplifier to power the left speaker. Disable the left speaker amplifier when SPKBYP = 1. 0 = Disabled 1 = Enabled 0x4A 0 DESCRIPTION Maxim Integrated Products107 MAX98088 Stereo Audio Codec with FlexSound Technology Click-and-Pop Reduction The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on, turn-off, and during volume changes. Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume changes are made. Instead of making a volume change immediately, the change is made when the audio signal crosses the midpoint. If no zero-crossing occurs within the timeout window, the change is forced. Volume slewing breaks up large volume changes into the smallest available step size and the steps through each step between the initial and final volume setting. When enabled, volume slewing also occurs at device turn-on and turn-off. During turn-on the volume is set to mute before the output is enabled. Once the output is on, the volume ramps to the desired level. At turn-off the volume is ramped to mute before the outputs are disabled. When there is no audio signal zero-crossing detection can prevent volume slewing from occurring. Enable enhanced volume slewing to prevent the volume controller from requesting another volume level until the previous one has been set. Each step in the volume ramp then occurs after a zero crossing has occurred in the audio signal or the timeout window has expired. During turn-off, enhance volume slewing is always disabled. Table 30. Click-and-Pop Reduction Register REGISTER BIT NAME DESCRIPTION VS2EN Enhanced Volume Smoothing During volume slewing, the controller waits for each step in the ramp to be applied before sending the next step. When zero-crossing detection is enabled this prevents large steps in the output volume when no zero crossings are detected. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. VSEN Volume Adjustment Smoothing Volume changes are smoothed by stepping through intermediate steps. Also ramps the volume from minimum to the programmed value at turn-on and back to minimum at turn-off. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. 5 ZDEN Zero-Crossing Detection Holds volume changes until there is a zero crossing in the audio signal. This reduces click and pop during volume changes (zipper noise). If no zero crossing is detected within 100ms, the volume change is forced. 0 = Enabled 1 = Disabled Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC, HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. 1 EQ2EN 0 EQ1EN 7 6 0x47 See the 5-Band Parametric EQ section. Maxim Integrated Products108 MAX98088 Stereo Audio Codec with FlexSound Technology Jack Detection The IC features jack detection that can detect the insertion and removal of a jack. When a jack is detected, an interrupt on IRQ can be triggered to alert the microcontroller of the event. Figure 32 shows the typical configuration for jack detection. Jack Detection and Removal When the IC is in normal operation and the MICBIAS is enabled, jack insertion and removal can be detected through JACKSNS. To detect a jack insertion and removal, the ICs must be powered on and MICBIAS enabled. Set JDETEN, MBEN, BIASEN, and VCMEN bits to enable jack detection circuitry. JACKSNS is pulled up by MICBIAS as long as no load is applied to JACKSNS. Table 31 shows the change in JKSNS that occurs when a jack is inserted and removed. HPL MICBIAS JACKSNS HPR MIC1P Figure 32. Typical Configuration for Jack Detection Table 31. Change in JKSNS Upon Jack Insertion JACK TYPE MBEN = 1, BIASEN = 1, VCMEN = 1 GND GND R L JKSNS: 1 e 0 MIC GND R L JKSNS: 1 e 0 Table 32. Change in JKSNS Upon Jack Removal JACK TYPE MBEN = 1, BIASEN = 1, VCMEN = 1 GND GND R L JKSNS: 0 e 1 MIC GND R L JKSNS: 0 e 1 Maxim Integrated Products109 MAX98088 Stereo Audio Codec with FlexSound Technology Table 33. Jack Detection Registers REGISTER 0x02 (Read Only) 0x4B BIT NAME 6 JKSNS 7 JDETEN 1 JDEB 0 DESCRIPTION JACKSNS State Reports the status of JACKSNS when JDETEN = 1, MBEN = 1, BIASEN = 1, and VCMEN = 1. 0 = JACKSNS low 1 = JACKSNS high Jack Detection Enable 0 = Disabled 1 = Enabled Jack Detection Debounce Configures the debounce time for setting JDET. 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms Battery Measurement The IC measures the voltage applied to SPKLVDD (typically the battery voltage) and reports the value in register 0x03. This value is also used by the speaker limiter circuitry to set accurate thresholds. When the battery measurement function is disabled, the battery voltage is user programmable. Table 34. Battery Measurement Registers REGISTER BIT NAME DESCRIPTION VBAT Battery Voltage Read VBAT when VBATEN = 1 to determine VSPKLVDD. Program VBAT when VBATEN = 0 to allow proper speaker amplifier signal processing. Calculate/program the battery voltage using the following formula: VBATTERY = 2.55V + [VBAT/10] 7 SHDN See the Power Management section. 6 VBATEN 3 PERFMODE See the Power Management section. 2 HPPLYBCK See the Power Management section. 1 PWRSV8K See the Power Management section. 0 PWRSV See the Power Management section. 4 3 0x03 2 1 0 0x51 Battery Measurement Enable. Enables an internal ADC to measure VSPKLVDD. 0 = Disabled (register 0x03 readable and writeable) 1 = Enabled (register 0x03 read only) Maxim Integrated Products110 MAX98088 Stereo Audio Codec with FlexSound Technology Device Status The IC uses register 0x00 and IRQ to report the status of various device functions. The status register bits are set when their respective events occur, and cleared upon reading the register. Device status can be determined either by poling register 0x00 or configuring the IRQ to pull low when specific events occur. IRQ is an open-drain output that requires a pullup resistor for proper operation. Register 0x0F determines which bits in the status register trigger IRQ to pull low. Table 35. Status and Interrupt Registers REGISTER BIT NAME DESCRIPTION CLD Full Scale 0 = All digital signals are less than full scale. 1 = The DAC or ADC signal path has reached or exceeded full scale. This typically indicates clipping. 6 SLD Volume Slew Complete SLD reports that any of the programmable-gain arrays or volume controllers has completed slewing from a previous setting to a new programmed setting. If multiple gain arrays or volume controllers are changed at the same time, the SLD flag is set after the last volume slew completes. SLD also reports when the digital audio interface soft-start or soft-stop process has completed. MCLK is required for proper SLD operation. 0 = No volume slewing sequences have completed since the status register was last read. 1 = Volume slewing complete. 5 ULK Digital Audio Interface Unlocked 0 = Both digital audio interfaces are operating normally. 1 = Either digital audio interface is configured incorrectly or receiving invalid clocks. 1 JDET Jack Configuration Change JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack Status bits are debounced before setting JDET. The debounce period is programmable using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first time power is applied to the IC. Read the status register following such an event to clear JDET and allow for proper jack detection. 0 = No change in jack configuration. 1 = Jack configuration has changed. 7 ICLD 6 ISLD 5 IULK 1 IJDET 7 0x00 (Read Only) 0x0F Full-Scale Interrupt Enable 0 = Disabled 1 = Enabled Volume Slew Complete Interrupt Enable 0 = Disabled 1 = Enabled Digital Audio Interface Unlocked Interrupt Enable 0 = Disabled 1 = Enabled Jack Configuration Change Interrupt Enable 0 = Disabled 1 = Enabled Maxim Integrated Products111 MAX98088 Stereo Audio Codec with FlexSound Technology Device Revision Table 36. Device Revision Register REGISTER BIT NAME DESCRIPTION 7 6 5 0xFF (Read Only) 4 3 Device Revision Code REV is always set to 0x40. REV 2 1 0 I2C Serial Interface The IC features an I2C/SMBusK-compatible, 2-wire serial interface comprising a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. Figure 5 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses. The IC transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors S protect the digital inputs of the IC from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 33). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Sr P SCL SDA Figure 33. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. Maxim Integrated Products112 MAX98088 Stereo Audio Codec with FlexSound Technology Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the IC, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21) configures the IC for read mode. Setting the read/write bit to 0 (slave address = 0x20) configures the ICs for write mode. The address is the first byte of information sent to the IC after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the IC uses to handshake receipt each byte of data when in write mode (Figure 34). The IC pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition. Write Data Format A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 35 illustrates the proper frame format for writing one byte of data to the IC. Figure 35 illustrates the frame format for writing n-bytes of data to the IC. CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 2 1 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 34. Acknowledge ACKNOWLEDGE FROM MAX98088 B7 ACKNOWLEDGE FROM MAX98088 S SLAVE ADDRESS B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX98088 A O A REGISTER ADDRESS DATA BYTE A P 1 BYTE R/W AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 35. Writing One Byte of Data to the ICs ACKNOWLEDGE FROM MAX98088 ACKNOWLEDGE FROM MAX98088 S SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX98088 O A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX98088 A DATA BYTE 1 1 BYTE B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE n A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 36. Writing n-Bytes of Data to the ICs Maxim Integrated Products113 MAX98088 Stereo Audio Codec with FlexSound Technology The slave address with the R/W bit set to 0 indicates that the master intends to write data to the ICs. The ICs acknowledge receipt of the address byte during the master-generated 9th SCL pulse. The first byte transmitted from the ICs is the content of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The second byte transmitted from the master configures the IC's internal register address pointer. The pointer tells the IC where to write the next byte of data. An acknowledge pulse is sent by the ICs upon receipt of the address pointer data. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the IC's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The third byte sent to the ICs contains the data that is written to the chosen register. An acknowledge pulse from the ICs signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0xC7 are reserved. Do not write to these addresses. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 37 illustrates the frame format for reading one byte from the IC.Figure 38 illustrates the frame format for reading multiple bytes from the ICs. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. ACKNOWLEDGE FROM MAX98088 S O SLAVE ADDRESS ACKNOWLEDGE FROM MAX98088 A ACKNOWLEDGE FROM MAX98088 A REGISTER ADDRESS Sr A R/W REPEATED START R/W 1 SLAVE ADDRESS NOT ACKNOWLEDGE FROM MASTER DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 37. Reading One Byte of Data from the ICs ACKNOWLEDGE FROM MAX98088 S SLAVE ADDRESS O ACKNOWLEDGE FROM MAX98088 A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX98088 A REPEATED START Sr SLAVE ADDRESS 1 R/W A DATA BYTE A 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 38. Reading n Bytes of Data from the ICs Maxim Integrated Products114 MAX98088 Stereo Audio Codec with FlexSound Technology Applications Information Typical Operating Circuits Figures 39 and 40 provide example operating circuits for the ICs. sThe external components shown are the minimum required for the ICs to operate. Additional components may be required by the application. 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF PVDD 1FF AVDD 1.8V TO 3.6V 1FF 1FF SPKLVDD 1FF SPKRVDD 1FF DVDDS2 10kI TO MICROCONTROLLER BCLKS2 IRQ BCLKS1 DIGITAL AUDIO PORT 1 I2C CONTROL PORT JACKSNS 1kI 2.2kI SDINS2 LRCLKS1 SDOUTS2 SDINS1 JACKSNS SDOUTS1 RECP/RXINP SDA RECN/RXINN SCL MICROPHONE OUTPUT TO BASEBAND BYPASS SWITCH INPUT 8I SPKLN MAX98088 SPKRP 8I SPKRN MICBIAS 1FF HPR MIC2P HEADSET MICROPHONE JACKSNS SPKLP MIC1P/DIGMICDATA MIC1N/DIGMICCLK DIGITAL AUDIO PORT 2 LRCLKS2 MCLK 10MHz TO 60MHz CLOCK INPUT HPL 1FF MIC2N HPSNS 1FF INA1/EXTMICP HANDSET MICROPHONE 1FF REF INA2/EXTMICN 1FF REG INB1 1kI LINE INPUT 1FF 1FF 2.2FF INB2 1FF DGND AGND HPGND SPKRGND SPKLGND HPVDD HPVSS 1FF C1N C1P 1FF 1FF Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch Maxim Integrated Products115 MAX98088 Stereo Audio Codec with FlexSound Technology 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF PVDD 1FF 1.8V TO 3.6V 1FF AVDD 1FF SPKLVDD 1FF SPKRVDD 1FF DVDDS2 10kI TO MICROCONTROLLER BCLKS2 IRQ 10MHz TO 60MHz CLOCK INPUT LRCLKS2 MCLK BCLKS1 DIGITAL AUDIO PORT 1 I2C CONTROL DATA DIGITAL MIC 1 DIGITAL MIC 2 PORT SDINS2 LRCLKS1 SDOUTS2 SDINS1 JACKSNS SDOUTS1 RECP/RXINP SDA RECN/RXINN SCL DATA MIC1N/DIGMICCLK 2.2kI 8I MAX98088 SPKRP 8I SPKRN MICBIAS 1FF HPR MIC2P HEADSET MICROPHONE 32I SPKLN CLOCK JACKSNS JACKSNS SPKLP MIC1P/DIGMICDATA CLOCK DIGITAL AUDIO PORT 2 HPL 1FF MIC2N HPSNS 1FF INA1/EXTMICP LINE INPUT REF 1FF INA2/EXTMICN 1FF REG INB1 LINE INPUT 1FF 1FF 2.2FF INB2 1FF DGND AGND HPGND SPKRGND SPKLGND HPVDD HPVSS 1FF C1N C1P 1FF 1FF Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier Maxim Integrated Products116 MAX98088 Stereo Audio Codec with FlexSound Technology Filterless Class D Operation In RF applications, improvements to both layout and component selection decrease the IC's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the IC. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference. Ideally, the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD peak to peak) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. Because the frequency of the IC's output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The IC is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product. Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors as it exhibits a frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at the RF frequencies of interest. These capacitors, when placed at the input pins, can effectively shunt the RF noise to ground. For these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane. Avoid using microvias to connect to the ground plane whenever possible as these vias do not conduct well at RF frequencies. Startup/Shutdown Sequencing To ensure proper device initialization and minimal clickand-pop, program the IC's SHDN = 1 after configuring all registers. Table 37 lists an example startup sequence for the device. To shut down the IC, simply set SHDN = 0. Table 37. Example Startup Sequence SEQUENCE DESCRIPTION REGISTERS 1 Ensure SHDN = 0 0x51 2 Configure clocks 0x10 to 0x13, 0x19 to 0x1B 3 Configure digital audio interface 0x14 to 0x17, 0x1C to 0x1F 4 Configure digital signal processing 0x18, 0x20, 0x3F to 0x46 5 Load coefficients 0x52 to 0xC9 6 Configure mixers 0x22 to 0x2D 7 Configure gain and volume controls 0x2E to 0x3E 8 Configure miscellaneous functions 0x47 to 0x4B 9 Enable desired functions 0x4C, 0x50 10 Set SHDN = 1 0x51 Maxim Integrated Products117 MAX98088 Stereo Audio Codec with FlexSound Technology Many configuration options in the ICs can be made while the devices are operating, however, some registers should only be adjusted when the corresponding audio path is disabled. Table 38 lists the registers that are sensitive during operation. Either disable the corresponding audio path or set SHDN = 0 while changing these registers. Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground (Figure 41). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the IC line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: 1 f-3dB = 2RINCIN Choose CIN so that f-3dB is well below the lowest frequency of interest. For best audio quality use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Table 38. Registers That Are Sensitive to Changes During Operation REGISTER DESCRIPTION 0x10 to 0x13, 0x19 to 0x1B Clock Control Registers 0x14 to 0x17, 0x1C to 0x1F Digital Audio Interface Configuration 0x18, 0x20 Digital Passband Filters 0x25 to 0x2D Analog Mixers 0x52 to 0xC9 Digital Signal Processing Coefficients SPK_P MAX98088 SPK_N Figure 41. Optional Class D Ferrite Bead Filter Maxim Integrated Products118 MAX98088 Stereo Audio Codec with FlexSound Technology Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external charge- pump capacitors dominate. Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVSS) value and ESR directly affect the ripple at HPVSS. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics section for more information Unused Pins Table 39 shows how to connect the IC's pins when unused. Table 39. Unused Pins NAME CONNECTION NAME CONNECTION SPKRP Unconnected INB1 Unconnected SPKRVDD Always connect INA2/MICEXTN Unconnected SPKLVDD Always connect LRCLKS2 Unconnected SPKLP Unconnected MCLK Always connect RECN/RXINN Unconnected SDINS2 AGND HPVDD Unconnected Unconnected C1P Unconnected IRQ MIC1P/DIGMICDATA HPGND AGND INA1/MICEXTP Unconnected Always connect Unconnected SPKRN Unconnected DGND SPKRGND Always connect BCLKS2 Unconnected SPKLGND Always connect SDA Always connect SPKLN Unconnected SCL Always connect RECP/RXINP Unconnected REG Always connect C1N Unconnected REF Always connect HPL Unconnected MIC1N/DIGMICCLK Unconnected HPVSS Unconnected MIC2P Unconnected SDINS1 AGND SDOUTS2 Unconnected LRCLKS1 Unconnected DVDDS2 DVDD HPSNS AGND DVDD Always connect INB2 Unconnected AVDD Always connect HPR Unconnected PVDD Always connect DVDDS1 DVDD AGND Always connect SDOUTS1 Unconnected MICBIAS Unconnected BCLKS1 Unconnected MIC2N Unconnected JACKSNS Unconnected Maxim Integrated Products119 MAX98088 Stereo Audio Codec with FlexSound Technology Recommended PCB Routing The IC uses a 63-bump WLP package. Figure 42 provides an example of how to connect to all active bumps using 3 layers of the PCB. To ensure uninterrupted ground returns, use layer 2 as a connecting layer between layer 1 and layer 2 and flood the remaining area with ground. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. When designing a PCB for the ICs, partition the circuitry so that the analog sections of the IC are separated from the digital sections. This ensures that the analog audio traces are not routed near digital traces. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND, DGND, HPGND, SPKLGND, and SPKRGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Ground the bypass capacitors on MICBIAS, REG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path length to AGND. Bypass AVDD directly to AGND. LAYER 1 LAYER 2 LAYER 3 Figure 42. Suggested Routing for the MAX98088 Connect all digital I/O termination to the ground plane with minimum path length to DGND. Bypass DVDD, DVDDS1, and DVDDS2 directly to DGND. Place the capacitor between C1P and C1N as close as possible to the ICs to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVDD and HPVSS with a capacitor located close to HPVSS with a short trace length to HPGND. Close decoupling of HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier. HPSNS senses ground noise on the headphone jack and adds the same noise to the output audio signal, thereby making the output (headphone output minus ground) noise free. Connect HPSNS to the headphone jack shield to ensure accurate pickup of headphone ground noise. Bypass SPKLVDD and SPKRVDD to SPKLGND and SPKRGND, respectively, with as little trace length as possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN to the stereo speakers using the shortest traces possible. Reducing trace length minimizes radiated EMI. Route SPKLP/SPKLN and SPKRP/SPKRN as differential pairs on the PCB to minimize loop area, thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close as possible to the IC to ensure maximum effectiveness. Minimize the trace length from any ground-connected passive components to SPKLGND and SPKRGND to further minimize radiated EMI. Maxim Integrated Products120 MAX98088 Stereo Audio Codec with FlexSound Technology Route microphone signals from the microphone to the ICs as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close as possible to the audio source and then treat the positive and negative traces as differential pairs. 0.24mm An evaluation kit (EV kit) is available to provide an example layout for the IC. The EV kit allows quick setup of the IC and includes easy-to-use software allowing all internal registers to be controlled. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and Its Applications. Figure 43 shows the dimensions of the WLP balls used on the MAX98088. 0.21mm Figure 43. WLP Ball Dimensions Ordering Information PART TEMP RANGE PIN-PACKAGE MAX98088EWY+ -40NC to +85NC 63 WLP +Denotes lead(Pb)-free/RoHS-compliant package. Maxim Integrated Products121 MAX98088 Stereo Audio Codec with FlexSound Technology Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 63 WLP W633A3+1 21-0462 Refer to Application Note 1891 Maxim Integrated Products122 MAX98088 Stereo Audio Codec with FlexSound Technology Revision History REVISION NUMBER REVISION DATE 0 6/10 1 6/11 DESCRIPTION Initial release PAGES CHANGED -- Made various updates, replaced TOCs 56 and 68 1, 5-27, 29, 30, 33, 35, 37, 39, 41, 43, 46, 54, 55, 56, 63-67, 69, 70, 70, 74, 75, 77, 80, 81, 83-86, 90, 94-99, 101, 103, 104, 105, 107, 109, 110, 111, 113, 114, 119, 120 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products 123 Maxim is a registered trademark of Maxim Integrated Products, Inc.