ispPAC30-01SNI - Lattice Semiconductor

www.latticesemi.com

pac30_01

ispPAC30

In-System Programmable Analog Circuit

October 2002 Data Sheet

Features

■

Flexible Interface and Programming Control

• Full conﬁguration capability, SPI or JTAG modes

• Unlimited device updates using SRAM register

•E

CMOS

for non-volatile conﬁguration storage

• Real-time microcontroller conﬁguration/control

■

Four Input Instrumentation Ampliﬁers (IA’s)

• High impedance: differential or single-ended

• 0V to 2.8V with programmable gains (±1 to ±10)

• Dual multiplexers (pin or serial port controlled)

• Connects easily to existing system circuits

■

Two Conﬁgurable Rail-to-Rail Output Amps

• Single-ended, 0V to 5V output swing

• Gain bandwidth product >15MHz

• Ampliﬁer, ﬁlter, integrator or comparator modes

•7 ﬁlter frequencies (50kHz to 600kHz)

■

Two 4-Quadrant, 8-Bit Multiplying DACs

• Full bandwidth when used as a multiplier

• Precision gain (<0.01 steps) with signal as input

• Precision offset (in 7 ranges) using internal Vref

■

Analog Input/Summation Routing Pools

• Routing of all I/O to any IA or MDAC

•Any IA/MDAC summed to either output ampliﬁer

• Circuits with and without feedback possible

• Routable to maintain pin location relationships

■

Other Product Features

• Single supply (+5V) operation

• Precision voltage reference output (2.5V)

•Power-down for

Watt power consumption

•Auto-calibration of internal offsets

•Available in 28-pin PDIP or 24-pin SOIC

■

Applications

• Reconﬁgurable or adaptive signal conditioning

• Analog front end for most A/D converters

• Programmable analog signal control loops

• Precision programmable gain ampliﬁers

Functional Block Diagram

Description

The ispPAC

30 is a member of the Lattice family of In-

System Programmable (ISP™) analog integrated cir-

cuits. It is digitally conﬁgured via SRAM and utilizes

CMOS memory for non-volatile storage of its conﬁgu-

ration. The ﬂexibility of ISP enables programming, veriﬁ-

cation and unlimited reconﬁguration, directly on the

printed circuit board.

The ispPAC30 is a complete front end solution for data

acquisition applications using 10 to 12-bit ADC's. It pro-

vides multiple single-ended or differential signal inputs,

multiplexing, precision gain, offset adjustment, ﬁltering,

and comparison functionality. It also has complete

routability of inputs or outputs to any input cell and then

from any input cell to either summing node of the two

output ampliﬁers. Designers conﬁgure the ispPAC30

and verify its performance using PAC-Designer

, an

easy to use, Microsoft Windows

compatible develop-

ment tool. Device programming is supported using PC

parallel port I/O operations.

Dual

12-Bit

ADC

µController

ispPAC30

Vin2

Vin1

Vin3

GND

CAL

MSEL2

MSEL1

TCK

TDI

TDO

TMS

ENSPI

IN4-

IN4+

IN3-

IN3+

SCOM

OUT2

OUT1

IN2-

IN2+

IN1-

IN1+

ispPAC30 24-Pin SOIC

Vref1

MDAC

Vref2

Compare

Integrate

Amplify

Filter

Compare

Integrate

Amplify

Filter

Summation Routing Pool

Input/Output Routing Pool

JTAG/SPI

Interface Logic

& Configuration

Memory

Auto-Calibration

2.5V Reference

VREFOUT

Lattice Semiconductor ispPAC30 Data Sheet

Electrical Characteristics

TA = 25°C; V

= 5.0V; 0V < V

< 2.8V; Gain = 1; Output load = 50pf, 1k

ΩΩ

. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,

MDAC2 connected to OA2. V

OUT

biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-

wise speciﬁed).

Symbol Parameter Condition Min. Typ. Max. Units

Analog Input

IN±

(1) Input Voltage Range Applied to either V

IN+

or V

IN-

0 2.8 V

IN-DIFF

(2) Differential Voltage Swing 2 |V

IN+

- V

IN-

| 5.6 V

(3) Differential Offset Voltage

(Input Referred)

G=1 1 2 mV

G = 10 100

∆

T Differential Offset Drift -40

C to +85

C; Any gain, input referred 50

Input Resistance 10

Ω

Input Capacitance 2 pF

Input Bias Current (at DC) at 25

C1pA

at 85

C 200 pA

Input Noise Voltage Density At 10kHz, referred to input, G=10 70

Analog Output

Output Voltage Swing High I

= 250

A 4.95 4.97 V

= 5mA 4.50 4.65 V

Output Voltage Swing Low I

= -250

A 0.03 0.05 V

= -5mA 0.11 0.15 V

Short Circuit Current Short to ground; V

OUT

= 4.9V 25 35 mA

OUT

Maximum Output Current See graph in typical performance curves ±30 mA

Static Performance

G Programmable Gain Range Individual input ampliﬁer gain 0 20 dB

Gain Error V

OUT

= 0.5V to 4.5V 1 3 %

Input Gain Matching Any two inputs; any output 1 3 %

∆

T Gain Drift -40

C to +85

C35ppm/

PSR Power Supply Rejection at 10kHz 74 dB

Reference Output (VREF

OUT

)

VREF

OUT

Reference Output Range Nominally 2.500V; I

LOAD

= 0 -0.2 0.2 %

IREF

OUT

Reference Output Current (VREF

OUT

change = -1%) source 40

(VREF

OUT

change = +1%) sink -350

Reference Output Drift -40 to +85

C 100 ppm/

Reference Output Noise 100kHz bandwidth 40

RMS

Power Supply Rejection 1kHz 80 dB

Comparator Mode Performance

Comparator Switching Time 10mV overdrive 4.0

100mV overdrive 2.5

Overload Recovery Time 2.8V overload 3.0

nV/ Hz

Lattice Semiconductor ispPAC30 Data Sheet

Electrical Characteristics, Continued

TA = 25°C; V

= 5.0V; 0V < V

< 2.8V; Gain = 1; Output load = 50pf, 1k

ΩΩ

. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,

MDAC2 connected to OA2. V

OUT

biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-

wise speciﬁed).

Symbol Parameter Condition Min. Typ. Max. Units

MDAC PACell Performance

Resolution 7+sign bits

INL Integral Non-Linearity 0.25 0.5 lsb

DNL Differential Non-Linearity Guaranteed monotonic -1 lsb

Offset Voltage 3mV

Gain Error 13 %

Input Bandwidth (F

3dB

= 3Vp-p; V

= 1.4V±0.75V 1.25 1.6 MHz

Internal Voltage Reference Performance

REF1

REF2

Voltage Output 64mV Setting 56 64 72 mV

128mV Setting 120 128 136 mV

256mV Setting 246 256 266 mV

512mV Setting 500 512 524 mV

1024mV Setting 1000 1024 1048 mV

2048mV Setting 2000 2048 2096 mV

2.500V Setting 2.450 2.500 2.550 V

Dynamic Performance

SNR Signal to Noise (4) 0.1Hz to 114kHz 83 dB

THD Total Harmonic Distortion F

= 10kHz -85 -74 dB

OUT

= 4Vpk (0.5V to 4.5V) F

= 100kHz -75 -60 dB

CMR Common Mode Rejection 10kHz 75 dB

= 0V to 2.8V) (5) 100kHz 65 dB

BW Small Signal Bandwidth All gains, minimum feedback capacitor 1 1.57 MHz

Full Power Bandwidth All gains 1.1 MHz

SR Slew Rate All gains 10 15 V/

Settling Time, 0.1% 4V output step, low to high 2 4

OUT

= 4Vpk (0.5V to 4.5V) 4V output step, high to low 4 8

Crosstalk (6) R

= 1k

Ω

, F

= 10kHz -100 dB

Filter Characteristics

Corner Frequency Range (7) 49 619 kHz

| Corner Frequency Accuracy Deviation from calculated -3db point 3 5 %

∆

T Corner Frequency Drift -40

C + 0 +85

C 0.05 %/

Digital I/O

Input Low Voltage 0 0.8 V

Input High Voltage 2 V

Lattice Semiconductor ispPAC30 Data Sheet

Electrical Characteristics, Continued

TA = 25°C; V

= 5.0V; 0V < V

< 2.8V; Gain = 1; Output load = 50pf, 1k

ΩΩ

. IA1, IA2, MDAC1 connected to OA1 and IA3, IA4,

MDAC2 connected to OA2. V

OUT

biased to swing from 0.5 to 4.5V. Auto-Cal initiated immediately prior. (Unless other-

wise speciﬁed).

Symbol Parameter Condition Min. Typ. Max. Units

Digital I/O (Continued)

, I

Input Leakage Current No pull-up/pull-down 10

With pull-up/pull-down (8) ±50

Hysteresis Schmitt Trigger 250 mV

Output Low Voltage (TDO) I

= 4.0mA 0.4 V

Output High Voltage (TDO) I

= -1.0mA 2.4 V

Programming and Calibration

Erase/Reprogram Cycles For E

CMOS cells 10K 1M cycles

Calibration Cycle Time Initial turn on 140 250 ms

Subsequent user initiated 50 100

Power Supplies

Operating Supply Voltage 4.75 5 5.25 V

Supply Current (8) V

= 5.0V 10 15 mA

Power Dissipation (9) V

= 5.0V 50 75 mW

Power Down Supply Current V

= 5.0V 10 30

Wakeup Time Time to resume normal operation 3.5 5.0

Temperature Range

Operation -40 85

Storage -65 150

Notes:

1. Inputs larger than this will be clipped.

2. Inputs can be used fully differential if care is taken to offset signals so as to not force the outputs below 0V or above V

. The total input

swing is measured from one differential extreme, with respect to polarity, to the other, or twice the peak single-ended input range.

3. To insure full spec performance, an auto-calibration should be performed after initial turn-on when the device reaches thermal stability.

4. For all gains except G=1, output is assumed to be driven to 5V by the input signal level (V

x Gain = 5V). When G=1, the maximum single

ended input possible is 2.8V. The consequence is an output of 2.8V instead of 5V. Computed SNR is then 5dB less because of the lower

effective signal. With a true differential 2.5V input and G=1, output will again be a full 5V and SNR will be equal to the value shown in the

speciﬁcation table.

5. V

IN+

and V

IN-

are connected together for this test.

6. Measured between analog outputs, with an identical signal path conﬁguration used for each. One channel is driven with a 10kHz signal and

the other is not (input grounded).

7. Computed 3db corner frequencies are 619kHz, 401kHz, 250kHz, 169kHz, 114kHz, 74kHz and 49kHz. Actual values found in PAC-

Designer software.

8. Logic inputs will exhibit positive current conﬁgured with a pull-down and negative current with a pull-up.

9. Conﬁgured so all internal circuitry is powered on.

Lattice Semiconductor ispPAC30 Data Sheet

Pin Descriptions

Pins

Symbol Name DescriptionPDIP SOIC

15, 16, 17, 18,

25, 26, 27, 28

13, 14, 15, 16,

21, 22, 23, 24 IN Inputs 1, 2, 3, 4 (+ or -)

Plus or Minus

Differential input pins, with two pins per input

(e.g., IN2+ and IN2-). Each are components of

VIN, where differential VIN = VIN+ - VIN-.

65MSEL1 Multiplexer 1 Control

Multiplexer logic input pin. Selects either of two

analog channels to IA1 (instrument ampliﬁer).

Programmable pull-up, pull-down (default), or

none.

44MSEL2 Multiplexer 2 Control

Multiplexer logic input pin. Selects either of two

analog channels to IA4 (instrument ampliﬁer).

Programmable pull-up, pull-down (default), or

none.

21, 22 18, 19 OUT Outputs 1 and 2 Single-ended output pins. Internal feedback to

inputs accommodated.

20 17 VREFOUT Voltage Reference Output

Internal voltage reference output pin (+2.5V

nominal). Must be bypassed to GND with a 1µF

capacitor.

13 11 ENSPI Enable SPI Mode

Enable SPI logic input pin. When high, causes

serial port to run in SPI mode. Programmable

pull-up or pull-down (default).

12 10 TMS Test Mode Select Serial interface logic mode select pin (input).

JTAG interface mode only. Internal pull-up.

11 9 TDO Test Data Out

Serial interface logic pin (output) for both JTAG

and SPI operation modes. Programmable slew

rate, high or low (default).

98TDI Test Data In Serial interface logic pin (input) for both JTAG

and SPI modes. Internal pull-up.

87TCK Test Clock

Serial interface logic clock pin (input) for both

JTAG and SPI modes. Programmable pull-up,

pull-down (default), or none.

76CS Chip Select Chip select logic input pin. SPI data transfer

enabled by this input. Internal pull-up.

33CAL Auto-Calibrate Digital pin (input). Commands an auto-calibration

sequence on a rising edge. Internal pull-down.

22PD Power Down

Power down enable logic pin (input). Shuts down

all power to device. Programmable pull-up

(default), pull-down or none.

14 12 VS Supply Voltage

Analog supply pin (5V nominal). Should be

bypassed to GND with 1µF and .01µF capaci-

tors.

11GND Ground Ground pin. Should normally be connected to

the analog ground plane.

23 20 SCOM Signal Common

Analog signal common pin (sense). Always con-

nected to GND. Auto-calibration accuracy is

determined with respect to this pin.

5, 10, 19, 24 — NC No Connects No internal connections are made to these pins

in the PDIP package.

Lattice Semiconductor ispPAC30 Data Sheet

Connection Notes:

1. All inputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected

externally by reversing pin connections or internally under user programmable control.

2. All analog output pins are “hard-wired” to internal output pins and should be left open if not used.

3. When the signal input is single-ended, the unused half or the differential input (usually the – or minus) must be

connected GND or some other reference point. If OA output is routed to an IA or MDAC input, the minus input

is automatically connected to 0V internally.

Absolute Maximum Ratings

Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V

Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . . 0 to VS

Logic and Analog Output Short Circuit Duration . . . . . . Indeﬁnite

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260°C

Ambient Temperature with Power Applied . . . . . . . . -55 to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional

operation of the device at these or at any other condition above those indicated in the operational sections of this speciﬁcation is

not implied.

GND

CAL

MSEL2

MSEL1

TCK

TDI

TDO

TMS

ENSPI

IN4-

IN4+

IN3-

IN3+

SCOM

OUT2

OUT1

IN2-

IN2+

IN1-

IN1+

ispPAC30 24-Pin SOIC

Vref1

MDAC

Vref2

Compare

Integrate

Amplify

Filter

Compare

Integrate

Amplify

Filter

Summation Routing Pool

Input/Output Routing Pool

JTAG/SPI

Interface Logic

& Configuration

Memory

Auto-Calibration

2.5V Reference

VREFOUT

IN4-

IN4+

IN3-

IN3+

SCOM

OUT2

OUT1

IN2-

IN2+

IN1-

IN1+

GND

CAL

MSEL2

MSEL1

TCK

TDI

TDO

TMS

ENSPI

ispPAC30 28-Pin PDIP

Vref1

MDAC

Vref2

Compare

Integrate

Amplify

Filter

Compare

Integrate

Amplify

Filter

Summation Routing Pool

Input/Output Routing Pool

JTAG/SPI

Interface Logic

& Configuration

Memory

Auto-Calibration

2.5V Reference

Lattice Semiconductor ispPAC30 Data Sheet

Part Number Description

ispPAC30 Ordering Information

Package Options

Part Number Package

ispPAC30-01PI 28-pin PDIP

ispPAC30-01SI 24-pin SOIC

Device Number

ispPAC30 – XX X X

Grade

Blank = Commercial

I = Industrial

Performance Grade

01 = Standard

Package

P = PDIP

S = SOIC

Device Family

ispPAC30

24-Pin SOIC

ispPAC30

28-Pin PDIP

Lattice Semiconductor ispPAC30 Data Sheet

Timing Speciﬁcations (JTAG Interface Mode)

Symbol Parameter Conditions Min Typ Max

tckmin Min Clock Period — 80ns

tckl TCK Low Time — 40ns

tckh TCK High Time — 40ns

tmss TMS Setup Time — 15ns

tmsh TMS Hold Time — 4ns

tdis TDI Setup Time — 15ns

tdih TDI Hold Time — 8ns

tdozx TDO Delay Float to Valid — 60ns

tdov TDO Delay Clock to Valid — 60ns

tdoxz TDO Delay Valid to Float — 145ns

calmin Minimum Calibration Pulse — 40ns

TCK

TMS

TDI

TDO

tdozx

tdov

tdihtdis

tmss tmsh

tckl tckhtckmin

calmin

tdoxz

CAL

Lattice Semiconductor ispPAC30 Data Sheet

Timing Speciﬁcations (SPI Interface Mode)

Symbol Parameter Min Typ Max

tckmin Min Clock Period 80ns

tckl TCK Low Time 40ns

tckh TCK High Time 40ns

tdis TDI Setup Time 5ns

tdih TDI Hold Time 8ns

tencss ENSPI Rising Edge to CS Falling Edge Setup Time 10ns

tcsens CS Rising Edge to ENSPI Falling Edge Setup Time 10ns

ttcsfs TCK Falling Edge to CS Falling Edge Setup Time 10ns

tcsfts CS Falling Edge to TCK Rising Edge Setup Time 8ns

ttcsrs TCK Falling Edge to CS Rising Edge Setup Time 25ns

tcsrts CS Rising Edge to TCK Rising Edge Setup Time 10ns

tcsbh CS Min High Time 60ns

tdozx TDO Delay Float to Valid 60ns

tdov TDO Delay Clock to Valid 60ns

tdoxz TDO Delay Valid to Float 145ns

calmin Minimum Calibration Pulse 30ns

ENSPI

TCK

TDI

TDO

MSBLSB

MSB

LSB LSB**

**LSB of TDI Byte Just Transferred

012….

tencss

ttcsfs

tcsfts

tckh tckl tckmin

tdis tdih

tdozx

tdov tdoxz

ttcsrs

tcsrts

tcsbh

tcsens

Lattice Semiconductor ispPAC30 Data Sheet

Timing Speciﬁcations (E2 Programming and Auto-cal)

Timing Speciﬁcations (Auto-cal)

Symbol Min Clock Period Conditions Min Typ Max

tpwp Time for a programming operation Executed in Run-Test/Idle 80ms 100ms

tpwe Time for an erase operation Executed in Run-Test/Idle 80ms 100ms

Symbol Min Clock Period Conditions Min Typ Max

tpwcal1 Time for auto-cal operation on power-up Automatically executed at power-up 140ms 250ms

tcalmin Minimum auto-cal pulse width — 30ns

tpwcal2 Time for user initiated auto-cal operation Executed on rising edge of CAL 50ms 100ms

tmss tmss

TCK

TMS

tpwp, tpwe

(PRGCFG/CLRALL executed in

Run-Test/Idle state)

CAL (Note: CAL internally

initiated at device turn-on.)

OUT = 0V

OUT

tpwcal1, tpwcal2

tcalmin

Lattice Semiconductor ispPAC30 Data Sheet

Typical Performance Characteristics

1 10 100 1k 10k 100k 1M

Frequency (Hz)

100

1000

Noise Voltage (nV Hz)√

Noise: Referred to Input

G = 10

10 100 1k 10k 100k 1M

Frequency (Hz)

Common Mode Rejection (dB)

100 1k 10k 100k 1M

Frequency (Hz)

Power Supply Rejection (dB)

Input Noise Spectrum

Small Signal BW vs. Gain

Gain Error (Gain = 1 & 10) Offset Voltage (VOS)V

OS Tempco

THD vs. Frequency Output Current Drive

CMR vs. Frequency PSR vs. Frequency

1k 10k 100k

Frequency (Hz)

-90

-100

-80

-70

-60

-50

-40

Total Harmonic Distortion (dB)

Gain = 1

Gain = 10

0 1 2 3 4 5

Nominal Output Voltage (V)

-50

-75

-25

Resulting Output Current (mA)

Vout Forced to

Nominal - 50mV

Vout Forced to

Nominal + 50mV

-1.0 -.2 +.2 +1.8+1.0-1.8

Gain Error (%)

3 Wafer Lots

PDIP Pkg

0°C to +85°C

-1 +1 +2-2

Offset (mV)

3 Wafer Lots

PDIP Pkg

+25°C

For All Gains,

Output Referred

-50 +50 +100-100

Percentage of Devices (%)

Offset Tempco ( V/°C)µ

3 Wafer Lots

PDIP Pkg

-40°C to +85°C

1k 10k 100k 1M 10M

Frequency (Hz)

-20

-25

-10

-15

-5

Output Amplitude (dB)

Gain = 10

Gain = 5

Gain = 2

Gain = 1

Lattice Semiconductor ispPAC30 Data Sheet

Typical Performance Characteristics, Continued

Gain = 1

Load = 1k ; 600pF

Ω

20mV 1µS

Gain = 1

Load = 1k ; 50pF

Ω

20mV 1µS

Gain = 1

Load = 1k ; 600pF

Ω

0.625V 1µS

Gain = 1

Load = 1k ; 50pFΩ

0.625V 1µS

Large-Signal Response

Small-Signal Response

Step Response Setup Diagram

IA1

VREF1

OA1

IA2

Cfb=min

2.5V

G=1

Vout

Vin+

Vin-

Vin+ 0.0 V 2.0 V 0.0 V 0.00 V 0.05 V 0.00 V

Vin- 2.0 V 0.0 V 2.0 V 0.05 V 0.00 V 0.05 V

VREF1 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V

Vout 0.5 V 4.5 V 0.5 V 2.45 V 2.55 V 2.45 V

Large-Signal Small-Signal

Lattice Semiconductor ispPAC30 Data Sheet

Theory of Operation

General Description

The ispPAC30 provides programmable, multiple single-ended or differential signal inputs, precision gain, offset

adjustment, ﬁltering, and comparison functionality all in a single device. It also has complete routability of inputs or

outputs to any input cell and then to either summing node of the internal output ampliﬁers. A key feature of the

ispPAC30 is its capability of being reconﬁgured in real time, apart from the operation of its non-volatile E2CMOS or

E2 conﬁguration memory. This enables the user to change or reconﬁgure the ispPAC30 an unlimited number of

times, such as in an automatic gain control circuit or other applications requiring ongoing parametric or routing

changes. Because a user chosen conﬁguration is always stored in non-volatile E2 conﬁguration memory as well,

there is a preset conﬁguration ready to go when the device is ﬁrst turned on, or whenever a return to that stored

state is required. Of course, the E2 conﬁguration can be updated at any time during normal device operation as a

completely transparent background operation. All of this functionality and ﬂexibility is combined into the ispPAC30

as a single integrated circuit that greatly simpliﬁes the otherwise burdensome task of designing and customizing

circuitry for a wide variety of analog applications.

The following sections of this data sheet give the user a thorough understanding of the general operation and

design considerations necessary when using the ispPAC30. Another resource that cannot be overlooked for under-

standing the ispPAC30 is associated with the PAC-Designer software design tool. Everything that can be conﬁg-

ured is accessible in a schematic entry based format. A complete appreciation of the ispPAC30’s capabilities is

enhanced by exploring and using this design software early to learn more about it. Because a simulator is included,

the user can quickly test and prove operational modes and arrive at an understanding sooner while exploring

device capabilities. Complete documentation of PAC-Designer is included with the software.

Further technical insight into the ispPAC30 can be gained by referring to the many application notes and circuit

solutions that directly relate to this device. All ispPAC technical support literature is available from the Lattice Semi-

conductor web site at www.latticesemi.com. In addition, Lattice provides expert applications support for all ispPAC

devices and their usage.

Device Input Cells

In an ispPAC30 device, any input pin can be routed to any of the four input instrument ampliﬁers (IA), two of which

have dual input multiplexers, or to either of the two multiplying DAC’s (MDAC), or any combination of these. In addi-

tion, either output ampliﬁer (OA) can be routed to any or all of these same input cells. This enables great ﬂexibility

in how an ispPAC30 is conﬁgured and allows many functions to be performed, such as signal summation, cas-

caded gain blocks, complex feedback circuits, etc.

At the ispPAC30 input pins, the input signal range that can be directly applied is 0 to 2.8V. When used differentially,

the input pins can be of any polarity with respect to each other as long as the resultant signal is not expected to

drive the OA outputs below 0V. Normally, input signals will be single ended, in which case the

minus input pin

IN-

)

can be tied to ground. Even with single ended measurements, the ispPAC30’s differential architecture can be used

to an advantage as it will sense ground at the point where it is connected and will also reject any noise common to

both ground and the input signal. Input impedances at all input nodes are the same as would be expected for MOS-

FET devices, and are typically in the Giga-Ohm range. Refer to the speciﬁcations section for more detail.

Input Instrument Ampliﬁers

The input ampliﬁers (IA’s) are referred to as instrument ampliﬁers because they take the difference of the two input

pins and multiply it by the gain setting for which they have been conﬁgured. With respect to true differential opera-

tion, this means that a negative gain setting is merely a reversal of the plus and minus input (VIN) pins. This is the

classical instrument ampliﬁer function and also includes the previously mentioned beneﬁt of remote sensing of sig-

nals (not necessarily 0V referenced) and rejection of common mode signals. Both IA’s and MDAC’s connected to

input signals also serve to buffer inputs by virtue of their very high input impedance.

Lattice Semiconductor ispPAC30 Data Sheet

Input Multiplexers

Two of the four input IA’s have dual input multiplexers in front of them. They constitute separately selectable input

paths to their respective IA’s. These paths can be conﬁgured either by external pin, or by setting internal E2 bits.

The control pins are named MSEL1 and MSEL2 and control the input path for IA1 and IA4, respectively. The deter-

mination of whether either of these select pins asserted high or low for choosing path “A” or “B” internally, and

whether an active pull-up or pull-down is programmed is all user-selectable from the software design interface

found in PAC-Designer. The initial conﬁguration is called out in the pin description table in the speciﬁcations section

of this data sheet. With multiplexer control, it is possible to bring in four different input signals and select between

them, performing selective signal conditioning on each as required. Or, one or more signals can be routed to one or

both multiplexers and thus achieve multiple signal conditioning paths for the same input, selectable by external

pins. Finally, all parameters can also be controlled and/or programmed into E2 conﬁguration memory in real time

using either the JTAG or SPI interface.

Internal Voltage References

Two separate voltage references (VREF1 and VREF2) are available to provide ﬁxed voltage references to the

ispPAC30’s four IA’s or two MDAC’s. Seven voltage levels are available from each VREF, and each VREF is inde-

pendently programmable from the other. Table 1 lists the binary weighted values that are available (in addition to

2.5V) and the corresponding least signiﬁcant bit (LSB) size if this VREF value is applied to the input of either of the

MDAC’s. Since the IA’s/MDAC’s have plus and minus polarity control, VREF outputs can be added or subtracted

from other signals via the summation bus in addition to being scaled from 1 to 10 by the IA’s or attenuated in 128

steps by the MDACs. By selective combination of these various settings, a very large number of user control offset

voltages can be summed with any input signal. This is also the basis of how the ispPAC30 can be conﬁgured as a

comparator. With the output ampliﬁer conﬁgured as a comparator, an unknown signal is summed with a precise ref-

erence value and an input above or below that reference level will cause a change in state of the output compara-

tor.

Table 1. Available VREF Outputs

Input MDACs

The ispPAC30 has two 8-bit (7+sign) multiplying digital to analog converters (MDAC’s) available that accept as their

reference input either external signals, internal signals or ﬁxed DC voltages (such as the internal VREFs). The mul-

tiplying DAC function means that the input is multiplied (attenuated) by a value corresponding to the code setting of

the DAC, resulting in an output that can range from 100% of the input down to a 1 LSB (least signiﬁcant bit weight)

fraction of that value. The exact values output by the MDAC versus input code are detailed in Table 2.

The ﬂexibility of the ispPAC30 allows the MDAC’s to act as adjustable attenuators of external input signals, thereby

providing fractional or ﬁne gain setting capability. It also means that in combination with the internal VREF’s they

can also be precision DC sources for providing ﬁxed setpoints, offsets, etc. For example, with the same input signal

applied to both an IA and MDAC, and combining both at the summing junction of one of the OA’s, an integer gain of

1 to 10 plus the fractional gain as a result of the MDAC attenuation is added together to achieve any gain value

from -11 to +11 with a resolution of greater than 0.01 throughout, for a total of more than 2,500 gain settings. See

the section on increasing MDAC resolution for more information using the MDAC’s as ﬁxed references.

VREF (V) MDAC LSB (mV)

0.064 0.5

0.128 1.0

0.256 2.0

0.512 4.0

1.024 8.0

2.048 16.0

2.500 19.5

Lattice Semiconductor ispPAC30 Data Sheet

More details about MDAC performance are found in the speciﬁcations section of the data sheet. It should be noted

that the speciﬁcations of the MDAC’s in regard to bandwidth, gain and offset errors, and drift over temperature are

equivalent to or better than those of the IA’s themselves. This means that in addition to having the same high-

impedance characteristics of the IA’s, the MDAC’s will perform in an equivalent fashion when used in combination

with the IA’s as signal conditioning elements. Predictable performance thereby results when mixing various combi-

nations of input resources together.

Table 2. Outputs vs. Digital Input Code

Increasing MDAC Effective Resolution

Because the value of the ispPAC30’s voltage references can be set to several output voltages, ranging from 64mV

to 2.5V, it is possible to use high-value MDAC settings (>50% full scale) to synthesize most desired thresholds. This

means that a given threshold (32mV or greater) can be set with a resolution of +/-0.8%.

If a higher degree of resolution is needed, the two voltage references and MDACs can be combined in a coarse-

ﬁne adjustment scheme, as shown in Figure 1. In this circuit, VREF1 and MDAC1 provide an adjustment range of

0-2.5V with 19.5mV of resolution, while VREF2 and MDAC2 provide an adjustment range of +/-64mV with 0.5mV of

resolution. By adding these two sources together, a total adjustment range of 0-2.56V with an effective resolution of

0.5mV is achieved.

Figure 1. Coarse-Fine Adjustment using Two References

Code MDAC Equivalent Voltage Output vs. VREF Input (in Volts)

DEC HEX 0.0640 0.128 0.256 0.512 1.024 2.048 2.5000 Vref Input (V)

000-100.0% -0.0640 -0.128 -0.256 -0.512 -1.024 -2.048 -2.5000 Full Scale

101-99.2% -0.0635 -0.127 -0.254 -0.508 -1.016 -2.032 -2.4805 Full Scale + 1 lsb

32 20 -75.0% -0.0480 -0.096 -0.192 -0.384 -0.768 -1.536 -1.8750

64 40 -50.0% -0.0320 -0.064 -0.128 -0.256 -0.512 -1.024 -1.2500

96 60 -25.0% -0.0160 -0.032 -0.064 -0.128 -0.256 -0.512 -0.6250

127 7F -0.8% -0.0005 -0.001 -0.002 -0.004 -0.008 -0.016 -0.0195 Bipolar Zero - 1 lsb

128 80 0.0% 0.0000 0.000 0.000 0.000 0.000 0.000 0.0000 Bipolar Zero

129 81 0.8% 0.0005 0.001 0.002 0.004 0.008 0.016 0.0195 Bipolar Zero + 1 lsb

160 A0 25.0% 0.0160 0.032 0.064 0.128 0.256 0.512 0.6250

192 C0 50.0% 0.0320 0.064 0.128 0.256 0.512 1.024 1.2500

224 E0 75.0% 0.0480 0.096 0.192 0.384 0.768 1.536 1.8750

254 FE 98.4% 0.0630 0.126 0.252 0.504 1.008 2.016 2.4609 +Full Scale - 1 lsb

255 FF 99.2% 0.0635 0.127 0.254 0.508 1.016 2.032 2.4805 +Full Scale

——0.78% 0.00025 0.0005 0.001 0.002 0.004 0.008 0.0098 1 lsb (with sign)

——1.56% 0.00050 0.0010 0.002 0.004 0.008 0.016 0.0195 2 lsb (1 lsb, no sign)

CP1

IA2

G=-1

MON

Links Open

Comparator Mode

OUT1

ispPAC30

MDAC1

MDAC2

VREF1=2.5V

VREF2=256mV

Lattice Semiconductor ispPAC30 Data Sheet

In this example, the effective resolution provided by combining the two references would normally require a 13-bit

DAC to replicate. Keep in mind, however, that resolution is not the same as accuracy. The absolute accuracy pro-

vided by an ispPAC30 using this technique is approximately equivalent to that provided by a 10-bit DAC.

In many situations, such as those in which a parameter is being interactively adjusted for optimal performance,

absolute accuracy may not be of paramount importance. In this case, stability and resolution of the adjustment are

more important than the absolute accuracy of the adjustment.

Interfacing to ispPAC Inputs

As mentioned in the previous IA section, any input voltage between 0 to 2.8V can be applied directly to an

ispPAC30 input. To keep the output from trying to swing below 0V, if Vin- is more positive than Vin+, an offsetting

signal must be applied to the appropriate summing node to balance or counteract the negative input. Single-ended

connections, however, only require that the minus input be connected to 0V or some other ﬁxed voltage. More infor-

mation on inputting signals to ispPAC30 can be found in application note AN6026, Interfacing to ispPAC Differential

Inputs.

Although differential signaling offers many signiﬁcant beneﬁts in a design, most analog designs today still use sin-

gle-ended signals where system ‘ground’ is used as a global zero-volt reference. The differential inputs provided on

ispPAC products provide more than enough ﬂexibility to accommodate single-ended signals.

Figure 2. DC Coupling a Single-ended Signal

When using an ispPAC30 with a single-ended input (Figure 2), tie the unused terminal to a reference voltage. Since

the common-mode input range for the ispPAC30 includes ground, the minus input is most often connected there.

This results in an internal signal value which corresponds directly to the input signal voltage (e.g. a +1.67V input

results in +1.67V of signal internally). When using an ispPAC30 in this manner, it will accommodate single-ended

input signals ranging from 0V to +2.8V.

In systems operating from single +5V supplies, it is often desirable to be able to accommodate rail-to-rail signals,

which range from ground to the positive supply voltage (+5V). Figure 3 shows an interface circuits that allows

ispPAC30 inputs to accept 0-5V signals, where R1 and R2 divide down the signal input.

Figure 3. Interfacing to a 0-5V DC Signal

0V to +2.8V

input

ispPAC30

100kΩ

ispPAC30

0V to +5V

Input

Lattice Semiconductor ispPAC30 Data Sheet

A Ground-Based Current Sense Technique

Because the ispPAC30’s common-mode input range extends down to ground, this part is straightforward to use in

applications with ground-referenced signals. An example of such an application is the current sensor shown in Fig-

ure 4. A 0-10A current input develops a voltage ranging from 0-1V across the 0.1Ω sense resistor. This application

also illustrates one of the primary beneﬁts of differential signal processing. Although one can sense the voltage at

the resistor’s input terminal with a single-ended ampliﬁer, this assumes that the ground terminal of the resistor is

really at ground. At ampere-level currents, this is a big, and often unwarranted assumption which can result in sig-

niﬁcant measurement errors. By sensing the actual voltage at both resistor terminals one can avoid this source of

measurement error.

Figure 4. ispPAC30 Sensing Differential Signals Near Ground

In this particular application, where high currents are being measured, there may be the possibility that the volt-

ages at the resistor terminals exceed those that the ispPAC30 can safely handle. If the input voltage becomes

lower than -0.6V or higher than +5.6V, input protection diodes inside the device will begin to turn on and shunt input

current to either ground or the positive power supply. In this case, since amperes of current are potentially avail-

able, signiﬁcant damage to the ispPAC30 could result if this occurs. Resistors R2 and R3 protect against this possi-

bility, by limiting maximum input current to safe levels (milliamperes) that the device’s input protection networks can

readily handle.

Voltage Reference Output

The 2.5V voltage reference output of the ispPAC30 (VREFOUT) has a high impedance voltage output which should

be buffered when using it as an external reference to drive other circuitry. It also should always be decoupled using

the recommended capacitor speciﬁed in the pin description table of this data sheet. If it is used to reference a high

impedance source (e.g., one that does not require more than 40µA), the VREFOUT output can be connected to it

directly. An example is shifting the DC level of a signal connected to the input pin of an ispPAC30. Also, by using a

current limiting resistor with the VREFOUT pin, it may also be used without buffering and still provide a DC refer-

ence. Check the ispPAC applications literature for numerous examples of these and other useful techniques for

using VREFOUT

. Note: If the VREFOUT pin is overloaded or disturbed, it will adversely affect the operation of the

rest of the ispPAC30.

Output Ampliﬁers

The ispPAC30 has two output ampliﬁers, or OA’s. The single-ended outputs of these ampliﬁers swing from 0V to

+5V and are hard-wired internally to the output pins. In addition, the outputs are also routed and available for con-

nection as inputs to any of the input IA’s or MDAC’s. Each OA can be conﬁgured independently to function as either

a full-bandwidth ampliﬁer, a low-pass ﬁlter, an integrator or a comparator. All these conﬁguration choices are

accessed by the user via the PAC-Designer design entry software. They can also be reconﬁgured along, with any

other part of the ispPAC30, using JTAG or SPI serial interface control to directly communicate with the device.

In addition to the multiple functions possible with the OA’s, another unique feature is that any or all of the IA’s and

MDAC’s can be selectively routed to either of the OA summing nodes. This provides the maximum amount of ﬂexi-

bility to the user over how the device is ultimately conﬁgured. IA’s can be connected in parallel to one OA or the

IIN

0.1Ω

20W

10kΩ

100mV/A0-10A

Lattice Semiconductor ispPAC30 Data Sheet

other as necessary to achieve higher gains, for example. Precision gain and offset conﬁgurations can be imple-

mented using different combinations of IA’s, MDAC’s and VREF’s to condition signals using a common summing

junction to deliver the desired output result. The combination of analog input and summing node route options

make the ispPAC30 very powerful in enabling so many different circuit possibilities. Examples of possible circuits

are included in the ispPAC30 applications literature.

Output Ampliﬁer Functional Modes

The ispPAC30 output ampliﬁers (OA’s) can be conﬁgured to act as wideband ampliﬁers, lowpass ﬁlters, integrators

or comparators. Each mode is determined by SRAM (or E2 conﬁguration memory at turn-on) control bits that open

and close feedback elements around the OA’s. All available modes of OA operation can be conﬁgured during the

design phase using PAC-Designer software or during normal operation via JTAG or SPI serial interface control.

Ampliﬁer/Filter Mode

When conﬁgured as a wideband ampliﬁer, an ispPAC30’s OA feedback resistor connection is closed and the feed-

back capacitor set to its minimum value. The feedback capacitance set is required to maintain necessary stability.

When used in ﬁlter mode, the ispPAC30 differs from the wideband ampliﬁer in that it has seven alternative feedback

capacitor values available to form the lowpass ﬁlter corner frequencies. See Table 3 for these values (listed as the

maximum corner frequencies in the precision ﬁlter range table). The capacitor values are trimmed for each device

to achieve an absolute pole frequency with an accuracy guaranteed to that given in the speciﬁcations section. The

ﬁrst order ﬁlter formed using the OA in this manner is not the only way a ﬁlter can be implemented using the

ispPAC30. In the following precision ﬁltering section, an example is given for using an OA in integrator mode and

providing proportional feedback by putting one of the MDAC’s into the feedback loop. When calculating equivalent

time constants for ispPAC30 in ﬁlter mode, a nominal resistance of 50kΩ can be assumed. The frequencies called

out in PAC-Designer that are associated with individual feedback capacitor values are computed based on the

measured –3dB frequency of a single IA/OA combination (gain=1). Again, absolute accuracy is guaranteed as

listed in the ﬁlter speciﬁcations section for all devices shipped.

Integrator Mode

In integrator mode, an OA’s feedback capacitor is closed and the feedback resistor is open. Operation then

becomes that of an integrator, with the expected non-ideal effects of a real operational ampliﬁer (having ﬁnite gain-

bandwidth properties). The gain-phase simulator in the PAC-Designer will give the user a very good representation

of these ﬁrst-order effects on ideal operation. The effective time-constant of any given integrator conﬁguration can

be computed knowing the feedback capacitor value and that an IA in a gain =1 will yield an effective input resis-

tance, R, equal to 50kΩ (1 time constant = 2 x π x RC). This value of R is divided by the gain setting of the IA, so in

a gain of 10 for example, R is equal to 5kΩ. When an MDAC is used as the input to an OA conﬁgured as an integra-

tor, the effective R is equal to 50kΩ divided by the fraction of the input signal passed by the MDAC. For example, if

the MDAC is set to a code that results in passing 50% of the input signal, then R is equal to 50kΩ/0.5 or 100kΩ.

This can, of course, be used to advantage to either extend the effective time constant range or to ﬁne tune it.

Comparator Mode

In comparator mode, both the feedback capacitor and resistor are opened around the OA. Also, the internal com-

pensation of the OA is altered to improve comparator output characteristics. Since only one input is available to the

OA in comparator mode, instead of the normally expected two, a slightly different approach is required to realize a

true comparison function. This is done by using the reference voltage and summing it with the value it is to be com-

pared with. Whenever the input to be compared is greater than the reference input value the OA output is high and

when it is less, the OA output is low. The logic sense of this comparator output can be controlled at will by selecting

either plus or minus gains in the IA/MDAC input sections. When examined closely, it may be observed that compar-

ator mode operation appears identical to that of the integrator mode with a minimum feedback capacitance. This is

true except in comparator mode the output compensation of the OA is altered to get optimum switching times. That

means using the OA in other linear modes without this compensation enabled will likely result in unstable opera-

tion. In PAC-Designer, the default conﬁguration modes will not allow this to happen.

Lattice Semiconductor ispPAC30 Data Sheet

Precision Filter Conﬁguration

Figure 5. Using the ispPAC30 as a Variable Lowpass Filter with Extended Frequency Range

Other ﬁlter frequencies are possible, in addition to the simple ﬁrst order ﬁlters available by selecting the seven avail-

able capacitors of each ispPAC30 output ampliﬁer. The ispPAC30 can be used to implement 1st-order tunable low-

pass ﬁlters over a range of 5kHz to over 600kHz.

Figure 5 shows the circuit for doing so. This circuit operates by using MDAC2 to emulate a programmable feedback

resistor around output ampliﬁer OA1. In this technique, the effective feedback resistance is inversely proportional to

MDAC gain. Because negative feedback is essential to maintaining a stable loop, MDAC2’s gain must be set to

only negative values.

In addition to decreasing the closed-loop bandwidth of OA1, fractional feedback gain also increases the closed

loop DC gain. This increase must be compensated for if the ﬁlter is to maintain unity gain from input to output.

Because there are two MDACs in an ispPAC30, one way to do this is to attenuate the input signal through MDAC1

by the same amount the feedback signal is attenuated by MDAC2. To maintain signal polarity, however, MDAC1

should be set to a positive gain. Deliberately mismatching the values of MDAC1 and MDAC2 also allows one to

alter the gain dynamically, providing a variable gain control feature. The following expressions can be used to esti-

mate the resulting corner frequency (FC) and gain, where FCAP is the frequency associated with the feedback.

FC = |FCAP MDAC2(n%)| (1)

Gain = |MDAC1(n%) / MDAC2(n%)| (2)

Note that MDAC2 (n%) must be negative, and that MDAC1 (n%) should normally be positive for the single-ended

system shown in Figure 5.

Although this technique can be used to control the corner frequency over a range of 128:1, the attenuation caused

by a very low MDAC1 setting can reduce the ﬁlter's overall signal-to-noise ratio and increase effective DC offset

and gain errors to unacceptable levels. Table 3 shows the ranges of corner frequencies that can be realized with

this technique when limiting MDAC2 settings between -10.16% and -100%.

MDAC1

MDAC2

OA1 OUT1

IN1

MDAC1 n%

MDAC2 n%

‘Integrator’ Mode

ispPAC30

VIN

Lattice Semiconductor ispPAC30 Data Sheet

Table 3. Precision Filter Conﬁguration Ranges

Power-Down Mode

The ispPAC30 features a power-down mode whereby the current consumption of the device is reduced to a few

microamps. In this mode, the logic sections of the device are still fully active, but draw very little power. This means

communication can be maintained with the device while it is in the powered-down state. In the analog sections, the

bias currents are reduced or turned off and all sections that can be, are shut down. The analog outputs go to a high

impedance state in power-down mode. The maximum current in shutdown mode and the time required to resume

normal operation all are speciﬁed in the speciﬁcations section of this data sheet. Programming or erasing of the E2

conﬁguration memory is not supported when an ispPAC30 is powered down. Power-down mode is commanded by

lowering the PD pin to a logic low, or by commanding it through JTAG or SPI serial mode commands.

In addition to full power-down mode, either of the output ampliﬁers can be shut down independently of all other cir-

cuitry. This can be done at any time by setting internal E2 bits under JTAG or SPI command to reduce power con-

sumption while the rest of the ispPAC30 is in normal operation. This could also be accomplished at the time the

device is programmed initially via dialog box commands available in the PAC-Designer software. Note: Any IA or

MDAC that has nothing connected to its input is also automatically shut down.

JTAG User Conﬁgurable Bits

There are a number of user-conﬁgured E

bits that control all aspects of ispPAC30. These bits can all be accessed

somewhere in either the pull-down menus or directly in the schematic design entry screen of the PAC-Designer soft-

ware used to interface to the ispPAC30. See the online help associated with the ispPAC30 in PAC-Designer for more

details of how to set/program various operation modes. The list of control E

bits available are listed in Tables 4 and 5.

Feedback

Capacitor #

OA1 Feedback

Capacitor Value (pF)

Minimum Corner

Frequency (kHz)

Maximum Corner

Frequency (kHz)

Frequency Step

(kHz)

1 4.320pF 63 619 4.86

2 7.156pF 41 401 3.13

3 11.97pF 25 250 1.95

4 18.16pF 17 169 1.31

5 27.29pF 11 114 0.88

6 42.37pF 7 74 0.58

7 64.01pF 5 49 0.38

Lattice Semiconductor ispPAC30 Data Sheet

Table 4. JTAG Conﬁguration Register (CFG) Bits

Table 5. JTAG UES Register and ESF Bits

Auto-Calibration Mode

Every time the ispPAC30 is powered up, an automatic auto-calibration sequence is initiated. If this adversely affects

system operation, provisions must be incorporated that minimize the result as auto-calibration cannot be defeated.

The auto-calibration of the ispPAC30 effectively isolates it from external connections and drives the inputs of the

device to 0V and checks to see that there is zero offset at the outputs. This check is done maintaining the input-to-

Symbol Name Description

ARP Bits Analog Routing Pool Bits

These various bits control the interconnect from input pins to IA’s and

MDACs, as well as where the VREF’s go and which input resources are

summed with one OA or the other and whether those OA’s are fed back to

any of the input cells.

CALSEL CAL Level Select

Any of the six input devices, IA1, IA2, IA3, IA4, MDAC1 and MDAC2 can be

selected independently to have auto calibration performed with 0V (default)

or 2.5V applied to their inputs. Because of common-mode errors, choose

the level closest to the operating levels for the lowest offset after an auto-cal

operation.

ENSPIPU Enable SPI Mode Pull-up

This bit can set the device for dedicated SPI mode operation without any

external strapping of the pin being required. Note that normal JTAG opera-

tions cannot occur, such as programming by PAC-Designer when SPI mode

is enabled.

FBCAP Feedback Capacitor Bits to control the seven capacitors of each of OA’s.

IAGAIN Input Ampliﬁer Gain These bits determine the gain of IA1, IA2, IA3, and IA4 (from 1 to 10).

IAPOL Input Ampliﬁer Polarity These bits determine polarity of IA1, IA2, IA3, and IA4 (positive or inverted).

MDACCode MDAC Code Bits to control the code settings of MDAC1 and MDAC2.

MSELPOL MUX Select 1 & 2 Polarity Determines via programmed bits whether a logic high activates input a or b

of either of the multiplexers in front of IA1 and IA4.

MSELPU1/2 MUX Select 1 & 2 PU/PD Programs whether MSEL1 and MSEL2 have internal pull-ups or pull-downs.

OACFG Output Amp Conﬁguration

Determines through various bits whether OA1 and OA2 are acting as ﬁlters

(both feedback resistor and capacitor in circuit), or as integrators (only the

capacitor in feedback), or as comparators (neither feedback resistor or

capacitor in circuit).

OAPD1/2 Output Amp Power-Down

Either or both of the output ampliﬁers can be commanded in power-down

mode without the rest of the chip having to be powered down. In this state,

their outputs are effectively in high-impedance mode.

PU/PD Bits Pull-Up/Down

A number of pins on the PAC30 have internal, programmable pull-up and

pull-down capability. See the pin description table in the speciﬁcation sec-

tion for details on which pins and their default (shipped) states.

TDOSlew Bit TDO Slew Rate

The serial digital data output pin has two output slew rates. The default is

low to reduce digital disruption of the analog circuitry. Sometimes a higher

slew rate is needed, so it is provided as a programmable option.

VREF1, VREF2 Voltage References 1 and 2 These bits set any of the seven available voltage outputs of VREF1 and

VREF2.

Symbol Name Description

UES Bits User Electronic Signature

These are uncommitted E2 bits that can be used to store device information

for future reference. The ispPAC30 contains 16 UES bits. These bits are

accessible from within PAC-Designer by using the Edit Symbol, UES Bits

command.

ESF Electronic Security Fuse

Setting this bit causes all subsequent readouts of the device conﬁguration

to be disabled (JTAG Verify commands). Can be reset by performing a

JTAG user bulk erase command and reprogramming the device. This fea-

ture is used to prevent unauthorized readout of the device’s conﬁguration.

Lattice Semiconductor ispPAC30 Data Sheet

output relationships determined by the current circuit conﬁguration, or in the case of initial turn-on, the stored con-

ﬁguration of the device. During the auto-calibration sequence, the output ampliﬁers are driven to 0V and any offset

error from input to output is calibrated out during a successive-approximation sequence using an internal offset cal-

ibration DAC. This calibration setting is not stored in E2, hence the need to perform calibration every time the device

is powered on. The ground reference for auto-calibration is the SCOM pin. The SCOM pin must be connected to

the GND pin (0V), preferably in a ground plane. Since SCOM must be at, or very near the same potential as GND,

connection to any other point is not recommended.

In addition to the automatic power-on calibration, an auto-calibration sequence can be commanded at any time

using the external CAL logic pin, or by issuing an ENCAL command via the JTAG or SPI serial interface. The timing

and length of the auto-calibration sequence is called out in the speciﬁcation tables of this data sheet.

Note: Two options are available for calibrating each of the four input IA’s and two MDACs, with respect to what input

level is used for auto-calibration. Normally, the inputs are calibrated with a 0V input reference (the default setting).

But when the input common mode voltage is recognized to be closer to 2.5V, the user can specify that 2.5V be set

as the input calibration level. The IA/MDAC inputs can be set to use any combination of 0V or 2.5V as their auto-cal

common-mode reference. This allows the least amount of common-mode error to enter into the offset adjustment,

dependent on the user’s predetermined operating conditions.

SPI vs. JTAG Operation

The JTAG serial interface is usually sufﬁcient for programming the ispPAC30, but complete support is also provided

for the Serial Peripheral Interface (SPI) mode as well. SPI is often chosen when an embedded µController or

µProcessor is used to actively control and conﬁgure an ispPAC30 in-system. SPI mode can be enabled via the

logic level setting of the ENSPI pin. To achieve full control of an ispPAC30, all possible bits used in conﬁguration

(112) must be set each time the conﬁguration is updated. This full set of conﬁguration bits is referred to as the CFG

or conﬁguration register. There is also a shorter conﬁguration register called the CFGQ or quick conﬁguration reg-

ister (40 bits). Here, only the bits most often used in reconﬁguration are accessed. Less commonly used bits, such

as those which determine routing, are left out to simplify and speed up the serial transfer of data. Detailed informa-

tion about SPI mode operation is found in application note AN6027, which is devoted entirely to the subject of SPI

control.

Software-Based Design Environment

Design Entry Software

Designers conﬁgure the ispPAC30 and verify its performance using PAC-Designer, an easy to use, Microsoft Win-

dows compatible program. Circuit designs are entered graphically and then veriﬁed, all within the PAC-Designer

environment. Full device programming is supported using PC parallel port I/O operations and a download cable

connected to the serial programming interface pins of the ispPAC30. A library of conﬁgurations is included with

basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading.

In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer

operation.

The PAC-Designer schematic window, shown below in Figure 6, provides access to all conﬁgurable ispPAC30 ele-

ments via its graphical user interface. All analog input and output pins are represented. Static or non-conﬁgurable

pins such as power, ground, VREFOUT, and the serial digital interface are omitted for clarity. Any element in the

schematic window can be accessed via mouse operations as well as menu commands. When completed, conﬁgu-

rations can be saved, simulated, and downloaded to devices.

Lattice Semiconductor ispPAC30 Data Sheet

Figure 6. PAC-Designer Design Entry Screen

Design Simulation Capability

A powerful feature of PAC-Designer is its simulation capability, enabling quick and accurate veriﬁcation of circuit

operation and performance. Once a circuit is conﬁgured via the interactive design process, gain and phase

response between any input and output can then be simulated. This function is part of the simulator capability

which derives a transfer equation between the two points and then sweeps it over the user-speciﬁed frequency

range. Figure 7 shows a typical screen plot of the gain/phase simulator.

Figure 7. PAC-Designer Simulation Plot Screen

PAC Designer - [ispPAC30.PAC: Schematic]

Ready

File Edit View Tools Options Window Help

OA1

1.02 pF

OA2

1.02 pF

IA1

-1

IA2

IA3

-1

IA4

MDAC1

Code: 00h

-100%

MDAC2

Code: 00h

-100%

VREF1: 64mV

VREF2: 64mV

Digital I/O

Configuration

MSEL1 = 0 (a)

MSEL2 = 0 (a) UES Bits = 0000000000000000

IN1

IN2

IN3

IN4

OUT1

OUT2

PAC Designer - [ispPAC30.PAC: Plot]

Ready

File Edit View Tools Options Window Help

-20

100 1K 10K 100K 1M

Gain Plot

-50

-100

-150

100

150

100 1K 10K 100K 1M

Phase Plot

Lattice Semiconductor ispPAC30 Data Sheet

In-System Programming

The ispPAC30 is an in-system programmable device. This is accomplished by integrating all E2 conﬁguration mem-

ory and SRAM control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial

JTAG interface at normal logic levels. Once a device is programmed, all conﬁguration information is stored on-chip,

in non-volatile E2CMOS memory cells. The speciﬁcs of the IEEE 1149.1 serial interface and all ispPAC30 instruc-

tions are described in the JTAG interface section of this data sheet.

User Electronic Signature

A user electronic signature (UES) feature is included in the E2CMOS memory of the ispPAC30. This consists of 16

bits that can be conﬁgured by the user to store unique data such as ID codes, revision numbers or inventory control

data. The speciﬁcs this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.

Electronic Security

An electronic security “fuse” (ESF) bit is provided in every ispPAC30 device to prevent unauthorized readout of the

E2CMOS conﬁguration bit patterns. Once programmed, this cell prevents further access to the functional user bits

in the device. This cell can only be erased by reprogramming the device, so the original conﬁguration can not be

examined once programmed. Usage of this feature is optional. The speciﬁcs of this feature are discussed in the

IEEE 1149.1 serial interface section of this data sheet.

Production Programming Support

Once a ﬁnal conﬁguration is determined, an ASCII format JEDEC ﬁle can be created using the PAC-Designer soft-

ware. Devices can then be ordered through the usual supply channels with the user’s speciﬁc conﬁguration already

preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production

programming equipment, giving customers a wide degree of freedom and ﬂexibility in production planning.

Evaluation Fixture

Included in the basic ispPAC30 Design Kit is an engineering prototype board that can be connected to the parallel

port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the ispPAC30 and can be

used in real time to check circuit operation as part of the design process. Input and output connections as well as a

“breadboard” circuit area are provided to speed debugging of the circuit. This board is also useful as a program-

ming ﬁxture for prototype and short production runs.

Figure 8. Download to a PC

IEEE Standard 1149.1 Interface

Serial Port Programming Interface Communication with the ispPAC30 is facilitated via an IEEE 1149.1 test access

port (TAP). It is used by the ispPAC30 as a serial programming interface, and not for boundary scan test purposes.

ispDownload

Cable (6')

Other

System

Circuitry

ispPAC30

Device

PAC-Designer

Software

Lattice Semiconductor ispPAC30 Data Sheet

There are no boundary scan logic cells in the ispPAC30 architecture. This does not prevent the ispPAC30 from

functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.

A brief description of the ispPAC30 JTAG interface follows. For complete details of the reference speciﬁcation, refer

to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now

includes IEEE Std 1149.1a-1993). For complete documentation on how to use ispPAC30 in an embedded serial

interface control environment using the SPI protocol, please refer to application note AN6027, Using SPI to Conﬁg-

ure and Control the ispPAC30.

Overview

An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the

ispPAC30. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence,

instructions are shifted into an instruction register which then determines subsequent data input, data output, and

related operations. Device programming is performed by addressing the conﬁguration register, shifting data in, and

then executing a program conﬁguration instruction, after which the data is transferred to internal E2CMOS cells. It is

these non-volatile cells that store the conﬁguration or the ispPAC30. A separate set of SRAM registers are pre-

loaded at turn-on and determine the conﬁguration of the ispPAC30 while it is under power. By cycling the TAP con-

troller through the necessary states, data can also be shifted out of the conﬁguration register to verify the current

ispPAC30 conﬁguration in the control SRAM or of the stored E2 conﬁguration memory. Instructions exist to access

all data registers and perform other internal control operations.

For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 speciﬁcation.

Others are functionally speciﬁed, but inclusion is strictly optional. Finally, there are provisions for optional data reg-

isters deﬁned by the manufacturer. The two required registers are the bypass and boundary-scan registers. For

ispPAC30, the bypass register is a 1-bit shift register that provides a short path through the device when boundary

testing or other operations are not being performed. The ispPAC30, as mentioned, has no boundary scan logic and

therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC30 in

the BYPASS mode to maintain compliance with the speciﬁcation. The optional identiﬁcation register described in

IEEE 1149.1 is also included in the ispPAC30.

Two additional data registers are included in the TAP of the ispPAC30 are the Lattice deﬁned CFG/CFGQ (conﬁgu-

ration and quick conﬁguration) and UES (user electronic signature) registers. Figure 9 shows how the instruction

and various data registers are placed in an ispPAC30.

Figure 9. TAP Registers

TDI TDO

TCK TMS

CFG/CFGQ REGISTER (112/40 bits)

IDCODE REGISTER (32 bits)

BYPASS REGISTER (1 bit)

INSTRUCTION REGISTER (6 bits)

TEST ACCESS PORT

(TAP) LOGIC

OUTPUT

LATCH

UES REGISTER (16 bits)

MULTIPLEXER

E2 NON-VOLATILE MEMORY

SRAM DEVICE CONFIGURATION

Lattice Semiconductor ispPAC30 Data Sheet

TAP Controller Speciﬁcs

The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether

an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a

small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as

shown in Figure 10. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)

becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-

Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But

there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a

reset of the test logic within ﬁve TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on

default state.

Figure 10. TAP States

When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state

and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift

is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruc-

tion shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing

only in their entry points. When either block is entered, the ﬁrst action is a capture operation. For the Data Regis-

ters, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previ-

ously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load

the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a

Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in a

compliant IEEE 1149.1 serial chain.

From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the

Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift

state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via

Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction

Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.

If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test

mode (steady state = test). This is when the device is actually programmed, erased or veriﬁed. All other instructions

are executed in the Update state.

Test-Logic-Rst

Run-Test/Idle Select-DR-Scan Select-IR-Scan

Capture-DR Capture-IR

Shift-DR Shift-IR

Exit1-DR Exit1-IR

Pause-DR Pause-IR

Exit2-DR Exit2-IR

Update-DR Update-IR

0011

11 1

Note: The value shown adjacent to each state transition in this figure

represents the signal present at TMS at the time of a rising edge at TCK.

Lattice Semiconductor ispPAC30 Data Sheet

Test Instructions

Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the

function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-

facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only

the BYPASS and EXTEST instruction code patterns being speciﬁcally called out (all ones and all zeroes respec-

tively). The ispPAC30 contains the required minimum instruction set as well as one from the optional instruction set.

In addition, there are several proprietary instructions that allow the device to be conﬁgured and veriﬁed. For

ispPAC30, the instruction word length is six bits. All ispPAC30 instructions available to users are shown in Table 6.

Table 6. ispPAC30 TAP Instructions Table

BYPASS is one of the three required JTAG instructions. It selects the Bypass Register to be connected between

TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the

ispPAC30. The bit code of this instruction is deﬁned to be all ones by the IEEE 1149.1 standard. With ispPAC30,

any instruction beginning with a one will default to BYPASS.

The JTAG required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between

TDI and TDO. The ispPAC30 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode

whenever this instruction is received. The bit code for this instruction is deﬁned by Lattice as shown in Table 6.

The EXTEST (external test) instruction is JTAG required and would normally place the device into an external

boundary test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO.

Again, since the ispPAC30 has no boundary-scan logic, the device is put in the BYPASS mode to ensure speciﬁca-

tion compatibility. The bit code of this instruction is deﬁned by the 1149.1 standard to be all zeros.

The optional IDCODE (identiﬁcation code) instruction is incorporated in the ispPAC30 and leaves it in its functional

mode when executed. It selects the Device Identiﬁcation Register to be connected between TDI and TDO. The

Identiﬁcation Register is a 32-bit shift register containing information regarding the IC manufacturer, device type

and version code (see Figure 12). Access to the Identiﬁcation Register is immediately available, via a TAP data

Instruction Code Description

EXTEST 000000 External Test. Defaults to BYPASS.

ADDCFG 000001 Address CFG data register (112 bits).

ADDCFGQ 000010 Address CFG Quick data register (40 bits).

ADDUES 000011 Address UES data register (16 bits).

LATCHCFG 000101 Latch CFG register into control SRAM.

READCFG 000110 Read CFG from E2 prior to ADDCFG command.

READUES 001010 Read UES from E2 prior to ADDUES command.

PROGUES 001011 Program shift register contents into UES E2.

PROGCFG 001100 Program shift register contents into CFG E2.

IDCODE 001101 Address Identiﬁcation Code data register.

PROGESF 010001 Program the Electronic Security Fuse bit.

POWERDN 010010 Command a Power Down sequence.

POWERUP 010011 Command a Power Up sequence.

RELOADCFG 010110 Load CFG E2 into control SRAM.

ERASECFG 010111 Erase the CFG/CFGQ E2 memory.

ERASEUES 011011 Erase the UES E2 memory.

ENCAL 011100 Enable a Calibration sequence.

CFGBE 011101 Bulk erase all E2 memory (CFG, UES and ESF).

SAMPLE 011110 Sample/Preload. Default to BYPASS.

BYPASS 111111 Bypass (connect TDI to TDO).

Lattice Semiconductor ispPAC30 Data Sheet

scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this

instruction is deﬁned by Lattice as shown in Table 6.

Figure 12. ID Code

ispPAC30 Speciﬁc Instructions

There are three unique address instructions speciﬁed by Lattice for the ispPAC30. They are ADDCFG (address

CFG), ADDCFGQ (address the CFG quick, or short register), and ADDUES (address the UES or user electronic

signature register). They all select their respective registers to be shifted into through TDI during a Shift-DR opera-

tion. Normal operation of a device is not interrupted by the execution of these instructions. They usually proceed a

program instruction (PROGCFG, or PROGUES) for putting the shifted data into E2 conﬁguration memory or a load

(LATCHCFG) for putting data into the device control SRAM directly. The bit codes for these instructions are found in

Ta b le 6.

There are three unique program instructions speciﬁed by Lattice for the ispPAC30. They are PROGUES (program

UES), PROGCFG (program CFG), and PROGESF (program the electronic security fuse bit). The ﬁrst two store

their respective registers into E2 conﬁguration memory. The third, PROGESF, has no register associated with it. It

simply sets the ESF bit so shifting out CFG information is no longer possible. The only way to recover the ability to

shift out meaningful data is to reset ESF by performing a CFGBE instruction. This, of course will reset the device

conﬁguration as well, but will keep an unauthorized user from learning the bit pattern of the device. Normal opera-

tion of the device is not interrupted during the actual programming time. A programming operation does not begin

until entry of the Run-Test/Idle state. The programming time required to insure data retention is given in the timing

speciﬁcations. The user must ensure that the recommended programming times are observed to ensure speciﬁed

data retention. Note: When initially programming or reprogramming the ispPAC30 with software other than PAC-

Designer, or an authorized third-party programmer (e.g., via microcontroller), refer to the additional Lattice techni-

cal literature covering the required algorithms necessary for complete JTAG and SPI device programming control of

the ispPAC30 (speciﬁc bit assignments, word lengths, etc.).

There are two unique load instructions speciﬁed by Lattice for the ispPAC30. They are the LATCHCFG (load CFG

stored E2 conﬁguration into the ispPAC30 device control SRAM. The LATCHCFG updates all or a portion of the

control SRAM, depending on whether the preceding address CFG was an ADDCFG or ADDCFGQ instruction. The

load operation does not occur until entry of the Run-Test/Idle state. Settling time for the new conﬁguration will

depend on the conﬁguration and time-constants of the particular circuit and can be anywhere from microseconds

to milliseconds. The actual switching to make the change, however, always occurs in less than a microsecond once

the Run-Test/Idle state is entered. The bit codes for these instructions are shown in Table 6.

There are two unique read instructions speciﬁed by Lattice for the ispPAC30. They are the READCFG (read CFG)

and READUES (read user electronic signature). These instructions read data out of the corresponding E2 conﬁgu-

ration memory into either the CFG or UES register. This is done in preparation for either an ADDCFG or ADDUES

and then a subsequent shifting out of the data in these registers. Normal operation of a device is not interrupted by

the execution of these instructions. The bit code for these instructions are shown in Table 6.

The ENCAL (enable calibration) is a unique Lattice instruction that enables the start of an auto-calibration

sequence. This operation causes both output ampliﬁers to go to 0V until the calibration sequence is completed

MSB

XXXX / 0000 0001 0011 0000 / 0000 0100 001 / 1

LSB

Version

(4-bits)

E2 Configured

Part Number

(16-bits)

0130h = PAC30

JEDEC Manfacturer

Identity Code for

Lattice Semiconductor

(11-bits)

Constant 1

(1-bit)

per 1149.1-1990

Lattice Semiconductor ispPAC30 Data Sheet

(see timing speciﬁcations). As with the programming instructions above, calibration does not begin until entry of the

Run-Test/Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This

means the state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration

would be to not clock the TAP during critical analog operations. The ﬁrst several milliseconds of the calibration rou-

tine are consumed waiting for conﬁgurations to settle, though, leaving more than enough time to clock the TAP back

to the Test-Logic-Reset state. The bit code for this instruction is shown in Table 6.

The POWERDN (power down command) and POWERUP (power up command) are unique instructions speciﬁed

by Lattice for the ispPAC30 to command the normal and low-power or shut-down states of the device. As with other

instructions above, these instructions do not begin until entry of the Run-Test/Idle state. Timing for coming out of

power-down mode as well as supply current used in this mode are speciﬁed in the spec tables of this data sheet.

All analog is shut down and outputs are in a high-impedance mode during power-down state. Device digital cir-

cuitry is not shut down and consumes no power unless it is clocked, and even then only a minimal amount. The bit

code for these instructions is shown in Table 6.

The last unique Lattice instructions are ERASECFG (erase or clear CFG), ERASEUES (erase or clear the UES)

and CFGBE (erase or clear all user memory). These instructions set all the bits of their respective E2 storage cells

to all zeros. Operation of the device is not interrupted during any of these instructions. The CFGBE is used to return

all user controlled bits to a zero state at the same time (CFG, UES and ESF) and is the only way to erase the ESF

bit. The condition after a CFGBE instruction is the default condition of parts shipped from the factory. The same

programming timing constraints apply to these instructions as for the PROG programming instructions listed above.

The bit code for these instructions are shown in Table 6. Important Note: Programming E2 conﬁguration memory

can only program ones into a device, not zeros. Erase instructions are required to change all bits to zero ﬁrst. The

normal sequence to re-program E2 conﬁguration memory is ﬁrst erase either the CFG or UES E2 cells and then

program them with the desired bit sequence and PRG instructions.

Once again, the JTAG PROG, LATCHCFG, ERASE, POWERUP, POWERDN, RELOADCFG and ENCAL instruc-

tions do not execute until entry of the Run-Test/Idle state. All other instructions are executed in the Update-IR state,

allowing shifts and other operations to occur without having to leave the inner loop of the JTAG controller.

It is recommended that when all serial interface operations are completed, the TAP controller be reset and left in

the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best ana-

log performance possible by minimizing the effects of digital logic “feed-through.”

Lattice Semiconductor ispPAC30 Data Sheet

Package Diagrams

28-Pin PDIP (Dimensions in inches)

24-Pin SOIC (Dimensions in millimeters)