www.infineon.com C164 Microcontrollers C166 Family 16-Bit Single-Chip Microcontroller C164 Data Sheet 1999-08 Preliminary C164 Revision History: Previous Versions: Page 1999-08 Preliminary 1998-02 04.97 (C161CI / Preliminary) (C161CI / Advance Information) Subjects Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Edition 1999-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53 D-81541 Munchen (c) Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. C166 Family of High-Performance CMOS 16-Bit Microcontrollers C164 Preliminary C164 16-Bit Microcontroller * High Performance 16-bit CPU with 4-Stage Pipeline - 80 ns Instruction Cycle Time at 25 MHz CPU Clock - 400 ns Multiplication (16 x 16 bit), 800 ns Division (32 / 16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 MBytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area * 16-Priority-Level Interrupt System with 32/33 Sources, Sample-Rate down to 40 ns * 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) * Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp. * On-Chip Memory Modules - 2 KBytes On-Chip Internal RAM (IRAM) - 2 KBytes On-Chip Extension RAM (XRAM) - 64 KBytes On-Chip ROM or Program Flash1) (Endur: 100 Prog./Er. Cycles min.) - 4 KBytes On-Chip DataFlash/EEPROM1) (Endur.: 100,000 Prog./Er. Cycles min.) * On-Chip Peripheral Modules - 8-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 s - Two Multi-Functional General Purpose Timer Units with 5 Timers - Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) - 8-Channel 16-bit General Purpose Capture/Compare Unit (CAPCOM2) - Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel) - On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full-CAN / Basic CAN) * Up to 4 MBytes External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width - Four Optional Programmable Chip-Select Signals * Idle and Power Down Modes with Flexible Power Management * Programmable Watchdog Timer and Oscillator Watchdog 1) Available only on devices in Flash technology. Data Sheet 1 1999-08 & * On-Chip Real Time Clock * Up to 59 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis * Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards * On-Chip Bootstrap Loader * 80-Pin MQFP Package, 0.65 mm pitch This document describes several derivatives of the C164 group. The table below enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 C164 Derivative Synopsis Derivative Program Memory EEPROM CAPCOM6 CAN Interf. SAK-C164CI-8RM 64 KByte ROM --- Full function CAN1 SAK-C164SI-8RM 64 KByte ROM --- Full function --- SAK-C164CL-8RM 64 KByte ROM --- Reduced fct. CAN1 SAK-C164SL-8RM 64 KByte ROM --- Reduced fct. --- SAK-C164CH-8FM 64 KByte Flash 4 KByte Full function CAN1 SAK-C164SH-8FM 64 KByte Flash 4 KByte Full function --- For simplicity all versions are referred to by the term C164 throughout this document. Data Sheet 2 1999-08 & Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * * * the derivative itself, i.e. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C164 please refer to the Product Catalog Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Introduction The C164 is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip program/data memory. The C164 derivative is especially suited for cost sensitive applications. VDD VSS PORT0 16 bit XTAL1 XTAL2 PORT1 16 bit RSTIN RSTOUT Port 3 9 bit NMI & EA Port 8 4 bit ALE RD WR Port 5 8 bit VAREF Figure 1 Data Sheet Port 4 6 bit VAGND Logic Symbol 3 1999-08 & VAGND P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P8.3/CC19IO / * P8.2/CC18IO / * P8.1/CC17IO / * P8.0/CC16IO / * NMI RSTOUT RSTIN P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11/EX3IN/T7IN /EX2IN P1H.2/A10/ P1H.1/A9/ /EX1IN VDD Pin Configuration MQFP Package (top view) 6 2 3 & & 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 6 2 3 & & 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 & 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS P1H.0/A8/&&326/EX0IN P1L.7/A7/&75$3 P1L.6/A6/COUT63 VSS XTAL1 XTAL2 VDD P1L.5/A5/COUT62 P1L.4/A4/CC62 P1L.3/A3/COUT61 P1L.2/A2/CC61 P1L.1/A1/COUT60 P1L.0/A0/CC60 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 Vss VDD P4.3/A19/CS0 * /P4.5/A20 * /P4.6/A21 RD WR/WRL ALE VPP/EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P0H.0/AD8 P0H.1/AD9 P0H.2/AD10 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VAREF P5.4/AN4/T2EUD P5.5/AN5/T4EUD P5.6/AN6/T2IN P5.7/AN7/T4IN VSS VDD P3.4/T3EUD P3.6/T3IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT/FOUT P4.0/A16/CS3 P4.1/A17/CS2 P4.2/A18/CS1 VSS Figure 2 *) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them. Table 2 on the pages below lists the possible assignments. The marked input signals are available only in devices with a full function CAPCOM6. They are not available in devices with a reduced CAPCOM6. Data Sheet 4 1999-08 & Table 2 Pin Definitions and Functions Symbol Pin Num. Input Outp. Function P5 I Port 5 is an 8-bit input-only port with Schmitt-Trigger charact. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp. AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN6, T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture AN7, T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 76 77 78 79 2 3 4 I I I I I I I P5.7 5 I P3 IO P3.4 P3.6 P3.8 P3.9 P3.10 P3.11 P3.12 8 9 10 11 12 13 14 P3.13 P3.15 15 16 Data Sheet I I I/O I/O O I/O O O I/O O O Port 3 is a 9-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T3EUD GPT1 Timer T3 External Up/Down Control Input T3IN GPT1 Timer T3 Count/Gate Input MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) External Memory High Byte Enable Signal, BHE External Memory High Byte Write Strobe WRH SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (=CPU Clock) FOUT Programmable Frequency Output 5 1999-08 & Table 2 Pin Definitions and Functions (continued) Symbol Pin Num. Input Outp. Function P4 IO Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines: 1) A16 Least Significant Segment Address Line, Chip Select 3 Output CS3 A17 Segment Address Line, Chip Select 2 Output CS2 A18 Segment Address Line, Chip Select 1 Output CS1 A19 Segment Address Line, Chip Select 0 Output CS0 A20 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A21 Most Significant Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output O O O O O O O O O I O O P4.0 17 P4.1 18 P4.2 19 P4.3 22 P4.5 23 P4.6 24 RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/ WRL 26 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. ALE 27 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 28 I External Access Enable pin. A low level at this pin during and after Reset forces the C164 to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. Data Sheet 6 1999-08 & Table 2 Pin Definitions and Functions (continued) Symbol Pin Num. Input Outp. PORT0 IO P0L.0-7 29 36 P0H.0-7 37-39, 42-46 Data Sheet Function PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 7 1999-08 & Table 2 Pin Definitions and Functions (continued) Symbol Pin Num. Input Outp. PORT1 IO P1L.0-7 47-52, 57-59 P1H.0-7 59, 62-68 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 47 48 49 50 51 52 57 58 I/O O I/O O I/O O O I P1H.0 59 P1H.1 62 P1H.2 63 P1H.3 64 I I I I I I I P1H.4 P1H.5 P1H.6 P1H.7 65 66 67 68 I/O I/O I/O I/O Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alt. functions: CC60 CAPCOM6: Input / Output of Channel 0 COUT60 CAPCOM6: Output of Channel 0 CC61 CAPCOM6: Input / Output of Channel 1 COUT61 CAPCOM6: Output of Channel 1 CC62 CAPCOM6: Input / Output of Channel 2 COUT62 CAPCOM6: Output of Channel 2 COUT63 Output of 10-bit Compare Channel CAPCOM6: Trap Input **) CTRAP CTRAP is an input pin with an internal pullup resistor. A low level on this pin switches the compare outputs of the CAPCOM6 unit to the logic level defined by software. CC6POS0 CAPCOM6: Position 0 Input, **) EX0IN Fast External Interrupt 0 Input CC6POS1 CAPCOM6: Position 1 Input, **) EX1IN Fast External Interrupt 1 Input CC6POS2 CAPCOM6: Position 2 Input, **) EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input, T7IN CAPCOM2: Timer T7 Count Input CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp. CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp. CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp. CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp. Note: The marked (**) input signals are available only in devices with a full function CAPCOM6. Data Sheet 8 1999-08 & Table 2 Pin Definitions and Functions (continued) Symbol Pin Num. Input Outp. Function XTAL2 XTAL1 54 55 O I XTAL2: XTAL1: RSTIN 69 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C164. An internal pullup resistor permits power-on reset using only a capacitor connected to 9SS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table. RST OUT 70 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 71 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C164 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Data Sheet Output of the oscillator amplifier circuit. Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. 9 1999-08 & Table 2 Pin Definitions and Functions (continued) Symbol Pin Num. Input Outp. Function P8 IO I/O I I/O O I/O I I/O O Port 8 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). Port 8 pins provide inputs/ outputs for CAPCOM2 and serial interface lines. 1) CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output P8.0 72 P8.1 73 P8.2 74 P8.3 75 9AREF 9AGND 9DD 1 - Reference voltage for the A/D converter. 80 - Reference ground for the A/D converter. 7, 21, 40, 53, 61 Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode. 9SS 6, 20, 41, 56, 60 Digital Ground. 1) The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected. Note: The following behaviour differences must be observed when the bidirectional reset is active: * Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. * The reset indication flags always indicate a long hardware reset. * The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. * Pin RSTIN may only be connected to external reset devices with an open drain output driver. * A short hardware reset is extended to the duration of the internal reset sequence. Data Sheet 10 1999-08 & Functional Description The architecture of the C164 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164. Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section). &&RUH 32 16 Data &38&RUH &38 Instr./Data Flash Dual Port 64K 64 KB Internal ROM (C164CI-8RM) ROM or or OTP (C164CI-8EM) 16 Data Internal RAM .%\WH 16 PLL-Oscillator 16 RTC up to 12 ext. IR Interrupt Bus WDT 16 Peripheral Data External Bus (8/16 bit; MUX only) & XBUS Control 8Channel 10-Bit ADC USART Sync. Channel (SPI) GPT 1 ASC SSC T3 BRG BRG T4 T2 General Purpose Capture/Compare Unit 8-Channel 16-bit Capture/Compare Unit (CAPCOM2) Capture/Compare Unit for PWM Generation (CAPCOM6) Timer 13 Port 0 16 Interrupt Controller Timer 8 Full-CAN Interface V2.0B active 3(& External Instr./Data Timer 7 P4.5/CAN_RxD P4.6/CAN_TxD progr. Multiplier: 0.5; 1; 1.5; 2; 2.5; 3; 4; 5 XBUS (16-bit NON MUX Data / Addresses) XTAL 1 Compare Channel 3/6 Capture/Compare Channels 5 Port 4 Port 5 Port 3 8 9 Port 8 Port 1 C164CI V1.2 Figure 3 Data Sheet 4 16 Block Diagram 11 1999-08 & Memory Organization The memory space of the C164 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C164 incorporates 64 KBytes of on-chip ROM or Flash memory for code or constant data. The Flash memory is organized as one 16 KByte sector, two 8 KByte sectors, and one 32 KByte sector. Each sector can be separately write protected, erased and programmed (in blocks of 64 Byte). The lower 32 KBytes of the on-chip ROM or Flash memory can be mapped either to segment 0 or segment 1. 2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. 4 KBytes of on-chip Data Flash memory, organized as four 1 KByte sectors, provide EEPROM functionality. Each byte/word can be erased or programmed separately. Each sector can be erased as a unit. The low granularity (byte/word) and the high endurance of the DataFlash/EEPROM support the non-volatile storage of changing system data. Note: The DataFlash/EEPROM is only incorporated in the Flash versions. In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller. Data Sheet 12 1999-08 & External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - - - - 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 4 external CS signals (3 windows plus default) can be generated in order to save external glue logic. The C164 offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). For applications which require less than 4 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used. Note: When the on-chip CAN Module is activated on Port 4 the segment address output is limited to 4 bits (i.e. A19...A16) due to the CAN interface pins. Data Sheet 13 1999-08 & Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C164's instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the socalled `Jump Cache', reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. Figure 4 Data Sheet CPU Block Diagram 14 1999-08 & The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C164 instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Data Sheet 15 1999-08 & Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C164 is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C164 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C164 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C164 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR). Data Sheet 16 1999-08 & Table 3 C164 Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 0 CC8IR CC8IE CC8INT 00'0060H 18H External Interrupt 1 CC9IR CC9IE CC9INT 00'0064H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00'0068H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00'006CH 1BH GPT1 Timer 2 T2IR T2IE T2INT 00'0088H 22H GPT1 Timer 3 T3IR T3IE T3INT 00'008CH 23H GPT1 Timer 4 T4IR T4IE T4INT 00'0090H 24H A/D Conversion Complete ADCIR ADCIE ADCINT 00'00A0H 28H A/D Overrun Error ADEIR ADEIE ADEINT 00'00A4H 29H ASC0 Transmit S0TIR S0TIE S0TINT 00'00A8H 2AH ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00'011CH 47H ASC0 Receive S0RIR S0RIE S0RINT 00'00ACH 2BH ASC0 Error S0EIR S0EIE S0EINT 00'00B0H 2CH SSC Transmit SCTIR SCTIE SCTINT 00'00B4H 2DH SSC Receive SCRIR SCRIE SCRINT 00'00B8H 2EH SSC Error SCEIR SCEIE SCEINT 00'00BCH 2FH CAPCOM Register 16 CC16IR CC16IE CC16INT 00'00C0H 30H CAPCOM Register 17 CC17IR CC17IE CC17INT 00'00C4H 31H CAPCOM Register 18 CC18IR CC18IE CC18INT 00'00C8H 32H CAPCOM Register 19 CC19IR CC19IE CC19INT 00'00CCH 33H CAPCOM Register 20 CC20IR CC20IE CC20INT 00'00D0H 34H CAPCOM Register 21 CC21IR CC21IE CC21INT 00'00D4H 35H CAPCOM Register 22 CC22IR CC22IE CC22INT 00'00D8H 36H CAPCOM Register 23 CC23IR CC23IE CC23INT 00'00DCH 37H CAPCOM Register 24 CC24IR CC24IE CC24INT 00'00E0H 38H CAPCOM Register 25 CC25IR CC25IE CC25INT 00'00E4H 39H CAPCOM Register 26 CC26IR CC26IE CC426NT 00'00E8H 3AH CAPCOM Register 27 CC27IR CC27IE CC27INT 00'00ECH 3BH CAPCOM Register 28 CC28IR CC28IE CC28INT 00'00E0H 3CH Data Sheet 17 1999-08 & Table 3 C164 Interrupt Nodes (continued) Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 29 CC29IR CC29IE CC29INT 00'0110H 44H CAPCOM Register 30 CC30IR CC30IE CC30INT 00'0114H 45H CAPCOM Register 31 CC31IR CC31IE CC31INT 00'0118H 46H CAPCOM Timer 7 T7IR T7IE T7INT 00'00F4H 3DH CAPCOM Timer 8 T8IR T8IE T8INT 00'00F8H 3EH CAPCOM 6 Interrupt CC6IR CC6IE CC6INT 00'00FCH 3FH CAPCOM 6 Timer 12 T12IR T12IE T12INT 00'0134H 4DH CAPCOM 6 Timer 13 T13IR T13IE T13INT 00'0138H 4EH CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00'013CH 4FH CAN Interface 1 XP0IR XP0IE XP0INT 00'0100H 40H DataFlash Termination XP1IR XP1IE XP1INT 00'0104H 41H 1) PLL Unlock / RTC XP3IE XP3INT 00'010CH 43H XP3IR 1) This interrupt node is only available in the Flash devices. Data Sheet 18 1999-08 & The C164 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Table 4 Hardware Trap Summary Exception Condition Trap Flag Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Trap Vector Vector Location Trap Trap Number Prio RESET RESET RESET 00'0000H 00'0000H 00'0000H 00H 00H 00H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H 02H 04H 06H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 0AH 0AH 0AH 0AH 0AH I I I I I 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H Reserved [2CH - 3CH] [0BH - 0FH] Software Traps: TRAP Instruction Any Any [00'0000H - [00H - 00'01FCH] 7FH] in steps of 4H Data Sheet 19 Current CPU Priority 1999-08 & The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array. Each dual purpose capture/compare register, which may be individually allocated to either CAPCOM timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Registers CC16 & CC24 pin CC16IO Registers CC17 & CC25 pin CC17IO Registers CC18 & CC26 pin CC18IO Registers CC19 & CC27 pin CC19IO Data Sheet 20 1999-08 & The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM output signal and is further used to modulate the capture/ compare output signals. In capture mode the contents of compare timer 12 is stored in the capture registers upon a signal transition at pins CCx. Period Register T12P Mode Select Reg. CC6MSEL Offset Register T12OF CC Channel 0 CC60 Compare Timer T12 16-bit 1) Control fCPU Prescaler Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked by the prescaled CPU clock. CC Channel 1 CC61 Trap Register CTRAP CC60 COUT60 Port Control Logic CC61 COUT61 CC62 COUT62 CC Channel 2 CC62 fCPU Prescaler Control Register CTCON Compare Timer T13 10-bit 1) Compare Register CMP13 COUT63 Block Commutation Control CC6MCON.H Period Register T13P CC6POS0 CC6POS1 CC6POS2 MCB04109.VSD 1) These registers are not directly accessible. The period and offset registers are loading a value into the timer registers. The shaded blocks are available in the full function module only. Figure 5 CAPCOM6 Block Diagram For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). Note: Multichannel signal generation is provided only in devices with a full CAPCOM6. Data Sheet 21 1999-08 & General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers (GPT1). Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Data Sheet 22 1999-08 & T2EUD fCPU U/D 2n : 1 T2IN fCPU Interrupt Request GPT1 Timer T2 T2 Mode Control Reload Capture Interrupt Request 2n : 1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 U/D T4EUD Figure 6 Data Sheet Interrupt Request MCT02141 Block Diagram of GPT1 23 1999-08 & Real Time Clock The Real Time Clock (RTC) module of the C164 consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (IRTC = IOSC / 32) and is therefore independent from the selected clock generation mode of the C164. All timers count up. The RTC module can be used for different purposes: * System clock to determine the current time and date * Cyclic time based interrupt * 48-bit timer for long term measurements T14REL Reload T14 8:1 fRTC Interrupt Request RTCL Figure 7 RTCL RTC Block Diagram Note: The registers associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed. Data Sheet 24 1999-08 & A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C164 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable). Data Sheet 25 1999-08 & Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 780 KBaud and half-duplex synchronous communication at up to 3.1 MBaud @ 25 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 6.25 Mbaud @ 25 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Data Sheet 26 1999-08 & CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the CPU clock signal and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus transceiver. The interface pins are assigned via software. Note: When the CAN interface is assigned to Port 4, the respective segment address lines on Port 4 cannot be used. This will limit the external address space. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2/ 4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 s and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz). Data Sheet 27 1999-08 & Parallel Ports The C164 provides up to 59 IO lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The other IO ports operate in push/pull mode. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of the CAPCOM unit, and/or serve as external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. Port 4 or port 8 may be used for the CAN interface lines. The edge characteristics (transition time) and driver characteristics (output current) of the C164's port drivers can be selected via the Port Output Control registers (POCONx). Data Sheet 28 1999-08 & Instruction Set Summary The table below lists the instructions of the C164 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailled description of each instruction. Table 6 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Data Sheet Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR 4 4 29 2/4 2/4 2/4 2 2 2 2 1999-08 & Table 6 Instruction Set Summary (continued) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Bytes 2/4 2/4 2/4 4 Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met 4 4 4 4 4 Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack und update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation 4 4 30 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2 1999-08 & Special Function Registers Overview The following table lists all SFRs which are implemented in the C164 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-Peripherals are marked with the letter "X" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Table 7 Name C164 Registers, Ordered by Name Physical Address 8-Bit Description Addr. Reset Value ADCIC b FF98H CCH A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0H D0H A/D Converter Control Register 0000H ADDAT FEA0H 50H A/D Converter Result Register 0000H ADDAT2 F0A0H E 50H A/D Converter 2 Result Register 0000H ADDRSEL1 FE18H 0CH Address Select Register 1 0000H ADDRSEL2 FE1AH 0DH Address Select Register 2 0000H ADDRSEL3 FE1CH 0EH Address Select Register 3 0000H ADDRSEL4 FE1EH 0FH Address Select Register 4 0000H b FF9AH CDH A/D Converter Overrun Error Interrupt Control Register 0000H BUSCON0 b FF0CH 86H Bus Configuration Register 0 0000H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000H BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000H BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000H ADEIC C1BTR EF04H X --- CAN1 Bit Timing Register C1CSR EF00H X --- CAN1 Control / Status Register C1GMS EF06H X --- CAN1 Global Mask Short UFUUH C1LARn EFn4H X --- CAN Lower Arbitration Register (msg. n) UUUUH C1LGML EF0AH X --- CAN Lower Global Mask Long UUUUH Data Sheet 31 UUUUH XX01H 1999-08 & Table 7 C164 Registers, Ordered by Name (continued) Name Physical Address 8-Bit Description Addr. Reset Value C1LMLM EF0EH X --- CAN Lower Mask of Last Message C1MCFGn EFn6H X --- CAN Message Configuration Register (msg. n) C1MCRn EFn0H X --- CAN Message Control Register (msg. n) UUUUH C1PCIR EF02H X --- CAN1 Port Control / Interrupt Register XXXXH C1UARn EFn2H X --- CAN Upper Arbitration Register (msg. n) UUUUH C1UGML EF08H X --- CAN Upper Global Mask Long UUUUH C1UMLM EF0CH X --- CAN Upper Mask of Last Message UUUUH UUUUH UUH CC10IC b FF8CH C6H External Interrupt 2 Control Register 0000H CC11IC b FF8EH C7H External Interrupt 3 Control Register 0000H FE60H 30H CAPCOM Register 16 0000H b F160H E B0H CAPCOM Reg. 16 Interrupt Ctrl. Reg. 0000H FE62H 31H CAPCOM Register 17 0000H b F162H E B1H CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000H FE64H 32H CAPCOM Register 18 0000H b F164H E B2H CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000H FE66H 33H CAPCOM Register 19 0000H b F166H E B3H CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000H FE68H 34H CAPCOM Register 20 0000H b F168H E B4H CAPCOM Reg. 20 Interrupt Ctrl. Reg. 0000H FE6AH 35H CAPCOM Register 21 0000H b F16AH E B5H CAPCOM Reg. 21 Interrupt Ctrl. Reg. 0000H FE6CH 36H CAPCOM Register 22 0000H b F16CH E B6H CAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000H FE6EH 37H CAPCOM Register 23 0000H b F16EH E B7H CAPCOM Reg. 23 Interrupt Ctrl. Reg. 0000H FE70H 38H CAPCOM Register 24 0000H b F170H E B8H CAPCOM Reg. 24 Interrupt Ctrl. Reg. 0000H FE72H 39H CAPCOM Register 25 0000H b F172H E B9H CAPCOM Reg. 25 Interrupt Ctrl. Reg. 0000H CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC Data Sheet 32 1999-08 & Table 7 C164 Registers, Ordered by Name (continued) Name Physical Address 8-Bit Description Addr. Reset Value CC26 FE74H 3AH CAPCOM Register 26 0000H b F174H E BAH CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000H FE76H 3BH CAPCOM Register 27 0000H b F176H E BBH CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000H FE78H 3CH CAPCOM Register 28 0000H b F178H E BCH CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000H FE7AH 3DH CAPCOM Register 29 0000H b F184H E C2H CAPCOM Reg. 29 Interrupt Ctrl. Reg. 0000H FE7CH 3EH CAPCOM Register 30 0000H b F18CH E C6H CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000H FE7EH 3FH CAPCOM Register 31 0000H b F194H E CAH CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000H CC60 FE30H 18H CAPCOM 6 Register 0 0000H CC61 FE32H 19H CAPCOM 6 Register 1 0000H CC62 FE34H 1AH CAPCOM 6 Register 2 0000H CC6EIC b F188H E C4H CAPCOM 6 Emergency Interrrupt Control Register 0000H CC6IC b F17EH E BFH CAPCOM 6 Interrupt Control Register 0000H CC6MCON b FF32H 99H CAPCOM 6 Mode Control Register 00FFH CC6MIC b FF36H 9BH CAPCOM 6 Mode Interrupt Ctrl. Reg. 0000H F036H E 1BH CAPCOM 6 Mode Select Register 0000H CC8IC b FF88H C4H External Interrupt 0 Control Register 0000H CC9IC b FF8AH C5H External Interrupt 1 Control Register 0000H CCM4 b FF22H 91H CAPCOM Mode Control Register 4 0000H CCM5 b FF24H 92H CAPCOM Mode Control Register 5 0000H CCM6 b FF26H 93H CAPCOM Mode Control Register 6 0000H CCM7 b FF28H 94H CAPCOM Mode Control Register 7 0000H CMP13 FE36H 1BH CAPCOM 6 Timer 13 Compare Reg. 0000H CP FE10H 08H CPU Context Pointer Register FC00H CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CC6MSEL Data Sheet 33 1999-08 & Table 7 C164 Registers, Ordered by Name (continued) Name Physical Address 8-Bit Description Addr. Reset Value CSP FE08H 04H CPU Code Segment Pointer Register (8 bits, not directly writeable) 0000H CTCON b FF30H 98H CAPCOM 6 Compare Timer Ctrl. Reg. 1010H DP0H b F102H E 81H P0H Direction Control Register 00H DP0L b F100H E 80H P0L Direction Control Register 00H DP1H b F106H E 83H P1H Direction Control Register 00H DP1L b F104H E 82H P1L Direction Control Register 00H DP3 b FFC6H E3H Port 3 Direction Control Register 0000H DP4 b FFCAH E5H Port 4 Direction Control Register 00H DP8 b FFD6H EBH Port 8 Direction Control Register 00H DPP0 FE00H 00H CPU Data Page Pointer 0 Reg. (10 bits) 0000H DPP1 FE02H 01H CPU Data Page Pointer 1 Reg. (10 bits) 0001H DPP2 FE04H 02H CPU Data Page Pointer 2 Reg. (10 bits) 0002H DPP3 FE06H 03H CPU Data Page Pointer 3 Reg. (10 bits) 0003H EXICON b F1C0H E E0H External Interrupt Control Register 0000H EXISEL b F1DAH E EDH External Interrupt Source Select Reg. 0000H IDCHIP F07CH E 3EH Identifier XXXXH IDMANUF F07EH E 3FH Identifier 1820H IDMEM F07AH E 3DH Identifier XXXXH IDPROG F078H E 3CH Identifier XXXXH ISNC b F1DEH E EFH Interrupt Subnode Control Register 0000H MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H MDH FE0CH 06H CPU Multiply Divide Reg. - High Word 0000H MDL FE0EH 07H CPU Multiply Divide Reg. - Low Word 0000H ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000H ODP4 b F1CAH E E5H Port 4 Open Drain Control Register 00H ODP8 b F1D6H E EBH Port 8 Open Drain Control Register 00H ONES b FF1EH 8FH Constant Value 1's Register (read only) FFFFH P0H b FF02H 81H Port 0 High Reg. (Upper half of PORT0) 00H P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00H Data Sheet 34 1999-08 & Table 7 Name C164 Registers, Ordered by Name (continued) Physical Address 8-Bit Description Addr. Reset Value P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00H P1L b FF04H 82H Port 1 Low Reg. (Lower half of PORT1) 00H P3 b FFC4H E2H Port 3 Register P4 b FFC8H E4H Port 4 Register (7 bits) P5 b FFA2H D1H Port 5 Register (read only) P5DIDIS b FFA4H D2H Port 5 Digital Input Disable Register P8 b FFD4H EAH Port 8 Register (8 bits) PECC0 FEC0H 60H PEC Channel 0 Control Register 0000H PECC1 FEC2H 61H PEC Channel 1 Control Register 0000H PECC2 FEC4H 62H PEC Channel 2 Control Register 0000H PECC3 FEC6H 63H PEC Channel 3 Control Register 0000H PECC4 FEC8H 64H PEC Channel 4 Control Register 0000H PECC5 FECAH 65H PEC Channel 5 Control Register 0000H PECC6 FECCH 66H PEC Channel 6 Control Register 0000H PECC7 FECEH 67H PEC Channel 7 Control Register 0000H PICON b F1C4H E E2H Port Input Threshold Control Register 0000H POCON0H F082H E 41H Port P0H Output Control Register 0000H POCON0L F080H E 40H Port P0L Output Control Register 0000H POCON1H F086H E 43H Port P1H Output Control Register 0000H POCON1L F084H E 42H Port P1L Output Control Register 0000H POCON20 F0AAH E 55H Dedicated Pin Output Control Register 0000H POCON3 F08AH E 45H Port P3 Output Control Register 0000H POCON4 F08CH E 46H Port P4 Output Control Register 0000H POCON8 F092H E 49H Port P8 Output Control Register 0000H b FF10H 88H CPU Program Status Word 0000H PTCR F0AEH E 57H Port Temperature Compensation Reg. 0000H RP0H b F108H E 84H System Startup Config. Reg. (Rd. only) RSTCON b F1E0H E --- Reset Control Register PSW 0000H 00H XXXXH 0000H 00H XXH 00XXH RTCH F0D6H E 6BH RTC High Register no RTCL F0D4H E 6AH RTC Low Register no Data Sheet 35 1999-08 & Table 7 C164 Registers, Ordered by Name (continued) Name Physical Address 8-Bit Description Addr. Reset Value S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Ctrl. Reg. 0000H FEB2H 59H Serial Channel 0 Receive Buffer Reg. (read only) S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H FEB0H 58H Serial Channel 0 Transmit Buffer Reg. (write only) 0000H b FF6CH B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12H 09H CPU System Stack Pointer Register FC00H SSCBR F0B4H E 5AH SSC Baudrate Register 0000H SSCCON b FFB2H D9H SSC Control Register 0000H SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000H SSCRB F0B2H E 59H SSCRIC b FF74H BAH SSCTB F0B0H E 58H SSCTIC b FF72H STKOV STKUN S0RBUF S0TBUF S0TIC SSC Receive Buffer XXXXH XXXXH SSC Receive Interrupt Control Register 0000H SSC Transmit Buffer 0000H B9H SSC Transmit Interrupt Control Register 0000H FE14H 0AH CPU Stack Overflow Pointer Register FA00H FE16H 0BH CPU Stack Underflow Pointer Register FC00H b FF12H 89H CPU System Configuration Register SYSCON1 b F1DCH E EEH CPU System Configuration Register 1 0000H SYSCON2 b F1D0H E E8H CPU System Configuration Register 2 0000H SYSCON3 b F1D4H E EAH CPU System Configuration Register 3 0000H T12IC b F190H E C8H CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 0000H F034H E 1AH CAPCOM 6 Timer 12 Offset Register 0000H SYSCON T12OF Data Sheet 36 1) 0xx0H 1999-08 & Table 7 C164 Registers, Ordered by Name (continued) Name Physical Address T12P F030H T13IC b F198H 8-Bit Description Addr. Reset Value E 18H CAPCOM 6 Timer 12 Period Register 0000H E CCH CAPCOM 6 Timer 13 Interrupt Ctrl. Reg. 0000H 0000H T13P F032H E 19H CAPCOM 6 Timer 13 Period Register T14 F0D2H E 69H RTC Timer 14 Register no T14REL F0D0H E 68H RTC Timer 14 Reload Register no T2 FE40H 20H GPT1 Timer 2 Register 0000H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H FE42H 21H GPT1 Timer 3 Register 0000H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000H FE44H 22H GPT1 Timer 4 Register 0000H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000H F050H E 28H CAPCOM Timer 7 Register 0000H T78CON b FF20H 90H CAPCOM Timer 7 and 8 Ctrl. Reg. 0000H T7IC b F17AH E BDH CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000H T7REL F054H E 2AH CAPCOM Timer 7 Reload Register 0000H T8 F052H E 29H CAPCOM Timer 8 Register 0000H b F17CH E BEH CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000H F056H E 2BH CAPCOM Timer 8 Reload Register 0000H T3 T4 T7 T8IC T8REL TFR b FFACH D6H Trap Flag Register 0000H TRCON b FF34H 9AH CAPCOM 6 Trap Enable Ctrl. Reg. 00XXH WDT FEAEH 57H Watchdog Timer Register (read only) 0000H WDTCON FFAEH D7H Watchdog Timer Control Register XP0IC b F186H E C3H CAN1 Module Interrupt Control Register 0000H XP1IC b F18EH E C7H Flash Termination Interrupt Control Reg. 0000H XP3IC b F19EH E CFH PLL/RTC Interrupt Control Register 0000H ZEROS b FF1CH 8EH Constant Value 0's Register (read only) 0000H 2) 00xxH 1) The system configuration is selected during reset. Data Sheet 37 1999-08 & 2) The reset value depends on the indicated reset source. Data Sheet 38 1999-08 & Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Symbol Limit Values min. Unit Notes max. 7ST 9DD -65 150 C -0.5 6.5 V 9IN -0.5 9DD+0.5 V Input current on any pin during overload condition -10 10 mA Absolute sum of all input currents during overload condition - |100| mA 1.5 W Storage temperature Voltage on 9DD pins with respect to ground (9SS) Voltage on any pin with respect to ground (9SS) Power dissipation 3DISS Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (9IN>9DD or 9IN<9SS) the voltage on 9DD pins with respect to ground (9SS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 39 1999-08 & Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C164. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Operating Condition Parameters Parameter Symbol Limit Values min. Standard digital supply voltage 9DD 9SS ,OV Overload current Absolute sum of overload |,OV| Unit Notes max. 4.5 5.5 V Active mode, ICPUmax = 25 MHz 2.5 1) 5.5 V PowerDown mode V Reference voltage 0 Digital ground voltage - 5 mA Per pin 2) - 50 mA 3) 3) currents External Load Capacitance &L - 100 pF Pin drivers in fast edge mode 4) Ambient temperature 7A 0 70 C SAB-C164... -40 85 C SAF-C164... -40 125 C SAK-C164... 1) Output voltages and output currents will be reduced when 9DD leaves the range defined for active mode. 2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. 9OV ! 9DD+0.5V or 9OV 9SS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 3) Not 100% tested, guaranteed by design characterization. 4) The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in dynamic current mode must be respected when designing the system. Data Sheet 40 1999-08 & Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C164 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C164 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C164. DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Input low voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 9IL1 SR - 0.5 0.3 VDD V - Input low voltage (TTL) 9IL SR - 0.5 0.2 9DD V - 0.1 - Input low voltage (Special Threshold) 9ILS SR - 0.5 2.0 V - Input high voltage RSTIN 9IH1 SR 0.6 9DD 9DD + V - V - V - V - 0.5 Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 9IH2 SR 0.7 9DD 9DD + Input high voltage (TTL) 9IH SR 0.2 9DD 9DD + Input high voltage (Special Threshold) 9IHS SR 0.8 9DD 9DD + Input Hysteresis (Special Threshold) HYS Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (P3.0, P3.1, P6.5, P6.6, P6.7) Data Sheet 0.5 + 0.9 0.5 - 0.2 0.5 400 - mV - 9OL CC - 0.45 V ,OL = 2.4 mA 9OL2 CC - 0.4 V ,OL2 = 3 mA 41 1999-08 & DC Characteristics (continued) (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Output low voltage (all other outputs) 9OL1 CC - 0.45 V ,OL = 1.6 mA Output high voltage 1) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 9OH CC 2.4 - V ,OH = -2.4 mA 0.9 9DD - V ,OH = -0.5 mA Output high voltage 1) (all other outputs) 9OH1 CC 2.4 - V 0.9 9DD - V Input leakage current (Port 5) ,OZ1 CC ,OZ2 CC ,RSTH 3) ,RSTL 4) ,RWH 3) ,RWL 4) ,ALEL 3) ,ALEH 4) ,P4H 3) ,P4L 4) ,P0H 3) ,P0L 4) ,IL CC &IO CC ,OH = -1.6 mA ,OH = -0.5 mA 0.45V < 9IN < 9DD 0.45V < 9IN < 9DD 9IN = 9IH1 9IN = 9IL 9OUT = 2.4 V 9OUT = 9OLmax 9OUT = 9OLmax 9OUT = 2.4 V 9OUT = 2.4 V 9OUT = 9OL1max 9IN = 9IHmin 9IN = 9ILmax 0 V < 9IN < 9DD I = 1 MHz 7A = 25 C Input leakage current (all other) RSTIN inactive current 2) RSTIN active current 2) Read/Write inactive current Read/Write active current ALE inactive current 5) 5) 5) ALE active current 5) Port 4 inactive current Port 4 active current 5) 5) PORT0 configuration current XTAL1 input current Pin capacitance 6) (digital inputs/outputs) 5) - 200 nA - 500 nA - -10 A -100 - A - -40 A -500 - A - 40 A 500 - A - -40 A -500 - A - -10 A -100 - A - 20 A - 10 pF 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 K. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) This specification is only valid during Reset, or during Adapt-mode. The Port 4 current values are only valid for pins P4.3-0, which can act as chip select outputs. 6) Not 100% tested, guaranteed by design characterization. Data Sheet 42 1999-08 & Power Consumption C164-8R (ROM) (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Power supply current (5V active) ,DD5 with all peripherals active - 1+ mA 2.5*ICPU RSTIN = 9IL2 ICPU in [MHz] 1) Idle mode supply current (5V) with all peripherals active ,IDX5 - 1+ mA 1.1*ICPU RSTIN = 9IH1 ICPU in [MHz] 1) Idle mode supply current (5V) with all peripherals deactivated, PLL off, SDD factor = 32 ,IDO5 - 500 + A 50*IOSC RSTIN = 9IH1 IOSC in [MHz] 1) Power-down mode supply current (5V) with RTC running ,PDR5 - 200 + A 25*IOSC 9DD = 9DDmax IOSC in [MHz] 3) Power-down mode supply current (5V) with RTC disabled ,PDO5 A 9DD = 9DDmax 3) 2) 2) - 50 1) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs at 9IL or 9IH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 2) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at 9DD - 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected. Data Sheet 43 1999-08 & Power Consumption C164-8F (Flash) (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Power supply current (5V active) ,DD5 with all peripherals active - 40 + mA 3.5*ICPU Idle mode supply current (5V) with all peripherals active ,IDX5 - 40 + mA 1.4*ICPU Idle mode supply current (5V) with all peripherals deactivated, PLL off, SDD factor = 32, Flash modules off ,IDO5 - 500 + A 50*IOSC ICPU in [MHz] 1) RSTIN = 9IH1 IOSC in [MHz] 1) Power-down mode supply current (5V) with RTC running ,PDR5 - 200 + A 25*IOSC 9DD = 9DDmax IOSC in [MHz] 3) Power-down mode supply current (5V) with RTC disabled ,PDO5 A 9DD = 9DDmax 3) 2) 2) - 50 RSTIN = 9IL2 ICPU in [MHz] 1) RSTIN = 9IH1 1) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs at 9IL or 9IH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 2) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at 9DD - 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected. Data Sheet 44 1999-08 & I [A] 1500 ,,'2PD[ 1250 1000 750 ,3'5PD[ 500 250 ,3'2PD[ 4 Figure 8 Data Sheet 8 12 16 IOSC [MHz] Idle and Power Down Supply Current as a Function of Oscillator Frequency 45 1999-08 & , [mA] 120 IDD5typ 90 C164-8F (Flash) IDD5max IIDX5max IIDX5typ IDD5max IDD5typ 30 IIDX5max C164-8R (ROM) 60 IIDX5typ 5 Figure 9 Data Sheet 10 15 20 25 ICPU [MHz] Supply/Idle Current as a Function of Operating Frequency 46 1999-08 & AC Characteristics Definition of Internal Timing The internal operation of the C164 is controlled by the internal CPU clock ICPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). 3KDVH/RFNHG/RRS2SHUDWLRQ I26& I&38 TCL TCL 'LUHFW&ORFN'ULYH I26& I&38 TCL TCL 3UHVFDOHU2SHUDWLRQ I26& I&38 TCL Figure 10 TCL Generation Mechanisms for the CPU Clock The CPU clock signal ICPU can be generated from the oscillator clock signal IOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate ICPU. This influence must be regarded when calculating the timings for the C164. Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). The table below associates the combinations of these three bits with the respective clock generation mode. Data Sheet 47 1999-08 & Table 10 C164 Clock Generation Modes P0.15-13 (P0H.7-5) CPU Frequency External Clock ICPU = IOSC * F Input Range 1) 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 IOSC * 4 IOSC * 3 IOSC * 2 IOSC * 5 IOSC * 1 IOSC * 1.5 IOSC / 2 IOSC * 2.5 2.5 to 6.25 MHz Notes Default configuration 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz Direct drive 2) 6.66 to 16.6 MHz 2 to 50 MHz CPU clock via prescaler 4 to 10 MHz 1) The external clock input range refers to a CPU clock range of 10...25 MHz. 2) The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When pins P0.15-13 (P0H.7-5) equal 001B during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of ICPU is half the frequency of IOSC and the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the period of the input clock IOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of IOSC for any TCL. Phase Locked Loop For all combinations of pins P0.15-13 (P0H.7-5) except for 001B and 011B the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. ICPU = IOSC * F). With every F'th transition of IOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of ICPU is constantly adjusted so it is locked to IOSC. The slight variation causes a jitter of ICPU which also effects the duration of individual TCLs. Data Sheet 48 1999-08 & The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: (N * TCL)min = N * TCLNOM - DN where N = number of consecutive TCLs DN [ns] = (13.3 + N*6.3) / ICPU [MHz], and 1 N 40. So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 * 6.3) / 25 = 1.288 ns, and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ ICPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below). 26.5 Max.jitter D1 [ns] 10 MHz This approximated formula is valid for 1 1 40 and 10MHz fCPU 25MHz. 20 16 MHz 20 MHz 10 25 MHz 1 1 Figure 11 Data Sheet 5 10 20 40 N Approximated Maximum Accumulated PLL Jitter 49 1999-08 & Direct Drive When pins P0.15-13 (P0H.7-5) equal 011B during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of ICPU directly follows the frequency of IOSC so the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock IOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: (DC = duty cycle) TCLmin = 1/IOSC * DCmin For two consecutive TCLs the deviation caused by the duty cycle of IOSC is compensated so the duration of 2TCL is always 1/IOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/IOSC. Note: The address float timings in Multiplexed bus mode (W11 and W45) use the maximum duration of TCL (TCLmax = 1/IOSC * DCmax) instead of TCLmin. Data Sheet 50 1999-08 & AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Parameter Symbol Direct Drive 1:1 min. Oscillator period WOSC SR High time 2) Low time 2) Rise time 2) Fall time 2) W1 W2 W3 W4 40 max. Prescaler 2:1 min. max. PLL 1:N min. Unit max. - 20 - 60 1) 500 1) ns SR 20 3) - 6 - 10 - ns SR 20 3) - 6 - 10 - ns SR - 10 - 6 - 10 ns SR - 10 - 6 - 10 ns 1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 2) The clock input signal must reach the defined levels 9IL and 9IH2. 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (ICPU) in direct drive mode depends on the duty cycle of the clock input signal. Figure 12 External Clock Drive XTAL1 Note: The main oscillator is optimized for oscillation with a crystal within a frequency range of 4...16 MHz. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Data Sheet 51 1999-08 & A/D Converter Characteristics (Operating Conditions apply) 4.0V (2.6V)9AREF 9DD + 0.1V (Note the influence on TUE.) 9SS - 0.1V 9AGND 9SS + 0.2V Parameter Symbol Limit Values min. Analog input voltage range Basic clock frequency Conversion time Total unadjusted error Unit Test Condition max. 9AIN SR 9AGND IBC 0.5 WC CC - 9AREF V 1) 6.25 MHz 2) TUE CC - 2 - 4 4) Internal resistance of reference voltage source 5AREF SR - Internal resistance of analog source 5ASRC SR - ADC input capacitance &AIN CC - 40 WBC + WS+2WCPU WBC / 60 3) WCPU = 1 / ICPU LSB 9AREF 4.0 V LSB 9AREF 2.6 V k WBC in [ns] 5) 6) - 0.25 WS / 450 k WS in [ns] 6) 7) pF 6) - 0.25 33 1) 9AIN may exceed 9AGND or 9AREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) The limit values for IBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. 3) This parameter includes the sample time WS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock WBC depend on the conversion time programming. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 4) TUE is tested at 9AREF=5.0V (3.3V), 9AGND=0V, 9DD=4.9V (3.2V). It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see ,OV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB (8 LSB @ 3V). 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, guaranteed by design. 7) During the sample time the input capacitance &I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within WS. After the end of the sample time WS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time WS depend on programming and can be taken from the table below. Data Sheet 52 1999-08 & Sample time and conversion time of the C164's A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for IBC must not be exceeded when selecting ADCTC. Table 11 A/D Converter Computation Table ADCON.15|14 (ADCTC) A/D Converter Basic clock IBC ADCON.13|12 Sample time (ADSTC) WS 00 ICPU / 4 ICPU / 2 ICPU / 16 ICPU / 8 00 01 10 11 01 10 11 WBC * 8 WBC * 16 WBC * 32 WBC * 64 Converter Timing Example: Assumptions: Basic clock Sample time Conversion time ICPU IBC WS WC = 25 MHz (i.e. WCPU = 40 ns), ADCTC = '00', ADSTC = '00'. = ICPU / 4 = 6.25 MHz, i.e. WBC = 160 ns. = WBC * 8 = 1280 ns. = WS + 40 WBC + 2 WCPU = (1280 + 6400 + 80) ns = 7.8 s. Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 12 Memory Cycle Variables Description Symbol Values ALE Extension WA WC WF TCL * <ALECTL> Memory Cycle Time Waitstates Memory Tristate Time Data Sheet 2TCL * (15 - <MCTC>) 2TCL * (1 - <MTTC>) 53 1999-08 & Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.45 V 0.8 V 0.8 V AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at 9IH min for a logic '1' and 9IL max for a logic '0'. Figure 13 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded 9OH/9OL level occurs (,OH/,OL = 20 mA). Figure 14 Data Sheet Float Waveforms 54 1999-08 & AC Characteristics Multiplexed Bus (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. ALE high time W5 CC 10 + WA - TCL - 10 +WA - ns Address setup to ALE W6 CC 4 +WA - TCL - 16 +WA - ns Address hold after ALE W7 CC 10 +WA - TCL - 10 +WA - ns ALE falling edge to RD, WR (with RW-delay) W8 CC 10 +WA - TCL - 10 +WA - ns ALE falling edge to RD, WR (no RW-delay) W9 CC -10 +WA - -10 +WA - ns Address float after RD, WR (with RW-delay) W10 CC - 6 - 6 ns Address float after RD, WR (no RW-delay) W11 CC - 26 - TCL + 6 ns RD, WR low time (with RW-delay) W12 CC 30 +WC - 2TCL - 10 +WC - ns RD, WR low time (no RW-delay) W13 CC 50 +WC - 3TCL10+WC - ns RD to valid data in (with RW-delay) W14 SR - 20 +WC - 2TCL - 20 +WC ns RD to valid data in (no RW-delay) W15 SR - 40 +WC - 3TCL - 20 +WC ns ALE low to valid data in W16 SR - 40 + WA + WC - 3TCL - 20 +WA +WC ns Address to valid data in W17 SR - 50 + 2WA - + WC 4TCL - 30 +2WA +WC ns Data hold after RD rising edge W18 SR 0 - 0 - ns Data float after RD W19 SR - 26 +WF - 2TCL - 14 +WF ns Data Sheet 55 1999-08 & Multiplexed Bus (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. Data valid to WR W22 CC 20 +WC - 2TCL - 20 +WC - ns Data hold after WR W23 CC 26 +WF - 2TCL - 14 +WF - ns ALE rising edge after RD, W25 CC 26 +WF WR - 2TCL - 14 +WF - ns W27 CC 26 +WF - 2TCL - 14 +WF - ns W38 CC -4 -WA W39 SR - 10 - WA -4 -WA 10 -WA ns 40 +WC +2WA - 3TCL - 20 +WC + 2WA ns CS hold after RD, WR 1) W40 CC 46 +WF - 3TCL - 14 + WF - ns ALE fall. edge to RdCS, WrCS (with RW delay) W42 CC 16 +WA - TCL - 4 +WA - ns ALE fall. edge to RdCS, WrCS (no RW delay) W43 CC -4 +WA - -4 +WA - ns Address float after RdCS, W44 CC - WrCS (with RW delay) 0 - 0 ns Address float after RdCS, W45 CC - WrCS (no RW delay) 20 - TCL ns Address hold after RD, WR ALE falling edge to CS 1) CS low to Valid Data In 1) RdCS to Valid Data In (with RW delay) W46 SR - 16 +WC - 2TCL - 24 +WC ns RdCS to Valid Data In (no RW delay) W47 SR - 36 +WC - 3TCL - 24 +WC ns RdCS, WrCS Low Time (with RW delay) W48 CC 30 +WC - 2TCL - 10 +WC - ns RdCS, WrCS Low Time (no RW delay) W49 CC 50 +WC - 3TCL - 10 +WC - ns Data Sheet 56 1999-08 & Multiplexed Bus (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. Data valid to WrCS W50 CC 26 +WC - 2TCL - 14 +WC - ns Data hold after RdCS W51 SR 0 W52 SR - - 0 - ns 20 +WF - 2TCL - 20 +WF ns Address hold after RdCS, WrCS W54 CC 20 +WF - 2TCL - 20 +WF - ns Data hold after WrCS W56 CC 20 +WF - 2TCL - 20 +WF - ns Data float after RdCS 1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). Data Sheet 57 1999-08 & W5 W16 W25 ALE W38 W39 W40 CSxL W17 A21-A16 (A15-A8) BHE, CSxE W27 Address W6 W7 W54 W19 W18 5HDG&\FOH BUS Address W8 Data In W10 W14 RD W42 W44 W12 W51 W46 RdCSx W52 W48 :ULWH&\FOH BUS W23 Address W8 WR, WRL, WRH W42 Data Out W10 W22 W56 W12 W44 W50 WrCSx W48 Figure 15 Data Sheet External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 58 1999-08 & W5 W16 W25 W39 W40 W17 W27 ALE W38 CSxL A21-A16 (A15-A8) BHE, CSxE Address W6 W7 W54 W19 W18 5HDG&\FOH BUS Address Data In W10 W8 W14 RD W44 W42 W12 W51 W46 RdCSx W52 W48 :ULWH&\FOH BUS W23 Address Data Out W10 W8 WR, WRL, WRH W44 W42 W22 W56 W12 W50 WrCSx W48 Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 59 1999-08 & W5 W16 W25 ALE W38 W39 W40 CSxL W17 A21-A16 (A15-A8) BHE, CSxE W27 Address W6 W7 W54 W19 W18 5HDG&\FOH BUS Address W9 Data In W11 RD W43 W15 W13 W45 RdCSx W51 W47 W52 W49 :ULWH&\FOH BUS W23 Address W9 WR, WRL, WRH W43 Data Out W11 W22 W45 W13 W50 W56 WrCSx W49 Figure 17 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 60 1999-08 & W5 W16 W25 W39 W40 W17 W27 ALE W38 CSxL A21-A16 (A15-A8) BHE, CSxE Address W6 W7 W54 W19 W18 5HDG&\FOH BUS Address Data In W9 W11 RD W15 W13 W43 W45 RdCSx W51 W47 W52 W49 :ULWH&\FOH BUS W23 Address W9 WR, WRL, WRH Data Out W11 W22 W56 W13 W43 W45 W50 WrCSx W49 Figure 18 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE 61 1999-08 & AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. ALE high time W5 CC 10 +WA - TCL - 10 +WA - ns Address setup to ALE W6 CC 4 +WA - TCL - 16 +WA - ns ALE falling edge to RD, WR (with RW-delay) W8 CC 10 +WA - TCL - 10 +WA - ns ALE falling edge to RD, WR (no RW-delay) W9 CC -10 +WA - -10 +WA - ns RD, WR low time (with RW-delay) W12 CC 30 +WC - 2TCL - 10 +WC - ns RD, WR low time (no RW-delay) W13 CC 50 +WC - 3TCL - 10 +WC - ns RD to valid data in (with RW-delay) W14 SR - 20 +WC - 2TCL - 20 +WC ns RD to valid data in (no RW-delay) W15 SR - 40 +WC - 3TCL - 20 +WC ns ALE low to valid data in W16 SR - 40 + - 3TCL - 20 +WA +WC ns Address to valid data in W17 SR - 50 + 2WA +WC - 4TCL - 30 +2WA +WC ns Data hold after RD rising edge W18 SR 0 - 0 - ns Data float after RD rising edge (with RW-delay 1)) W20 SR - 26 + 2WA +WF - 2TCL - 14 +22WA +WF 1) ns WA +WC 1) Data float after RD rising edge (no RW-delay 1)) W21 SR - 10 + - 1) 2WA +WF TCL - 10 +22WA +WF 1) ns Data valid to WR W22 CC 20 +WC - - ns Data Sheet 62 2TCL - 20 +WC 1999-08 & Demultiplexed Bus (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. W24 CC 10 +WF Data hold after WR max. min. max. - TCL - 10 +WF - ns - -10 +WF - ns - 0 +WF - ns 10 -WA -4 -WA 10 -WA ns CS low to Valid Data In 3) W28 CC 0 +WF W38 CC -4 -WA W39 SR - 40 + WC+2WA - 3TCL - 20 +WC + 2WA ns CS hold after RD, WR 3) W41 CC 6 +WF - TCL - 14 +WF - ns ALE falling edge to RdCS, WrCS (with RWdelay) W42 CC 16 +WA - TCL - 4 +WA - ns ALE falling edge to RdCS, WrCS (no RWdelay) W43 CC -4 +WA - -4 +WA - ns RdCS to Valid Data In (with RW-delay) W46 SR - 16 +WC - 2TCL - 24 +WC ns RdCS to Valid Data In (no RW-delay) W47 SR - 36 +WC - 3TCL - 24 ns +WC RdCS, WrCS Low Time (with RW-delay) W48 CC 30 +WC - 2TCL - 10 +WC - ns RdCS, WrCS Low Time (no RW-delay) W49 CC 50 +WC - 3TCL - 10 +WC - ns Data valid to WrCS W50 CC 26 +WC - 2TCL - 14 +WC - ns Data hold after RdCS W51 SR 0 W53 SR - - 0 - ns 20 +WF - 2TCL - 20 ns +2WA +WF 1) W68 SR - 0 +WF - TCL - 20 ns 1) +2WA +WF ALE rising edge after RD, W26 CC -10 +WF WR Address hold after WR 2) ALE falling edge to CS Data float after RdCS (with RW-delay) 1) Data float after RdCS (no RW-delay) 1) Data Sheet 3) 63 1999-08 & Demultiplexed Bus (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. Address hold after RdCS, WrCS W55 CC -6 +WF - -6 +WF - ns Data hold after WrCS W57 CC 6 +WF - TCL - 14 + - ns WF 1) RW-delay and WA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). Data Sheet 64 1999-08 & W5 W16 W26 ALE W38 W39 W41 CSxL W17 A21-A16 A15-A0 BHE, CSxE W28 Address W6 W55 W20 W18 5HDG&\FOH BUS (D15-D8) D7-D0 Data In W8 W14 RD W12 W42 RdCSx W51 W46 W53 W48 :ULWH&\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH W24 Data Out W8 W22 W57 W12 W42 W50 WrCSx W48 Figure 19 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet 65 1999-08 & W5 W16 W26 ALE W38 W39 W41 CSxL W17 A21-A16 A15-A0 BHE, CSxE W28 Address W6 W55 W20 W18 5HDG&\FOH BUS (D15-D8) D7-D0 Data In W8 W14 RD W12 W42 W51 W46 RdCSx W53 W48 :ULWH&\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH W24 Data Out W8 W22 W57 W12 W42 W50 WrCSx W48 Figure 20 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 66 1999-08 & W5 W16 W26 ALE W38 W39 W41 CSxL W17 A21-A16 A15-A0 BHE, CSxE W28 Address W6 5HDG&\FOH BUS (D15-D8) D7-D0 W55 W21 W18 Data In W9 W15 RD W43 W13 W51 W47 RdCSx W68 W49 :ULWH&\FOH BUS (D15-D8) D7-D0 W24 Data Out W9 W22 WR, WRL,WRH W57 W13 W50 W43 WrCSx W49 Figure 21 Data Sheet External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE 67 1999-08 & W5 W16 W26 ALE W38 W39 W41 CSxL W17 A21-A16 A15-A0 BHE,CSxE W28 Address W6 W55 W21 W18 5HDG&\FOH BUS (D15-D8) D7-D0 Data In W9 W15 RD W13 W43 W51 W47 RdCSx W68 W49 :ULWH&\FOH BUS (D15-D8) D7-D0 W24 Data Out W9 W22 WR, WRL, WRH W57 W13 W43 W50 WrCSx W49 Figure 22 Data Sheet External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE 68 1999-08 & AC Characteristics CLKOUT (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge W29 W30 W31 W32 W33 W34 max. 40 2TCL 2TCL ns CC 14 - TCL - 6 - ns CC 10 - TCL - 10 - ns CC - 4 - 4 ns CC - 4 - 4 ns CC 0 +WA 10 +WA 0 +WA 10 +WA ns t32 MUX/Tristate 3) t33 t30 t31 t34 t29 ALE Command RD, WR Figure 23 max. CC 40 Running cycle 1) CLKOUT min. 4) 2) CLKOUT Timing Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 4) The next external bus cycle may start here. Data Sheet 69 1999-08 & Package Outlines Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) Figure 24 Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Data Sheet Dimensions in mm 70 1999-08 & Data Sheet 71 1999-08 & Published by Infineon Technologies AG Data Sheet 72 1999-08