MBM29F400TA-12PF - Fujitsu

DS05-20812-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

FLASH MEMORY

CMOS

4M (512K

8/256K

16)

MBM29F400TA/MBM29F400BA

■

DISTINCTIVE CHARACTERISTICS

• Single 5.0 V read, write, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard word-wide pinouts

48-pin TSOP (Package sufﬁx: PFTN–Normal Bend Type, PFTR–Reversed Bend Type)

44-pin SOP (Package sufﬁx: PF)

• Minimum 100,000 write/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and veriﬁes data at speciﬁed address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Low power consumption

20 mA typical active read current for Byte Mode

28 mA typical active read current for Word Mode

30 mA typical write/erase current

A typical standby current

•Low V

write inhibit

≤

3.2 V

• Sector protection

Hardware method disables any combination of sectors from write or erase operations

• Temporary sector unprotection

Hardware method enable temporarily any combination of sectors from write or erase operations.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

MBM29F400TA/MBM29F400BA

■

PACKAGE

Marking Side

48-pin TSOP 44-pin SOP

Marking Side

(FPT-48P-M20) (FPT-44P-M16)

(FPT-48P-M19)

MBM29F400TA/MBM29F400BA

■

GENERAL DESCRIPTION

The MBM29F400TA/BA is a 4M-bit, 5.0 V-only Flash memor y organized as 512K bytes of 8 bits each or 256K

words of 16 bits each. The MBM29F400TA/BA is offered in a 48-pin TSOP and 44-pin SOP packages. This

de vice is designed to be programmed in-system with the standard system 5.0 V V

supply. A 12.0 V V

is not

required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

The MBM29F400TA/BA is erased when shipped from the factory.

The standard MBM29F400TA/BA offers access times between 70 ns and 120 ns, allowing operation of high-

speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable

(CE), write enable (WE) and output enable (OE) controls.

The MBM29F400TA/BA is pin and command set compatible with JEDEC standard 4M-bit E

PROMs. Commands

are written to the command register using standard microprocessor wr ite timings. Register contents ser ve as

input to an internal state-machine which controls the erase and programming circuitry . Write cycles also internally

latch addresses and data needed f or the prog ramming and er ase oper ations . Reading data out of the device is

similar to reading from 12.0 V Flash or EPROM devices.

The MBM29F400TA/BA is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the progr am pulse widths

and veriﬁes proper cell margin. Typically, each sector can be programmed and v eriﬁed in less than one second.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the arra y if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

veriﬁes proper cell margin.

The entire chip or any individual sector is typically erased and veriﬁed in 1.5 seconds. (If already completely

preprogrammed.)

This device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors.

The de vice features single 5.0 V po w er supply oper ation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the T oggle Bit feature on DQ

, or the RY/BY pin. Once the end of a program or erase cycle has been completed,

the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E

PROM exper ience to produce the highest levels

of quality, reliability and cost effectiveness. The MBM29F400TA/BA memor y electrically erases the entire chip

or all bits within a sector simultaneously via F o wler-Nordhiem tunneling. The b ytes/w ords are progr ammed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29F400TA/MBM29F400BA

■

FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 16K byte, two 8K bytes, one 32K byte and seven 64K bytes.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user deﬁnable.

16K byte

8K byte

32K byte

64K byte



7FFFFH

7BFFFH

79FFFH

77FFFH

6FFFFH

5FFFFH

4FFFFH

3FFFFH

2FFFFH

1FFFFH

0FFFFH

00000H



64K byte

64K byte

32K byte

8K byte

16K byte



MBM29F400TA Sector Architecture MBM29F400BA Sector Architecture

7FFFFH

6FFFFH

5FFFFH

4FFFFH

3FFFFH

2FFFFH

1FFFFH

0FFFFH

07FFFH

05FFFH

03FFFH

00000H

MBM29F400TA/MBM29F400BA

■

PRODUCT SELECTOR GUIDE

■

BLOCK DIAGRAM

Part No. MBM29F400TA/MBM29F400BA

Ordering Part No. V

= 5.0 V

5% –70 — —

= 5.0V

10% — –90 –12

Max. Access Time (ns) 70 90 120

CE Access (ns) 70 90 120

OE Access (ns) 30 35 50

VSS

VCC

A0 to A17

Erase Voltage

Generator

DQ0 to DQ15

State 

Control

Command

Generator

VCC Detector Address

Latch X-Decoder

Y-Decoder

Cell Matrix

Y-Gating

Chip Enable

Output Enable

Logic Data Latch

Input/Output

Buffers

STB

Timer

A-1

BYTE

RESET

RY/BY

Buffer RY/BY

MBM29F400TA/MBM29F400BA

■

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

N.C.

WE

RESET

N.C.

RY/BY

N.C.

A17

A7

A6

A5

A4

A3

A2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24



48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

MBM29F400TA/MBM29F400BA

Standard Pinout

MBM29F400TA/MBM29F400BA

Reverse Pinout

TSOP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

N.C.

RY/BY

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE

VSS

OE

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET

WE

A8

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

SOP

(Top View)

A16

BYTE

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

VSS

CE

A0

CE

VSS

OE

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

VCC

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

VSS

BYTE

A16

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

A1

A2

A3

A4

A5

A6

A7

A17

N.C.

RY/BY

N.C.

RESET

WE

N.C.

A8

A9

A10

A11

A12

A13

A14

A15

(Marking Side)

FPT-48P-M19

FPT-48P-M20

FPT-44P-M16

(Marking Side)

MBM29F400TA/MBM29F400BA

■

LOGIC SYMBOL

Table 1 MBM29F400TA/BA Pin Conﬁguration

Pin Function

-1

, A

to A

Address Inputs

to DQ

Data Inputs/Outputs

CE Chip Enable

OE Output Enable

WE Write Enable

RY/BY Ready-Busy Output

RESET Hardware Reset Pin/Sector Protection

Unlock

BYTE Selects 8-bit or 16-bit mode

N.C. No Internal Connection

Device Ground

Device Power Supply

(5.0 V

10% or

5%)

18 A0 to A17

DQ0 to DQ15

16 or 8

BYTE

RESET

A-1

RY/BY

MBM29F400TA/MBM29F400BA

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ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29F400 TA –70 PFTN

DEVICE NUMBER/DESCRIPTION

MBM29F400

4Mega-bit (512K × 8-Bit or 256K × 16-Bit) CMOS Flash Memory

5.0 V-only Read, Write, and Erase

PACKA GE TYPE

PFTN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PF = 44-Pin Small Outline Package

SPEED OPTION

See Product Selector Guide

BOOT CODE SECTOR ARCHITECTURE

TA = Top sector

BA = Bottom sector

MBM29F400TA/MBM29F400BA

Legend

: L = V

, H = V

, X = V

or V

. See DC Characteristics for voltage levels.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer

to Table 7.

2. WE can be V

if OE is V

, OE at V

initiates the write operations.

3. Refer to the section on Sector Protection.

Table 2 MBM29F400TA/BA User Bus Operations (BYTE = V

)

Operation CE OE WE A

to DQ

RESET

Auto-Select Manufacturer Code (1) L L H L L L V

Code H

Auto-Select Device Code (1) L L H H L L V

Code H

Read (2) L L H A

OUT

Standby H XXXXXXHIGH-Z H

Output Disable L H H XXXXHIGH-Z H

Write L H L A

A6A9DIN H

Enable Sector Protection (3) L VID LXXLVID XH

Verify Sector Protection (3) L LHLHLVID Code H

Temporary Sector Unprotection XXXXXXX X VID

Reset (Hardware)/Standby XXXXXXXHIGH-Z L

Table 3 MBM29F400TA/BA User Bus Operations (BYTE = VIL)

Operation CE OE WE DQ15/A-1 A0A1A6A9DQ0 to DQ7RESET

Auto-Select Manufacturer Code (1) L L H L L L L VID Code H

Auto-Select Device Code (1) L L H L H L L VID Code H

Read (2) L L H A-1 A0A1A6A9DOUT H

Standby H X X X XXXXHIGH-Z H

Output Disable L H H X XXXXHIGH-Z H

Write L H L A-1 A0A1A6A9DIN H

Enable Sector Protection (3) L VID LXXXLVID XH

Verify Sector Protection (3) L L H L L H L VID Code H

Temporary Sector Unprotection X X X X XXXX X VID

Reset (Hardware)/Standby X X X X XXXXHIGH-Z L

MBM29F400TA/MBM29F400BA

Read Mode

The MBM29F400TA/BA has two control functions which must be satisﬁed in order to obtain data at the outputs.

CE is the pow er control and should be used for a de vice selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC-tCE time.)

Standby Mode

There are two ways to implement the standby mode on the MBM29F400TA/BA device, one using both the CE

and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC±0.3 V.

Under this condition the current consumed is less than 100 µA. A TTL standby mode is achieved with CE and

RESET pins held at VIH. Under this condition the current is reduced to less than 1 mA. The device can be read

with standard access time (tCE) from either of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VCC±0.3 V

(CE = H or L). Under this condition the current consumed is less than 100 µA. A TTL standb y mode is achieved

with RESET pin held at VIL (CE= H or L). Under this condition the current is reduced to less than 1 mA. Once

the RESET pin is taken high, the de vice requires 500 ns of wake up time before outputs are valid f or read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Output Disable

With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the device to be programmed with its corresponding programming algor ithm. This mode is functional over the

entire temperature range of the device.

To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two

identiﬁer bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All

addresses are DON’T CARES except A0, A1 and A6.

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29F400TA/BA is erased or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 7. (Refer to Autoselect Command section.)

A0 = VIL represents the manufacturer’s code (Fujitsu = 04H) and A0 = VIH represents the device identiﬁer code

(MBM29F400TA = 23H and MBM29F400BA = ABH for ×8 mode; MBM29F400TA = 2223H and MBM29F400BA

= 22ABH for ×16 mode). All identiﬁers for manufacturer and device will exhibit odd parity with DQ7 deﬁned as

the parity bit. In order to read the proper device codes when ex ecuting the autoselect, A1 must be VIL. (See Tables

4.1 and 4.2.)

MBM29F400TA/MBM29F400BA

*1: A-1: Byte mode

*2: Outputs 01H at protected sector addresses

(B): Byte mode

(W): W ord mode

Write

Device erasure and programming are accomplished via the command register . The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occup y an y addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The

command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on

the falling edge of WE or CE, whichever happens later ; while data is latched on the r ising edge of WE or CE,

whichever happens ﬁrst. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for speciﬁc timing parameters.

Sector Protection

The MBM29F400TA/BA feature hardware sector protection. This feature will disable both program and erase

operations in any n umber of sectors (0 through 10). The sector protection f eature is enabled using programming

equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest

VID = 11.5 V) and CE = VIL and A6 = VIL. The sector addresses (A17, A16, A15, A14, A13, and A12) should be set to

the sector to be protected. Tables 5 and 6 deﬁne the sector address for each of the eleven (11) individual sectors.

Programming of the protection circuitry begins on the falling edge of the WE pulse and is ter minated with the

Table 4.1 MBM29F400TA/BA Sector Protection Verify Autoselect Codes

Type A12 to A17 A6A1A0A-1*1 Code

(HEX)

Manufacturer’s Code X VIL VIL VIL VIL 04H

MBM29F400A

Device

Code

MBM29F400TA Byte XVIL VIL VIH VIL 23H

Word X 2223H

MBM29F400BA Byte XVIL VIL VIH VIL ABH

Word X 22ABH

Sector Protection Sector

Addresses VIL VIH VIL VIL 01H*2

Table 4.2 Expanded Autoselect Code Table

Type Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

Manufacturer’s Code 04H A-1/00 0 0 0 0 0 000000100

MBM29F400A

Device

Code

MBM29F400TA (B)

(W) 23H

2223H A-1

0HI-Z

1HI-Z

0HI-Z

1HI-Z

MBM29F400BA (B)

(W) ABH

22ABH A-1

0HI-Z

1HI-Z

0HI-Z

1HI-Z

Sector Protection 01H A-1/00 0 0 0 0 0 000000001

MBM29F400TA/MBM29F400BA

rising edge of the same. Sector addresses must be held constant during the WE pulse. Refer to ﬁgures 14 and

20 for sector protection algorithm and waveforms.

To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A17, A16, A15, A14, A13 and A12) while (A6,

A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 f or a protected sector . Otherwise the device

will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6 are

DON’T CARE. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing

a read operation at the address location XX02H, where the higher order addresses (A17, A16, A15, A14, A13 and

A12) are the sector address will produce a logical “1” at DQ0 for a protected sector. See Tab le 4.1 for Autoselect

codes.

Temporary Sector Unprotection

This f eature allows temporary unprotection of previously protected sectors of the MBM29F400TA/BA de vices in

order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12

V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.

Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.

MBM29F400TA/MBM29F400BA

Table 5 Sector Address Tables (MBM29F400TA)

Sector

Address A17 A16 A15 A14 A13 A12 Address Range

SA0 0 0 0 X X X 00000H to 0FFFFH

SA1 0 0 1 X X X 10000H to 1FFFFH

SA2 0 1 0 X X X 20000H to 2FFFFH

SA3 0 1 1 X X X 30000H to 3FFFFH

SA4 1 0 0 X X X 40000H to 4FFFFH

SA5 1 0 1 X X X 50000H to 5FFFFH

SA6 1 1 0 X X X 60000H to 6FFFFH

SA71110XX70000H to 77FFFH

SA811110078000H to 79FFFH

SA91111017A000H to 7BFFFH

SA10 11111X7C000H to 7FFFFH

Table 6 Sector Address Tables (MBM29F400BA)

Sector

Address A17 A16 A15 A14 A13 A12 Address Range

SA000000X00000H to 03FFFH

SA100001004000H to 05FFFH

SA200001106000H to 07FFFH

SA30001XX08000H to 0FFFFH

SA4 0 0 1 X X X 10000H to 1FFFFH

SA5 0 1 0 X X X 20000H to 2FFFFH

SA6 0 1 1 X X X 30000H to 3FFFFH

SA7 1 0 0 X X X 40000H to 4FFFFH

SA8 1 0 1 X X X 50000H to 5FFFFH

SA9 1 1 0 X X X 60000H to 6FFFFH

SA10 1 1 1 X X X 70000H to 7FFFFH

MBM29F400TA/MBM29F400BA

Notes: 1. Address bits A15 to A17 = X = H or L for all address commands except or Program Address (PA) and

Sector Address (SA).

2. Bus operations are deﬁned in Tables 2 and 3.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will uniquely

select any sector.

4. RD =Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.

5. The system should generate the following address patterns:

Word Mode: 5555H or 2AAAH to addresses A0 to A14

Byte Mode: AAAAH or 5555H to addresses A-1 to A14

* :Either of the two reset commands will reset the device.

Command Deﬁnitions

Device operations are selected by writing speciﬁc address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the de vice to read

mode. Table 7 deﬁnes the valid register command sequences. Note that the Erase Suspend (B0H) and Erase

Resume (30H) commands are v alid only while the Sector Er ase oper ation is in progress. Moreover both Read/

Reset commands are functionally equivalent, resetting the de vice to the read mode. Please note that commands

are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

The read or reset operation is initiated b y writing the read/reset command sequence into the command register .

Microprocessor read cycles retriev e arra y data from the memory. The de vice remains enab led for reads until the

command register contents are altered.

Table 7 MBM29F400TA/BA Command Deﬁnitions

Command

Sequence

Bus

Write

Cycles

Req'd

First Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle Fourth Bus

Read/Write

Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset* Word 1 XXXXH F0H ——————————

Byte

Read/Reset* Word 35555H AAH 2AAAH 55H 5555H F0HRARD————

Byte AAAAH 5555H AAAAH

Autoselect Word 35555H AAH 2AAAH 55H 5555H 90H——————

Byte AAAAH 5555H AAAAH

Program Word 45555H AAH 2AAAH 55H 5555H A0HPAPD————

Byte AAAAH 5555H AAAAH

Chip Erase Word 65555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH

Sector

Erase Word 65555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H

Byte AAAAH 5555H AAAAH AAAAH 5555H

Sector Erase Suspend Erase can be suspended during sector erase with Addr (H or L). Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (H or L). Data (30H)

MBM29F400TA/MBM29F400BA

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retr ieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the speciﬁc timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the device resides in the target system. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the autoselect command sequence into the command register .

F ollowing the command write, a read cycle from address XX00H retriev es the manuf acture code of 04H. A read

cycle from address XX01H for ×16 (XX02H for ×8) returns the device code (MBM29F400TA = 23H and

MBM29F400BA = ABH for ×8 mode; MBM29F400TA = 2223H and MBM29F400BA = 22ABH for ×16 mode).

(See Tables 4.1 and 4.2.)

All manufacturer and device codes will exhibit odd parity with DQ7 deﬁned as the parity bit.

Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical

“1” at device output DQ0 for a protected sector.

To terminate the operation, it is necessary to write the read/reset command sequence into the register and also

to write the auto select command during the operation, execute it after writing read/reset command sequence.

Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unloc k” write cycles. These are f ollo w ed b y the prog ram set-up command and data write cycles.

Addresses are latched on the f alling edge of CE or WE, whichev er happens later and the data is latched on the

rising edge of CE or WE, whichever happens ﬁrst. The rising edge of CE or WE (whiche ver happens ﬁrst) begins

programming. Upon executing the Embedded ProgramTM Algorithm command sequence the system is not

required to provide further controls or timings. The device will automatically provide adequate internally generated

program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit (See Write Operation Status section.) at which time the device returns to the read mode and addresses are

no longer latched. Therefore, the device requires that a valid address to the device be supplied by the system

at this particular instance of time. Hence, Data P olling must be perf ormed at the memory location which is being

programmed.

Any commands written to the chip during this period will be ignored. If operating hardware reset dur ning the

programming, it is impossible the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 15 illustrates the Embedded Progr amming Algorithm using typical command strings and bus oper ations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by wr iting the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

MBM29F400TA/MBM29F400BA

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM

Algorithm command sequence the device automatically will program and verify the entire memory f or an all zero

data pattern prior to electrical erase. The system is not required to provide any controls or timings during these

operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the

mode.

Figure 16 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six b us cycle oper ation. There are tw o “unlock” write cycles. These are followed b y writing the

“set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of WE, while the command

(Data=30H) is latched on the rising edge of WE . A time-out of 50 µs from the rising edge of the last sector erase

command will initiate the sector erase command(s).

Multiple sectors may be erased sequentially by writing the six bus cycle operations as descr ibed above. This

sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be

concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be

accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to

guarantee this condition. The interr upts can be re-enabled after the last Sector Erase command is written. A

time-out of 50 µs from the rising edge of the last WE will initiate the e x ecution of the Sector Erase command(s).

If another falling edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to

determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command

other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode,

ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in

that sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write

Operation Status section f or Sector Erase Timer operation.) Loading the sector er ase buff er may be done in an y

sequence and with any number of sectors (0 to 10).

Sector erase does not require the user to progr am the de vice prior to erase. The de vice automatically progr ams

all memory locations in the sector(s) to be erased prior to electrical erase. When er asing a sector , the remaining

unselected sectors are not affected. The system is not required to provide any controls or timings during these

operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.)

at which time the de vice returns to the read mode. Data polling must be perf ormed at an address within any of

the sectors being erased.

Figure 16 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.

Erase Suspend

Erase Suspend command allows the user to interrupt the chip and then perf orm data reads (not program) from

a non-busy sector during a Sector Erase oper ation. (Which may take up to several seconds.) This command is

applicable ONLY during the Sector Erase operation and will be ignored if written during the chip Erase or

Programming operation. The Erase Suspend command (B0H) which is allowed only during the Sector Erase

Operation includes the sector erase time-out period after the Sector Erase commands (30H). Writing this

command during the time-out will result in immediate termination of the time-out period. An y subsequent writes

of the Sector Erase command will be taken as the Erase Resume command. Note that any other commands

during the time out will reset the device to read mode. The addresses are DON’T CARES when writing the Erase

Suspend or Erase Resume commands.

When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 0.1

µs to 15 µs to suspend the erase operation and go into erase suspended read mode (pseudo-read mode), during

MBM29F400TA/MBM29F400BA

which the user can read from a sector that is NOT being erased. A read from a sector being erased may result

in invalid data. The user m ust monitor the toggle bit (DQ6) to determine if the chip has entered the pseudo-read

mode, at which time the toggle bit stops toggling. An address of a sector NOT being erased must be used to

read the toggle bit, otherwise the user ma y encounter intermittent problems. Note that the user must k eep trac k

of what state the chip is in since there is no exter nal indication of whether the chip is in pseudo-read mode or

actual read mode. After the user wr ites the Erase Suspend command, the user must wait until the toggle bit

stops toggling before data reads from the device can be performed. Any fur ther writes of the Erase Suspend

command at this time will be ignored.

Every time an Erase Suspend command f ollowed b y an Erase Resume command is written, the internal (pulse)

counters are reset. These counters are used to count the number of high voltage pulses the memory cell requires

to program or er ase. If the count exceeds a certain limit, then the DQ5 bit will be set (Exceeded Time Limit ﬂag).

This resetting of the counters is necessary since the Erase Suspend command can potentially interrupt or disrupt

the high voltage pulses.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Write Operation Status

Notes: 1. DQ0, DQ1, and DQ2 are reserve pins for future use.

2. DQ8 to DQ15 = DON’T CARE for ×16 mode.

3. DQ4 is for Fujitsu internal use only.

Table 8 Hardware Sequence Flags

Status DQ7DQ6DQ5DQ3DQ2 to DQ0

In Progress

Auto-Programming DQ7Toggle 0 0

(D)

(Note 1)

Program/Erase in Auto Erase 0 Toggle 0 1

Erase Suspended Read Mode

(Sector being suspended erasure) 1100

Erase Suspended Read Mode

(Sector not being suspended erasure) Data Data Data Data

Exceeded

Time Limits Auto-Programming DQ7Toggle 1 0

Program/Erase in Auto-Erase 0 Toggle 1 1

MBM29F400TA/MBM29F400BA

DQ7

Data Polling

The MBM29F400TA/BA device features Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device

will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. Dur ing the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The ﬂowchar t

for Data Polling (DQ7) is shown in Figure 17.

For chip erase, the Data P olling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.

For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling

must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise,

the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the

MBM29F400TA/BA data pins (DQ7) may change asynchronously while the output enab le (OE ) is asserted low.

This means that the de vice is driving status information on DQ7 at one instant of time and then that b yte’s valid

data at the ne xt instant of time . Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data,

the data outputs on DQ0 to DQ6 ma y be still inv alid. The valid data on DQ 0 to DQ7 will be read on the successiv e

read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out. (See Table 8.)

See Figure 8 for the Data Polling timing speciﬁcations and diagrams.

DQ6

Toggle Bit

The MBM29F400TA/BA also features the “Toggle Bit” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algor ithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.

F or chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.

For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit

is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 2 µs and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause DQ6 to toggle.

See Figure 9 for the Toggle Bit timing speciﬁcations and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the speciﬁed limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the devices under this

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).

The OE and WE pins will control the output disable functions as described in Table 2 and 3.

MBM29F400TA/MBM29F400BA

If this f ailure condition occurs during sector erase oper ation, it speciﬁes that a particular sector is bad and it may

not be reused. However, other sectors are still functional and may be used for the program or erase operation.

The device must be reset to use other sectors. Write the Reset command sequence to the device, and then

execute program or erase command sequence. This allows the system to continue to use the other active sectors

in the device.

If this failure condition occurs during the chip erase operation, it speciﬁes that the entire chip is bad or combination

of sectors are bad.

If this failure condition occurs during the byte programming operation, it speciﬁes that the entire sector containing

that byte is bad and this sector may not be reused. (Other sectors are still functional and can be reused.)

The DQ5 f ailure condition ma y also appear if a user tries to program a non blank location without er asing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the

DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the de vice w as incorrectly

used.

DQ3

Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. DQ3

will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a v alid erase command, DQ 3 ma y be

used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase

cycle has begun; attempts to write subsequent commands to the device will be ignored until the er ase operation

is completed as indicated by Data P olling or Toggle Bit. If DQ3 is low (“0”), the de vice will accept additional sector

erase commands. To insure the command has been accepted, the system software should check the status of

DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status

check, the command may not have been accepted.

Refer to Table 8: Hardware Sequence Flags.

RY/BY

Ready/Busy

The MBM29F400T A/BA provides a RY/BY output pin as a way to indicate to the host system that the EmbeddedTM

Algorithms are either in progress or completed. If the output is low, the device is busy with either a program or

erase operation. If the output is high, the device is ready to accept an y read/write or erase operation. When the

RY/BY pin is low, the device will not accept an y additional prog ram or erase commands. If the MBM29F400TA/

BA is placed in an Erase Suspend mode , the R Y/BY output will be high. Also , since this is an open drain output,

many RY/BY pins can be tied together in parallel with a pull up resistor to VCC.

During programming, the RY/BY pin is dr iven low after the rising edge of the four th WE pulse in the four write

pulse sequence. Dur ing an erase operation, the RY/BY pin is driven low after the r ising edge of the sixth WE

pulse in the six write pulse sequence. The RY/BY pin should be ignored while RESET pin is at VIL.

Refer to Figure 10, 11 for a detailed timing diagram.

MBM29F400TA/MBM29F400BA

RESET

Hardware Reset

The MBM29F400TA/BA device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept lo w (VIL) f or at least 500 ns in order to properly reset the internal state machine .

Any operation in the process of being executed will be terminated and the inter nal state machine will be reset

20 µs after the RESET pin is driven low. (Furthermore, once the RESET pin goes high, the device requires an

additional 50 ns before it will allow read access.) When the RESET pin is low, the device will be in the standby

mode f or the duration of the pulse and all the data output pins will be tri-stated. If a hardw are reset occurs during

a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY

output signal should be ignored during the RESET pulse. Refer to Figure 11 for the timing diagram. Refer to

Temporary Sector Unprotection for additional functionality.

Byte/Word Conﬁguration

The BYTE pin selects the byte (8-bit) mode or w ord (16-bit) mode f or the MBM29F400TA/BA de vice. When this

pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0 to

DQ15. When this pin is dr iven low, the device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ 8 to DQ14 bits are tristated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Ref er

to Figures 12 and 13 for the timing diagram.

Data Protection

The MBM29F400TA/BA is designed to offer protection against accidental erasure or programming caused by

spurious system lev el signals that ma y e xist during power tr ansitions. During pow er up the de vice automatically

resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of speciﬁc multi-bus cycle command sequences.

The device also incor porates several features to prevent inadvertent wr ite cycles resulting for m VCC power-up

and power-down transitions or system noise.

Low VCC Write Inhibit

To av oid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode . Subsequent writes will be ignored until

the VCC le v el is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above 3.2 V.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the r ising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

MBM29F400TA/MBM29F400BA

■ABSOLUTE MAXIMUM RATINGS

Storage Temperature ..................................................................................................–45 °C to +125°C

Ambient Temperature with Power Applied...................................................................–25°C to +85°C

Voltage with Respect to Ground All pins except A9, OE, and RESET (Note 1)...........–2.0 V to +7.0 V

VCC (Note 1) ................................................................................................................–2.0 V to +7.0 V

A9, OE, and RESET (Note 2)......................................................................................–2.0 V to +13.5 V

Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may negative

ov ershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC

+0.5 V. During voltage transitions, outputs may overshoot to VCC +2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,

and RESET may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A9, OE, and RESET pins are +13.0 V which may overshoot to 13.5 V for periods of up to

20 ns.

WARNING: Stresses abov e those listed under “Absolute Maxim um Ratings” ma y cause permanent damage to the

device. This is a stress rating only; functional operation of the device at these or any other conditions

above those indicated in the operational sections of this speciﬁcation is not implied. Exposure of the

device to absolute maximum rating conditions for extended periods may affect device reliability.

■OPERATING RANGES

Commercial Devices

Ambient Temperature (T A)..................................0°C to +70°C

VCC Supply Voltages

VCC for MBM29F400TA-70/BA-70.......................+4.75 V to +5.25 V

VCC for MBM29F400TA-90, 12 /BA-90, 12..........+4.50 V to +5.50 V

Operating ranges deﬁne those limits between which the functionality of the device is guaranteed.

MBM29F400TA/MBM29F400BA

■MAXIMUM OVERSHOOT

+0.8 V

–0.5 V

20 ns

–2.0 V 20 ns

20 ns

Figure 1 Maximum Negative Overshoot Waveform

VCC + 0.5 V

+ 2.0 V

VCC + 2.0 V 20 ns

20 ns20 ns

Figure 2 Maximum Positive Overshoot Waveform

VCC + 0.5 V

+13.0 V

13.5 V 20 ns

20 ns20 ns

*: This waveform is applied for A9, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform

MBM29F400TA/MBM29F400BA

■DC CHARACTERISTICS

• TTL/NMOS Compatible

Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component

(at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2. ICC active while Embedded Algorithm (program or erase) is in progress.

Parameter

Symbol Parameter Description Test Condition Min. Max. Unit

ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. — ±1.0 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max. — ±1.0 µA

ILIT Input Leakage Current VCC = VCC Max.,

A9, OE, RESET = 12.0 V —50µA

ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH Byte —40 mA

Word 50

ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH —60mA

ICC3 VCC Current (Standby) VCC = VCC Max., CE = VIH, RESET = VIH — 1.0 mA

ICC4 VCC Current (Standby, Reset) VCC = VCC Max., RESET = VIL — 1.0 mA

VIL Input Low Level — –0.5 0.8 V

VIH Input High Level — 2.0 VCC+0.5 V

VID Voltage for Autoselect and

Sector Protection (A9, OE,

RESET) VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage Level IOL = 5.8 mA, VCC = VCC Min. — 0.45 V

VOH Output High Voltage Level IOH = –2.5 mA, VCC = VCC Min. 2.4 — V

VLKO Low VCC Lock-Out Voltage — 3.2 4.2 V

MBM29F400TA/MBM29F400BA

• CMOS Compatible

Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component

(at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2. ICC active while Embedded Algorithm (program or erase) is in progress.

Parameter

Symbol Parameter Description Test Condition Min. Max. Unit

ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. — ±1.0 µA

ILO Output Leakage Current VCC = VCC Max.,

A9, OE, RESET = 12.0 V —±1.0 µA

ILIT Input Leakage Current VOUT = VSS to VCC, VCC = VCC Max. — 50 µA

ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH Byte —40 mA

Word 50

ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH —60mA

ICC3 VCC Current (Standby) VCC = VCC Max., CE = VCC ± 0.3 V,

RESET = VCC ± 0.3 V — 100 µA

ICC4 VCC Current (Standby, Reset) VCC = VCC Max.,

RESET = VCC ± 0.3 V — 100 µA

VIL Input Low Level — –0.5 0.8 V

VIH Input High Level — 0.7 × VCC VCC + 0.3 V

VID Voltage for Autoselect and

Sector Protect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage Level IOL = 5.8 mA, VCC = VCC Min. — 0.45 V

VOH1 Output High Voltage Level IOH = –2.5 mA, VCC = VCC Min. 0.85 × VCC —V

VOH2 IOH = –100 µA, VCC = VCC Min. VCC – 0.4 — V

VLKO Low VCC Lock-Out Voltage — 3.2 4.2 V

MBM29F400TA/MBM29F400BA

■AC CHARACTERISTICS

• Read Only Operations Characteristics

Notes:1. Test Conditions: Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

2. Test Conditions: Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 20 ns

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference level

.Input: 0.8 V and 2.0 V

Output: 0.8 V and 2.0 V

Parameter

Symbol Description Test Setup –70

(Note 1) –90

(Note 2) –12

(Note 2) Unit

JEDEC Standard

tAVAV tRC Read Cycle Time — Min. 70 90 120 ns

tAVQV tACC Address to Output Delay CE = VIL

OE = VIL Max. 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE = VIL Max. 70 90 120 ns

tGLQV tOE Output Enable to Output Delay — Max. 30 35 50 ns

tEHQZ tDF Chip Enable to Output High-Z — Max. 20 20 30 ns

tGHQZ tDF Output Enable to Output High-Z — Max. 20 20 30 ns

tAXQX tOH Output Hold Time From Addresses,

CE or OE, Whichever Occurs First — Min. 0 0 0 ns

—tREADY RESET Pin Low to Read Mode — Max. 20 20 20 µs

—tELFL

tELFH CE or BYTE Switching Low or High — Max. 5 5 5 ns

MBM29F400TA/MBM29F400BA

• Write/Erase/Program Operations

Alternate WE Controlled Writes

(Continued)

Notes: 1. This does not include the preprogramming time.

2. These timings are for Sector Protection operation.

3. Not 100% tested.

4. Output Driver Disable Time.

Parameter Symbol Description –70 –90 –12 Unit

JEDEC Standard

tAVAV tWC Write Cycle Time (Note 3) Min. 70 90 120 ns

tAVWL tAS Address Setup Time Min. 0 0 0 ns

tWLAX tAH Address Hold Time Min. 45 45 50 ns

tDVWH tDS Data Setup Time Min. 30 45 50 ns

tWHDX tDH Data Hold Time Min. 0 0 0 ns

—tOES Output Enable Setup Time (Note 3) Min. 0 0 0 ns

—tOEH Output

Enable

Hold Time

Read (Note 3) Min. 0 0 0 ns

Toggle and Data Polling (Note 3) Min. 10 10 10 ns

5.0 V

Diodes = IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

IN3064

or Equivalent

6.2 kΩ

Notes: For –70: CL = 30 pF including jig capacitance

For all others: CL = 100 pF including jig capacitance

Figure 4 Test Conditions

MBM29F400TA/MBM29F400BA

(Continued)

Notes: 1. This does not include the preprogramming time.

2. These timings are for Sector Protection operation.

3. Not 100% tested.

4. Output Driver Disable Time.

Parameter Symbol Description –70 –90 –12 Unit

JEDEC Standard

tGHWL tGHWL Read Recover Time Before Write Min. 0 0 0 ns

tELWL tCS CE Setup Time Min. 0 0 0 ns

tWHEH tCH CE Hold Time Min. 0 0 0 ns

tWLWH tWP Write Pulse Width Min. 35 45 50 ns

tWHWL tWPH Write Pulse Width High Min. 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ. 16 16 16 µs

tWHWH2 tWHWH2 Erase Operation (Note 1) Typ. 1.5 1.5 1.5 sec

Max. 30 30 30 sec

—tVCS VCC Setup Time (Note 3) Min. 50 50 50 µs

—tVLHT Voltage Transition Time (Notes 2, 3) Min. 4 4 4 µs

—tWPP Write Pulse Width (Note 2) Min. 100 100 100 µs

—tOESP OE Setup Time to WE Active (Notes 2, 3) Min. 4 4 4 µs

—tCSP CE Setup Time to WE Active (Note 3) Min. 4 4 4 µs

—tRP RESET Pulse Width Min. 500 500 500 ns

—tFLQZ BYTE Switching Low to Output High-Z (Notes 3, 4) Max. 20 30 30 ns

—tBUSY Program/Erase Valid to RY/BY Delay (Note 3) Min. 30 35 50 ns

MBM29F400TA/MBM29F400BA

• Write/Erase/Program Operations

Alternate CE Controlled Writes

Notes: 1. This does not include the preprogramming time.

2. Not 100% tested.

Parameter Symbol Description –70 –90 –12 Unit

JEDEC Standard

tAVAV tWC Write Cycle Time (Note 2) Min. 70 90 120 ns

tAVEL tAS Address Setup Time Min. 0 0 0 ns

tELAX tAH Address Hold Time Min. 45 45 50 ns

tDVEH tDS Data Setup Time Min. 30 45 50 ns

tEHDX tDH Data Hold Time Min. 0 0 0 ns

—tOES Output Enable Setup Time Min. 0 0 0 ns

—tOEH Output Enable

Hold Time

(Note 2)

Read (Note 2) Min. 0 0 0 ns

Toggle and Data Polling Min. 10 10 10 ns

tGHEL tGHEL Read Recover Time Before Write Min. 0 0 0 ns

tWLEL tWS WE Setup Time Min. 0 0 0 ns

tEHWH tWH WE Hold Time Min. 0 0 0 ns

tELEH tCP CE Pulse Width Min. 35 45 50 ns

tEHEL tCPH CE Pulse Width High Min. 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ. 16 16 16 µs

tWHWH2 tWHWH2 Erase Operation (Note 1) Typ. 1.5 1.5 1.5 sec

Max. 30 30 30 sec

—tVCS VCC Setup Time (Note 2) Typ. 50 50 50 µs

—tRP RESET Pulse Width Min. 500 500 500 ns

—tFLQZ BYTE Switching Low to Output High-Z (Note 2) Max. 20 30 30 ns

—tBUSY Program/Erase Valid to RY/BY Delay (Note 2) Min. 30 35 50 ns

MBM29F400TA/MBM29F400BA

■SWITCHING W A VEFORMS

• Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

Must Be

Steady

May

Change

from H to L

May

Change

from L to H

DON’T CARE:

Any Change

Permitted

Does Not

Apply

Will Be

Steady

Will Be

Changing

from H to L

Will Be

Changing

from L to H

Changing

State

Unknown

Center Line is

High-

Impedance

“Off” State

tACC

(tDF)

(tOH)

(tCE)

tOEH

tOE

Outputs

tRC

Addresses Addresses Stable

High-Z Output Valid High-Z

Figure 5 AC Waveforms for Read Operations

MBM29F400TA/MBM29F400BA

Figure 6 Alternate WE Controlled Program Operation Timings

tGHWL

tWP

tDF

tDS

tWHWH1

tWC tAH

5.0 V

tRC

Addresses

Data

tAS

tOE

tWPH

tCS

tDH

DQ 7

A0H DOUT

tCE

5555H PA PA

tOH

Data Polling

3rd Bus Cycle

Notes:1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode.

MBM29F400TA/MBM29F400BA

Figure 7 Alternate CE Controlled Program Operation Timings

tGHEL

tCP

tDS

tWHWH1

tWC tAH

5.0 V

Addresses

Data

tAS

t WH

tCPH

tWS

tDH

DQ 7

A0H DOUT

5555H PA PA

Data Polling3rd Bus Cycle

Notes:1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode.

MBM29F400TA/MBM29F400BA

Figure 8 AC Waveforms Chip/Sector Erase Operations

tGHWL

tDS

VCC

Addresses

Data

tDH

tAH

5555H 2AAAH 5555H

5555H 2AAAH SA

tWPH

tCS

tWP

tVCS

tAS

AAH 55H 80H AAH 55H 10H/

30H

Notes:1. SA is the sector address for Sector Erase. Addresses = 5555H for Word, AAAAH for Byte.

2. These waveforms are for the ×16 mode.

MBM29F400TA/MBM29F400BA

tOEH

tOE

tWHWH1 or 2

tOH

DQ7

tOE

tDF

tCH

tCE

High-Z

DQ7 =

Valid Data

DQ0 to DQ6DQ0 to DQ6 = Invalid

DQ0 to DQ6

alid Data

DQ7

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

* : DQ7 = Valid Data (The device has completed the Embedded operation.)

tOEH

DQ6

Data

(DQ0 to DQ7)DQ6 = Toggle DQ6 = Toggle DQ6 = 

Stop Toggling DQ0 to DQ7

Valid

tOE

tOES

Figure 10 AC Waveforms for Toggle Bit during Embedded Algorithm Operations

* : DQ6 stops toggling. (The device has completed the Embedded operation.)

MBM29F400TA/MBM29F400BA

Figure 11 RY/BY Timing Diagram during Program/Erase Operations

The rising edge of the last WE signal

RY/BY

t BUSY

Entire programming

or erase operations

Figure 12 RESET/RY/BY Timing Diagram

RY/BY

tRP

RESET

tREADY

MBM29F400TA/MBM29F400BA

Figure 13 BYTE Timing Diagram for Read Operations

tFLQZ

BYTE

DQ0 to DQ14

DQ15/A–1

Data Output

(DQ0 to DQ14)

Data Output

(DQ0 to DQ7)

Address

Input

DQ15

Output

tELFL

tELFH

Figure 14 BYTE Timing Diagram for Write Operations

The falling edge of the last WE signal

tHOLD

BYTE

(tAH)

tSET

(tAS)

MBM29F400TA/MBM29F400BA

tVLHT

SAX: Sector Address for initial sector

SAX

A17, A16

A15, A14

A13, A12 SAY

12 V

5 V

tVLHT

12 V

5 V

tVLHT

tOESP

tCSP

tWPP

tOE

01H

Data

SAY: Sector Address for next sector

Note: Byte mode: A-1 = VIL

Figure 15 AC Waveforms for Sector Protection

12 V

5 V 5 V

RESET

RY/BY Program or Erase Command Sequence

tVLHT

Figure 16 Temporary Sector Group Unprotection

MBM29F400TA/MBM29F400BA

* :Device is either powered-down, erase inhibit or program inhibit.

Table 9 Embedded Programming Algorithm

Bus Operation Command Sequence Comment

Standby* — —

Write Program Valid Address/Data Sequence

Read — Data Polling to Verify Programming

Standby* — Compare Data Output to Data Expected

Figure 17 Embedded Programming Algorithm

EMBEDDED ALGORITHMS

Yes

Start

Program Command Sequence (Address/Command):

5555H/AAH

2AAAH/55H

5555H/A0H

Write Program Command 

Sequence

(See Below)

Data Polling Device

Increment Address Last Address

Programming Completed

Program Address/Program Data

MBM29F400TA/MBM29F400BA

* :Device is either powered-down, erase inhibit or program inhibit.

Table 10 Embedded Erase Algorithm

Bus Operation Command Sequence Comment

Standby* — —

Write Erase —

Read — Data Polling to Verify Erasure

Standby* — Compare Output to FFH

Start

5555H/AAH

2AAAH/55H

5555H/AAH

5555H/80H

5555H/10H

2AAAH/55H

5555H/AAH

2AAAH/55H

5555H/AAH

5555H/80H

2AAAH/55H

Additional sector

erase commands

are optional.

Write Erase Command

Sequence

(See Below)

Data Polling or Toggle Bit

Successfully Completed

Erasure Completed

Chip Erase Command Sequence

(Address/Command):

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Sector Address/30H

Figure 18 Embedded Erase Algorithm

EMBEDDED ALGORITHMS

MBM29F400TA/MBM29F400BA

Fail

DQ7 = Data ?

DQ5 = 1 ?

Pass

Yes

Start

Read Byte

(DQ0 to DQ7)

Addr. = VA

Read Byte

(DQ0 to DQ7)

Addr. = VA

Yes

Figure 19 Data Polling Algorithm

Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

VA = Byte address for programming

= Any of the sector addresses

within the sector being erased

during sector erase operation.

= XXXXH during chip erase

MBM29F400TA/MBM29F400BA

Figure 20 Toggle Bit Algorithm

Fail

DQ6 = Toggle

Yes

DQ6 = Toggle

DQ5 = 1 ?

Pass

Yes

Start

Read Byte

(DQ0 to DQ7)

Addr. = VA

Read Byte

(DQ0 to DQ7)

Addr. = H or L

Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1” .

MBM29F400TA/MBM29F400BA

Figure 21 Sector Protection Algorithm

Set Up Sector Addr.

(A17, A16, A15, A14, A13, A12)

Activate WE Pulse



VIH, CE

VIL

A9 should remain VID

Yes

VID, A9

VID, 

VIL, RESET

VIH

PLSCNT = 1

Time out 100 µs

Read from Sector

Addr. = SA, A0 = 0, A1 = 1, A6 = 0

Remove VID from A9 

Write Reset Command

Increment PLSCNT

Yes

Protect Another Sector?

Start

Device Failed

Sector Protection

Completed

Data = 01H ?

PLSCNT = 25

Remove VID from A9 

Write Reset Command

MBM29F400TA/MBM29F400BA

Figure 22 Temporary Sector Unprotection Algorithm

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Start

Temporary Sector

Unprotection Completed

(Note 2)

1. All protected sectors are unprotected.

2. All previously protected sectors are protected once again.

Notes:

MBM29F400TA/MBM29F400BA

■ERASE AND PROGRAMMING PERFORMANCE

■TSOP PIN CAPACITANCE

Notes: 1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz

■SOP PIN CAPACITANCE

Notes: 1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz

Parameter Limit Unit Comment

Min. Typ. Max.

Sector Erase Time — 1.5 30 sec Excludes 00H programming

prior to erasure

Byte Programming Time — 16 1,000 µsExcludes system-level

overhead

Chip Programming Time — 8.5 50 sec Excludes system-level

overhead

Erase/Program Cycle 100,000 1,000,000 — Cycles

Parameter

Symbol Parameter Description Test Setup Typ. Max. Unit

CIN Input Capacitance VIN = 0 8 9 pF

COUT Output Capacitance VOUT = 0 8 10 pF

CIN2 Control Pin Capacitance VIN = 0 8.5 11.5 pF

Parameter

Symbol Parameter Description Test Setup Typ. Max. Unit

CIN Input Capacitance VIN = 0 7.5 9 pF

COUT Output Capacitance VOUT = 0 8 10 pF

CIN2 Control Pin Capacitance VIN = 0 8.5 11 pF

MBM29F400TA/MBM29F400BA

■PACKAGE DIMENSIONS

+0.25

–0.20 +.010

–.008

–.002

+.004

–0.05

+0.10

26.67(1.050)REF

0.10(.004)

0.15±0.05

(.567±.008)

14.40±0.20

28.45 1.120

(STAND OFF)

LEAD No.

44 23

221

0(0)MIN

(.031±.008)

0.80±0.20

(.630±.008)(.512±.004) 16.00±0.20

13.00±0.10

2.50(.098)MAX

(.006±.002)

1.27(.050)NOM

Ø0.13(.005) M

.016

0.40

INDEX

"A"

Details of "A" part

0.30(.012)

0.15(.006)

0.18(.007)MAX

0.58(.025)MAX

(MOUNTING HEIGHT)

(Sufﬁx: PFN)

(FPT-44P-M16) *2 Resin Protrusion:(Each Side:0.38(.015)MAX)

*1 Resin Protrusion:(Each Side:0.15(.006)MAX)

Dimensions in mm(inches)

+0.10

–0.05

+.004

–.002

12.00±0.20(.472±.008)*

LEAD No.

2524

STAND OFF

0.10(.004) M

1.10

.043

0(0)MIN

(.008±.004)

0.20±0.10

TYP

0.50(.0197)

11.50(.460)REF

(.006±.002)

0.15±0.10

(.020±.004)

0.50±0.10

0.10(.004)

(.748±.008)

19.00±0.20

(.787±.008)

20.00±0.20

(.724±.008)

18.40±0.20

"A"

INDEX

0.25(.010)0.15(.006) MAX

0.35(.014)

MAX

0.15(.006)

Details of "A" part

1994 FUJITSU LIMITED F48030S 1C 1

(Sufﬁx: PFTN)

(FPT-48P-M19)

(MOUNTING HEIGHT)

* Resin Protrusion:(Each Side:0.15(.006)MAX)

Dimensions in mm(inches)

MBM29F400TA/MBM29F400BA

+0.10

–0.05

+.004

–.002

(.472±.008)

12.00±0.20

LEAD No.

2524

STAND OFF

0.10(.004)

1.10

.043

0(0)MIN

(.008±.004)

0.20±0.10

TYP

0.50(.0197)

(.460)

11.50REF

(.006±.002)

0.15±0.05

(.020±.004)

0.50±0.10

0.10(.004)

(.748±.008)

19.00±0.20

(.787±.008)

20.00±0.20

(.724±.008)

18.40±0.20

"A"

INDEX

0.25(.010)0.15(.006) MAX

0.35(.014)

MAX

0.15(.006)

Details of "A" part

(Sufﬁx: PFTR)

(FPT-48P-M20)

* Resin Protrusion:(Each Side:0.15(.006)MAX)

(MOUNTING HEIGHT)

Dimensions in mm(inches)

MBM29F400TA/MBM29F400BA

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-88, Japan

Tel: (044) 754-3753

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Asia Paciﬁc

FUJITSU MICROELECTR ONICS ASIA PTE. LIMITED

No. 51 Bras Basah Road,

Plaza By The Park,

#06-04 to #06-07

Singapore 189554

Tel: 336-1600

Fax: 336-1609

F9606

 FUJITSU LIMITED Printed in Japan

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