 
   
SCAS535C − SEPTEMBER 1995 − REVISED OCT OBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D4.5-V to 5.5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 10 ns at 5 V
DInputs Are TTL-Voltage Compatible
SN54ACT08 ... J OR W PACKAGE
SN74ACT08 ... D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
SN54ACT08 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
3Y
3A V
2Y
GND
NC
NC − No internal connection
CC
4B
description/ordering information
The ’ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean functions
Y = A B or Y = A + B in positive logic.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74ACT08N SN74ACT08N
SOIC − D
Tube SN74ACT08D
ACT08
SOIC − D Tape and reel SN74ACT08DR ACT08
−40°C to 85°CSOP − NS Tape and reel SN74ACT08NSR ACT08
−40 C to 85 C
SSOP − DB Tape and reel SN74ACT08DBR AD08
TSSOP − PW
Tube SN74ACT08PW
AD08
TSSOP − PW Tape and reel SN74ACT08PWR AD08
CDIP − J Tube SNJ54ACT08J SNJ54ACT08J
−55°C to 125°CCFP − W Tube SNJ54ACT08W SNJ54ACT08W
−55 C to 125 C
LCCC − FK Tube SNJ54ACT08FK SNJ54ACT08FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
OUTPUT
Y
H H H
LXL
X L L
Copyright 2003, Texas Instruments Incorporated
  ! " #$%! "  &$'(#! )!%*
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"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/  (( &%!%"*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 &)$#!" #&(! ! 0122 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)*  (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"*
 
   
SCAS535C − SEPTEMBER 1995 − REVISED OCT OBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram, each gate (positive logic)
Y
A
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT08 SN74ACT08
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
IOH High-level output current −24 −24 mA
IOL Low-level output current 24 24 mA
∆t/∆vInput transition rise or fall rate 8 8 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
 
   
SCAS535C − SEPTEMBER 1995 − REVISED OCT OBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54ACT08 SN74ACT08
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
IOH = −50 A
4.5 V 4.4 4.49 4.4 4.4
IOH = −50 µA5.5 V 5.4 5.49 5.4 5.4
VOH
IOH = −24 mA
4.5 V 3.86 3.7 3.76
V
VOH IOH = −24 mA 5.5 V 4.86 4.7 4.76 V
IOH = −50 mA†5.5 V 3.85
IOH = −75 mA†5.5 V 3.85
IOL = 50 A
4.5 V 0.001 0.1 0.1 0.1
IOL = 50 µA5.5 V 0.001 0.1 0.1 0.1
VOL
IOL = 24 mA
4.5 V 0.36 0.5 0.44
V
VOL IOL = 24 mA 5.5 V 0.36 0.5 0.44 V
IOL = 50 mA†5.5 V 1.65
IOL = 75 mA†5.5 V 1.65
IIVI = VCC or GND 5.5 V "0.1 "1"1µA
ICC VI = VCC or GND, IO = 0 5.5 V 2 80 20 µA
DICC‡One input at 3.4 V,
Other inputs at GND or VCC 5.5 V 0.6 1.6 1.5 mA
CiVI = VCC or GND 5 V 4.5 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C SN54ACT08 SN74ACT08
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
A or B
Y
1 6.5 9 1 10 1 10
ns
tPHL
A or B
Y
1 6.5 9 1 10 1 10
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 20 pF
 
   
SCAS535C − SEPTEMBER 1995 − REVISED OCT OBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output 50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
500 Ω
500 Ω Open
S1TEST
tPLH/tPHL Open
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 9-Mar-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-89547022A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
89547022A
SNJ54ACT
08FK
5962-8954702CA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8954702CA
SNJ54ACT08J
5962-8954702DA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8954702DA
SNJ54ACT08W
SN74ACT08D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD08
SN74ACT08DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT08N
SN74ACT08NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT08
SN74ACT08PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD08
SN74ACT08PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 AD08
SN74ACT08PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD08
SNJ54ACT08FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
89547022A
SNJ54ACT
08FK
PACKAGE OPTION ADDENDUM
www.ti.com 9-Mar-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54ACT08J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8954702CA
SNJ54ACT08J
SNJ54ACT08W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8954702DA
SNJ54ACT08W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Mar-2021
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF SN54ACT08, SN74ACT08 :
•Catalog: SN74ACT08
•Enhanced Product: SN74ACT08-EP, SN74ACT08-EP
•Military: SN54ACT08
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ACT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT08DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74ACT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT08DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74ACT08DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT08DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ACT08NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74ACT08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74ACT08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74ACT08PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT08DR SOIC D 14 2500 853.0 449.0 35.0
SN74ACT08DR SOIC D 14 2500 364.0 364.0 27.0
SN74ACT08DR SOIC D 14 2500 333.2 345.9 28.6
SN74ACT08DRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74ACT08DRG4 SOIC D 14 2500 853.0 449.0 35.0
SN74ACT08DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74ACT08NSR SO NS 14 2000 853.0 449.0 35.0
SN74ACT08PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74ACT08PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74ACT08PWRG4 TSSOP PW 14 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER
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