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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DFour 8-Bit D/A Converters
DProgrammable Settling Time
of 2.5 µs or 8.5 µs Typ
DTMS320, (Q)SPI, and Microwire
Compatible Serial Interface
DLow Power Consumption:
7 mW, Slow Mode − 5-V Supply
3 mW, Slow Mode − 3-V Supply
DReference Input Buffers
DMonotonic Over Temperature
DDual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
DHardware Power Down
DSoftware Power Down
DSimultaneous Update
applications
DBattery Powered Test Instruments
DDigital Offset and Gain Adjustment
DIndustrial Process Controls
DMachine and Motion Control Devices
DArbitrary Waveform Generation
description
The TLV5627 is a four channel, 8-bit voltage
output digital-to-analog converter (DAC) with a
flexible 4-wire serial interface. The 4-wire serial
interface allows glueless interface to TMS320,
SPI, QSPI, and Microwire serial ports. The
TLV5627 is programmed with a 16-bit serial word
comprised of a DAC address, individual DAC
control bits, and an 8-bit DAC value.
The device has provision for two supplies: one
digital supply for the serial interface (via pins
DVDD and DGND), and one for the DACs,
reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and
can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be
controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs
operating on a 5-V supply. The digital and analog supplies can be tied together.
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down
mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable
to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a dif ferent reference voltage than DACs C and D.
The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The
TLV5627C is characterized for operation from 0°C to 70°C. The TLV5627I is characterized for operation from
−40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(
!,'&$% &!" $ %)(&&#$% )(! $-( $(!"% (.#% %$!'"($%
%$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',(
$(%$1 #++ )#!#"($(!%
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DVDD
PD
LDAC
DIN
SCLK
CS
FS
DGND
AVDD
REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND
(TOP VIEW)
D OR PW PACKAGE
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
SLAS232A − JUNE1999 − REVISED JULY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TASOIC
(D) TSSOP
(PW)
0°C to 70°C TLV5627CD TLV5627CPW
−40°C to 85°C TLV5627ID TLV5627IPW
functional block diagram
7
5
Power-On
Reset
10-Bit
Data
and
Control
Register
REFINAB
AGND
CS
DIN
DAC A
Serial
Input
Register
6
9
8-Bit
DAC
Latch
2-Bit
Control
Data
Latch Power Down/
Speed Control
_
+
8
22
8
10
OUTA
DAC
Select/
Control
Logic
FS
DAC B
DAC C
DAC D
OUTB
OUTC
OUTD
LDAC PD
DGND
AV
DD
DV
DD
4
15 16 1
8
32
11
12
13
14
REFINCD
SCLK
2
x2
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 9 Analog ground
AVDD 16 Analog supply
CS 6 I Chip select. This terminal is active low.
DGND 8 Digital ground
DIN 4 I Serial data input
DVDD 1Digital supply
FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
to the TLV5627.
PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
LDAC 3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
REFINAB 15 I Voltage reference input for DACs A and B.
REFINCD 10 I Voltage reference input for DACs C and D.
SCLK 5 I Serial clock input
OUTA 14 O DAC A output
OUTB 13 O DAC B output
OUTC 12 O DAC C output
OUTD 11 ODAC D output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, (DVDD, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage difference, (AVDD to DVDD) −2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5627C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5627I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DVDD
5-V supply 4.5 5 5.5
V
Supply voltage, AVDD, DVDD 3-V supply 2.7 3 3.3 V
High-level digital input voltage, VIH
DVDD = 2.7 V 2
V
High-level digital input voltage, VIH DVDD = 5.5 V 2.4 V
Low-level digital input voltage, VIL
DVDD = 2.7 V 0.6
V
Low-level digital input voltage, VIL DVDD = 5.5 V 1V
Reference voltage, Vref to REFINAB, REFINCD terminal
5-V supply (see Note 1) 0 2.048 AVDD−1.5
V
Reference voltage, Vref to REFINAB, REFINCD terminal 3-V supply (see Note 1) 0 1.024 AVDD−1.5 V
Load resistance, RL2 10 kΩ
Load capacitance, CL100 pF
Serial clock rate, SCLK 20 MHz
Operating free-air temperature
TLV5627C 0 70
°C
Operating free-air temperature TLV5627I −40 85 °C
NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 8 bits
Integral nonlinearity (INL), end point adjusted See Note 2 ±0.3 ±0.5 LSB
Differential nonlinearity (DNL) See Note 3 ±0.03 ±0.5 LSB
EZS Zero scale error (offset error at zero scale) See Note 4 ±10 mV
Zero scale error temperature coefficient See Note 5 10 ppm/°C
EGGain error See Note 6 ±0.6 %of FS
voltage
Gain error temperature coefficient See Note 7 10 ppm/°C
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − EZS (Tmin)]/Vref × 106/(Tmax − Tmin).
6. Gain error is the deviation from the ideal output (2V ref − 1 LSB) with an output load of 10 k Ω excluding the effects of the zero-error .
7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).
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electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVoltage output RL = 10 kΩ0AVDD−0.4 V
Output load regulation accuracy RL = 2 kΩ vs 10 kΩ0.1 0.25 % of FS
voltage
reference input (REFINAB, REFINCD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range See Note 8 0AVDD−1.5 V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF
Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 9) −75 dB
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc
Slow 0.5
MHz
Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc Fast 1 MHz
NOTES: 8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0−D11, CS, WEB, LDAC, PD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = DVDD ±1µA
IIL Low-level digital input current VI = 0 V ±1µA
CIInput capacitance 3 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
5-V supply, No load, Clock running
Slow 1.4 2.2
mA
IDD
Power supply current
5-V supply, No load, Clock running Fast 3.5 5.5 mA
IDD Power supply current
3-V supply, No load, Clock running
Slow 1 1.5
mA
3-V supply, No load, Clock running Fast 3 4.5 mA
Power down supply current, See Figure 12 1µA
PSRR
Power supply rejection ratio
Zero scale gain
See Notes 10 and 11
−68
dB
PSRR Power supply rejection ratio Gain See Notes 10 and 11 −68 dB
10. Zero-scale-error rejection ratio (EZS−RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
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electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Output slew rate
CL = 100 pF, RL = 10 kΩ,
VO = 10% to 90%,
Fast 5 V/µs
SR Output slew rate
LL
V
O
= 10% to 90%,
Vref = 2.048 V, 1024 V Slow 1 V/µs
ts
Output settling time
To
±
0.1 LSB, CL = 100 pF,
Fast 2.5 4
s
tsOutput settling time
To ±0.1 LSB, CL = 100 pF,
RL = 10 kΩ, See Notes 12 and 14 Slow 8.5 18 µs
ts(c)
Output settling time, code to code
To
±
0.1 LSB, CL = 100 pF,
Fast 1
s
ts(c) Output settling time, code to code
To ±0.1 LSB, CL = 100 pF,
RL = 10 kΩ, See Notes 13 and 14 Slow 2 µs
Glitch energy Code transition from 7F0 to 800 10 nV-sec
SNR Signal-to-noise ratio
Sinewave generated by DAC,
57
S/(N+D) Signal to noise + distortion
Sinewave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
49
dB
THD Total harmonic distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS, fOUT = 1.1 kHz sinewave,
CL = 100 pF, RL = 10 kΩ, BW = 20 kHz
−50 dB
SFDR Spurious free dynamic range
fs = 400 KSPS, fOUT = 1.1 kHz sinewave,
CL = 100 pF, RL = 10 kΩ, BW = 20 kHz 60
NOTES: 12. Settling time is the time for the output signal to remain within ±0.1 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020.
13. Settling time is the time for the output signal to remain within ±0.1 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
digital input timing requirements
MIN NOM MAX UNIT
tsu(CS−FS) Setup time, CS low before FS↓10 ns
tsu(FS−CK) Setup time, FS low before first negative SCLK edge 8 ns
tsu(C16−FS) Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS 10 ns
tsu(C16−CS) Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge. 10 ns
twH Pulse duration, SCLK high 25 ns
twL Pulse duration, SCLK low 25 ns
tsu(D) Setup time, data ready before SCLK falling edge 8 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
twH(FS) Pulse duration, FS high 20 ns
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PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
123451516
D15 D14 D13 D12 D1 D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
tsu(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
Figure 2
0.20
0.10
0.05
0
− Output Voltage − V
0.25
0.30
Load Current − mA
LOAD REGULATION
0.35
0.15
VO
0 0.02 0.04 0.1 0.2 0.4 1 2 40.8
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
5 V Slow Mode, Sink
5 V Fast Mode, Sink
Figure 3
0.10
0.08
0.04
0
0.16
0.18
LOAD REGULATION
0.20
0.14
0.12
0.06
0.02
− Output Voltage − V
Load Current − mA
VO
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
3 V Slow Mode, Sink
3 V Fast Mode, Sink
0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8
Figure 4
3.994
3.99
3.986
3.984
3.996
4.00
LOAD REGULATION
4.002
3.998
3.992
3.988
− Output Voltage − V
Load Current − mA
VO
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
5 V Slow Mode, Source
5 V Fast Mode, Source
0 0.02 0.04 0.1 0.2 0.4 1 2 40.8
Figure 5
2.0015
2.0005
1.9995
1.999
2.002
2.0025
LOAD REGULATION
2.003
2.001
2
− Output Voltage − V
Load Current − mA
VO
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
3 V Slow Mode, Source
3 V Fast Mode, Source
0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8
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TYPICAL CHARACTERISTICS
Figure 6
2.5
2
1.5
0.5
− Supply Current − mA
3
3.5
SUPPLY CURRENT
vs
TEMPERATURE
4
1
T − Temperature − °C
IDD
−40 −20 0 20 40 60 80 100
Fast Mode
Slow Mode
VDD = 3 V,
VREF = 1.024 V,
VO = Full Scale
Figure 7
2.5
2
1.5
0.5
− Supply Current − mA
3
3.5
SUPPLY CURRENT
vs
TEMPERATURE
4
1
T − Temperature − °C
IDD
−40 −20 0 20 40 60 80 100
Fast Mode
Slow Mode
VDD = 5 V,
VREF = 1.024 V,
VO = Full Scale
Figure 8
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 9
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Slow Mode
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10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion And Noise − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 11
−−40
−50
−70
−80 0 5 10 20
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
THD − Total Harmonic Distortion And Noise − dB
Slow Mode
2000
1500
1000
00 200 400 600
− Supply Current −
3000
3500
t − Time − ns
SUPPLY CURRENT
vs
TIME
(WHEN ENTERING POWER-DOWN MODE)
4000
800 1000
2500
500
IDD Aµ
Figure 12
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TYPICAL CHARACTERISTICS
Figure 13
−0.20
−0.15
−0.10
−0.05
−0.00
0.05
0.10
0.15
0.20
0 255
DNL − Differential Nonlinearity − LSB
Digital Output Code
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
12864 192
Figure 14
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
0 255
INL − Integral Nonlinearity − LSB
Digital Output Code
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
64 128 192
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12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The T LV5627 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buf fer , a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
2REFCODE
2n[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n−1, where
n=8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format
section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS
rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.
The serial interface of the TLV5627 can be used in two basic modes:
DFour wire (with chip select)
DThree wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5627s connected directly to a TMS320 DSP.
TMS320
DSPXF0
XF1
FSX
DX
CLKX
TLV5627
CS FS DIN SCLK
TLV5627
CS FS DIN SCLK
Figure 15. TMS320 Interface
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APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5627 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSPFSX
DX
CLKX
TLV5627
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5627
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5627
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5627. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
fSCLKmax +1
twH(min) )twL(min) +20 MHz
The maximum update rate is:
fUPDATEmax +1
16 ǒtwH(min))twL(min)Ǔ+1.25 MHz
The maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5627
has to be considered also.
data format
The 16-bit data word for the TLV5627 consists of two parts:
DControl bits (D15 . . . D12)
DNew DAC value (D11 ...D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 PWR SPD New DAC value (8 bits) 0000
SPD: Speed control bit. 1 → fast mode 0 → slow mode
PWR: Power control bit. 1 → power down 0 → normal operation
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APPLICATION INFORMATION
In power-down mode, all amplifiers within the TLV5627 are disabled. A particular DAC (A, B, C, D) of the
TLV5627 is selected by A1 and A0 within the input word.
A1 A0 DAC
0 0 A
0 1 B
1 0 C
1 1 D
TLV5627 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example of how to connect the TLV5627 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the
TLV5627. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose
input/output port bits IO0 and IO1 are used to generate the chip select (CS) and DAC latch update (LDAC)
inputs to the TLV5627. The active low power down (PD) is pulled high all the time to ensure the DACs are
enabled.
DX
CLKX
FSX
I/O 0
I/O 1
TMS320C203
SDIN
SCLK
FS
CS
LDAC
REF
VDD
PD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
TLV5627
REFINAB
REFINCD
Figure 17. TLV5627 Interfaced with TMS320C203
SLAS232A − JUNE1999 − REVISED JULY 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TLV5627 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5627 to an MCS51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5627. The active low power
down pin (PD) of the TLV5627 is pulled high to ensure that the DACs are enabled.
RxD
TxD
P3.3
P3.4
MCS®51
SDIN
SCLK
FS
CS
LDAC
REF
VDD
PD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
TLV5627
P3.4
REFINAB
REFINCD
Figure 18. TLV5627 Interfaced with MCS51
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage of fset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
DAC Code
Output
Voltage
0 V
Negative
Offset
Figure 19. Effect of Negative Offset (single supply)
MCS is a registered trademark of Intel Corporation.
SLAS232A − JUNE1999 − REVISED JULY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies (continued)
The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes of fer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well-managed and there are negligible voltage drops across the ground plane.
A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 20 shows the ground plane layout and bypassing technique.
0.1 µF
Analog Ground Plane
1
2
3
4
8
7
6
5
Figure 20. Power-Supply Bypassing
SLAS232A − JUNE1999 − REVISED JULY 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SLAS232A − JUNE1999 − REVISED JULY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65 M
0,10
0°−ā8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV5627CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627IPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5627IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2008
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5627CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV5627CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV5627IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5627CDR SOIC D 16 2500 346.0 346.0 33.0
TLV5627CPWR TSSOP PW 16 2000 346.0 346.0 29.0
TLV5627IPWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 2
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