1
LTC1759
Smart Battery Charger
The LTC
®
1759 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construc-
tion of an SBS compliant system. The LTC1759 imple-
ments a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A thermistor
on the battery being charged is monitored for tempera-
ture, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to it,
including thermistor status (via the ChargerStatus com-
mand). The charger also provides an interrupt to the host
whenever a status change is detected (e.g., battery
removal,
AC adapter connection).
Charging current and voltage are restricted to chemistry
specific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Addi-
tionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging cur-
rent. When supplying system load current, charging cur-
rent is automatically reduced to prevent adapter overload.
■
Single Chip Smart Battery Charger Controller
■
100% Compliant (Rev 1.0) SMBus Support
Allows for Operation with or without Host
■
SMBus Accelerator Improves SMBus Timing
■
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
■
High Efficiency Synchronous Buck Charger
■
0.5V Dropout Voltage; Maximum Duty Cycle > 99.5%
■
AC Adapter Current Limit Maximizes Charge Rate*
■
1% Voltage Accuracy; 5% Current Accuracy
■
Up to 8A Charging Current Capability
■
Dual 10-Bit DACs for Charger Voltage and Current
Programming
■
User-Selectable Overvoltage and Overcurrent Limits
■
High Noise Immunity Thermistor Sensor
■
Small 36-Lead Narrow (0.209") SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
Figure 1. 4A SMBus Smart Battery Charger
■
Portable Computers
■
Portable Instruments
■
Docking Stations
*US Patent Number 5,723,970
UV
V
DD
SYNC
SDB
CHGEN
V
LIMIT
I
LIMIT
DGND
I
SET
PROG
V
C
COMP1
AGND
RNR
THERM
SDA
SCL
INTB
22
21
8
32
9
10
2
33
34
1
3
35
30
29
31
23
26
36
3.83k
1.5k
LTC1759
1k
1k
499Ω
475k 10k
0.1µF
0.33µF
V
DD
V
DD
1µF
0.68µF
33k
0.033Ω
200Ω
68Ω
200Ω
15.8k 1k
0.47µF
2.2µF
0.68µF
0.047µF
0.1µF
1µF
15µH
22µF
SYSTEM
POWER
0.025Ω
33k
7
16
4
5
12
25
24
18
17
28
27
11
6
20
19
14
15
13
DCIN
DCDIV
INFET
V
CC
CLP
CLN
TGATE
BOOSTC
GBIAS
BOOST
SW
BGATE
SPIN
SENSE
BAT1
BAT2
V
SET
PGND 0.015µF
22µF
0.1µF
10µF
35V
Al
AC
ADAPTER
INPUT
SMART
BATTERY
INTB SMBus
TO
HOST
SCL
SDA
1759 F01
+
+
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
2
LTC1759
ABSOLUTE MAXIMUM RATINGS
W
WW
U
(Note 1)
Voltage at V
CC
, UV, BAT1, CLP,CLN, SPIN,
SENSE with respect to AGND ....................–0.3V to 27V
Voltage at DCIN, BAT2 with Respect
to DGND ....................................................–0.3V to 27V
Voltage at INTB, SDA, SCL, DCDIV with Respect
to DGND ..................................................... – 0.3V to 7V
BOOST, BOOSTC Voltage with Respect to V
CC
........ 10V
Voltage at V
DD
with Respect to DGND ........ –0.3V to 7V
SW Voltage with Respect to AGND .............. –2V to V
CC
GBIAS, SYNC ............................................ –0.3V to 10V
V
C
, PROG, V
SET
Voltage with Respect
to AGND ......................................................–0.3V to 7V
TGATE, BGATE Current Continuous ..................±200mA
TGATE, BGATE Output Energy (per Cycle) ................2µJ
PGND, DGND with Respect to AGND .................... ±0.3V
Current into Any Pin .........................................±100mA
Operating Ambient Temperature Range...... 0°C to 70°C
Operating Junction
Temperature Range .............................. –40°C to 125°C
Storage Temperature ........................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
Consult factory for Industrial and Military grade parts.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PGND
BGATE
GBIAS
BOOSTC
V
CC
BAT1
SPIN
SENSE
PROG
V
C
V
SET
V
LIMIT
I
LIMIT
BAT2
DCIN
DCDIV
RNR
THERM
BOOST
TGATE
SW
SYNC
SDB
AGND
UV
INFET
CLP
CLN
COMP1
CHGEN
INTB
SDA
SCL
V
DD
I
SET
DGND
T
JMAX
= 125°C, θ
JA
= 85°C/ W
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply and Reference
DCIN, V
CC
Operating Voltage ●11 24 V
V
CC
Operating Current V
CC
≤ 24V ●12 20 mA
DCIN Operating Current V
DCIN
= 24V ●85 150 µA
UV Lockout Threshold Voltage on UV Pin Rising ●6.3 6.7 7.25 V
UV Pin Input Current 0V ≤ V
UV
≤ 8V ●–1 5 µA
Battery Discharge Current V
UV
≤ 0.4V, All Connected Pins 40 80 µA
V
DD
Operating Voltage ●3.0 5.5 V
V
DD
Operating Current Charging, V
DD
= 5.5V, Shorted Thermistor 1.35 2 mA
Not Charging, V
DD
= 5.5V 80 150 µA
V
DD
Undervoltage Lockout ●1.6 2.2 2.9 V
Switching Regulator
Charging Voltage Accuracy (Notes 3, 5) 2.465V ≤ V
BAT2
≤ V
MAX
●–1 1 %
Charging Current Accuracy (Note 3) R
SET
Tolerance = 1% –5 5 %
PACKAGE/ORDER INFORMATION
W
UU
LTC1759CG
3
LTC1759
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
BOOST Pin Current V
BOOST
= V
SW
+ 8V, 0V ≤ V
SW
≤ 20V
TGATE High 2 3 mA
TGATE Low 2 3 mA
V
BOOST
Threshold to Turn T
GATE
Off Measured at (V
BOOST
– V
SW
)
(Note 6) Low to High ●6.8 7.3 7.6 V
Hysteresis 0.25 V
BOOSTC Pin Current V
BOOSTC
= V
CC
+ 8V 1 mA
Sense Amplifier CA1 Gain and Input Offset Voltage 11V ≤ V
CC
≤ 24V, 0V ≤ V
BAT
≤ 20V
(With R
S2
= R
S3
= 200Ω)R
SET
= 4.93k ●92 100 108 mV
(Measured Across R
S1
) (Note 4) R
SET
= 49.3k 7 10 13 mV
CA1 Bias Current (SENSE, BAT1) V
SDB
= High ●–50 –120 µA
V
SDB
= Low (Shutdown) –10 µA
CA1 Input Common Mode Range ●–0.25 V
CC
– 0.3 V
SPIN Input Current V
SDB
= High, V
SPIN
= 12.6V ●2mA
V
SDB
= Low 10 µA
CL1 Turn-On Threshold 0.5mA Output Current 87 92 97 mV
CL1 Transconductance Output Current from 50µA to 500µA 0.5 1 3 mho
CLP Input Current 0.5mA Output Current 1 3 µA
CLN Input Current 0.5mA Output Current 0.8 2 mA
CA2 Transconductance V
C
= 1V, I
VC
= ±1µA 150 200 300 µmho
V
A
Transconductance (Note 5) Ouput Current from 50µA to 500µA 0.21 0.6 1 mho
Gate Drivers
V
GBIAS
V
CC
≥ 11V, I
GBIAS
≤ 15mA, V
SDB
= High ●8.4 9.1 9.6 V
V
TGATE
High (V
TGAGE
– V
SW
)I
TGATE
≤ 20mA ●5.6 6.6 V
V
BGATE
High I
BGATE
≤ 20mA ●6.2 7.2 V
V
TGATE
Low (V
TGATE
– V
SW
)I
TGATE
≤ 50mA ●0.8 V
V
BGATE
Low I
BGATE
≤ 50mA ●0.8 V
INFET “ON” Clamping Voltage (V
CC
– V
INFET
)●6.5 7.8 9 V
INFET “ON” Drive Current V
INFET
= V
CC
– 6V ●820 mA
INFET “OFF” Clamping Voltage V
CC
Not Connected, I
INFET
< –2µA 1.4 V
INFET “OFF” Drive Current V
CC
= 12.4V, (V
CC
– V
INFET
) ≥ 2V –2.5 mA
V
TGATE
, V
BGATE
at Shutdown V
SDB
= Low, I
TGATE
= I
BGATE
= 10µA●1V
Trip Points
DCDIV Threshold V
DCDIV
Rising from 0.8V to 1.2V ●0.9 1.0 1.1 V
DCDIV Hysteresis 25 mV
DCDIV Input Bias Current V
DCDIV
= 1V ●100 nA
Power-Fail Indicator (V
BAT2
≥ V
DCIN
)
(Note 7) AC_PRESENT = 1, V
DCIN
= 6V ●0.84 0.89 0.97 V/V
Power-Fail Indicator Hysteresis (V
BAT2
≥ V
DCIN
) AC_PRESENT = 1, V
DCIN
= 6V 0.02 V/V
SYNC Pin Threshold 0.9 1.4 2.0 V
SYNC Pin Input Current V
SYNC
= 0V –500 µA
V
SYNC
= 2V –30 µA
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
4
LTC1759
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Thermistor Decoder (Note 11)
Combined Input Leakage on RNR and THERM 200 nA
Thermistor Trip (COLD/OR) R
WEAK
= 475k ±1% ●80 100 120 kΩ
Thermistor Trip (IDEAL/COLD) R
NR
= 10k ±1% ●26.4 30 33.6 kΩ
Thermistor Trip (HOT/IDEAL) R
NR
= 10k ±1% ●2.64 3 3.36 kΩ
Thermistor Trip (UR/HOT) R
UR
= 1k ±1% ●440 500 560 Ω
DACs
Charging Current Resolution Guaranteed Monotonic Above I
MAX
/16 10 bits
Charging Current Granularity R
ILIMIT
= 0 1 mA
R
ILIMIT
= 10k ±1% 2 mA
R
ILIMIT
= 33k ±1% 4 mA
R
ILIMIT
= Open (or Short to V
DD
)8mA
Wake-Up Charging Current (I
WAKE-UP
) (Note 8) 80 mA
Charging Current Limit (I
MAX
)R
ILIMIT
= 0 1023 mA
R
ILIMIT
= 10k ±1% 2046 mA
R
ILIMIT
= 33k ±1% 4092 mA
R
ILIMIT
= Open (or Short to V
DD
) 8184 mA
I
SET
R
DS(ON)
25 Ω
I
SET
I
OFF
V
ISET
= 2.7V ●1µA
Charging Voltage Resolution Guaranteed Monotonic (2.5V ≤ V
BAT
≤ 21V) 10 bits
Charging Voltage Granularity R
VLIMIT
= 0 16 mV
R
VLIMIT
= 10k ±1% 16 mV
R
VLIMIT
= 33k ±1% 32 mV
R
VLIMIT
= 100k ±1% 32 mV
R
VLIMIT
= Open (or Short to V
DD
)32mV
Charging Voltage Limit R
VLIMIT
= 0 ●8.33 8.432 8.485 V
R
VLIMIT
= 10k ±1% ●12.50 12.64 12.72 V
R
VLIMIT
= 33k ±1% ●16.67 16.864 16.97 V
R
VLIMIT
= 100k ±1% ●20.82 21.056 21.18 V
R
VLIMIT
= Open (or Short to V
DD
)
(Note 2) 32.736 V
Logic Levels (Note 12)
SCL/SDA Input Low Voltage (V
IL
)●0.6 V
SCL/SDA Input High Voltage (V
IH
)●1.4 V
SDA Output Low Voltage (V
OL
)I
PULLUP
= 350µA●0.4 V
SCL/SDA Input Current (I
IL
)V
SDA
, V
SCL
= V
IL
●1µA
SCL/SDA Input Current (I
IH
)V
SDA
, V
SCL
= V
IH
●1µA
INTB Output Low Voltage (V
OL
)I
PULLUP
= 500µA●0.4 V
INTB Output Pull-Up Current V
INTB
= V
OL
●3.5 10 17.5 µA
CHGEN Output Low Voltage (V
OL
)I
OL
= 200µA●0.4 V
CHGEN Output High Voltage (V
OH
)I
OH
= –200µA●V
DD
– 0.4 V
SDB Shutdown Threshold ●12V
SDB Pin Current 0V ≤ V
SDB
≤ 3V 8 µA
Power-On Reset Duration V
DD
Ramp from 0V to > 3V in < 5µs 100 µs
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
5
LTC1759
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This limit is greater than the absolute maximum for the charger.
Therefore, there is no effective limitation on voltage when this option is
selected. If the charger is requested to charge with a higher voltage than
the nominal limit, the VOLTAGE_OR bit will be set.
Note 3: Total system accuracy from SMBus request to output voltage or
output current.
Note 4: Test Circuit #1.
Note 5: Voltage accuracy is calculated using measured reference voltage,
obtained from V
SET
pin using Test Circuit #2, and VDAC resistor divider
ratio.
Note 6: When supply and battery voltage differential is low, high oscillator
duty cycle is required. The LTC1759 has a unique design to achieve duty
cycle greater than 99% by skipping cycles. Only when V
BOOST
drops below
the comparator threshold, will TGATE be turned off. See Applications
Information section.
Note 7: Power failure bit is set when the battery voltage is above 89% of
the power adapter voltage (V
DCIN
).
Note 8: The charger provides wake-up current when a battery is inserted
into the connector, prior to the battery requesting charging current and
voltage. See Smart Battery Charger Specification (Revision 1.0), section
6.1.3 and 6.1.8.
Note 9: In system start-up, C6 (boost capacitor) has no charge stored in it.
The LTC1759 will keep TGATE off, and turn BGATE on for 0.2µs, thus
charging C6. A comparator senses V
BOOST
and switches to the normal
PWM mode when V
BOOST
is above its threshold.
Note 10: Refer to Smart Battery Charge Specification (Revision 1.0),
section 6.1.2.
Note 11: Maximum total external capacitance on RNR and THERM pins
is 75pF.
Note 12: SMBus operation guaranteed by design from –40°C to 85°C.
The ● denotes specifications which apply over the full operating temperature range (TJ = 0°C to 100°C), otherwise specifications are
TA = 25°C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Charger Timing
V
TGATE
, V
BGATE
Rise/Fall Time 1nF Load 25 ns
TGATE, BGATE Peak Drive Current 10nF Load 1 A
Regulator Switching Frequency ●170 200 230 kHz
Synchronization Frequency ●240 280 kHz
Maximum Duty Cycle in Start-Up Mode (Note 9) ●85 90 %
t
TIMEOUT
for Wake-Up Charging a ●140 175 210 sec
Cold or Underrange Battery
SMBus Timing (refer to System Management Bus Specification, Revision 1.0, section 2.1 for timing diagrams) (Note 12)
SCL Serial Clock High Period (t
HIGH
)I
PULLUP
= 350µA, C
LOAD
= 150pF ●4µs
SCL Serial Clock Low Period (t
LOW
)I
PULLUP
= 350µA, C
LOAD
= 150pF ●4.7 µs
SDA/SCL Rise Time (t
r
)C
LOAD
= 150pF ●1000 ns
SDA/SCL Fall Time (t
f
)●30 300 ns
SMBus Accelerator Boosted Pull-Up Current V
DD
= 3V ●1 2.5 mA
Start Condition Setup Time (t
SU:STA
)●4.7 µs
Start Condition Hold Time (t
HD:STA
)●4.0 µs
SDA to SCL Rising-Edge Setup Time (t
SU:DAT
)●250 ns
SDA to SCL Falling-Edge Hold Time, ●300 ns
Slave Clocking in Data (t
HD:DAT
)
t
TIMEOUT
Between Receiving Valid ●140 175 210 sec
ChargingCurrent() and ChargingVoltage()
Commands (Note 10)
6
LTC1759
TYPICAL PERFOR A CE CHARACTERISTICS
UW
1µs/DIV
1759 G02
5V
0V
R
PULLUP
= 15k
LTC1759
V
CC
= 5V
C
LD
= 200pF
T
A
= 25°C
TEMPERATURE (°C)
0
DCDIV (V)
1.10
1.05
1.00
0.95
0.90
1759 G03
10 20 30 40 50 60 70 80
V
DD
= 5.5V
V
DD
= 3V
V
BAT
(V)
6 8 10 12 14 16 18 20 22 24
I
BAT
(µA)
1759 G04
90
80
70
60
50
40
30
20
10
T
A
= 25°C
V
DD
(V)
3.0 3.5 4.0 4.5 5.0 5.5
I
DD
(µA)
1759 G05
120
110
100
90
80
70
60
T
A
= 25°C
CHARGING CURRENT (mA)
256 1256 2256 3256 4256
OUTPUT CURRENT ERROR (mA)
1759 G06
0
–10
–20
–30
–40
–50
–60
R
ILIMIT
= 33k
V
IN
= 15V
V
OUT
= 12V
T
A
= 25°C
V
DD
= 5.5V
V
DD
= 3V
CHARGING VOLTAGE (mV)
2000 3000 4000 5000 6000 7000 8000 9000
OUTPUT VOLTAGE ERROR (mV)
1759 G07
0
–5
–10
–15
–20
–25
–30
R
VLIMIT
= 0
LOAD CURRENT = 15mA
T
A
= 25°C
V
DD
= 5.5V
V
DD
= 3V
CHARGING VOLTAGE (mV)
2000 6000 10000 14000 18000
OUTPUT VOLTAGE ERROR (mV)
1759 G08
0
–5
–10
–15
–20
–25
–30
R
VLIMIT
= 33k
LOAD CURRENT = 15mA
T
A
= 25°C
V
DD
= 5.5V
V
DD
= 3V
SMBus Accelerator Operation DCDIV Trip Point vs Temperature
IDD vs VDD (Not Charging) Programmed Current Accuracy
Current from Battery vs Battery
Voltage (Does Not Include VDD
Current)
Charging Voltage ErrorCharging Voltage Error
CHARGING CURRENT (mA)
050 100 150 200 250 300
OUTPUT CURRENT (mA)
1759 G01
350
300
250
200
150
100
50
0
R
ILIMIT
= 33k
V
IN
= 15V
V
OUT
= 12V
T
A
= 25°C
C
PROG
= 1nF
R
SET
= 3.83k
Low Current Mode
CHARGING CURRENT (A)
0.5 1.5 2.5 3.5
EFFICIENCY (%)
1759 G09
100
95
90
85
80
75
70
16.8V
12.6V
VIN = 20V
Charger Efficiency
7
LTC1759
Input Power-Related Pins
UV (Pin 7): Charger Section Undervoltage Lockout Pin.
The rising threshold is 6.7V with a hysteresis of 0.5V.
Switching stops in undervoltage lockout. Connect this
input to the input voltage source with no resistor divider.
UV must be pulled below 0.7V when there is no input
voltage source (5k resistor from adapter output to ground
is required) to obtain the lowest quiescent battery current.
INFET (Pin 8): Gate Drive to Input P-channel FET. For very
low dropout applications, use an external P-channel FET to
connect the adapter output and V
CC
. INFET is clamped to
7.8V below V
CC
.
CLP (Pin 9): Positive Input to the Input Current Limit
Amplifier CL1. When used to limit supply current, a filter
(R3 and C1 of Figure 10) is needed to filter out the
switching noise. The threshold is set at 92mV.
CLN (Pin 10): Negative Input to the Input Current Limit
Amplifier CL1. It should be connected to V
CC
(to the V
CC
bypass capacitor C2 for less noise).
COMP1 (Pin 11): Compensation Node for the Input Cur-
rent Limit Amplifier CL1. At input adapter current limit, this
node rises to 1V. By forcing COMP1 low with an external
transistor, amplifier CL1 will be defeated (no adapter
current limit). COMP1 can source 200µA. Ground (to
AGND) this pin if the adapter current limiting function is
not used.
Battery Charging-Related Pins
BOOST (Pin 1): This pin is used to bootstrap and supply
power for the topside power switch gate drive and control
circuity. In normal operation, V
BOOST
is powered from an
internally generated 8.6V regulator V
GBIAS
, V
BOOST
≈ V
CC
+ 9.1V when TGATE is high. Do not force an external
voltage on BOOST pin.
TGATE (Pin 2): This pin provides gate drive to the topside
power FET. When TGATE is driven on, the gate voltage will
be approximately equal to V
SW
+ 6.6V. A series resistor of
5Ω to 10Ω should be used from this pin to the gate of the
topside FET.
PIN FUNCTIONS
UUU
SW (Pin 3): This pin is the reference point for the floating
topside gate drive circuitry. It is the common connection
for the top and bottom side switches and the output
inductor. This pin switches between ground and V
CC
with
very high dv/dt rates. Care needs to be taken in the PC
layout to keep this node from coupling to other sensitive
nodes. A 1A Schottky clamping diode should be placed
very close to the chip from the ground pin to this pin to
prevent the chip substrate diode from turning on. See
Applications Information for more details.
SYNC (Pin 4): External Clock Synchronization Input. Pulse
width range: 10% to 90%.
SDB (Shutdown Bar) (Pin 5): Active Low Digital Input. The
charger is disabled when asserted. This pin is connected
to the CHGEN pin to enable charger control through the
SMBus interface.
CHGEN (Pin 12): Digital Output to Enable Charger Func-
tion. Connect CHGEN to SDB.
I
SET
(Pin 17): Open-Drain CMOS Switch to DGND. An
external resistor, R
SET
, is connected from I
SET
to the
current programming input, the PROG pin of the battery
charger section, which sets the range of the charging
current.
I
LIMIT
(Pin 24): An external resistor is connected between
this pin and DGND. The value of the external resistor
programs the range and resolution of the programmed
charger current. See Electrical Characteristics table for
more information.
V
LIMIT
(Pin 25): An external resistor is connected between
this pin and DGND. The value of the external resistor
programs the range and resolution of the V
SET
divider. See
Electrical Characteristics table for more information.
V
SET
(Pin 26): This is the tap point of the programmable
resistor divider, which provides battery voltage feedback
to the charger.
8
LTC1759
V
C
(Pin 27): This is the control signal of the inner loop of
the current mode PWM. Switching starts at 0.9V. Higher
V
C
corresponds to higher charging current in normal
operation. A capacitor of at least 0.33µF to AGND filters out
noise and controls the rate of soft start.
PROG (Pin 28): This pin is for programming the charging
current and for system loop compensation. During normal
operation, the pin voltage is approximately 2.465V.
SENSE (Pin 29): Current Amplifier CA1 Input. Sensing
must be at the positive terminal of the battery.
SPIN (Pin 30): This pin is for the internal amplifier
CA1 bias. It must be connected to R
SENSE
as shown in
Figure 1.
BAT1 (Pin 31): Current Amplifier CA1 Input.
BOOSTC (Pin 33): This pin is used to bootstrap and supply
the current sense amplifier CA1 for very low dropout
conditions. V
CC
can be as low as only 0.4V above the
battery voltage. A diode and a capacitor are needed to get
the voltage from V
BOOST
. If low dropout is not needed and
V
CC
is always 3V or greater than V
BAT
, this pin can be left
floating or tied to V
CC
. Do not force this pin to a voltage
lower than V
CC
.
BGATE (Pin 35): Drives the gate of the bottom external
N-channel FET of the charger buck converter.
Monitor/Fault Diagnostic Pins
DCDIV (Pin 21): Supply Divider Input. This is a high
impedance comparator input with a 1V threshold (rising
edge) and hysteresis.
DCIN (Pin 22): Input connected to the DC input source to
monitor the DC input for power-fail condition.
BAT2 (Pin 23): Sensing Point for Voltage Control Loop.
Connect this to the positive terminal of the battery.
Internal Power Supply Pins
AGND (Pin 6): DC Accurate Ground for Analog Circuitry.
V
DD
(Pin 16): Low Voltage Power Supply Input. Bypass
this pin with 0.1µF.
DGND (Pin 18): Ground for Digital Circuitry and DACs.
Should be connected to AGND at the negative terminal
of the charger output filter capacitor.
V
CC
(Pin 32): Power Input for Battery Charger Section.
Bypass this pin with 0.47µF.
GBIAS (Pin 34): 8.6V Regulator Output for Bootstrapping
V
BOOST
and V
BOOSTC
. A bypass capacitor of at least 2µF is
needed. Switching will stop if V
BOOST
drops below 7.1V.
PGND (Pin 36): High Current Ground Return for Charger
Gate Drivers.
SBS Interface Pins
INTB (Interrupt Bar) (Pin 13): Active Low Interrupt Output
to Host. Signals host that there has been a change of status
in the charger registers and that the host should read the
LTC1759 status registers to determine if any action on its
part is required. This signal can be connected to the
optional SMBALERT# line of the SMBus. Open drain with
weak current source pull-up to V
DD
(with Schottky to allow
it to be pulled to 5V externally, see Figure 2).
SDA (Pin 14): SMBus Data Signal from Main (Host-
controlled) SMBus.
SCL (Pin 15): SMBus Clock Signal from Main (Host-
Controlled) SMBus. External pull-up resistor is required.
THERM (Pin 19): Thermistor Force/Sense Pin to Smart
Battery. See Electrical Characteristics table for more
detail. Maximum allowed combined capacitance on THERM
and RNR is 75pF.
RNR (Pin 20): Thermistor Force/Sense Pin to Smart
Battery. See Electrical Characteristics table for more
detail. Maximum allowed combined capacitance on THERM
and RNR is 75pF.
PIN FUNCTIONS
UUU
9
LTC1759
BLOCK DIAGRA
W
Figure 2
+
+
–
+
+
7
UV
4
SYNC
6
AGND
27
V
C
V
DD
10µA
9
CLP
10
CLN
11
COMP1
12
CHGEN
19
THERM
20
RNR
15
SCL
14
SDA
18
DGND
13
13
INTB
V
REF
1k
V
REF
20k
290k
812.5k
8INFET
7.8V
34 GBIAS
35 BGATE
36
33
PGND
BOOSTC
30 SPIN
29 SENSE
28 PROG
75k
21 DCDIV
22 DCIN
23 BAT2
V
SET
BAT1
BAT1
1.3V
92mV
V
CC
V
CC
32
31
SDB
+
6.7V 6.7V
1V
8.9V
65k 612k
72k
ONE
SHOT 200kHz
OSC
PWM
LOGIC
SLOPE COMP
C1
+
CL1
+
AC_PRESENT
PWR_FAIL
+
B1
+
CA2
+
VA
S
RQ
1BOOST
2TGATE
3SW
+
CA1
+
0.2V
+
26
I
LIMIT
24
V
LIMIT
25
I
SET
17
V
DD
1759 F02
16
10-BIT
VOLTAGE
DAC
LIMIT
DECODER
CHARGER
CONTROLLER
THERMISTOR
DECODER
SMBus
CONTROLLER 10-BIT
CURRENT
DAC
5
–
–
–
–
–
–
–
SHDN
–
–
––
10
LTC1759
TEST CIRCUITS
–
+
V
REF
≈ 0.65V
V
BAT
V
C
CA2
–
+
–
+
CA1
+
300Ω
20k
1k
1k
R
SENSE
10Ω
BAT1
SENSE
SPIN
1759 TC01
PROG
R
SET
0.047µF
LTC1759
1µF
75k
LT1006
+
R
S2
200Ω
R
S3
200Ω
V
REF
2.465V
–
+
–
+
VA
+
2k 2nF
V
SET
1759 TC02
I
PROG
R
SET
LTC1759
PROG
LT1013
0.47µF
Test Circuit 1
Test Circuit 2
11
LTC1759
Overview (Refer to Block Diagram and Figure 10)
The LTC1759 is composed of a battery charger section, a
charger controller, two 10-bit DACs to control charger
parameters, a thermistor decoder, limit decoder and an
SMBus controller block. If no battery is present, the
thermistor decoder indicates a THERM_OR condition and
charging is disabled by the charger controller (CHGEN =
Low). Charging will also be disabled if AC_PRESENT is
low, or the battery thermistor is decoded as THERM_HOT.
If a battery is inserted or AC power is connected, the
battery will be charged with an 80mA “wake-up” current.
The wake-up current is discontinued after three minutes
if the thermistor is decoded as THERM_UR or
THERM_COLD, and the battery or host doesn’t transmit
charging commands.
The SMBus controller block receives ChargingCurrent()
and ChargingVoltage() commands via the SMBus. If
ChargingCurrent() and ChargingVoltage() command pairs
are received within a three-minute interval, the values are
stored in the current and voltage DACs and the charger
controller asserts the CHGEN line if the decoded ther-
mistor value will allow charging to commence.
ChargingCurrent () and ChargingVoltage() values are com-
pared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The charger controller will assert INTB whenever a status
change is detected. The host may query the charger, via
the SMBus, to obtain ChargerStatus() information. INTB
will be deasserted upon a successful read of
ChargerStatus() or a successful Alert Response Address
(ARA) request.
Battery Charger Section
The LTC1759 is synchronous current mode PWM step-
down (Buck) switcher. The battery DC charging current is
programmed with a current DAC via the SMBus interface.
Amplifier CA1 converts the charging current through
R
SENSE
to a much lower current I
PROG
(I
PROG
= I
BAT
•
R
SENSE
/R
S2
) fed into the PROG pin. Amplifier CA2 com-
pares the output of CA1 with the programmed current and
drives the PWM loop to force them to be equal. High DC
OPERATIO
U
accuracy is achieved with averaging capacitor C
PROG
.
Note that I
PROG
has both AC and DC components. I
PROG
generates a ramp signal that is fed to the PWM control
comparator C1 through buffer B1 and level shift resistors
forming the current mode inner loop. The BOOST pin
supplies the top power switch gate drive. The LTC1759
generates a 8.9V V
GBIAS
for bootstrapping V
BOOST
and
V
BOOSTC
as well as to drive the bottom power FET. The
BOOSTC pin supplies the current amplifier CA1 with a
voltage higher than V
CC
for low dropout applications.
Amplifier VA reduces the charging current when the bat-
tery voltage reaches the set voltage programmed by the
VDAC and the 2.465V reference voltage.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (92mV/
R
CL
). At input current limit, CL1 will supply the program-
ming current I
PROG
and thus reduce battery charging
current.
The INFET pin drives an external input P-channel FET for
low dropout applications.
SMBus Interface
All communications over the SMBus are interpreted by the
SMBus controller block. The SMBus controller is an
SMBus slave device. All internal LTC1759 registers may
be updated and accessed through the SMBus controller,
and charger controller as required. The SMBus protocol is
a derivative of the I
2
C
TM
bus (Reference
“I
2
C-Bus and How
to Use It, V1.0”
by Philips and
“System Management Bus
Specification”
by the Smart Battery System Organiza-
tion*, for a complete description of the bus protocol
requirements.)
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condition,
or power-on reset via the V
DD
undervoltage lockout, will
reset the controller to an initial state at any time.
The LTC1759 command set is interpreted by the SMBus
controller and passed onto the charger controller block as
control signals or updates to internal registers.
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
12
LTC1759
OPERATIO
U
Table 1: Supported Charger Functions
SMBus ADDRESS COMMAND CODE
FUNCTION (7-BIT) (8-BIT hex) ACCESS DATA TYPE
ChargerSpecInfo() b0001_001 h11 r Register
ChargerMode() b0001_001 h12 w Register
ChargerStatus() b0001_001 h13 r Register
ChargingCurrent() b0001_001 h14 w Register
ChargingVoltage() b0001_001 h15 w Register
AlarmWarning() b0001_001 h16 w Control
LTCVersionFunction() b0001_001 h3c r Register
OptionalMfgFunction3() b0001_001 h3d – Not Supported
OptionalMfgFunction2() b0001_001 h3e – Not Supported
OptionalMfgFunction1() b0001_001 h3f – Not Supported
Alert Response Address
1
b0001_100 N/A Read Byte Interrupt Address
1
Read-byte format. 89h is returned as the interrupt address of the LTC1759. Rev 1.0 SMBus Compliant.
Table 2: SMBus Word Bit Definitions for All Allowed LTC1759 Functions
POWER-ON
WORD BIT RESET VALUE
FUNCTION FIELD MAPPING (BINARY) ALLOWED VALUES
ChargerSpecInfo CHARGER_SPEC 3:0 0001 • The CHARGER_SPEC Reports the Version of the Smart Battery
Charger Specification the Charger Supports
• 0001 – Version 1.0
• All Other Codes Reserved
• Always Returns 0001
• Read Only. Write Will NACK
SELECTOR_SUPPORT 4 0 • 0 – Charger Does Not Support the Optional Smart Battery Selector
Commands
• 1 – Charger Supports the Optional Smart Battery Selector
Commands
• Always Returns 0
• Read Only. Write Will NACK
Reserved 15:5 0 • These Bits Are Reserved and Must Return Zero
• Read Only. Write Will NACK
ChargerMode() INHIBIT_CHARGE 0 0 • 0 – Enable Charging (Power-On Default)
• 1 – Inhibit Charging
• Write Only. Read Will NACK
• Cleared to Power-On Reset Value When:
1) POR_RESET = 1
2) AC_PRESENT = 0
3) BATTERY_PRESENT = 0
ENABLE_POLLING 1 0 • 0 – Disable Polling (Power-On Default for Smart Battery Controlled
Chargers)
• 1 – Enable Polling (Power-On Default for Host Controlled Chargers).
• Ignored by LTC1759
• Write Only. Read Will NACK
POR_RESET 2 0 • 0 – Mode Unchanged (Default)
• 1 – Set Charger to Power-On Defaults
• This Reset Only Affects the Charger_Controller Block
• Write Only. Read Will NACK
13
LTC1759
OPERATIO
U
POWER-ON
WORD BIT RESET VALUE
FUNCTION FIELD MAPPING (BINARY) ALLOWED VALUES
RESET_TO_ZERO 3 0 • 0 – Charging Value Unchanged
• 1 – Set Charging Values to Zero
NOTE:
This function is implemented by forcing the charger to
CHARGING_NONE_STATE and not allowing charge to resume until a
valid ChargingCurrent() and ChargingVoltage() Pair Is received.
• Write Only. Read Will NACK
Reserved 15:4 0 • Not Implemented. Writes to These Bits Are Ignored.
• Write Only. Read Will NACK
ChargerStatus() CHARGE_INHIBITED 0 0 This Is the ChargerMode() INHIBIT_CHARGE Bit
• 0 – Charger Is Enabled
• 1 – Charger Is Inhibited
• Read Only. Write Will NACK
MASTER_MODE 1 0 • 0 – Charger Is in Slave Mode (Polling Disabled)
• 1 – Charger Is in Master Mode (Polling Enabled)
• Always Returns 0
• Read Only. Write Will NACK
VOLTAGE_NOTREG 2 0 • 0 – Charger’s Output Voltage Is in Regulation
• 1 – Requested ChargingCurrent() Is Not Being Met
• Not Supported; Always Returns 0
• Read Only. Write Will NACK
CURRENT_NOTREG 3 0 • 0 – Charger’s Output Current Is in Regulation
• 1 – Requested ChargingCurrent() Is Not Being Met
• Not Supported; Always Returns 0
• Read Only. Write Will NACK
LEVEL_3:LEVEL_2 5:4 01 • 00 – Reserved
• 01 – Charger Is a Smart Battery Controlled
• 10 – Reserved
• 11 – Charger Is a Host Controlled
• Always Returns 01
• Read Only. Write Will NACK
CURRENT_OR 6 0 • 0 – ChargingCurrent() Value Is Valid
• 1 – ChargingCurrent() Value Is Invalid
• This Value Is Valid Only When Charging with
CHARGE_INHIBITED = 0 or 1
• Read Only. Write Will NACK
VOLTAGE_OR 7 0 • 0 – ChargingVoltage() Value Is Valid
• 1 – ChargingVoltage() Value Is Invalid
• This Value Is Valid Only When Charging with
CHARGE_INHIBITED = 0 or 1
• Read Only. Write Will NACK
THERM_OR 8 Value • 0 – Thermistor Indicates Not Overrange
• 1 – Thermistor Indicates Overrange
• Read Only. Write Will NACK
THERM_COLD 9 Value • 0 – Thermistor Indicates Not Cold
• 1 – Thermistor Indicates Cold
• Read Only. Write Will NACK
THERM_HOT 10 Value • 0 – Thermistor Indicates Not Hot
• 1 – Thermistor Indicates Hot
• Read Only. Write Will NACK
14
LTC1759
POWER-ON
WORD BIT RESET VALUE ALLOWED VALUES
FUNCTION FIELD MAPPING (BINARY)
THERM_UR 11 Value • 0 – Thermistor Indicates Not Underrange
• 1 – Thermistor Indicates Underrange
• Read Only. Write Will NACK
ALARM_INHIBITED 12 0 • 0 – Charger Not Alarm Inhibited
• 1 – Charger Alarm Inhibited. This Bit Is Set but Never Cleared by
AlarmWarning()
• Read Only. Write Will NACK
• Cleared to Power-On Reset Value When:
1) POR_RESET = 1
2) BATTERY_PRESENT = 0
3) AC_PRESENT = 0
4) A Valid ChargingVoltage(), ChargingCurrent() Pair Is Received
POWER_FAIL 13 Value • 0 – V
BAT
/V
DCIN
< 0.9
• 1 – V
BAT
/V
DCIN
> 0.9
• Read Only. Write Will NACK
BATTERY_PRESENT 14 Value • 0 – Battery Is Not Present
• 1 – Battery Is Present
• Read Only. Write Will NACK
AC_PRESENT 15 Value • 0 – Charge Power Is Not Available
• 1 – Charge Power Is Available
• Read Only. Write Will NACK
ChargingCurrent() CHARGING_CURRENT 15:0 0 • Unsigned Integer Representing Charger Current in mA
[15:0] • Three Possible Responses
– Supply the Current Requested
– Supply Its Programmatic Maximum Current If the Request Is
Greater Than Its Programmatic Value and Less Than hffff
– Supply Its Maximum Safe Current If the Request Is hffff [Supply
Current Required to Meet ChargingVoltage()].
• Write Only. Read Will NACK
ChargingVoltage() CHARGING_VOLTAGE 15:0 0 • Unsigned Integer Representing Charger Voltage in mV
[15:0] • Three Possible Responses
– Supply the Voltage Requested
– Supply Its Programmatic Maximum Voltage If the Request Is
Greater Than Its Programmatic Value and Less Than hffff
– Supply Its Maximum Voltage If the Request Is hffff [Supply
Voltage Required to Meet ChargingCurrent()].
• Write Only. Read Will NACK
AlarmWarning() OVER_CHARGED_ 15 0 • 1 – Terminate Charging Immediately
ALARM • Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored
TERMINATE_CHARGE_ 14 0 • 1 – Terminate Charging Immediately
ALARM • Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
RESERVED_ALARM1 13 0 • 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
OVER_TEMP_ALARM 12 0 • 1 – Terminate Charging Immediately
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored.
OPERATIO
U
15
LTC1759
POWER-ON
WORD BIT RESET VALUE ALLOWED VALUES
FUNCTION FIELD MAPPING (BINARY)
TERMINATE_ 11 0 • This Bit May Be Used to Signal That the Charger May Be Restarted
DISCHARGE_ALARM After a Battery Conditioning Cycle Has Been Completed
• Write Only. Read Will NACK
• Writing a 0 to This Bit Will Be Ignored
• Not Supported by LTC1759
Reserved 10 – • Not Supported by LTC1759
• Write Only. Read Will NACK
REMAINING_ 9 – • Intended for Host
CAPACITY_ALARM • Not Supported by LTC1759
• Write Only. Read Will NACK
REMAINING_TIME_ 8 – • Intended for Host
ALARM • Not Supported by LTC1759
• Write Only. Read Will NACK
INITIALIZED 7 – • Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
DISCHARGING 6 – • Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
FULLY_CHARGED 5 – • Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
FULLY_DISHARGED 4 – • Intended for Host
• Not Supported by LTC1759
• Write Only. Read Will NACK
ERROR 3:0 – • Intended for Host
• All Bits Set High Prior to AlarmWarning() Transmission
• Not Supported by LTC1759
• Write Only. Read Will NACK
LTCVersionFunction LTC_VERSION 15:0 0101hex • Returns LTC Version Number
() • Read Only
• Always Returns 0101hex
OPERATIO
U
SMBus Accelerator Pull-Ups
Both SCL and SDA have SMBus accelerator circuits which
reduce the rise time on systems with significant capaci-
tance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
2mA to 5mA pull-up to V
DD
for approximately 1µs (exter-
nal pull-up resistors are still required to supply DC cur-
rent). This action allows the bus to meet SMBus rise time
requirements with as much as 150pF on each SMBus
signal. The improved rise time will benefit all of the devices
which use the SMBus, especially those devices that use
the I
2
C logic levels. Note that the dynamic pull-up circuits
only pull to V
DD
, so some SMBus devices that are not
compliant to the SMBus specifications may still have rise
time compliance problems if the SMBus pull-up resistors
are terminated with voltages higher than V
DD
.
16
LTC1759
The Charger Controller Block
The LTC1759 charger operations are handled by the
charger controller block. This block is capable of charging
the selected battery autonomously or under host control.
The charger controller can request communications with
the system management host (SMHost) by asserting
INTB = 0; this will cause the SMHost, if present, to poll the
LTC1759.
The charger controller receives SMBus slave commands
from the SMBus controller block.
The charge controller allows the LTC1759 to meet the
following Smart Battery-controlled (Level 2) charger
requirements:
1. Implements the Smart Battery’s critical warning mes-
sages over the SMBus.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output characteristics
accordingly.
OPERATIO
U
The charger controller allows the LTC1759 to meet the
following host-controlled (Level 3) Smart Battery charger
requirements.
1. In a host-controlled system the host is able to operate
as an SMBus master device.
2. The host may determine the appropriate charging algo-
rithm by querying the battery or providing an alternative
special charging algorithm.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcasting
the charging commands to the LTC1759 over the SMBus.
4. The LTC1759 will still respond to Smart Battery critical
warning messages without host intervention.
The charger controller block uses the state machine of
Figure 3. The functional features for state transitions and
general control are detailed in Table 3.
0
8 OR 9
8 OR 9
NOTE: NUMBERS REFER TO CONDITIONS AND STATE DESCRIPTION IN TABLE 3
3 OR 4 OR 5
OR 6 OR 16
15
7
15
1 OR 2
15
1759 F03
14
10 OR 11 OR 12
OR 13 OR 16
15
CHARGING_CONTROLLED_STATE
21
CHARGING_RESET_STATE
19
CHARGING_NONE_STATE
22
CHARGING_WAKE-UP_STATE
20
Figure 3. Charger Controller State Machine
17
LTC1759
OPERATIO
U
Table 3. Charger_Controller Functional Features
# CONDITION ACTION
0 POWER_ON_RESET = 1 CHARGING_RESET_STATE =1
(Asynchronously Reset the Charger_Controller State Machine During
Power-On Reset)
1 CHARGING_RESET_STATE = 1 AND the Battery Is Present CHARGING _WAKE-UP_STATE = 1
AND AC_PRESENT = 1 AND INHIBIT_CHARGE = 0 AND Thermistor Is The Charger_Controller Will “Wake Up” Charge the Battery
Ideal at I
WAKE-UP
Indefinitely
2 CHARGING_RESET_STATE = 1 AND the Battery Is Present CHARGING_WAKE-UP_STATE = 1
AND AC_PRESENT =1 AND INHIBIT_CHARGE = 0 AND THERM_ The Charger_Controller Will “Wake Up” Charge the Battery
UR = 1 OR THERM_COLD = 1 at I
WAKE-UP
Until Condition 3 Is Met
3 CHARGING_WAKE-UP_STATE = 1 AND the Time-Out Period CHARGING_NONE_STATE = 1
Exceeds t
TIMEOUT
AND THERM_UR = 1 OR THERM_COLD = 1 The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
4 CHARGING_WAKE-UP_STATE = 1 AND an AlarmWarning() Message CHARGING_NONE_STATE =1
Is Received with Any Bit in the Upper Nibble Set The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
5 CHARGING_WAKE-UP_STATE = 1 (from Condition 1 above) AND CHARGING_NONE_STATE = 1
THERM_HOT Changes from 0 to 1 AND THERM_UR = 0 The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
6 CHARGING_WAKE-UP_STATE = 1 (from Condition 2 above) AND CHARGING_NONE_STATE = 1
THERM_UR Changes from 1 to 0 AND THERM_HOT = 1 The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
7 CHARGING_WAKE-UP-STATE = 1 AND INHIBIT_CHARGE Is CHARGING_WAKE-UP_STATE =1
Set to 1 The Charger_Controller Stops Charging the Selected Battery. The Timer
Continues to Run. The Charger Can Resume “Wake-Up” Charging If
INHIBIT_CHARGE = 0
8 (CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1) CHARGING_CONTROLLED_STATE = 1
AND (Both ChargingCurrent() AND ChargingVoltage() Commands The Charger_Controller Will Supply “Controlled Charge” to the
Are Received within t
TIMEOUT
) AND INHIBIT_CHARGE = 0 Battery as Specified in the Current and Voltage Commands
AND THERM_HOT = 0
9 (CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1) CHARGING_CONTROLLED_STATE = 1
AND (Both ChargingCurrent() AND ChargingVoltage() Commands The Charger_Controller Will Supply “Controlled Charge” to the
Are Received within t
TIMEOUT
) AND INHIBIT_CHARGE = 0 Battery as Specified in the Current and Voltage Commands
AND THERM_UR = 1
10 CHARGING_CONTROLLED_STATE = 1 CHARGING_NONE_STATE = 1
AND No New ChargingCurrent() and ChargingVoltage() Commands Are The Charger_Controller Stops Charging the Battery. It Cannot
Received for a Time-Out Period of t
TIMEOUT
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
11 CHARGING_CONTROLLED_STATE = 1 CHARGING_NONE_STATE = 1
The Charger_Controller Is Supplying “Controlled Charge” to the The Charger_Controller Stops Charging the Battery. It Cannot
Battery AND (an AlarmWarning() Message Is Received “Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
with Any Bit in the Upper Nibble Set) “Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
18
LTC1759
# CONDITION ACTION
12 CHARGING_CONTROLLED_STATE = 1 AND THERM_HOT CHARGING_NONE_STATE = 1
Changes from 0 to 1 AND THERM_UR = 0 The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
13 CHARGING_CONTROLLED_STATE = 1 AND THERM_UR CHARGING_NONE_STATE = 1
Changes from 1 to 0 AND THERM_HOT = 1 The Charger_Controller Stops Charging the Battery. It Cannot
“Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met
14 CHARGING_CONTROLLED_STATE = 1 CHARGING_CONTROLLED_STATE = 1
AND INHIBIT_CHARGE Is Set to 1 INHIBIT_CHARGE Asynchronously Inhibits Charging Without
Affecting the Charger_Controller State Machine. This Means the Charger
Stops Charging the Battery but Continues to Accept New
ChargingCurrent() and ChargingVoltage() Commands, Continues to
Monitor the Battery Thermistor Input and Continues to Track the
Communication Time-Out. It Will Resume Charging the Battery If
INHIBIT_CHARGE Is Cleared to 0, Possibly at Different Current and
Voltage If New Commands Have Been Sent in the Interim
15 ANY STATE CHARGING_RESET_STATE= 1
The Charger_Controller Is in Any State AND (the Battery Is Removed The Charger_Controller Is Set to Its Power-On Default State
OR AC_PRESENT = 0 OR a 1 Is Written to POR_RESET)
NOTE:
Condition 15 Takes Precedence Over Any Other Condition.
16 (CHARGING_CONTROLLED_STATE = 1) OR CHARGING_NONE_STATE = 1
CHARGING_WAKE-UP_STATE = 1) AND The Charger_Controller Stops Charging the Battery. It Cannot
A 1 Is Written to RESET_TO_ZERO “Wake Up” Charge Again Until Condition 15 Is Met. It Can Supply
“Controlled Charge” to the Battery If Conditions 8 or 9 Are Met.
The Valid Charge Command Timer Is Cleared When RESET_TO_ZERO =
1. This Prevents Charging from Continuing Until After a Valid
ChargeCurrent() and ChargeVoltage() Pair Is Received
18 ANY STATE AND Alert SMHost of Change by Setting INTB = 0
AC_PRESENT Transitions 0 to 1 or 1 to 0 OR
BATTERY_PRESENT Transitions 0 to 1 or 1 to 0
19 CHARGING_RESET_STATE = 1 CHGEN = 0
The Charger Is Not Charging
20 CHARGING _WAKE-UP_STATE = 1 CHGEN = ~INHIBIT_CHARGE
The Charger Will Provide a Wake-Up Current When CHGEN = 1
21 CHARGING_CONTROLLED_STATE = 1 CHGEN = ~INHIBIT_CHARGE
The Charger Will Provide Specified Charging Voltage and Current
When CHGEN = 1
A Zero Value for ChargingVoltage() Is Handled by Forcing CHGEN = 0
22 CHARGING_NONE_STATE = 1 CHGEN = 0
The Charger Is Not Charging
OPERATIO
U
19
LTC1759
OPERATIO
U
The Thermistor Decoder Block
This block measures the resistance of the battery’s ther-
mistor and features high noise immunity at critical trip
points. The low power standby mode supports all SMB
charger reporting requirements when AC is not present.
The thermistor decoder is shown in Figure 4.
Thermistor sensing is accomplished by a state machine
that reconfigures the switches of Figure 4 using RNR_SELB
and RUR_SELB. The three allowable modes are as follows:
1. Overrange Detection. The RUR_SELB and RNR_SELB
switches are off and the external R
WEAK
resistor forms
a voltage divider with R
THERM
. The resulting voltage is
monitored at THERM, compared to an internal refer-
ence and sampled at the output of the OR comparator.
This detection mode is always active allowing low
power operation when AC power is not available.
2. Cold/Ideal/Hot Range Detection. The RNR_SELB
switch is on and the RUR_SELB switch is off. The
external R
NR
and R
WEAK
resistors form a voltage divider
with R
THERM
. The resulting voltage is monitored at
THERM, compared to an internal reference and sampled
at the output of the cold and hot comparators. This
detection mode is only activated if OR tested low.
3. Underrange Detection. The RNR_SELB switch is off
and the RUR_SELB switch is on. The external R
UR
and
R
WEAK
resistors form a voltage divider with R
THERM
.
The resulting voltage is monitored at RNR, compared to
an internal reference and sampled at the output of the
UR comparators. This detection mode is only activated
if HOT tested high.
NOTE: The underrange detection scheme is a very impor-
tant feature of the LTC1759. The R
UR
/R
THERM
divider trip
point of 0.333 • V
DD
(1V) is well above the 0.047 • V
DD
(140mV) threshold of a system using a 10k pull-up. A
system using a 10k pull-up would not be able to resolve the
important underrange to hot transition point with a mod-
est 100mV of ground offset between battery and ther-
mistor detection circuitry. Such offsets are anticipated
when charging at normal current levels.
Figure 4. Thermistor Decoder Block
V
DD
V
DD
R
NR
THERM
HYSTERESIS
R
WEAK
475k
1%
R
THERM
TOTAL
PARASITIC
CAPACITANCE
MUST BE LESS
THAN 75pF
R
NR
10k
1%
RNR_SELB
R
UR
1k
1%
V
DD
V
DD
THERM_COLD
THERM_UR
THERM_HOT
THERM_OR
1759 F04
RUR_SELB
+
–
+
–
+
–
+
–
THERM
LATCH
COLD
HOT
OR
UR
20
LTC1759
OPERATIO
U
When AC power is not available the thermistor block
supports the following low power operating features:
1. Only the low power THERM_OR detection circuitry is
kept alive to support battery present interrupts.
2. The ChargeStatus() read function forces the thermistor
block to update thermistor status at the beginning of the
read. The low power mode is immediately reentered
upon completion of the read.
The thermistor impedance is interpreted according to
Table 4.
Table 4. Thermistor State Ranges
THERMISTOR CHARGE
RESISTANCE STATUS BITS DESCRIPTION
0Ω to 500ΩTHERM_UR, Underrange
THERM_HOT
BATTERY_PRESENT
500Ω to 3kΩTHERM_HOT Hot
BATTERY_PRESENT
3kΩ to 30kΩ(NONE) Ideal
BATTERY_PRESENT
30kΩ to 100kΩTHERM_COLD Cold
BATTERY_PRESENT
Above 100kΩTHERM_OR Overrange
THERM_COLD
The required values for R
WEAK
, R
UR
and R
NR
are shown in
Table 5.
Table 5. Thermistor External Resistor Values
EXTERNAL RESISTOR VALUE (
Ω
)
R
WEAK
475k ±1%
R
UR
1k ±1%
R
NR
10k ±1%
Note: The maximum allowed total external capacitance on THERM and
RNR is 75pF, due to settling time requirements.
Figure 5. Simplified VLIMIT Circuit Concept (ILIMIT Is Similar)
provide a measure of safety with a hardware restriction on
charging current which cannot be overridden by software.
VLIMIT
12.5k
25k
33k
25k
25k
12.5k
RLIMIT
VDD
VLIM [3:0]
1759 F05
AC_PRESENT
4
+
–
+
–
+
–
+
–
ENCODER
The V
LIMIT
Decoder Block
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are
applied to the charger output value. These limits provide
a measure of safety with a hardware restriction on charg-
ing voltage which cannot be overridden by software.
Table 6. ILIMIT Trip Points and Ranges
EXTERNAL NOMINAL
RESISTOR CHARGING
(R
ILIMIT
)I
LIMIT
VOLTAGE CURRENT RANGE GRANULARITY
0V
ILIMIT
< 0.09V
DD
0 < I < 1023mA 1mA
10k ±1% 0.17V
VDD
< V
ILIMIT
0 < I < 2046mA 2mA
< 0.34V
VDD
33k ±1% 0.42V
VDD
< V
ILIMIT
0 < I < 4092mA 4mA
< 0.59V
Open (>250k, 0.66V
VDD
< V
ILIMIT
0 < I < 8184mA 8mA
or Short to
V
DD
)
The I
LIMIT
Decoder Block
The value of an external resistor connected from this pin
to GND determines one of four current limits that are used
to limit the maximum charging current value. These limits
21
LTC1759
Table 7. VLIMIT Trip Points and Ranges
NOMINAL
EXTERNAL CHARGING
RESISTOR VOLTAGE (V
OUT
)
(R
VLIMIT
)V
LIMIT
VOLTAGE RANGE GRANULARITY
0V
VLIMIT
< 0.09V
VCCP
2465mV < V
OUT
16mV
< 8432mV
10k ±1% 0.17V
VDD
< V
VLIMIT
2465mV < V
OUT
16mV
< 0.34V
VDD
< 12640mV
33k ±1% 0.42V
VCCP
< V
VLIMIT
2465mV < V
OUT
32mV
< 0.59V
VDD
< 16864mV
100k ±1% 0.66V
VDD
< V
VLIMIT
2465mV < V
OUT
32mV
< 0.84V
VDD
< 21056mV
Open or 0.91V
VDD
< V
VLIMIT
2465mV < V
OUT
32mV
Tied to V
DD
< 32768mV
PROGRAMMED VALUE (V)
NOTE: THE USER MUST ADJUST THE VALUE OF
THE EXTERNAL CURRENT SENSING COMPONENTS
(R
S1
, R
S2
, R
SENSE
, R
SET
) TO MAINTAIN CONSISTENCY
WITH I
LIMIT
RANGES. SEE APPLICATIONS INFORMATION
0
CHARGER V
OUT
(V)
25
20
15
10
5
010 20 25
1759 F06
515 30 35
Figure 6. Transfer Function of Charger
I
PROG
(FROM CA1 AMP)
1759 F07
+
–
R
SET
V
REF
I
SET
PROG TO
ERROR
AMP
CHARGINGCURRENT()
VALUE
∆-∑
MODULATOR
Figure 7. Current DAC Operation
The Voltage DAC Block
Note that the charge output voltage is offset by V
REF
.
Therefore, the value of V
REF
is subtracted from the SMBus
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 2.465V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage() value is above the limit set by the V
LIMIT
pin, then the charger output voltage is set to the value
determined by the V
LIMIT
resistor and the VOLTAGE_OR
bit is set. These limits are demonstrated in Figure 6.
The Current DAC Block
The current DAC is a delta-sigma modulator which con-
trols the effective value of an external resistor, R
SET
, used
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the ChargingCurrent() value,
received via the SMBus, to a variable resistance equal to:
1.25R
SET
/ChargingCurrent()/I
LIMIT[x]
)
Therefore, programmed current is equal to:
0.8V
REF
/R
SET
(ChargingCurrent()/I
LIMIT
[x]),
for ChargingCurrent() < I
LIMIT[x]
.
When a value less than 1/16th of the maximum current
allowed by I
LIMIT
is applied to the current DAC input, the
current DAC enters a different mode of operation. The
current DAC output is pulse width modulated with a high
I
LIMIT
/8
AVERAGE CHARGER CURRENT
1750 F08
~40ms
0
Figure 8. Charging Current Waveform in Low Current Mode
OPERATIO
U
frequency clock having a duty cycle value of 1/8. There-
fore, the maximum output current provided by the charger
is I
MAX
/8. The delta-sigma output gates this low duty cycle
signal on and off. The delta-sigma shift registers are then
clocked at a slower rate, about 45ms/bit, so that the
charger has time to settle to the I
MAX
/8 value. The resulting
average charging current is equal to that requested by the
ChargingCurrent() value.
22
LTC1759
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, inde-
pendent of the I
LIMIT
setting.
Note:
The external resistor connected to the I
SET
pin must be
multiplied by 0.8 to compensate for the 80% maximum
duty cycle of the sigma-delta modulator. Note also that the
80% duty cycle converts the rise/fall time mismatches to
a small gain error, rather than a nonlinearity. The parasitic
OPERATIO
U
capacitance at the I
SET
pin should be minimized to keep
these errors small.
The Battery Monitor Block (PWR_FAIL)
Two internal resistor dividers compare the BAT2 terminal
to the DCIN terminal. When BAT2 is above 89% of the
voltage at DCIN the PWR_FAIL bit is set to 1. A small
amount of proportional hysteresis, ~2%, is used for noise
immunity. The PWR_FAIL bit is set low if AC_PRESENT
is low.
APPLICATIONS INFORMATION
WUUU
Adapter Limiting
An important feature of the LTC1759 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across R
S4
, connected
between the CLP and CLN pins. When this voltage exceeds
92mV, the amplifier will override programmed charging
current to limit adapter current to 92mV/R
S4
. A lowpass
filter formed by 500Ω and 1µF is required to eliminate
switching noise. If the current limit is not used, both CLP
and CLN pins should be connected to V
CC
.
Setting Input Current Limit
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 5% for the
input current limit tolerance and use that current to deter-
mine the resistor value.
R
S4
= 92mV/I
LIMIT
I
LIMIT
=
Adapter Min Current – (Adapter Min Current • 5%)
Table 7. Common RS4 Resistor Values
ADAPTER R
S4
VALUE* R
S4
POWER R
S4
POWER
RATING (A) (Ω) 1% DISSIPATION (W) RATING (W)
1.5 0.06 0.135 0.25
1.8 0.05 0.162 0.25
2 0.045 0.18 0.25
2.3 0.039 0.206 0.25
2.5 0.036 0.225 0.5
2.7 0.033 0.241 0.5
3 0.03 0.27 0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 7).
Figure 9. Adapter Current Limiting
92mV
–
+
500Ω
CLP
CLN
V
CC
1759 F09
LTC1759
1µF
+
R
S4
*
C
IN
V
IN
CL1
AC ADAPTER
INPUT
*R
S4
= 92mV
ADAPTER CURRENT LIMIT
+
23
LTC1759
APPLICATIONS INFORMATION
WUUU
Charge Termination Issues
Batteries with constant current charging and voltage-
based charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Setting Output Current Limit (Refer to Figure 10)
The LTC1759 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Table 8. Recommended Resistor Values
I
MAX
R
SENSE
R
SENSE
R
S1
= R
S2
R
SET
R
ILIMIT
(A) (Ω) 1% (W) (Ω) 1% (Ω) 1% (Ω) 1%
1.023 0.100 0.25 200 3.83k 0
2.046 0.05 0.25 200 3.83k 10k
4.092 0.025 0.5 200 3.83k 33k
8.184 0.012 1 200 4.02k Open
Warning
DO NOT CHANGE THE VALUE OF R
ILIMIT
DURING OPERA-
TION. The value must remain fixed and track the R
SENSE
and R
SET
values at all times. Changing the current setting
can result in currents that greatly exceed the requested
value and potentially damage the battery or overload the
wall adapter if no input current limiting is provided.
Example Calculations
Setting up the output current to the desired value involves
calculating these values:
1. R
SENSE
: This resistor is the current sense resistor on the
charger output.
2. R
SET
: This resistor sets the current DAC output pro-
gramming current scale.
3. R
ILIMIT
: This resistor programs the full-scale value of
the current DAC (I
MAX
).
The value of R
SENSE
and R
SET
are directly related to each
other based on the values chosen for R
S1
and R
S2
. To
prevent current sense op amp input bias errors, the value
of R
S1
and R
S2
are kept the same, about 200Ω. R
SET
is
used to scale the PROG pin current relative to the R
SENSE
voltage drop to set the maximum current value.
The following example is for a 4A design.
UV
V
DD
SYNC
SDB
CHGEN
V
LIMIT
I
LIMIT
DGND
I
SET
PROG
V
C
COMP1
AGND
RNR
THERM
SDA
SCL
INTB
22
21
8
32
9
10
2
33
34
1
3
35
30
29
31
23
26
36
R
SET
, 3.83k
R4, 1.5k
LTC1759
R7, 1k
RUR
1k
R3
499Ω
R
WEAK
475k RNR
10k
C9, 0.1µF
C13, 0.33µF
V
DD
V
DD
C11, 1µF
C12, 0.68µF
R
VLIMIT
, 33k
R
CL
, 0.033Ω
R
S1
, 200Ω
R6
68Ω
R
S2
, 200Ω
R1
15.8k R2
1k
C2
0.47µF
C5, 2.2µF
C6
0.68µF
C8
0.047µF
C4, 0.1µF
C1
1µF
Q1
Q3 D1
Q2 L1
15µH
C16
22µF
SYSTEM
POWER
R
SENSE
0.025Ω
D2 D2
R
ILIMIT
, 33k
7
16
4
5
12
25
24
18
17
28
27
11
6
20
19
14
15
13
DCIN
DCDIV
INFET
V
CC
CLP
CLN
TGATE
BOOSTC
GBIAS
BOOST
SW
BGATE
SPIN
SENSE
BAT1
BAT2
V
SET
PGND C7
0.015µF
C3
22µF
C14
0.1µF
C15
10µF
35V
Al
AC
ADAPTER
INPUT
SMART
BATTERY
INTB SMBus
TO
HOST
D1: MBRS130LT3
D2: FMMD7000
L1: SUMIDA CDRH127-150
Q1: Si3457DV
Q2, Q3: Si3456DV
SCL
SDA
1759 F10
+
+
Figure 10. 4A SMBus Smart Battery Charger
24
LTC1759
Step 1: Determine R
SENSE
. Using your chosen I
MAX
for
your maximum charge current, calculate the sense resis-
tor value and round to the nearest standard value. Any
rounding error is made up by the R
SET
resistor calculation.
The value of the V
SENSE
voltage is user-definable. A good
trade-off between minimize power dissipation in the cur-
rent sense resistor and maintaining good current scale
accuracy is to use V
SENSE
= 100mV for full-scale current.
R
SENSE
= V
SENSE
/I
MAX
R
SENSE
=
0.1V/4.092A = 0.024Ω
Use R
SENSE
= 0.025Ω
Step 2: Determine the value of R
SET
. V
REF
is 2.465V.
Round R
SET
to the nearest standard value.
R
SET
= V
REF
/(1.25 • I
MAX
) • R
S1
/R
SENSE
R
SET
= 2.465/(1.25 • 4.092) • 200/0.025 = 3.855k
Use R
SET
= 3.83kΩ
Step 3: Determine the value of R
ILIMIT
. This is simply a
lookup function based on your I
MAX
value. See the Electri-
cal Characteristics table for allowable R
ILIMIT
values. Refer
to Table 8 per recommended resistor values.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆I
L
decreases
with higher frequency and increases with higher V
IN
.
∆IfLVV
V
L OUT OUT
IN
=
()()
−
11
Accepting larger values of ∆I
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I
L
= 0.4(I
MAX
). Remember the
maximum ∆I
L
occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET is
on. Lower inductor values (higher ∆I
L
) will cause this to
occur at higher load currents, which can cause a dip in
APPLICATIONS INFORMATION
WUUU
efficiency in the upper range of low current operation. In
practice 15µH is the lowest value recommended for use.
Calculating IC Power Dissipation
The power dissipation of the LTC1759 is dependent upon
the gate charge of Q2 and Q3. The gate charge is deter-
mined from the manufacturer’s data sheet and is depen-
dent upon both the gate voltage swing and the drain
voltage swing of the FET.
P
D
= (V
VCC
– V
GBIAS
)[f
PWM
(Q
G2
+ Q
G3
)] + V
VCC
• I
VCC
Example: V
VCC
= 18V, V
GBIAS
= 9.1V, f
PWM
= 230kHz,
Q
G2
= Q
G3
= 20nC, I
VCC
= 20mA.
P
D
= (18V – 9.1V)(230kHz • 40nC) + 18V • 20mA
= 441mW
Soft Start and Undervoltage Lockout
The LTC1759 is soft started by the 0.33µF capacitor on the
V
C
pin. On start-up, V
C
pin voltage will rise quickly to 0.5V,
then ramp up at a rate set by the internal 45µA pull-up
current and the external capacitor. Battery charging cur-
rent starts ramping up when V
C
voltage reaches 0.7V and
full current is achieved with V
C
at 1.1V. With a 0.33µF
capacitor, time to reach full charge current is about 10ms
and it is assumed that input voltage to the charger will
reach full value in less than 10ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
In any switching regulator, conventional timer-based soft
starting can be defeated if the input voltage rises much
slower than the time out period. This happens because the
switching regulators in the battery charger and the com-
puter power supply are typically supplying a fixed amount
of power to the load. If input voltage comes up slowly
compared to the soft start time, the regulators will try to
deliver full power to the load when the input voltage is still
well below its final value. If the adapter is current limited,
it cannot deliver full power at reduced output voltages and
the possibility exists for a quasi “latch” state where the
adapter output stays in a current limited state at reduced
output voltage. For instance, if maximum charger plus
computer load power is 30W, a 15V adapter might be
current limited at 2.5A. If adapter voltage is less than
(30W/2.5A = 12V) when full power is drawn, the adapter
25
LTC1759
voltage will be pulled down by the constant 30W load until
it reaches a lower stable state where the switching regu-
lators can no longer supply full load. This situation can be
prevented by utilizing the DCDIV resistor divider, set
higher than the minimum adapter voltage where full power
can be achieved.
Input and Output Capacitors
In the 4A Lithium Battery Charger (Figure 10), the input
capacitor (C14) is assumed to absorb all input switching
ripple current in the converter, so it must have adequate
ripple current rating. Worst-case RMS ripple current will
be equal to one half of output charging current. Actual
capacitance value is not critical. Solid tantalum low ESR
capacitors have high ripple current rating in a relatively
small surface mount package,
but caution must be used
when tantalum capacitors are used for input or output
bypass
. High input surge currents can be created when the
adapter is hot-plugged to the charger or when a battery is
connected to the charger. Solid tantalum capacitors have
a known failure mechanism when subjected to very high
turn-on surge currents. Only Kemet T495 series of “Surge
Robust” low ESR tantalums are rated for high surge
conditions such as battery to ground.
The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event.
Highest possible voltage rating on the capacitor will mini-
mize problems. Consult with the manufacturer before use.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. How-
ever, using ceramic capacitors in the output filter of the
charger can lead to acoustic noise radiation that can be
confused with instability. At low charge currents, the
charger operates in discontinuous current mode at an
audible frequency. Other alternative capacitors include
OSCON capacitors from Sanyo.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
APPLICATIONS INFORMATION
WUUU
IRMS =
(L1)(f)
VBAT
VCC
()
0.29 (VBAT) 1 –
For example, V
CC
= 19V, V
BAT
= 12.6V, L1 = 10µH, and
f = 200kHz, I
RMS
= 0.6A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the 200kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery imped-
ance. If the ESR of C3
is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
Charger Crowbar Protection
If V
IN
connector of Figure 1 charger can be instantaneously
shorted (crowbarred) to ground, then a small
P-channel FET M4 should be used to fast turn off the input
P-channel FET M3 (see Figure 11), otherwise, high surge
current might damage M3. M3 can also be replaced by a
diode if dropout voltage and heat dissipation are not
problems.
Note that LT1759 will operate even when V
BAT
is grounded.
If V
BAT
of Figure 1 charger gets shorted to ground very
quickly (crowbarred) from a high battery voltage, slow
loop response may allow charge current to build up and
damage the topside N-channel FET M1. A small diode D5
(see Figure 12) from SDB pin to V
BAT
will shut down
switching and protect the charger.
Note that M4 and/or D5 are needed only if the charger
system can be potentially crowbarred.
Protecting SMBus Inputs
The SMBus inputs, SCL and SDA, are exposed to uncon-
trolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to ESD which can cause
damage after repeated exposure. Also, if the battery’s
positive terminal makes contact to the connector before
the negative terminal, the SMBus inputs can be forced
26
LTC1759
APPLICATIONS INFORMATION
WUUU
M3
1759 F11
M4
TPO610
R
S4
INFET
LTC1759
V
CC
V
IN
Figure 12. VBAT Crowbar Protection
Figure 11. VIN Crowbar Protection
1759 F12
SDB
LTC1759
D5
1N4148
100k
V
BAT
CHGEN
CONNECTOR
TO BATTERY TO SYSTEM
1759 F13
FOR ESD PROTECTION
FOR ESD AND LATCH-UP
PROTECTION
V
DD
Figure 13
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 13.
PCB Layout Considerations
The LTC1759 has two layout critical areas. The first is the
I
SET
pin and the second is the DC/DC converter switching
circuity.
I
SET
Pin Layout: The LTC1759 I
SET
pin lead length is
critical and should be kept to a minimum to reduce
parasitic capacitance. Any parasitic capacitance on this
node will cause errors in the programmed current values.
Place R
SET
resistor directly next to the I
SET
pad. The trace
from R
SET
to the LTC1759 PROG pin pad is not critical.
DC/DC PCB Layout Hints: For maximum efficiency, the
switch node rise and fall time is kept as short as possible.
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary).
1. Keep the highest frequency loop path as small and tight
as possible. This includes the bypass capacitors, with
the higher frequency capacitors being closer to the
noise source than the lower frequency capacitors. The
highest frequency power path loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to
keep the impedance down (see Figure 15).
2. Run long power traces in parallel. Best results are
achieved if you run each trace on separate PCB layer
one on top of the other for maximum capacitance
coupling and common mode noise rejection.
3. If possible, use a ground plane under the switcher
circuitry to minimize capacitive interplane noise cou-
pling.
4. Keep signal or analog ground separate. Tie this analog
ground back to the power supply at the output ground
using a single point connection.
5. For best current programming accuracy provide a Kelvin
connection from R
SENSE
to R
S1
and R
S2
. See Figure 14
as an example.
Interfacing with a Selector
The LTC1759 is designed to be used with a true analog
multiplexer for the thermistor sensing path. Some selec-
tor ICs from various manufacturers may not implement
this. Consult LTC applications department for more infor-
mation.
Electronic Loads
The LTC1759 is designed to work with a real battery.
Electronic loads will create instability within the LTC1759
preventing accurate programming currents and voltages.
Consult LTC applications department for more informa-
tion.
27
LTC1759
Figure 14. Kelvin Sensing of Charging Current
TO R
S1
AND R
S2
1759 F14
DIRECTION OF CHARGING CURRENT
R
SENSE
APPLICATIONS INFORMATION
WUUU
Charging Indication
When a CHARGECURRENT() command with a value of
zero is sent to the LTC1759, current stops flowing into the
battery. However, the command does not cause the CHGEN
pin to pull low. This prevents use of the CHGEN pin as a
charge termination indication. Figure 16 shows a circuit
that reliably indicates when the battery is receiving a
charge current.
The circuit shown, except for the optional 555 timer IC,
filters out the I
SET
DAC 80kHz output into a smooth signal.
Q1 and R5 partially isolate the capacitance of C1 from
effecting the I
SET
pin of the LTC1759. Q1 is configured as
1759 F15
VBAT
L1
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
CIN COUT
D1
Figure 15. High Speed Switching Path
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
a crude voltage level detector looking for voltage going
below approximately one volt on the emitter. The RC
circuit consisting of R4 and C1 filters low pulses from the
I
SET
pin. Q2 buffers the RC filter circuit allowing a more
logic level type interface. The circuit is powered from the
logic output driver of the CHGEN pin of the LTC1759. The
circuit does not need any capacitive supply bypassing to
function and draws little current. When the CHGEN pin
goes low, the current consumption of the circuit is elimi-
nated. Note that some resistor values must change de-
pending on the supply voltage connected to the V
DD
pin of
the LTC1759. An optional low power 555 timer can be
added to to give a blinking LED charge indication.
UV
V
DD
SYNC
SDB
CHGEN
V
LIMIT
I
LIMIT
DGND
I
SET
PROG
V
C
COMP1
AGND
RNR
THERM
SDA
SCL
INTB
22
21
8
32
33
9
10
2
3
35
1
34
30
29
31
23
26
36
U2
LTC1759
7
16
4
5
12
25
24
18
17
28
27
11
6
20
19
14
15
13
DCIN
DCDIV
INFET
V
CC
BOOSTC
CLP
CLN
TGATE
SW
BGATE
BOOST
GBIAS
SPIN
SENSE
BAT1
BAT2
V
SET
PGND
GROUND
TRIGGER
OUTPUT
RESET
8
7
6
5
LMC555
(OPTIONAL, SEE TEXT)
R1
R1
3.3V = 240Ω
5V = 510Ω
CHARGE
CHARGE (H)
1
2
3
4
V
CC
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
1759 F16
R2
4.7k
R3
2.7M
C3
0.1µFV
DD
V
DD
C1
0.1µF
C2
0.1µF
R4
4.7M
R5
10k
R6
R6
3.3V = 330k
5V = 680k
Q1
MMBT3904
D
Q2, 2N7002
G
S
R7
330k
Figure 16. Battery Charge Indicator Circuit
28
LTC1759
1759fs, sn1759 LT/TP 0500 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
TYPICAL APPLICATION
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1473 Dual PowerPathTM Switch Driver Switches Between Two Voltages
LTC1479 PowerPath Controller for Dual Battery Systems Switches Two Batteries, AC Adapter and Charger
LT1505 High Efficiency Constant-Current/Constant-Voltage Charger Up to 97% Efficiency with Input Current Limiting
LT1511 Monolithic 3A Constant-Current/Constant-Voltage Charger Input Current Limiting; No External MOSFETs
LTC1694 SMBus Accelerator in SOT-23 Package Improves SMBus Data Integrity
LT1769 Monolithic 2A Constant-Current/Constant-Voltage Charger Similar to LT1511 but 2A Rating, 28-Pin SSOP Package
PowerPath is a trademark of Linear Technology Corporation.
UV
V
DD
SYNC
SDB
CHGEN
V
LIMIT
I
LIMIT
DGND
I
SET
PROG
V
C
COMP1
AGND
RNR
THERM
SDA
SCL
INTB
22
21
8
32
9
10
2
33
34
1
3
35
30
29
31
23
26
36
R
SET
, 3.83k
R4, 1.5k
LTC1759
R7, 1k
RUR
1k
R3
499Ω
R
WEAK
475k RNR
10k
C9, 0.1µF
C13, 0.33µF
V
DD
V
DD
C11, 1µF
C12, 0.68µF
R
VLIMIT
, 33k
R
CL
, 0.033Ω
R
S1
, 200Ω
R6
68Ω
R
S2
, 200Ω
R1
15.8k R2
1k
C2
0.47µF
C5, 2.2µF
C6
0.68µF
C8
0.047µF
C4, 0.1µF
C1
1µF
Q1
Q3 D1
Q2 L1
15µH
C16
22µF
SYSTEM
POWER
R
SENSE
0.025Ω
D2 D2
R
ILIMIT
, 33k
7
16
4
5
12
25
24
18
17
28
27
11
6
20
19
14
15
13
DCIN
DCDIV
INFET
V
CC
CLP
CLN
TGATE
BOOSTC
GBIAS
BOOST
SW
BGATE
SPIN
SENSE
BAT1
BAT2
V
SET
PGND C7
0.015µF
C3
22µF
C14
0.1µF
C15
10µF
35V
Al
AC
ADAPTER
INPUT
SMART
BATTERY
INTB SMBus
TO
HOST
D1: MBRS130LT3
D2: FMMD7000
L1: SUMIDA CDRH127-150
Q1: Si3457DV
Q2, Q3: Si3456DV
SCL
SDA
1759 F10
+
+
4A SMBus Smart Battery Charger
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
U
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
G36 SSOP 1098
0.13 – 0.22
(0.005 – 0.009)
0° – 8°
0.55 – 0.95
(0.022 – 0.037)
5.20 – 5.38**
(0.205 – 0.212)
7.65 – 7.90
(0.301 – 0.311)
12345678 9 10 11 12 14 15 16 17 1813
12.67 – 12.93*
(0.499 – 0.509)
2526 22 21 20 19232427282930313233343536
1.73 – 1.99
(0.068 – 0.078)
0.05 – 0.21
(0.002 – 0.008)
0.65
(0.0256)
BSC 0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
