IS61LPS25632T/D/J IS61LPS25636T/D/J IS61LPS51218T/DJ ISSI 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM FEATURES * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Linear burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP and 119-pin PBGA package * Power Supply +3.3V VDD +3.3V or 2.5 VDDQ (I/O) * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * JTAG Boundary Scan for PBGA package * T Version (three chips selects) * D Version (two chips selects) * J Version (PBGA Package with JTAG) (R) APRIL 2003 DESCRIPTION The ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, and IS61LPS51218T/D/J are high-speed, low-power synchronous static RAMs designed to provide burstable, highperformance memory for communication and networking applications. The IS61LPS25632T/D/J is organized as 262,144 words by 32 bits and the IS61LPS25636T/D/J is organized as 262,144 words by 36 bits. The IS61LPS51218T/ D/J is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE). Input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -225 2.8 4.4 225 -200 3.1 5 200 -166 3.5 6 166 Units ns ns MHz Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 1 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J BLOCK DIAGRAM MODE Q0 CLK CLK A0 A0' BINARY COUNTER Q1 CE ADV ADSC ADSP 256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY CLR 18/19 A A1' A1 16/17 D 18/19 Q ADDRESS REGISTER CE CLK 32, 36, or 18 GW BWE BWd (x32/x36) D 32, 36, or 18 Q DQd BYTE WRITE REGISTERS CLK BWc (x32/x36) D DQc Q BYTE WRITE REGISTERS CLK D BWb (x32/x36/x18) Q DQb BYTE WRITE REGISTERS CLK BWa (x32/x36/x18) D DQa Q BYTE WRITE REGISTERS CLK CE (T,D) CE2 (T,D) CE2 (T) 32, 36, or 18 4 D Q ENABLE REGISTER INPUT REGISTERS CLK OUTPUT REGISTERS CLK DQa - DQd OE CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI PIN CONFIGURATION 119-pin PBGA (D Version) (Top View) 1 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ NC CE2 A ADSC A A NC NC A A VDD A A NC DQc NC GND NC GND NC DQb DQc DQc GND CE GND DQb DQb VDDQ DQc GND OE GND DQb VDDQ DQc DQc BWc ADV BWb DQb DQb DQc DQc GND GW GND DQb DQb VDDQ VDD NC VDD NC VDD VDDQ DQd DQd GND CLK GND DQa DQa DQd DQd BWd NC BWa DQa DQa VDDQ DQd GND BWE GND DQa VDDQ DQd DQd GND A1 GND DQa DQa DQd NC GND A0 GND NC DQa NC A MODE VDD NC A NC NC NC A A A NC ZZ VDDQ NC NC NC NC NC VDDQ A B C D E F G H J K L M N P R T U 256K x 32 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 3 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI PIN CONFIGURATION 100-Pin TQFP (D Version) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC A A CE CE2 BWd BWc BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP (T Version) 256K x 32 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE 4 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J PIN CONFIGURATION 119-pin PBGA (D Version) (Top View) 119-pin PBGA (J Version) (Top View) 1 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ 1 2 3 4 5 6 7 VDDQ A NC CE2 A ADSP A A VDDQ A ADSC A A NC NC A A VDD A A NC DQc DQPc GND NC GND DQPb DQb DQc DQc GND CE GND DQb DQb VDDQ DQc GND OE GND DQb VDDQ DQc DQc BWc ADV BWb DQb DQb DQc DQc GND GW GND DQb DQb VDDQ VDD NC VDD NC VDD VDDQ DQd DQd GND CLK GND DQa DQa DQd DQd BWd NC BWa DQa DQa VDDQ DQd GND BWE GND DQa VDDQ DQd DQd GND A1 GND DQa DQa DQd DQPd GND A0 GND DQPa DQa NC A MODE VDD NC A NC NC NC A A A NC ZZ VDDQ TMS TDI TCK TDO NC VDDQ A A B B NC CE2 A ADSC A A NC C C NC A A VDD A A NC D D DQc DQPc GND NC GND DQPb DQb E E DQc DQc GND CE GND DQb DQb F F VDDQ DQc GND OE GND DQb VDDQ G G DQc DQc BWc ADV BWb DQb DQb H H DQc DQc GND GW GND DQb DQb J J VDDQ VDD NC VDD NC VDD VDDQ K K DQd DQd GND CLK GND DQa DQa L L DQd DQd BWd NC BWa DQa DQa M M VDDQ DQd GND BWE GND DQa VDDQ DQd DQd GND A1 GND DQa DQa DQd DQPd GND A0 GND DQPa DQa N N P P R R NC A MODE VDD NC A NC NC NC A A A NC ZZ VDDQ NC NC NC NC NC VDDQ T T U U 256K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO JTAG Boundry Scan Pins GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O 5 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI PIN CONFIGURATION 100-Pin TQFP (T Version) DQPb DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa DQPa DQPc DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd DQPd MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A DQPc A A CE CE2 BWd BWc BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP (D Version) 256K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE 6 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J PIN CONFIGURATION 119-pin PBGA (J Version) (Top Version) 119-pin PBGA (D Version) (Top Version) 1 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ A NC CE2 A ADSC A A NC B NC A A VDD A A NC C DQb NC GND NC GND DQPa NC D NC DQb GND CE GND NC DQa VDDQ NC GND OE GND DQa VDDQ NC DQb BWb ADV GND NC DQa DQb NC GND GW GND DQa NC VDDQ VDD NC VDD NC VDD VDDQ NC DQb GND CLK GND NC DQa DQb NC GND NC BWa DQa NC VDDQ DQb GND BWE GND NC VDDQ DQb NC GND A1 GND DQa NC NC DQPb GND A0 GND NC DQa NC A MODE VDD NC A NC NC A A NC A A ZZ VDDQ NC NC NC NC NC VDDQ A B C D E F G H 1 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ NC CE2 A ADSC A A NC NC A A VDD A A NC DQb NC GND NC GND DQPa NC NC DQb GND CE GND NC DQa VDDQ NC GND OE GND DQa VDDQ NC DQb BWb ADV GND NC DQa E F G H J DQb NC GND GW GND DQa NC VDDQ VDD NC VDD NC VDD VDDQ J K K L NC DQb GND CLK GND NC DQa DQb NC GND NC BWa DQa NC VDDQ DQb GND BWE GND NC VDDQ DQb NC GND A1 GND DQa NC NC DQPb GND A0 GND NC DQa NC A MODE VDD NC A NC L M M N N P P R R T T U NC A A NC A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ U 512K x 18 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable TMS, TDI TCK, TDO JTAG Boundry Scan Pins GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O 7 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI PIN CONFIGURATION 100-Pin TQFP (T Version) A A CE CE2 NC NC BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 NC NC BWb BWa CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP (D Version) NC NC NC A NC NC VDDQ GND NC DQPa DQa DQa GND VDDQ DQa DQa GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa NC NC GND VDDQ NC NC NC NC NC NC VDDQ GND NC NC DQb DQb GND VDDQ DQb DQb VDD VDD NC GND DQb DQb VDDQ GND DQb DQb DQPb NC GND VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ GND NC DQPa DQa DQa GND VDDQ DQa DQa GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa NC NC GND VDDQ NC NC NC MODE A A A A A1 A0 NC NC GND VDD NC A A A A A A A A MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A VDDQ GND NC NC DQb DQb GND VDDQ DQb DQb VDD VDD NC GND DQb DQb VDDQ GND DQb DQb DQPb NC GND VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 512K x 18 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BWa-BWd BWE 8 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O ZZ DQPa-DQPd Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J TRUTH TABLE(1-8) ADDRESS CE CE2 CE2 ZZ OE CLK DQ Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D OPERATION ADSP ADSC ADV WRITE Q NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa's and DQPa. BWb enables WRITEs to DQb's and DQPb. BWc enables WRITEs to DQc's and DQPc. BWd enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 9 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE BWa BWb BWc BWd H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C VDD 3.3V 5% VDDQ 3.3V 5% 2.5V 5% -40C to +85C 3.3V 5% 3.3V 5% 2.5V 5% LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs VDD Voltage on Vdd Supply Relatiive to GND Value -55 to +150 1.6 100 -0.5 to VDDQ + 0.5 -0.5 to VDD + 0.5 Unit C W mA V V -0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 2.5V (I/O) Min. Max. 3.3V (I/O) Min. Max. IOH = -4.0 mA (3.3V) IOH = 1.0 mA (2.5V) 2.0 -- 2.4 -- V IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) -- 0.4 -- 0.4 V Input HIGH Voltage 1.7 VDD + 0.3 2.0 VDD + 0.3 V VIL Input LOW Voltage -0.3 0.7 -0.3 0.8 V ILI Input Leakage Current GND VIN VDD(1) -5 5 -5 5 A ILO Output Leakage Current GND VOUT VDDQ, OE = VI -5 5 -5 5 A Symbol Parameter Test Conditions VOH Output HIGH Voltage VOL Output LOW Voltage VIH Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 Unit 11 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -250 Max Max x18 x36 -225 Max Max x18 x36 Symbol Parameter Test Conditions Unit ICC AC Operating Supply Current Device Selected, OE = VIH, ZZ VIL, All Inputs VIL or VIH, Cycle Time tKC min. Com. IND. 135 140 130 140 135 145 mA ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. COM. Ind. 65 -- 65 -- 60 65 60 65 mA ISBI Standby Current CMOS Input Device Deselected, Com. VDD = Max., Ind. VIN GND + 0.2V or VDD - 0.2V f=0 30 -- 30 -- 30 40 30 40 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits 30 A maximum leakage current when tied to GND + 0.2V or VDD - 0.2V. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol -200 Max Max x18 x36 -166 Max Max x18 x36 Parameter Test Conditions Unit ICC AC Operating Supply Current Device Selected, OE = VIH, ZZ VIL, All Inputs VIL or VIH, Cycle Time tKC min. Com. IND. 125 135 130 140 120 130 125 135 mA ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. COM. Ind. 55 60 55 60 50 55 50 55 mA ISBI Standby Current CMOS Input Device Deselected, Com. VDD = Max., Ind. VIN GND + 0.2V or VDD - 0.2V f=0 30 40 30 40 30 40 30 40 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits 30 A maximum leakage current when to GND + 0.2V or VDD - 0.2V. 12 tied Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 ZO = 50 +3.3V OUTPUT OUTPUT 50 351 5 pF Including jig and scope 1.5V Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 13 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 +2.5V ZO = 50 OUTPUT OUTPUT 50 1,538 5 pF Including jig and scope 1.25V Figure 3 14 Figure 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J Read/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter -166 Min. Max. -200 Min. Max. -225 Min. Max -250 Min. Max Unit fMAX Clock Frequency -- 166 -- 200 -- 225 -- 250 ns tKC Cycle Time 6 -- 5 -- 4.4 -- 4 -- ns tKH Clock High Pulse Width 2.3 -- 2 -- 1.8 -- 1.7 -- ns tKL Clock Low Pulse Width 2.3 -- 2 -- 1.8 -- 1.7 -- ns Clock Access Time -- 3.5 -- 3.1 -- 2.8 -- 2.6 ns Clock High to Output Invalid 1.5 -- 1.0 -- 1.0 -- 0.8 -- ns Clock High to Output Low-Z 0 -- 0 -- 0 -- 0 -- ns tKQHZ Clock High to Output High-Z -- 3.5 -- 3.0 -- 2.8 -- 2.6 ns tOEQ Output Enable to Output Valid -- 3.5 -- 3.1 -- 2.8 -- 2.6 ns tOELZ Output Enable to Output Low-Z 0 -- 0 -- 0 -- 0 tOEHZ(1,2) Output Enable to Output High-Z -- 3.5 -- 3.0 -- 2.8 -- 2.6 ns tAS Address Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tSS Address Status Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tWS Write Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tCES Chip Enable Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tAVS Address Advance Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tAH Address Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tSH Address Status Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tWH Write Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tCEH Chip Enable Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tAVH Address Advance Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tKQ (1) tKQX tKQLZ(1,2) (1,2) (1,2) -- ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 1,2,3,4.. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 15 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS Address tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BWx tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE tKQX tOELZ DATAOUT High-Z 1a 2a 2b 2c tKQLZ Pipelined Read High-Z Single Read 16 3a tKQHZ tKQ DATAIN 2d Burst Read Unselected Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC Cycle Time tKH -166 Min. Max. -200 Min. Max. -225 Min. Max -250 Min. Max Unit 6 -- 5 -- 4.4 -- 4 -- ns Clock High Pulse Width 2.3 -- 2 -- 1.8 -- 1.7 -- ns tKL Clock Low Pulse Width 2.3 -- 2 -- 1.8 -- 1.7 -- ns tAS Address Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tSS Address Status Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tWS Write Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tDS Data In Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tCES Chip Enable Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tAVS Address Advance Setup Time 1.5 -- 1.4 -- 1.4 -- 1.2 -- ns tAH Address Hold Time 0.5 -- 0.4 -- 0.4 -- 1.2 -- ns tSH Address Status Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tDH Data In Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tWH Write Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tCEH Chip Enable Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns tAVH Address Advance Hold Time 0.5 -- 0.4 -- 0.4 -- 0.3 -- ns Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 17 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC tAVH ADV must be inactive for ADSP Write tAVS ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH GW BWE tWS BWx tWH WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z DATAIN High-Z tDS Single Write 18 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b Burst Write 2c 2d 3a Write Unselected Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit ISB2 Current during SNOOZE MODE ZZ Vih, Com. ZZ Vih, Ind. -- -- 30 40 mA tPUS ZZ inactive to input sampled 2 -- cycle tZZI ZZ active to SNOOZE current -- 2 cycle tRZZI ZZ inactive to exit SNOOZE current 0 -- ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 19 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) - TEST CLOCK The IS61LPS25636T/D/J and IS61LPS51218T/D/JT/D/ JT/D/J have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package or with the IS61LPS25632T/D/J.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (GND) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. TEST MODE SELECT (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. TAP CONTROLLER BLOCK DIAGRAM 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry Selection Circuitry 31 30 29 . . . 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS 20 TAP CONTROLLER Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (GND) when the BYPASS instruction is executed. Boundary Scan Register TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70 TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 21 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J IDENTIFICATION (ID) REGISTER The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.The IDCODE instruction is loaded into the instruction register upon powerup or whenever the TAP controller is given a test logic reset state. Die Revision Code Part Configuration Vendor Defomotopm Part # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 256K X X X X 0 0 1 1 0 0 0 1 0 0 X X X X X X 0 0 0 1 512K X X X X 0 0 1 1 1 0 0 0 1 1 X X X X X X 0 0 0 1 Presence Register ID REGISTER CONTENTS ISSI Technology JEDEC Vendor ID Code 7 1 1 6 5 4 0 1 0 0 1 0 3 2 1 0 1 0 1 1 1 0 1 1 SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the CaptureDR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set- 22 up plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J INSTRUCTION CODES Code Instruction Description 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 23 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J TAP Electrical Characteristics Over the Operating Range(1,2) Symbol Parameter Test Conditions Min. Max. Units VOH1 Output HIGH Voltage IOH = -2.0 mA 1.7 -- V VOH2 Output HIGH Voltage IOH = -100 mA 2.1 -- V VOL1 Output LOW Voltage IOL = 2.0 mA -- 0.7 V VOL2 Output LOW Voltage IOL = 100 mA -- 0.2 V VIH Input HIGH Voltage 1.7 VDD +0.3 V VIL Input LOW Voltage IOLT = 2mA -0.3 0.7 V IX Input Load Current GND V I VDDQ -5 5 mA Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) VDD +1.5V for t tTCYC/2, Undershoot:VIL (AC) 0.5V for t tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. TAP AC ELECTRICAL CHARACTERISTICS(1) (OVER OPERATING RANGE) Symbol Parameter Min. Max. Unit tTCYC TCK Clock cycle time 100 -- ns fTF TCK Clock frequency -- 10 MHz tTH TCK Clock HIGH 40 -- ns tTL TCK Clock LOW 40 -- ns tTMSS TMS setup to TCK Clock Rise 10 -- ns tTDIS TDI setup to TCK Clock Rise 10 -- ns tCS Capture setup to TCK Rise 10 -- ns tTMSH TMS hold after TCK Clock Rise 10 -- ns tTDIH TDI Hold after Clock Rise 10 -- ns tCH Capture hold after Clock Rise 10 -- ns tTDOV TCK LOW to TDO valid -- 20 ns tTDOX TCK LOW to TDO invalid 0 -- ns Notes: 1. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. 24 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J TAP AC TEST CONDITIONS Input pulse levels 0 to 2.5V Input rise and fall times 1ns Input timing reference levels 1.25V Output reference levels 1.25V Test load termination supply voltage 1.25V TAP Output Load Equivalent 50 1.25V TDO 20 pF Z0 = 50 GND TAP TIMING 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 25 (R) ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J BOUNDARY SCAN ORDER (256K X 36) Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Bump Name ID 1 A 2R 19 DQb 7G 37 BWa 5L 55 DQd 2K 2 A 3T 20 DQb 6F 38 BWb 5G 56 DQd 1L 3 A 4T 21 DQb 7E 39 BWc 3G 57 DQd 2M 4 A 5T 22 DQb 7D 40 BWd 3L 58 DQd 1N 5 A 6R 23 DQb 7H 41 CE2 2B 59 DQd 1P 6 A 3B 24 DQb 6G 42 CE 4E 60 DQd 1K 7 A 5B 25 DQb 6E 43 A 3A 61 DQd 2L 8 DQa 6P 26 DQb 6D 44 A 2A 62 DQd 2N 9 DQa 7N 27 A 6A 45 DQc 2D 63 DQd 2P 10 DQa 6M 28 A 5A 46 DQc 1E 64 MODE 3R 11 DQa 7L 29 ADV 4G 47 DQc 2F 65 A 2C 12 DQa 6K 30 ADSP 4A 48 DQc 1G 66 A 3C 13 DQa 7P 31 ADSC 4B 49 DQc 2H 67 A 5C 14 DQa 6N 32 OE 4F 50 DQc 1D 68 A 6C 15 DQa 6L 33 BWE 4M 51 DQc 2E 69 A1 4N 16 DQa 7K 34 GW 4H 52 DQc 2G 70 A0 4P 17 ZZ 7T 35 CLK 4K 53 DQc 1H 18 DQb 6H 36 A 6B 54 NC 5R BOUNDARY SCAN ORDER (512K X 18) Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Bump Name ID 1 A 2R 14 DQa 7G 27 CLK 4K 40 DQb 2K 2 A 2T 15 DQa 6F 28 A 6B 41 DQb 1L 3 A 3T 16 DQa 7E 29 BWa 5L 42 DQb 2M 4 A 5T 17 DQa 6D 30 BWb 3G 43 DQb 1N 5 A 6R 18 A 6T 31 CE2 2B 44 DQb 2P 6 A 3B 19 A 6A 32 CE 4E 45 MODE 3R 7 A 5B 20 A 5A 33 A 3A 46 A 2C 8 DQa 7P 21 ADV 4G 34 A 2A 47 A 3C 9 DQa 6N 22 ADSP 4A 35 DQb 1D 48 A 5C 10 DQa 6L 23 ADSC 4B 36 DQb 2E 49 A 6C 11 DQa 7K 24 OE 4F 37 DQb 2G 50 A1 4N 12 ZZ 7T 25 BWE 4M 38 DQb 1H 51 A0 4P 13 DQa 6H 26 GW 4H 39 NC 5R 26 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI ORDERING INFORMATION ORDERING INFORMATION (T Version) Commercial Range: 0C to +70C (T Version) Industrial Range: -40C to +85C Package Speed Order Part Number IS61LPS25632T-166TQ TQFP 166Mhz IS61LPS25632T-166TQI TQFP 200Mhz IS61LPS25632T-200TQ TQFP 200Mhz IS61LPS25632T-200TQI TQFP 225Mhz IS61LPS25632T-225TQ TQFP 225Mhz IS61LPS25632T-225TQI TQFP 250Mhz IS61LPS25632T-250TQ TQFP Speed Order Part Number 166Mhz (D Version) Commercial Range: 0C to +70C Speed Order Part Number Package (D Version) Industrial Range: -40C to +85C Package Speed Order Part Number Package 166 MHz 166Mhz IS61LPS25632D-166B IS61LPS25632D-166TQ BGA TQFP 166 MHz 166Mhz IS61LPS25632D-166BI IS61LPS25632D-166TQI BGA TQFP 200 MHz 200Mhz IS61LPS25632D-200B IS61LPS25632D-200TQ BGA TQFP 200 MHz 200Mhz IS61LPS25632D-200BI IS61LPS25632D-200TQI BGA TQFP 225 MHz 225Mhz IS61LPS25632D-225B IS61LPS25632D-225TQ BGA TQFP 225 MHz 225Mhz IS61LPS25632D-225BI IS61LPS25632D-225TQI BGA TQFP 250 MHz 250Mhz IS61LPS25632D-250B IS61LPS25632D-250TQ BGA TQFP Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 27 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI ORDERING INFORMATION ORDERING INFORMATION (T Version) Commercial Range: 0C to +70C (T Version) Industrial Range: -40C to +85C Speed Order Part Number Package Speed Order Part Number 166Mhz IS61LPS25636T-166TQ TQFP 166Mhz IS61LPS25636T-166TQI TQFP 200Mhz IS61LPS25636T-200TQ TQFP 200Mhz IS61LPS25636T-200TQI TQFP 225Mhz IS61LPS25636T-225TQ TQFP 225Mhz IS61LPS25636T-225TQI TQFP 250Mhz IS61LPS25636T-250TQ TQFP (D Version) Commercial Range: 0C to +70C Speed Order Part Number Package (D Version) Industrial Range: -40C to +85C Package Speed Order Part Number Package 166 MHz 166Mhz IS61LPS25636D-166B IS61LPS25636D-166TQ BGA TQFP 166 MHz 166Mhz IS61LPS25636D-166BI IS61LPS25636D-166TQI BGA TQFP 200 MHz 200Mhz IS61LPS25636D-200B IS61LPS25636D-200TQ BGA TQFP 200 MHz 200Mhz IS61LPS25636D-200BI IS61LPS25636D-200TQI BGA TQFP 225 MHz 225Mhz IS61LPS25636D-225B IS61LPS25636D-225TQ BGA TQFP 225 MHz 225Mhz IS61LPS25636D-225BI IS61LPS25636D-225TQI BGA TQFP 250 MHz 250Mhz IS61LPS25636D-250B IS61LPS25636D-250TQ BGA TQFP (J Version) Industrial Range: -40C to +85C Speed Order Part Number (J Version) Commercial Range: 0C to +70C Package Speed Order Part Number Package 166 MHz IS61LPS25636J-166BI BGA 166 MHz IS61LPS25636J-166B BGA 200 MHz IS61LPS25636J-200BI BGA 200 MHz IS61LPS25636J-200B BGA 225 MHz IS61LPS25636J-225BI BGA 225 MHz IS61LPS25636J-225B BGA 250 MHz IS61LPS25636J-250B BGA 28 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 04/01/03 (R) IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J ISSI ORDERING INFORMATION ORDERING INFORMATION (T Version) Commercial Range: 0C to +70C (T Version) Industrial Range: -40C to +85C Speed Order Part Number Package Speed Order Part Number 166Mhz IS61LPS51218T-166TQ TQFP 166Mhz IS61LPS51218T-166TQI TQFP 200Mhz IS61LPS51218T-200TQ TQFP 200Mhz IS61LPS51218T-200TQI TQFP 225Mhz IS61LPS51218T-225TQ TQFP 225Mhz IS61LPS51218T-225TQI TQFP 250Mhz IS61LPS51218T-250TQ TQFP (D Version) Commercial Range: 0C to +70C Speed Order Part Number Package (D Version) Industrial Range: -40C to +85C Package Speed Order Part Number Package 166 MHz 166Mhz IS61LPS51218D-166B IS61LPS51218D-166TQ BGA TQFP 166 MHz 166Mhz IS61LPS51218D-166BI IS61LPS51218D-166TQI BGA TQFP 200 MHz 200Mhz IS61LPS51218D-200B IS61LPS51218D-200TQ BGA TQFP 200 MHz 200Mhz IS61LPS51218D-200BI IS61LPS51218D-200TQI BGA TQFP 225 MHz 225Mhz IS61LPS51218D-225B IS61LPS51218D-225TQ BGA TQFP 225 MHz 225Mhz IS61LPS51218D-225BI IS61LPS51218D-225TQI BGA TQFP 250 MHz 250Mhz IS61LPS51218D-250B IS61LPS51218D-250TQ BGA TQFP (J Version) Commercial Range: 0C to +70C Speed Order Part Number (J Version) Industrial Range: -40C to +85C Package Speed Order Part Number Package 166 MHz IS61LPS51218J-166B BGA 166 MHz IS61LPS51218J-166BI BGA 200 MHz IS61LPS51218J-200B BGA 200 MHz IS61LPS51218J-200BI BGA 225 MHz IS61LPS51218J-225B BGA 225 MHz IS61LPS51218J-225BI BGA 250 MHz IS61LPS51218J-250B BGA Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 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