General Description
The MAX15053 high-efficiency, current-mode, synchro-
nous step-down switching regulator with integrated power
switches delivers up to 2A of output current. The device
operates from 2.7V to 5.5V and provides an output volt-
age from 0.6V up to 94% of the input voltage, making
the device ideal for distributed power systems, portable
devices, and preregulation applications.
The MAX15053 utilizes a current-mode control archi-
tecture with a high gain transconductance error ampli-
fier. The current-mode control architecture facilitates
easy compensation design and ensures cycle-by-cycle
current limit with fast response to line and load transients.
The MAX15053 offers selectable skip-mode functional-
ity to reduce current consumption and achieve a higher
efficiency at light output load. The low RDS(ON) integrated
switches ensure high efficiency at heavy loads while
minimizing critical inductances, making the layout design
a much simpler task with respect to discrete solutions.
Utilizing a simple layout and footprint assures first-pass
success in new designs.
The MAX15053 features a 1MHz, factory-trimmed, fixed-
frequency PWM mode operation. The high switching fre-
quency, along with the PWM current-mode architecture,
allows for a compact, all-ceramic capacitor design.
The MAX15053 offers a capacitor-programmable soft-
start reducing inrush current, startup into PREBIAS
operations, and a PGOOD open-drain output that can be
used as an interrupt and for power sequencing.
The MAX15053 is available in a 9-bump (3 x 3 array),
1.5mm x 1.5mm WLP package and is specified over the
-40NC to +85NC temperature range.
Applications
●Distributed Power Systems
●Preregulators for Linear Regulators
●Portable Devices
●Notebook Power
●Server Power
●IP Phones
Benets and Features
●Simpler, Smaller Design than Discrete Solutions
• Integrated30mΩ(typ)RDS(ON) High-Side
and18mΩ(typ)Low-SideMOSFETsat5V
• Factory-Trimmed,1MHzSwitchingFrequency
• Stable with Low-ESR Ceramic Output Capacitors
• SupportedbyFreeEE-Sim® Design and
Simulation Tool
●High Performance Suits Wide Range of Point-of-
Load Applications
• ±1% Output-Voltage Accuracy Over Load, Line,
and Temperature
• Continuous 2A Output Current Over Temperature
• Operates from 2.7V to 5.5V Supply
• Adjustable Output from 0.6V to Up to 0.94 x VIN
●High Efficiency Across Light and Heavy Loads
Reduces Power Consumption and Heat
• 96% Efficiency with 3.3V Output at 2A
• Internal30mΩ(typ)RDS(ON) High-Side and 18mI
(typ)Low-SideMOSFETsat5V
• Skip-ModeFunctionalityforLightLoads
●Control Power Startup and Sequencing for Glitch-
FreeProcessorOperation
• Enable Input/Power-Good Output Enables
Sequencing
• Safe-Startup Into Prebiased Output
• Programmable Soft-Start
• External Reference Input Can be Used to Drive
Soft-Start Directly
● IntegratedProtectionFeaturesforImprovedPower-
Supply Reliability
• FullyProtectedAgainstOvercurrentand
Overtemperature
• Input Undervoltage Lockout
• Cycle-by-Cycle Overcurrent Protection
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit appears at end of data sheet.
Ordering Information
19-5240; Rev 3; 4/15
EVALUATION KIT AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX15053EWL+ -40°C to +85°C 9 WLP
EE-Sim is a registered trademark of Maxim Integrated
Products, Inc.
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Electrical Characteristics
(VIN = 5V, TA = -40NC to +85NC, unless otherwise noted, typical values are at TA = +25NC.) (Note 4)
Absolute Maximum Ratings
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should not exceed the IC’s package
power dissipation limits.
Note 2: Limit the junction temperature to +105NC for continuous operation at maximum output current.
WLP
Junction-to-Case Thermal Resistance (BJC) ...................26NC/W
Junction-to-Ambient Thermal Resistance (BJA) ..............71NC/W
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board.Fordetailedinformationonpackagethermalconsiderations,refertowww.maximintegrated.com/thermal-tutorial.
Package Thermal Characteristics (Note 3)
IN, PGOOD to GND ................................................-0.3V to +6V
LX to GND ..................................................-0.3V to (VIN + 0.3V)
LX to GND .......................................-1V to (VIN + 0.3V) for 50ns
EN, COMP, FB, SS/REFIN, SKIP to GND ... -0.3V to (VIN + 0.3V)
LX Current (Note 1) ................................................... -5A to +5A
Output Short-Circuit Duration .................................... Continuous
Continuous Power Dissipation (TA = +70NC)
9-Bump WLP Multilayer Board
(derate 14.1mW/NC above TA = +70NC) .................... 1127mW
Operating Temperature Range .......................... -40NC to +85NC
Operating Junction Temperature (Note 2) ......................+105NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IN Voltage Range VIN 2.7 5.5 V
IN Shutdown Supply Current VEN = 0V 0.2 2 FA
IN Supply Current IIN VEN = 5V, VFB = 0.65V, no switching 1.56 2.3 mA
VIN Undervoltage Lockout
Threshold LX starts switching, VIN rising 2.6 2.7 V
VIN Undervoltage Lockout
Hysteresis LX stops switching, VIN falling 200 mV
ERROR AMPLIFIER
Transconductance gMV 1.5 mS
Voltage Gain AVEA 90 dB
FBSet-PointAccuracy VFB Over line, load, and temperature 594 600 606 mV
FBInputBiasCurrent IFB VFB = 0.6V -500 +500 nA
COMP to Current-Sense
Transconductance gMC 18 A/V
COMP Clamp Low VFB = 0.65V, VSS = 0.6V 0.94 V
POWER SWITCHES
LX On-Resistance, High-Side
pMOS 30 mI
LX On-Resistance, Low-Side
nMOS 18 mI
High-Side Switch Current-Limit
Threshold IHSCL 4 A
Low-Side Switch Sink Current-
Limit Threshold 4 A
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Electrical Characteristics (continued)
(VIN = 5V, TA = -40NC to +85NC, unless otherwise noted, typical values are at TA = +25NC.) (Note 4)
Note 4: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and characterization.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-Side Switch Source Current-
Limit Threshold 4 A
LX Leakage Current VEN = 0V 10 FA
RMS LX Output Current 2 A
OSCILLATOR
SwitchingFrequency fSW 850 1000 1150 kHz
Maximum Duty Cycle DMAX 94 95.8 %
Minimum Controllable On-Time 70 ns
Slope Compensation Ramp
Valley 1.15 V
Slope Compensation Ramp
Amplitude VSLOPE Extrapolated to 100% duty cycle 320 mV
ENABLE
EN Input High Threshold Voltage VEN rising 1.45 V
EN Input Low Threshold Voltage VEN falling 0.4 V
EN Input Leakage Current VEN = 5V 0.025 FA
SKIP Input Leakage Current VSKIP = VEN = 5V 25 FA
SOFT-START, PREBIAS, REFIN
Soft-Start Current ISS VSS/REFIN = 0.45V, sourcing 10 FA
SS/REFINDischargeResistance RSS ISS/REFIN = 10mA, sinking 8.3 I
SS/REFINPrebiasModeStop
Voltage VSS/REFIN rising 0.58 V
External Reference Input Range 0VIN -
1.8 V
HICCUP
Number of Consecutive Current-
Limit Events to Hiccup 8 Events
Timeout 1024 Clock
Cycles
POWER-GOOD OUTPUT
PGOOD Threshold VFB rising 0.535 0.555 0.575 V
PGOOD Threshold Hysteresis VFB falling 28 mV
PGOOD VOL IPGOOD = 5mA, VFB = 0.5V 20 60 mV
PGOOD Leakage VPGOOD = 5V, VFB = 0.65V 0.013 FA
THERMAL SHUTDOWN
Thermal Shutdown Threshold 150 NC
Thermal Shutdown Hysteresis Temperature falling 20 NC
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX15053 toc07
OUTPUT VOLTAGE (V)
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
OUTPUT CURRENT (A)
0 0.5 1.0 2.01.5 2.5 3.0
VOUT = 5V
VOUT = 3.3V
OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX15053 toc06
OUTPUT VOLTAGE (V)
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
SUPPLY VOLTAGE (V)
2.7 3.2 3.7 4.74.2 5.2
IOUT = 0.5A
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
MAX15053 toc05
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
920
940
960
980
1000
1020
1040
1060
1080
1100
900
2.7 3.2 3.7 4.74.2 5.2
EFFICIENCY vs. OUTPUT CURRENT
(SKIP MODE)
MAX15053 toc04
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
55
60
65
70
75
80
85
90
95
100
50
200
400
600
800
1000
1200
1400
1600
1800
2000
VIN = 3.3V
VOUT = 2.5V VOUT = 1.5V
VOUT = 1.8V VOUT = 1.2V
EFFICIENCY vs. OUTPUT CURRENT
(SKIP MODE)
MAX15053 toc03
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
55
60
65
70
75
80
85
90
95
100
50
200
400
600
800
1000
1200
1400
1600
1800
2000
VIN = 5V
VOUT = 3.3V
VOUT = 2.5V VOUT = 1.5V
VOUT = 1.8V VOUT = 1.2V
EFFICIENCY vs. OUTPUT CURRENT
(PWM MODE)
MAX15053 toc02
OUTPUT CURRENT (mA)
EFFICIENCY (%)
200016001200800400
55
60
65
70
75
80
85
90
95
100
50
0 2400
VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V
VIN = 3.3V
VOUT = 1.5V
EFFICIENCY vs. OUTPUT CURRENT
(PWM MODE)
MAX15053 toc01
OUTPUT CURRENT (mA)
EFFICIENCY (%)
200016001200800400
55
60
65
70
75
80
85
90
95
100
50
0 2400
VOUT = 3.3V VOUT = 1.8V VOUT = 1.2V
VIN = 5V
VOUT = 2.5V VOUT = 1.5V
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated
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Typical Operating Characteristics
(VIN = 5V, VOUT = 1.8V, ILOAD = 2A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.)
SHUTDOWN WAVEFORM
MAX15053 toc12
VOUT
1V/div
VENABLE
5V/div
VPGOOD
5V/div
ILX
1A/div
10µs/div
INPUT AND OUTPUT RIPPLE VOLTAGE
WAVEFORM (IOUT = 2A)
MAX15053 toc11
INPUT
20mV/div
AC-COUPLED
OUTPUT
100mV/div
AC-COUPLED
400ns/div
SWITCHING WAVEFORM IN SKIP MODE
(IOUT = 10mA)
MAX15053 toc10
VOUT
50mV/div
AC-COUPLED
VLX
5V/div
ILX
1A/div
10µs/div
SWITCHING WAVEFORMS
MAX15053 toc09b
VOUT
50mV/div
AC-COUPLED
VLX
5V/div
ILX
1A/div
0A
400
n
s/div
VIN = 3.3V
SWITCHING WAVEFORMS
(IOUT = 2A)
MAX15053 toc9a
VOUT
50mV/div
AC-COUPLED
VLX
5V/div
ILX
1A/div
0A
400
n
s/div
VIN = 5V
LOAD-TRANSIENT RESPONSE
MAX15053 toc08
VOUT
100mV/div
AC-COUPLED
IOUT
1A/div
0A
40
µ
s/div
PWM MODE
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated
│
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Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.8V, ILOAD = 2A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.8V, ILOAD = 2A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.)
FB VOLTAGE vs. TEMPERATURE
MAX15053 toc17
AMBIENT TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
806040200-20
596
598
600
602
604
606
594
-40
NO LOAD
RMS INPUT CURRENT
vs. INPUT VOLTAGE
MAX15053 toc16
INPUT VOLTAGE (V)
RMS INPUT CURRENT (mA)
5.24.74.23.73.2
10
20
30
40
50
60
70
80
90
100
0
2.7
SHORT CIRCUIT ON OUTPUT
SHORT-CIRCUIT HICCUP MODE
MAX15053 toc15
IIN
500mA/div
VOUT
1V/div
IOUT
5A/div
200µs/div
QUIESCENT CURRENT
vs. INPUT VOLTAGE
MAX15053 toc14
INPUT VOLTAGE (V)
QUIESCENT CURRENT (nA)
5.24.74.23.73.2
10
20
30
40
50
60
70
80
90
100
0
2.7
VEN = 0V
SOFT-START WAVEFORMS (SKIP MODE)
(IOUT = 2A)
MAX15053 toc13b
VOUT
1V/div
VENABLE
5V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
SOFT-START WAVEFORMS (PWM)
(IOUT = 2A)
MAX15053 toc13a
VOUT
1V/div
VENABLE
5V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated
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Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.8V, ILOAD = 2A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.)
STARTING INTO A PREBIASED OUTPUT
(IOUT = 2A)
MAX15053 toc19
VENABLE
5V/div
VOUT
1V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
PWM MODE
STARTING INTO A PREBIASED OUTPUT
HIGHER THAN SET OUTPUT
MAX15053 toc21
VOUT
500mV/div
VSS/REFIN
500mV/div
IL
1A/div
400µs/div
1.8V
10I LOAD AT OUT
STARTING INTO A PREBIASED OUTPUT
MAX15053 toc20b
VENABLE
5V/div
VOUT
1V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
STARTING INTO A PREBIASED OUTPUT
(NO LOAD)
MAX15053 toc20a
VENABLE
5V/div
VOUT
1V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
PWM MODE
SOFT-START WAVEFORMS
(EXTERNAL REFIN) (SKIP MODE)
MAX15053 toc18b
VSS/REFIN
500mV/div
VOUT
1V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
NO LOAD
SOFT-START WAVEFORMS
(EXTERNAL REFIN) (PWM MODE)
MAX15053 toc18a
VSS/REFIN
500mV/div
VOUT
1V/div
VPGOOD
5V/div
ILX
1A/div
200µs/div
NO LOAD
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated
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Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.8V, ILOAD = 2A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.)
INPUT CURRENT (mA)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
INPUT CURRENT IN SKIP MODE
vs. OUTPUT VOLTAGE
MAX15053 toc23
OUTPUT VOLTAGE (V)
1.2 1.7 2.2 2.7 3.2
NO LOAD
VCC = 3.3V
VCC = 5.0V
CASE TEMPERATURE
vs. AMBIENT TEMPERATURE
MAX15053 toc22
AMBIENT TEMPERATURE (°C)
CASE TEMPERATURE (°C)
806040200-20
-20
0
20
40
60
80
100
-40
-40
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated
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Pin Description
Pin Conguration
BUMP NAME FUNCTION
A1 GND Analog Ground/Low-Side Switch Source Terminal. Connect to the PCB copper plane at one point near
the input bypass capacitor return terminal.
A2 LX Inductor Connection. Connect LX to the switched side of the inductor. LX is high impedance when the
IC is in shutdown mode.
A3 IN Input Power Supply. Input supply range is from 2.7V to 5.5V. Bypass with a minimum 10FF ceramic
capacitor to GND. See Figures 5 and 6.
B1 COMP Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to GND. See
the Closing the Loop: Designing the Compensation Circuitry section.
B2 SKIP Skip-Mode Input. Connect to EN to select skip mode or leave unconnected for normal operation.
B3 EN Enable Input. EN is a digital input that turns the regulator on and off. Drive EN high to turn on the regulator.
Connect to IN for always-on operation.
C1 FB Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to
set the output voltage from 0.6V up to 94% of VIN.
C2 SS/REFIN
Soft-Start/External Voltage Reference Input. Connect a capacitor from SS/REFIN to GND to set the startup
time. See the Setting the Soft-Start Time section for details on setting the soft-start time. Apply a voltage
reference from 0V to VIN - 1.5V to drive soft-start externally.
C3 PGOOD Open-Drain Power-Good Output. PGOOD goes high when FB is above 555mV and pulls low if FB is
below 527mV.
WLP
TOP VIEW
(BUMPS ON BOTTOM)
SS/REFINFB PGOOD
SKIPCOMP EN
LXGND IN
MAX15053
A1
B1
C1 C2 C3
B2 B3
A3A2
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Block Diagram
BIAS
GENERATOR
EN LOGIC, IN UVLO
THERMAL SHDN
SKIP-MODE
LOGIC
CONTROL
LOGIC
SKPM
0.58V
CK
GND
PGOOD
EN
SS/REFIN
FB
RAMP
CK
COMP
SKIP
LX
IN
SHDN
VOLTAGE
REFERENCE
OSCILLATOR
RAMP GEN
SKPM
LX
SKPM
LX
IN
IN
IN
SINK
SOURCE
ZX
LOW-SIDE SOURCE-SINK
CURRENT LIMIT AND ZERO-
CROSSING COMPARATOR
0.6V
HIGH-SIDE
CURRENT LIMIT
STRONG PREBIASED
FORCED START
SS/REFIN BUFFER
ERROR AMPLIFIER
10µA
PWM
COMPARATOR
POWER-GOOD
COMPARATOR
CURRENT-SENSE
AMPLIFIER
0.555V RISING,
0.527V FALLING
MAX15053
C
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Detailed Description
The MAX15053 high-efficiency, current-mode switch-
ing regulator can deliver up to 2A of output current. The
MAX15053 provides output voltages from 0.6V to 0.94 x
VIN from 2.7V to 5.5V input supplies, making the device
ideal for on-board point-of-load applications.
The MAX15053 delivers current-mode control architec-
ture using a high gain transconductance error amplifier.
The current-mode control architecture facilitates easy
compensation design and ensures cycle-by-cycle current
limit with fast response to line and load transients.
The MAX15053 features a 1MHz fixed switching frequen-
cy, allowing for all-ceramic capacitor designs and fast
transient responses. The high operating frequency mini-
mizes the size of external components. The MAX15053 is
available in a 1.5mm x 1.5mm (3 x 3 array) x 0.5mm pitch
WLP package.
The MAX15053 offers a selectable skip-mode functional-
ity to reduce current consumption and achieve a higher
efficiency at light output loads. The low RDS(ON) inte-
grated switches (30mI high-side and 18mI low-side,
typ) ensure high efficiency at heavy loads while minimiz-
ing critical inductances, making the layout design a much
simpler task with respect to discrete solutions. Utilizing a
simple layout and footprint assures first-pass success in
new designs.
The MAX15053 features 1MHz Q15%, factory-trimmed,
fixed-frequency PWM mode operation. The MAX15053 also
offers capacitor-programmable, soft-start reducing inrush
current, startup into PREBIAS operation, and a PGOOD
open-drain output for sequencing with other devices.
Controller Function–PWM Logic
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-sideMOSFETs.Thecontrol logicblock controlsthe
break-before-make logic and all the necessary timing.
Thehigh-sideMOSFETturnsonatthebeginningofthe
oscillator cycle and turns off when the COMP voltage
crosses the internal current-mode ramp waveform, which
is the sum of the slope compensation ramp and the
current-mode ramp derived from inductor current (current-
senseblock).Thehigh-sideMOSFETalsoturnsoffifthe
maximum duty cycle is 94%, or when the current limit is
reached.Thelow-sideMOSFETturnsonfortheremain-
der of the oscillation cycle.
Starting into a Prebiased Output
The MAX15053 can soft-start into a prebiased output
without discharging the output capacitor. In safe pre-
biased startup, both low-side and high-side MOSFETs
remain off to avoid discharging the prebiased output.
PWM operation starts when the voltage on SS/REFIN
crossesthevoltageonFB.
The MAX15053 can start into a prebiased voltage higher
than the nominal set point without abruptly discharg-
ing the output. Forced PWM operation starts when the
SS/REFINvoltagereaches0.58V(typ),forcingthecon-
verter to start. In case of prebiased output, below or above
the output nominal set point, if low-side sink current-limit
threshold (set to the reduced value of -0.4A (typ) for the
first 32 clock cycles and then set to -4A typ) is reached,
the low-side switch turns off before the end of the clock
period, and the high-side switch turns on until one of the
following conditions is satisfied:
• High-side source current hits the reduced high-side
current limit (0.4A, typ); in this case, the high-side
switch is turned off for the remaining time of the clock
period.
• The clock period ends. Reduced high-side current
limit is activated to recirculate the current into the
high-side power switch rather than into the internal
high-side body diode, which could be damaged.
Low-side sink current limit is provided to protect the
low-side switch from excessive reverse current during
prebiased operation.
In skip mode operation, the prebias output needs to be
lower than the set point.
Enable Input
The MAX15053 features independent device enable con-
trol and power-good signal that allow for flexible power
sequencing. Drive the enable input (EN) high to enable
the regulator, or connect EN to IN for always-on opera-
tion. Power-good (PGOOD) is an open-drain output that
asserts when VFB is above 555mV (typ), and deasserts
low if VFB is below 527mV (typ).
Programmable Soft-Start (SS/REFIN)
The MAX15053 utilizes a soft-start feature to slowly
ramp up the regulated output voltage to reduce input
inrush current during startup. Connect a capacitor from
SS/REFINtoGNDtosetthestartuptime(seetheSetting
the Soft-Start Time section for capacitor selection details).
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
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Error Amplier
A high-gain error amplifier provides accuracy for the
voltage-feedback loop regulation. Connect the necessary
compensation network between COMP and GND (see
the Compensation Design Guidelines section). The error-
amplifier transconductance is 1.5mS (typ). COMP clamp
low is set to 0.94V (typ), just below the slope ramp com-
pensation valley, helping COMP to rapidly return to the
correct set point during load and line transients.
PWM Comparator
The PWM comparator compares COMP voltage to the
current-derived ramp waveform (LX current to COMP
voltage transconductance value is 18A/V typ). To avoid
instability due to subharmonic oscillations when the duty
cycle is around 50% or higher, a slope compensation
ramp is added to the current-derived ramp waveform.
The compensation ramp slope (0.3V x 1MHz = 0.3V/Fs)
is equivalent to half the inductor current downslope in the
worst case (load 2A, current ripple 30% and maximum
duty-cycle operation of 94%). The slope compensation
ramp valley is set to 1.15V (typ).
Overcurrent Protection and Hiccup
When the converter output is shorted or the device is
overloaded,eachhigh-side MOSFETcurrent-limit event
(4A typ) turns off the high-side MOSFET and turns on
thelow-sideMOSFET.Oneachcurrent-limiteventa3-bit
counter is incremented. The counter is reset after three
consecutive high-side MOSFETs turn on without reach-
ing current limit. If the current-limit condition persists, the
counter fills up reaching eight events. The control logic
thendischargesSS/REFIN,stopsbothhigh-sideandlow-
sideMOSFETs,andwaitsforahiccupperiod(1024clock
cycles typ) before attempting a new soft-start sequence.
The hiccup mode is also enabled during soft-start time.
Thermal-Shutdown Protection
The MAX15053 contains an internal thermal sensor that
limits the total power dissipation to protect the device in
the event of an extended thermal fault condition. When
the die temperature exceeds +150NC (typ), the thermal
sensor shuts down the device, turning off the DC-DC
converter to allow the die to cool. After the die tempera-
ture falls by 20NC (typ), the device restarts, following the
soft-start sequence.
Skip Mode Operation
The MAX15053 operates in skip mode when SKIP is con-
nected to EN. When in skip mode, LX output becomes
high impedance when the inductor current falls below
200mA (typ). The inductor current does not become nega-
tive. If during a clock cycle the inductor current falls below
the 200mA threshold (during off-time), the low side turns
off. At the next clock cycle, if the output voltage is above
set point, the PWM logic keeps both high-side and low-
sideMOSFETsoff.Ifinsteadtheoutputvoltageisbelow
the set point, the PWM logic drives the high-side on for a
minimum fixed on-time (300ns typ). In this way the system
can skip cycles, reducing frequency of operations, and
switches only as needed to service load at the cost of
an increase in output voltage ripple (see the Skip Mode
Frequency and Output Ripple section). In skip mode,
power dissipation is reduced and efficiency is improved
atlightloadsbecausepowerMOSFETsdonotswitchat
every clock cycle.
Applications Information
Setting the Output Voltage
The MAX15053 output voltage is adjustable from 0.6V
up to 94% of VINbyconnectingFBtothecentertapofa
resistor-dividerbetweentheoutputandGND(Figure1).
ChooseR1andR2sothattheDCerrorsduetotheFB
input bias current (Q500nA) do not affect the output volt-
age accuracy. With lower value resistors, the DC error
is reduced, but the amount of power consumed in the
resistor-divider increases. A typical value for R2 is 10kI,
but values between 5kI and 50kI are acceptable. Once
R2 is chosen, calculate R1 using:
OUT
FB
V
R1 = R2 1
V

×−


where the feedback threshold voltage, VFB = 0.6V (typ).
When regulating for an output of 0.6V in skip mode, short
FBtoOUTandkeepR2connectedfromFBtoGND.
Inductor Selection
A high-valued inductor results in reduced inductor ripple
current, leading to a reduced output ripple voltage.
However, a high-valued inductor results in either a larger
physical size or a high series resistance (DCR) and
a lower saturation current rating. Typically, choose an
inductor value to produce a current ripple equal to 30%
of load current. Choose the inductor with the following
formula:
OUT OUT
SW LOAD IN
VV
L1
f LIR I V

= ×−

×× 
where fSW is the internally fixed 1MHz switching frequen-
cy, and LIR is the desired inductor current ratio (typically
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
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set to 0.3). In addition, the peak inductor current, IL_PK,
must always be below the minimum high-side current-
limit value, IHSCL, and the inductor saturation current
rating, IL_SAT.
Ensure that the following relationship is satisfied:
( )
L_PK LOAD L HSCL, L_SAT
1
I I I min I I
2
= +∆ <
Input Capacitor Selection
The input capacitor reduces the peak current drawn from
the input power supply and reduces switching noise in the
device. The total input capacitance must be equal to or
greater than the value given by the following equation to
keep the input ripple voltage within the specification and
minimize the high-frequency ripple current being fed back
to the input source:
LOAD OUT
IN SW IN_RIPPLE IN
IV
CfV V
= ×
×∆
where DVIN_RIPPLE is the maximum-allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage, fSW is
the switching frequency (1MHz), and ILOAD is the output
load. The impedance of the input capacitor at the switch-
ing frequency should be less than that of the input source
so high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor.
The input capacitor must meet the ripple current require-
ment imposed by the switching currents. The RMS input
ripple current is given by:
( )
OUT IN OUT
RIPPLE LOAD
IN
V VV
II
V

×−

=


where IRIPPLE is the input RMS ripple current.
Output Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage rating. The param-
eters affect the overall stability, output ripple voltage, and
transient response of the DC-DC converter. The output
ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
Figure 1. Peak Current-Mode Regulator Transfer Model
L
VCOMP IOUT
COMPARATOR
COMP
VCOMP
VFB
RC
ROUT
gMV
VIN
POWER MODULATOR OUTPUT FILTER
AND LOAD
NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
THE INDUCTOR, IL, INJECTED INTO THE OUTPUT LOAD, IOUT, e.g., IL = IOUT.
THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER
STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA.
*NOTE: CFF IS OPTIONAL AND DESIGNED TO EXTEND THE
REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE
MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.
ERROR AMPLIFIERFEEDBACK
DIVIDER
SLOPE
COMPENSATION
RAMP
gMC
DCR
IL
QLS
VOUT
VOUT
QHS IOUT
ESR
COUT
RLOAD
CC
REF
ROUT = 10AVEA(dB)/20/gMV
*CFF
FB
R1
R2
GMOD
PWM
CONTROL
LOGIC
C
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
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ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL as follows:
OUT OUT
OUT ESR_COUT
SW IN SW OUT
VV 1
V 1R
f L V 8f C


∆ = ×− × +


× ××


Forceramiccapacitors,ESRcontributionisnegligible:
ESR_OUT SW OUT
1
R8f C
<< ××
Fortantalumorelectrolyticcapacitors,ESRcontribution
is dominant:
ESR_OUT SW OUT
1
R8f C
>> ××
Use these equations for initial output-capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current is
a factor of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capacitors
for low ESR and low ESL at the switching frequency of
the converter. The ripple voltage due to ESL is negligible
when using ceramic capacitors.
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
instantly changes by ESR x DILOAD. Before the control-
ler can respond, the output deviates further, depending
on the inductor and output capacitor values. After a short
time, the controller responds by regulating the output volt-
age back to the predetermined value.
Use higher COUT values for applications that require light
load operation or transition between heavy load and light
load, triggering skip mode, causing output undershooting
or overshooting. When applying the load, limit the output
undershoot by sizing COUT according to the following
formula:
LOAD
OUT CO OUT
I
C3f x V
∆
≅∆
where DILOAD is the total load change, fCO is the regula-
tor unity-gain bandwidth (or zero crossover frequency),
and DVOUT is the desired output undershooting. When
removing the load and entering skip mode, the device
cannot control output overshooting, since it has no sink
current capability; see the Skip Mode Frequency and
Output Ripple section to properly size COUT.
Skip Mode Frequency and Output Ripple
In skip mode, the switching frequency (fSKIP) and output
ripple voltage (VOUT-RIPPLE)showninFigure2arecal-
culated as follows:
tON is a fixed time (300ns, typ); the peak inductor current
reached is:
IN OUT
SKIP LIMIT ON
VV
It
L
−−
= ×
Figure 2. Skip Mode Waveform
IL
VOUT
ISKIP-LIMIT
tON
ILOAD
VOUT-RIPPLE
tOFF1 tOFF2 = n × tCK
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tOFF1 is the time needed for inductor current to reach the
zero-current crossing limit (~ 0A):
SKIP LIMIT
OFF1 OUT
LI
tV
−
×
=
During tON and tOFF1, the output capacitor stores a
chargeequalto(seeFigure2):
( )
2
SKIP LIMIT LOAD IN OUT OUT
OUT
11
Lx I I x VV V
Q2
−

−+

−

∆=
During tOFF2(= n x tCK, number of clock cycles skipped),
output capacitor loses this charge:
( )
OUT
OFF2 LOAD
2
SKIP LIMIT LOAD IN OUT OUT
OFF2 LOAD
Q
tI
11
Lx I I x VV V
t2xI
−
∆
= ⇒

−+

−

=
Finally,frequencyinskipmodeis:
SKIP ON OFF1 OFF2
1
ftt t
=++
Output ripple in skip mode is:
( )
( )
( )
( )
OUT RIPPLE COUT RIPPLE ESR RIPPLE
SKIP LIMIT LOAD ON
OUT
ESR,COUT SKIP LIMIT LOAD
SKIP LIMIT
OUT RIPPLE ESR,COUT
OUT IN OUT
SKIP LIMIT LOAD
VV V
I I xt
C
R xI I
LxI
VR
C xV V
xI I
− −−
−
−
−
−
−
= +
−
=
+−

= +

−


−
To limit output ripple in skip mode, size COUT based on
the above formula. All the above calculations are appli-
cable only in skip mode.
Compensation Design Guidelines
The MAX15053 uses a fixed-frequency, peak-current-mode
control scheme to provide easy compensation and fast tran-
sient response. The inductor peak current is monitored on
a cycle-by-cycle basis and compared to the COMP voltage
(output of the voltage error amplifier). The regulator’s duty
cycle is modulated based on the inductor’s peak current
value. This cycle-by-cycle control of the inductor current
emulates a controlled current source. As a result, the induc-
tor’s pole frequency is shifted beyond the gain bandwidth of
the regulator. System stability is provided with the addition of
a simple series capacitor-resistor from COMP to GND. This
pole-zero combination serves to tailor the desired response
of the closed-loop system. The basic regulator loop consists
of a power modulator (comprising the regulator’s pulse-width
modulator, current sense and slope compensation ramps,
control circuitry, MOSFETs, and inductor), the capacitive
output filter and load, an output feedback divider, and a
voltage-loop error amplifier with its associated compensation
circuitry.SeeFigure 1.
The average current through the inductor is expressed as:
L MOD COMP
IG V= ×
where IL is the average inductor current and GMOD is the
power modulator’s transconductance.
Forabuckconverter:
OUT LOAD L
VR I= ×
where RLOAD is the equivalent load resistor value.
Combining the above two relationships, the power modu-
lator’s transfer function in terms of VOUT with respect to
VCOMP is:
OUT LOAD L LOAD MOD
COMP L
MOD
V RI
RG
VI
G
×
= = ×
The peak current-mode controller’s modulator gain is
attenuated by the equivalent divider ratio of the load
resistance and the current-loop gain’s impedance. GMOD
becomes:
( ) ( )
MOD MC LOAD S
SW
1
G DC g R
1 K 1 D 0.5
fL
= ×


+ × ×− −


×

where RLOAD = VOUT/IOUT(MAX), fSW is the switching
frequency, L is the output inductance, D is the duty cycle
(VOUT/VIN), and KS is a slope compensation factor calcu-
lated from the following equation:
( )
SLOPE SLOPE SW MC
SN IN OUT
S V f Lg
K1 1
S VV
× ××
=+=+ −
where:
SLOPE
SLOPE SLOPE SW
SW
V
S Vf
t
= = ×
( )
IN OUT
NMC
VV
SLg
−
=×
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
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As previously mentioned, the power modulator’s domi-
nant pole is a function of the parallel effects of the load
resistance and the current-loop gain’s equivalent imped-
ance:
( )
PMOD 1
S
OUT LOAD SW
1
f
K 1 D 0.5
1
2 C ESR R fL
−
=



×− −


π× × + +



×



And knowing that the ESR is typically much smaller than
the parallel combination of the load and the current loop:
( )
LOAD SW
K 1 D 0.5
ESR R fL


×− −


<< +

×

( )
PMOD 1
S
OUT LOAD SW
1
f
K 1 D 0.5
1
2C R fL
−
≈


×− −

π× × +


×

which can be expressed as:
( )
S
PMOD OUT LOAD SW OUT
K 1 D 0.5
1
f2 C R 2 f LC

×− −

≈+
π× × π× × ×
Note: Depending on the application’s specifics, the
amplitude of the slope compensation ramp could have a
significantimpactonthemodulator’sdominatepole.For
low duty-cycle applications, it provides additional damp-
ing (phase lag) at/near the crossover frequency (see the
Closing the Loop: Designing the Compensation Circuitry
section). There is no equivalent effect on the power modu-
lator zero, fZMOD.
ZMOD ZESR OUT
1
ff
2 C ESR
= = π× ×
GAIN
1ST ASYMPTOTE
R2 × (R1 + R2)-1 × 10AVEA(dB)/20 × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1
2ND ASYMPTOTE
R2 × (R1 + R2)-1 × gMV × (2GCC)-1 × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1
3RD ASYMPTOTE
R2 × (R1 + R2)-1 × gMV × (2GCC)-1 × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1 ×
(2GCOUT × {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1)-1
4TH ASYMPTOTE
R2 × (R1 + R2)-1 × gMV × RC × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1 ×
(2πCOUT × {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1)-1
5TH ASYMPTOTE
R2 × (R1 + R2)-1 × gMV × RC × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1 ×
(2GCOUT × {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1)-1 × (0.5 × fSW)2 × (2Gf)-2
6TH ASYMPTOTE
R2 × (R1 + R2)-1 × gMV × RC × gMC × RLOAD × {1 + RLOAD × [KS × (1 - D) - 0.5] × (L × fSW)-1}-1 ×
ESR × {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1 × (0.5 × fSW)2 × (2Gf)-2
UNITY
1ST POLE
[2GCC × (10AVEA(dB)/20 - gMV-1)]-1
2ND POLE
fPMOD*
3RD POLE (DBL)
0.5 × fSW
2ND ZERO
(2GCOUTESR)-1
FREQUENCY
fCO
1ST ZERO
(2GCCRC)-1
NOTE:
ROUT = 10AVEA(dB)/20 × gMV-1
fPMOD = [2GCOUT × (ESR + {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1)]-1
WHICH FOR
ESR << {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1
BECOMES
fPMOD = [2GCOUT × {RLOAD-1 + [KS × (1 - D) - 0.5] × (L × fSW)-1}-1]-1
fPMOD = (2GCOUT × RLOAD)-1 + [KS × (1 - D) - 0.5] × (2GCOUT × L × fSW)-1
Figure 3. Asymptotic Loop Response of Current-Mode Regulator
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
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The effect of the inner current loop at higher frequencies
is modeled as a double-pole (complex conjugate) fre-
quency term, GSAMPLING(s), as shown:
( )
( )
SAMPLING 2
2SW C
SW
1
Gs
ss
1
fQ
f
=
++
π× ×
π×
where the sampling effect quality factor, QC, is:
( )
CS
1
QK 1 D 0.5
=

π× × − −

And the resonant frequency is:
ωSAMPLING(s) = π × fSW
or:
SW
SAMPLING
f
f2
=
Having defined the power modulator’s transfer function,
the total system transfer can be written as follows (see
Figure3):
Gain(s) = GFF(s) × GEA(s) × GMOD(DC) × GFILTER(s) ×
GSAMPLING(s)
where:
( )
( )
( )
FF
FF FF
sC R1 1
R2
GsR1 R2 sC R1 || R2 1
+
= ×
+

+

Leaving CFF empty, GFF(s) becomes:
( )
FF
R2
GsR1 R2
=+
Also:
( )
( )
VEA
VEA
A (dB)/20 CC
EA A (dB)/20
CC MV
sC R 1
G s 10
10
sC R 1
g
+
= ×




++




which simplifies to:
( )
( )
VEA
VEA
A (dB)/20 CC
EA A (dB)/20
CMV
sC R 1
G s 10
10
sC 1
g
+
= ×




+




VEA
A (dB)/20
CMV
10
when R g
<<
( )
( )
( )
OUT
FILTER LOAD 1
S
OUT LOAD SW
sC ESR 1
G sR
K 1 D 0.5
1
sC 1
R fL
−
+
= ×



×− −



++


×




The dominant poles and zeros of the transfer loop gain
are shown below:
( )
( )
VEA
MV
P1 A (dB)/20 C
P2 S1
OUT LOAD SW
P3 SW
Z1 CC
Z2 OUT
g
f
2 10 C
1
fK 1 D 0.5
1
2C R fL
1
ff
2
1
f2 CR
1
f2 C ESR
−
=π× ×
=


×− −


π× +

×


=
=π×
=π×
The order of pole-zero occurrence is:
P1 P2 Z1 CO P3 Z2
ff ff f f< ≤< ≤ <
Under heavy load, fP2, approaches fZ1.Figure3shows
a graphical representation of the asymptotic system
closed-loop response, including dominant pole and zero
locations.
Theloopresponse’sfourthasymptote(inbold,Figure3)
is the one of interest in establishing the desired crossover
frequency (and determining the compensation component
values). A lower crossover frequency provides for stable
closed-loop operation at the expense of a slower load-
and line-transient response. Increasing the crossover
frequency improves the transient response at the (poten-
tial) cost of system instability. A standard rule of thumb
sets the crossover frequency between 1/10 and 1/5 of
theswitching frequency.First, select thepassivepower
and decoupling components that meet the application’s
requirements. Then, choose the small-signal compen-
sation components to achieve the desired closed-loop
frequency response and phase margin as outlined in the
Closing the Loop: Designing the Compensation Circuitry
section.
Closing the Loop: Designing the
Compensation Circuitry
1) Select the desired crossover frequency. Choose fCO
approximately 1/10 to 1/5 of the switching frequency
(fSW).
2) Determine RC by setting the system transfer’s fourth
asymptote gain equal to unity (assuming fCO > fZ1,
fP2, and fP1) where:
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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( )
( )
LOAD S
SW
C CO OUT
MV MC LOAD
S
LOAD SW
R K 1 D 0.5
1Lf
R1 R2
R 2f C
R2 g g R
1
ESR K 1 D 0.5
1
R Lf


−−

+


×
+

= × ×π ×
××



+



−−


+



×



and where the ESR is much smaller than the parallel
combination of the equivalent load resistance and the
current loop impedance, e.g.,:
( )
S
LOAD SW
ESR K 1 D 0.5
1
R Lf
<<

−−

+
×
RC becomes:
CO OUT
CMV MC
2f C
R1 R2
RR2 g g
+
= × ×
3) Determine CC by selecting the desired first sys-
tem zero, fZ1, based on the desired phase margin.
Typically, setting fZ1 below 1/5 of fCO provides suf-
ficient phase margin.
CO
Z1 CC
f
1
f2 CR 5
= ≤
π×
therefore:
CCO C
5
C2f R
≥π× ×
4) For low duty-cycle applications, the addition of a
phase-leading capacitor (CFF in Figure 1) helps
mitigate the phase lag of the damped half-frequency
double pole. Adding a second zero near to but below
the desired crossover frequency increases both the
closed-loop phase margin and the regulator’s unity-
gain bandwidth (crossover frequency). Select the
capacitor as follows:
( )
FF CO
1
C2 f R1 || R2
=π× ×
This guarantees the additional phase-leading zero occurs
at a frequency lower than fCO from:
PHASE_LEAD FF
1
f2 C R1
=π× ×
Using CFF the zero-pole order is adjusted as follows:
P1 P2 Z1 FF FF
CO P3 Z2
11
ff f2 C R1 2 C (R1 || R2)
f ff
< ≤< < ≈
ππ
≤<
Confirm the desired operation of CFF empirically. The
phase lead of CFF diminishes as the output voltage is
a smaller multiple of the reference voltage, e.g., below
about 1V. Do not use CFF when VOUT = VFB.
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
reducing input inrush current during startup. Size the CSS
capacitor to achieve the desired soft-start time, tSS, using:
SS SS
SS FB
It
CV
×
=
ISS, the soft-start current, is 10FA (typ) and VFB, the out-
put feedback voltage threshold, is 0.6V (typ). When using
large COUT capacitance values, the high-side current
limit can trigger during the soft-start period. To ensure the
correct soft-start time, tSS, choose CSS large enough to
satisfy:
OUT SS
SS OUT
HSCL OUT FB
VI
CC(I I ) V
×
>> × −×
IHSCL is the typicalhigh-sideMOSFETcurrent-limitvalue.
An external tracking reference with steady-state value
between 0V and VIN-1.8VcanbeappliedtoSS/REFIN.
In this case, connect an RC network from external track-
ing reference and SS/REFIN, as shown in Figure 4.
The recommended value for RSS is approximately 1kI.
RSS is needed to ensure that, during hiccup period,
SS/REFINcanbeinternallypulleddown.
WhenanexternalreferenceisconnectedtoSS/REFIN,
the soft-start must be provided externally.
Figure 4. RC Network for External Reference at SS/REFIN
CSS
RSS
VREF_EXT SS/REFIN
MAX15053
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Power Dissipation
The MAX15053 is available in a 9-bump WLP package
and can dissipate up to 1127mW at TA = +70NC. When
the die temperature exceeds +150NC, the thermal-shut-
down protection is activated (see the Thermal-Shutdown
Protection section).
Layout Procedure
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX15053 Evaluation Kit layout for optimum perfor-
mance. If deviation is necessary, follow these guidelines
for good PCB layout:
1) Connect the signal and ground planes at a single point
immediately adjacent to the GND bump of the IC.
2) Place capacitors on IN and SS/REFIN as close as
possible to the IC and the corresponding pad using
direct traces.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
4) Connect IN, LX, and GND separately to a large copper
area to help cool the IC to further improve efficiency.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors and compensation com-
ponents as close as possible to the IC.
6) Route high-speed switching nodes (such as LX) away
from sensitive analog areas(suchasFBandCOMP).
Figure 5. Application Circuit for PWM Mode Operation
LX
GND
FB
COMP
COUT
22µF
OUTPUT
1.8V AT 2A
R2
4.02kI
R1
8.06kI
RC
2.32kI
CC
3.3nF
LOUT
1µH
CFF
100pF
1.2I
1nF
RPULL
20kI
CIN
22µF
IN
PGOOD
ENENABLE
SKIP
ON
OFF
CSS
22nF
SS/REFIN
MAX15053
INPUT
2.7V TO 5.5V
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Package Information
Forthelatestpackageoutlineinformationandlandpatterns,go
to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Chip Information
PROCESS: BiCMOS
Figure 6. Application Circuit for Skip Mode Operation
Typical Operating Circuit
IN LX
OUTPUT
1.8V/2A
INPUT
2.7V TO 5.5V
GND
FB
COMP
PGOOD
EN
SKIP
SS/REFIN
ON
OFF
ENABLE
MAX15053
LX
GND
FB
COMP
COUT
22µF
OUTPUT
1.8V AT 2A
R2
4.02kI
R1
8.06kI
RC
2.32kI
CC
3.3nF
LOUT
1µH
CFF
100pF
1.2I
1nF
RPULL
20kI
CIN
22µF
IN
PGOOD
ENENABLE
SKIP
ON
OFF
CSS
22nF
SS/REFIN
MAX15053
INPUT
2.7V TO 5.5V
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
9 WLP W91E1Z+1 21-0508
Refer to
Application
Note 1891
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/10 Initial release —
1 3/11 Revised Package Information section. —
2 7/11 Changed the 1.65mm x 1.65mm, 9-bump package information to 1.5mm x 1.5mm,
9-bump package information. Inserted Typical Operating Circuit on page one. 1, 11
3 4/15 Updated Benefits and Features section 1
MAX15053 High-Efciency, 2A, Current-Mode Synchronous,
Step-Down Switching Regulator
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015MaximIntegratedProducts,Inc.│ 21
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.