LM63CIMA/NOPB - NATIONAL SEMICONDUCTOR

LM63

VDD

D+

D-

PWM

SMBCLK

SMBDAT

ALERT / TACH

GND

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

LM63 ±1°C/±3°C Accurate Remote Diode Digital Temperature Sensor with Integrated Fan

Control

Check for Samples: LM63

1FEATURES DESCRIPTION

The LM63 is a remote diode temperature sensor with

23• Accurately Senses Diode-Connected 2N3904 integrated fan control. The LM63 accurately

Transistors or Thermal Diodes On Board Large measures: (1) its own temperature and (2) the

Processors or ASICs temperature of a diode-connected transistor, such as

• Accurately Senses its Own Temperature a 2N3904, or a thermal diode commonly found on

Computer Processors, Graphics Processor Units

• Factory Trimmed for Intel®Pentium®4 and (GPU) and other ASIC's. The LM63 remote

Mobile Pentium 4 Processor-M Thermal Diodes temperature sensor's accuracy is factory trimmed for

• Integrated PWM Fan Speed Control Output the series resistance and 1.0021 non-ideality of the

• Acoustic Fan Noise Reduction With User- Intel 0.13 µm Pentium 4 and Mobile Pentium 4

Programmable 8-Step Lookup Table Processor-M thermal diode. The LM63 has an offset

• Multi-Function, User-Selectable Pin for Either ideality factors of other thermal diodes.

ALERT Output, or Tachometer Input,

Functions The LM63 also features an integrated, pulse-width-

modulated (PWM), open-drain fan control output. Fan

• Tachometer Input for Measuring Fan RPM speed is a combination of the remote temperature

• Smart-Tach Modes for Measuring RPM of Fans reading, the lookup table and the register settings.

With Pulse-Width-Modulated Power as Shown The 8-step Lookup Table enables the user to

in Typical Application program a non-linear fan speed vs. temperature

• Offset Register can Adjust for a Variety of transfer function often used to quiet acoustic fan

Thermal Diodes noise.

• 10 Bit Plus Sign Remote Diode Temperature CONNECTION DIAGRAM

Data Format, With 0.125°C Resolution

• SMBus 2.0 Compatible Interface, Supports

TIMEOUT

• LM86-Compatible Pinout

• LM86-Compatible Register Set

• 8-Pin SOIC Package

APPLICATIONS Figure 1. 8-Pin SOIC (D Package)

• Computer Processor Thermal Management

(Laptop, Desktop, Workstations, Servers)

• Graphics Processor Thermal Management

• Electronic Test Equipment

• Projectors

• Office Equipment

• Industrial Controls

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Intel, Pentium are registered trademarks of Intel Corporation.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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KEY SPECIFICATIONS

• Remote Diode Temp Accuracy (with quantization error)

Ambient Temp Diode Temp IPWML Max Version Max Error

30 to 50°C 60 to 100°C 5 mA LM63C ±1.0°C

30 to 50°C 60 to 100°C 5 mA LM63D ±3.0°C

0 to 85°C 25 to 125°C 8 mA All ±3.0°C

• Local Temp Accuracy (includes quantization error)

Ambient Temp Max Error

25°C to 125°C ±3.0°C

• Supply Voltage: 3.0 V to 3.6 V

• Supply Current: 1.3 mA (typ)

PIN DESCRIPTIONS

PIN NAME INPUT/OUTPUT FUNCTION AND CONNECTION

Connect to a low-noise +3.3 ± 0.3 VDC power supply, and bypass to GND with a

1 VDD Power Supply Input 0.1 µF ceramic capacitor in parallel with a 100 pF ceramic capacitor. A bulk

capacitance of 10 µF needs to be in the vicinity of the LM63's VDD pin.

Connect to the anode (positive side) of the remote diode. A 2.2 nF ceramic capacitor

2 D+ Analog Input must be connected between pins 2 and 3.

Connect to the cathode (negative side) of the remote diode. A 2.2 nF ceramic capacitor

3 D−Analog Input must be connected between pins 2 and 3.

Open-Drain Open-Drain Digital Output. Connect to fan drive circuitry. The power-on default for this

4 PWM Digital Output pin is low (pin 4 pulled to ground).

5 GND Ground This is the analog and digital ground return.

Depending on how the LM63 is programmed, this pin is either an open-drain ALERT

6 ALERT/TACH Digital I/O output or a tachometer input for measuring fan speed. The power-on default for this pin

is the ALERT function.

Digital Input/

7 SMBDAT This is the bi-directional SMBus data line.

Open-Drain Output

8 SMBCLK Digital Input Digital Input. This is the SMBus clock input.

Product Folder Links: LM63

Diode

Bias and

Control

Internal Diode

LM63

D+

D-

'6 ADC

2 - Wire

Serial

Interface

SMBDAT

SMBCLK

Temp Reading,

Temp Limit,

Hysteresis, and

Temp Sensor

Filter Registers

Status and Status

Mask Registers

Comparators

PWM Fan Control

Registers

PWM Fan

Control

PWM

ALERT/Tach

ALERT

Tach

Tachometer

Detection

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

SIMPLIFIED BLOCK DIAGRAM

Figure 2.

Product Folder Links: LM63

LM63

4 5

2.2 nF

+3.3 VDC from motherboard

SMBCLK

SMBDAT

PWM Output

To SMBus

interface

control

circuitry

ALERT / Tach

GND

VDD

D+

D-

PWM

Remote diode-

connected transistor

inside of an Intel®

Pentium® 4 Processor

ALERT to system

shutdown circuitry

+3.3 VDC

470

MMBT2222A

Tach. input

from Fan

Fan voltage

+12 or +5 VDC

10k

13k

0.2W

Tach In

0.1

100 pF

10 PFThese two capacitors

are close to Pin 1

DC brushless

fan module with

Tachometer

Fan V+

Fan V-

Processor

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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TYPICAL APPLICATION

Figure 3.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM63

SNP

V+

GND

ESD

Clamp

I/O

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

ABSOLUTE MAXIMUM RATINGS(1)(2)

Supply Voltage, VDD −0.3 V to 6.0 V

Voltage on SMBDAT, SMBCLK, ALERT/Tach, PWM Pins −0.5 V to 6.0 V

Voltage on Other Pins −0.3 V to (VDD + 0. 3 V)

Input Current, D−Pin ±1 mA

Input Current at All Other Pins(3) 5 mA

Package Input Current(3) 30 mA

Package Power Dissipation See(4)

SMBDAT, ALERT, PWM pins Output Sink Current 10 mA

Storage Temperature −65°C to +150°C

Human Body Model 2000 V

ESD Susceptibility(5) Machine Model 200 V

Vapor Phase (60 seconds) 215°C

Soldering Information, Lead Temperature SOIC-8 Package(6) Infrared (15 seconds) 220°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure performance limits. For ensured specifications and test conditions, see the Electrical

Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade

when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise noted.

(3) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > V+), the current at that pin should be limited to

5 mA. Parasitic components and/or ESD protection circuitry for the LM63's pins are shown in Figure 4 and Table 1. The nominal

breakdown voltage of D3 is 6.5 V. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D−. Doing

so by more than 50 mV may corrupt temperature measurements. An "X" means it exists in the circuit.

(4) Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 168°C/W.

(5) Human body model, 100 pF discharged through a 1.5 kΩresistor. Machine model, 200 pF discharged directly into each pin. See

Figure 4 and Table 1 for the ESD Protection Input Structure.

(6) See the URL http://www.ti.com/packaging for other recommendations and methods of soldering surface mount devices.

Figure 4. ESD Protection Input Structure

Table 1. ESD Protection Input Structure

PIN NAME PIN # D1 D2 D3 D4 D5 D6 R1 SNP ESD CLAMP

VDD 1 X X

D+ 2 X X X X X X

D−3 X X X X X X

PWM 4 X X X X

ALERT/Tach 6 X X X X

SMBDAT 7 X X X X

SMBCLK 8 X X

Product Folder Links: LM63

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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OPERATING RATINGS(1)(2)

Specified Temperature Range (TMIN ≤TA≤TMAX) LM63CIM, LM63DIM 0°C ≤TA≤+85°C

Remote Diode Temperature Range 0°C ≤TA≤+125°C

Supply Voltage Range (VDD) +3.0 V to +3.6 V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure performance limits. For ensured specifications and test conditions, see the Electrical

Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade

when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise noted.

DC ELECTRICAL CHARACTERISTICS

TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS

The following specifications apply for VDD = 3.0 VDC to 3.6 VDC, and all analog source impedance RS= 50Ωunless

otherwise specified in the conditions. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= +25°C. UNITS

PARAMETER CONDITIONS VERSION TYPICAL(1) LIMITS(2) (LIMITS)

TD= +60 to +100°C LM63C ±1 °C (max)

Temperature Error Using the TA= +30 to +50°C TD= Remote Diode

Remote Thermal Diode of an Intel IPWML ≤5 mA LM63D ±3 °C (max)

Junction Temperature

Pentium 4 or Mobile Pentium 4

Processor-M with typical non- TA= +0 to +85°C TD= +25 to +125°C All ±3 °C (max)

ideality of 1.0021. IPWML ≤8 mA

Temperature Error Using the Local TA= +25 to +125°C(3)(4) All ±1 ±3 °C (max)

Diode 11 Bits

Remote Diode Resolution All 0.125 °C

8 Bits

Local Diode Resolution All 1 °C

Conversion Time, All Temperatures Fastest Setting All 31.25 34.4 ms (max)

D−Source Voltage All 0.7 V

315 µA (max)

(VD+ −VD−) = +0.65 V; High Current All 160 110 µA (min)

Diode Source Current 20 µA (max)

Low Current All 13 7µA (min)

(1) “Typicals” are at TA= 25°C and represent most likely parametric norm. They are to be used as general reference values not for critical

design calculations.

(2) Limits are specified to AOQL (Average Outgoing Quality Level).

(3) Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the

internal power dissipation of the LM63 and the thermal resistance. For the thermal resistance to be used in the self-heating calculation,

see the table footnote about Thermal resistance junction-to-ambient.

(4) Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 168°C/W.

OPERATING ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS TYPICAL(1) LIMITS(2) UNITS

ALERT PWM

ALERT and PWM Output Saturation Voltage IOUT 4 mA 5 mA 0.4 V (max)

IOUT 6 mA 0.55

2.4 V (max)

Power-On-Reset Threshold Voltage 1.8 V (min)

SMBus Inactive, 16 Hz 1.1 2.0 mA (max)

Conversion Rate

Supply Current (3)

STANDBY Mode 300 µA

(1) “Typicals” are at TA= 25°C and represent most likely parametric norm. They are to be used as general reference values not for critical

design calculations.

(2) Limits are specified to AOQL (Average Outgoing Quality Level).

(3) The supply current will not increase substantially with an SMBus transaction.

Product Folder Links: LM63

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

AC ELECTRICAL CHARACTERISTICS

The following specifications apply for VDD = 3.0 VDC to 3.6 VDC, and all analog source impedance RS= 50Ωunless

otherwise specified in the conditions. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= +25°C. UNITS

SYMBOL PARAMETER CONDITIONS TYPICAL(1) LIMITS(2) (LIMIT)

TACHOMETER ACCURACY

Fan Control Accuracy ±10 % (max)

Fan Full-Scale Count 65535 (max)

Fan Counter Clock Frequency 90 kHz

Fan Count Update Frequency 1.0 Hz

FAN PWM OUTPUT

Frequency Accuracy ±10 % (max)

(1) “Typicals” are at TA= 25°C and represent most likely parametric norm. They are to be used as general reference values not for critical

design calculations.

(2) Limits are specified to AOQL (Average Outgoing Quality Level).

DIGITAL ELECTRICAL CHARACTERISTICS UNITS

SYMBOL PARAMETER CONDITIONS TYPICAL(1) LIMITS(2) (LIMIT)

VIH Logical High Input Voltage 2.1 V (min)

VIL Logical Low Input Voltage 0.8 V (max)

IIH Logical High Input Current VIN = VDD 0.005 +10 µA (max)

IIL Logical Low Input Current VIN = GND −0.005 −10 µA (max)

CIN Digital Input Capacitance 20 pF

(1) “Typicals” are at TA= 25°C and represent most likely parametric norm. They are to be used as general reference values not for critical

design calculations.

(2) Limits are specified to AOQL (Average Outgoing Quality Level).

SMBus LOGICAL ELECTRICAL CHARACTERISTICS

The following specifications apply for VDD = 3.0 VDC to 3.6 VDC, and all analog source impedance RS= 50Ωunless

otherwise specified in the conditions. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= +25°C. UNITS

SYMBOL PARAMETER CONDITIONS TYPICAL(1) LIMITS(2) (LIMIT)

SMBDAT OPEN-DRAIN OUTPUT

VOL Logic Low Level Output Voltage IOL = 4 mA 0.4 V (max)

IOH High Level Output Current VOUT = VDD 0.03 10 µA (max)

SMBDAT, SMBCLK INPUTS

VIH Logical High Input Voltage 2.1 V (min)

VIL Logical Low Input Voltage 0.8 V (max)

VHYST Logic Input Hysteresis Voltage 320 mV

(1) “Typicals” are at TA= 25°C and represent most likely parametric norm. They are to be used as general reference values not for critical

design calculations.

(2) Limits are specified to AOQL (Average Outgoing Quality Level).

Product Folder Links: LM63

VIH

VIL

SMBCLK

VIH

VIL

SMBDAT

tBUF tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT tSU;STA tSU;STO

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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SMBus DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD = +3.0 VDC to +3.6 VDC, CL(load capacitance) on output lines =

80 pF. Boldface limits apply for TA= TJ; TMIN ≤TA≤TMAX;all other limits TA= TJ= +25°C, unless otherwise noted. The

switching characteristics of the LM63 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM63. They adhere

to, but are not necessarily the same as the SMBus bus specifications. UNITS

SYMBOL PARAMETER CONDITIONS LIMITS(1) (LIMIT)

10 kHz (min)

fSMB SMBus Clock Frequency 100 kHz (max)

tLOW SMBus Clock Low Time From VIN(0) max to VIN(0) max 4.7 µs (min)

From VIN(1) min to VIN(1) min 4.0 µs (min)

tHIGH SMBus Clock High Time 50 µs (max)

tRSMBus Rise Time See (2) 1µs (max)

tFSMBus Fall Time See (3) 0.3 µs (max)

tOF Output Fall Time CL= 400 pF, IO= 3 mA 250 ns (max)

SMBData and SMBCLK Time Low for Reset of 25 ms (min)

tTIMEOUT Serial Interface. See (4).35 ms (max)

tSU:DAT Data In Setup Time to SMBCLK High 250 ns (min)

300 ns (min)

tHD:DAT Data Out Hold Time after SMBCLK Low 930 ns (max)

Hold Time after (Repeated) Start Condition. After

tHD:STA 4.0 µs (min)

this period the first clock is generated.

Stop Condition SMBCLK High to SMBDAT Low

tSU:STO 100 ns (min)

(Stop Condition Setup)

SMBus Repeated Start-Condition Setup Time,

tSU:STA 4.7 µs (min)

SMBCLK High to SMBDAT Low

SMBus Free Time between Stop and Start

tBUF 4.7 µs (min)

Conditions

(1) Limits are specified to AOQL (Average Outgoing Quality Level).

(2) The output rise time is measured from (VIL max - 0.15 V) to (VIH min + 0.15 V).

(3) The output fall time is measured from (VIH min + 0.15 V) to (VIL min - 0.15 V).

(4) Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM63’s SMBus state machine,

therefore setting SMBDAT and SMBCLK pins to a high-impedance state.

Figure 5. SMBus Timing Diagram for SMBCLK and SMBDAT Signals

Product Folder Links: LM63

0.01 0.1 1.0 10 100

CONVERSION RATE (Hz)

200

500

800

1100

1400

1700

2000

2300

2600

SUPPLY CURRENT (PA

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

FUNCTIONAL DESCRIPTION

The LM63 Remote Diode Temperature Sensor with Integrated Fan Control incorporates a ΔVBE-based

temperature sensor using a Local or Remote diode and a 10-bit plus sign ΔΣ ADC (Delta-Sigma Analog-to-Digital

Converter). The pulse-width modulated (PWM) open-drain output, with a pullup resistor, can drive a switching

transistor to modulate fan speed. When the ALERT/Tach is programmed to the Tach mode the LM63 can

measure the fan speed on the pulses from the fan’s tachometer output. The LM63 includes a smart-tach

measurement mode to accommodate the corrupted tachometer pulses when using switching transistor drive.

When the ALERT/Tach pin is programmed to the ALERT mode the ALERT open-drain output will be pulled low

when the measured temperature exceeds certain programmed limits when enabled. Details are contained in the

sections to follow.

The LM63's two-wire interface is compatible with the SMBus Specification 2.0. For more information the reader is

directed to www.smbus.org.

In the LM63 digital comparators are used to compare the measured Local Temperature (LT) to the Local High

Setpoint user-programmable temperature limit register. The measured Remote Temperature (RT) is digitally

compared to the Remote High Setpoint (RHS), the Remote Low Setpoint (RLS), and the Remote T_CRIT

Setpoint (RCS) user-programmable temperature limits. An ALERT output will occur when the measured

temperature is: (1) higher than either the High Setpoint or the T_CRIT Setpoint, or (2) lower than the Low

Setpoint. The ALERT Mask register allows the user to prevent the generation of these ALERT outputs.

The temperature hysteresis is set by the value placed in the Hysteresis Register (TH).

The LM63 may be placed in a low-power Standby mode by setting the Standby bit found in the Configuration

allow the PWM output signal to continue, or not, by programming the PWM Disable in Standby bit in the

Configuration Register.

The Local Temperature reading and setpoint data registers are 8-bits wide. The format of the 11-bit remote

temperature data is a 16-bit left justified word. Two 8-bit registers, high and low bytes, are provided for each

setpoint as well as the temperature reading. Two Remote Temperature Offset (RTO) Registers: High Byte and

Low Byte (RTOHB and RTOLB) may be used to correct the temperature readings by adding or subtracting a

fixed value based on a different non-ideality factor of the thermal diode if different from the 0.13 micron Intel

Pentium 4 or Mobile Pentium 4 Processor-M processor’s thermal diode. See the DIODE NON-IDEALITY section.

CONVERSION SEQUENCE

The LM63 takes approximately 31.25 ms to convert the Local Temperature (LT), Remote Temperature (RT), and

to update all of its registers. The Conversion Rate may be modified using the Conversion Rate Register. When

the conversion rate is modified a delay is inserted between conversions, the actual conversion time remains at

31.25 ms. Different Conversion Rates will cause the LM63 to draw different amounts of supply current as shown

in Figure 6.

Figure 6. Supply Current vs Conversion Rate

Product Folder Links: LM63

Remote High Limit

RDTS Measurement

LM63 ALERT Pin

Status Register: RTDS High

Time

Temperature

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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THE ALERT/TACH PIN AS ALERT OUTPUT

The ALERT/Tach pin is a multi-use pin. In this section, we will address the ALERT active-low open-drain output

function. When the ALERT/Tach Select bit is written as a zero in the Configuration Register the ALERT output is

selected. Also, when the ALERT Mask bit in the Configuration register is written as zero the ALERT interrupts

are enabled.

The LM63's ALERT pin is versatile and can produce three different methods of use to best serve the system

designer: (1) as a temperature comparator (2) as a temperature-based interrupt flag, and (3) as part of an

SMBus ALERT System. The three methods of use are further described in the following sections: ALERT

OUTPUT AS A TEMPERATURE COMPARATOR,ALERT OUTPUT AS AN INTERRUPT, and ALERT OUTPUT

AS AN SMBus ALERT. The ALERT and interrupt methods are different only in how the user interacts with the

LM63.

The remote temperature (RT) reading is associated with a T_CRIT Setpoint Register, and both local and remote

temperature (LT and RT) readings are associated with a HIGH setpoint register (LHS and RHS). The RT is also

associated with a LOW setpoint register (RLS). At the end of every temperature reading a digital comparison

determines whether that reading is above its HIGH or T_CRIT setpoint or below its LOW setpoint. If so, the

corresponding bit in the ALERT Status Register is set. If the ALERT mask bit is low, any bit set in the ALERT

Status Register, with the exception of Busy or Open, will cause the ALERT output to be pulled low. Any

temperature conversion that is out of the limits defined in the temperature setpoint registers will trigger an

ALERT. Additionally, the ALERT Mask Bit must be cleared to trigger an ALERT in all modes.

The three different ALERT modes will be discussed in the following sections: ALERT OUTPUT AS A

TEMPERATURE COMPARATOR,ALERT OUTPUT AS AN INTERRUPT, and ALERT OUTPUT AS AN SMBus

ALERT.

ALERT OUTPUT AS A TEMPERATURE COMPARATOR

When the LM63 is used in a system in which does not require temperature-based interrupts, the ALERT output

could be used as a temperature comparator. In this mode, once the condition that triggered the ALERT to go low

is no longer present, the ALERT is negated (Figure 7). For example, if the ALERT output was activated by the

comparison of LT > LHS, when this condition is no longer true, the ALERT will return HIGH. This mode allows

operation without software intervention, once all registers are configured during set-up. In order for the ALERT to

be used as a temperature comparator, the Comparator Mode bit in the Remote Diode Temperature Filter and

Comparator Mode Register must be asserted. This is not the power-on default state.

Figure 7. ALERT Output as Temperature Comparator Response Diagram

Product Folder Links: LM63

Remote High Limit RDTS Measurement

Time

Temperature

ALERT mask set in

response to reading of

status register by master

LM63

ALERT pin

Status Register: RTDS High

End of Temperature

conversion

LM63

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

ALERT OUTPUT AS AN INTERRUPT

The LM63's ALERT output can be implemented as a simple interrupt signal when it is used to trigger an interrupt

service routine. In such systems it is desirable for the interrupt flag to repeatedly trigger during or before the

interrupt service routine has been completed. Under this method of operation, during the read of the ALERT

Status Register the LM63 will set the ALERT Mask bit in the Configuration Register if any bit in the ALERT

Status Register is set, with the exception of Busy and Open. This prevents further ALERT triggering until the

master has reset the ALERT Mask bit, at the end of the interrupt service routine. The ALERT Status Register bits

are cleared only upon a read command from the master (see Figure 8 ) and will be re-asserted at the end of the

next conversion if the triggering condition(s) persist(s). In order for the ALERT to be used as a dedicated

interrupt signal, the Comparator Mode bit in the Remote Diode Temperature Filter and Comparator Mode

system that uses the ALERT output pin as an interrupt flag:

1. Master senses ALERT low.

2. Master reads the LM63 ALERT Status Register to determine what caused the ALERT.

3. LM63 clears ALERT Status Register, resets the ALERT HIGH and sets the ALERT Mask bit in the

Configuration Register.

4. Master attends to conditions that caused the ALERT to be triggered. The fan is started, setpoint limits are

adjusted, etc.

5. Master resets the ALERT Mask bit in the Configuration Register.

Figure 8. ALERT Output as an Interrupt Temperature Response Diagram

ALERT OUTPUT AS AN SMBus ALERT

An SMBus alert line is created when the ALERT output is connected to: (1) one or more ALERT outputs of other

SMBus compatible devices, and (2) to a master. Under this implementation, the LM63's ALERT should be

operated using the ARA (Alert Response Address) protocol. The SMBus 2.0 ARA protocol, defined in the SMBus

specification 2.0, is a procedure designed to assist the master in determining which part generated an interrupt

and to service that interrupt.

The SMBus alert line is connected to the open-drain ports of all devices on the bus, thereby AND'ing them

together. The ARA method allows the SMBus master, with one command, to identify which part is pulling the

SMBus alert line LOW. It also prevents the part from pulling the line LOW again for the same triggering condition.

When an ARA command is received by all devices on the bus, the devices pulling the SMBus alert line LOW:

(1) send their address to the master and (2) release the SMBus alert line after acknowledgement of their

address.

The SMBus Specifications 1.1 and 2.0 state that in response to and ARA (Alert Response Address) “after

acknowledging the slave address the device must disengage its ALERT pulldown”. Furthermore, “if the host still

sees ALERT low when the message transfer is complete, it knows to read the ARA again.” This SMBus

“disengaging ALERT requirement prevents locking up the SMBus alert line. Competitive parts may address the

“disengaging of ALERT” differently than the LM63 or not at all. SMBus systems that implement the ARA protocol

as suggested for the LM63 will be fully compatible with all competitive parts.

Product Folder Links: LM63

Remote High Limit

RDTS Measurement

Time

Temperature

ALERT mask set in

response to ARA

from master

LM63

ALERT Pin

Status Register: Remote High

LM63

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The LM63 fulfills “disengaging of ALERT” by setting the ALERT Mask Bit in the Configuration Register after

sending out its address in response to an ARA and releasing the ALERT output pin. Once the ALERT Mask bit is

activated, the ALERT output pin will be disabled until enabled by software. In order to enable the ALERT the

master must read the ALERT Status Register, during the interrupt service routine and then reset the ALERT

Mask bit in the Configuration Register to 0 at the end of the interrupt service routine.

The following sequence describes the ARA response protocol.

1. Master senses SMBus alert line low

2. Master sends a START followed by the Alert Response Address (ARA) with a Read Command.

3. Alerting Device(s) send ACK.

4. Alerting Device(s) send their address. While transmitting their address, alerting devices sense whether their

address has been transmitted correctly. (The LM63 will reset its ALERT output and set the ALERT Mask bit

once its complete address has been transmitted successfully.)

5. Master/slave NoACK

6. Master sends STOP

7. Master attends to conditions that caused the ALERT to be triggered. The ALERT Status Register is read and

fan started, setpoints adjusted, etc.

8. Master resets the ALERT Mask bit in the Configuration Register.

The ARA, 000 1100, is a general call address. No device should ever be assigned to this address.

The ALERT Configuration bit in the Remote Diode Temperature Filter and Comparator Mode Register must be

set low in order for the LM63 to respond to the ARA command.

The ALERT output can be disabled by setting the ALERT Mask bit in the Configuration Register. The power-on

default is to have the ALERT Mask bit and the ALERT Configuration bit low.

Figure 9. ALERT Output as an SMBus ALERT Temperature Response Diagram

SMBus INTERFACE

Since the LM63 operates as a slave on the SMBus the SMBCLK line is an input and the SMBDAT line is bi-

directional. The LM63 never drives the SMBCLK line and it does not support clock stretching. According to

SMBus specifications, the LM63 has a 7-bit slave address. All bits, A6 through A0, are internally programmed

and cannot be changed by software or hardware.

The complete slave address is:

A6 A5 A4 A3 A2 A1 A0

1001100

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POWER-ON RESET (POR) DEFAULT STATES

For information on the POR default states, see REGISTER MAP IN FUNCTIONAL ORDER.

TEMPERATURE DATA FORMAT

Temperature data can only be read from the Local and Remote Temperature registers. The High, Low and

T_CRIT setpoint registers are Read/Write.

Remote temperature data is represented by an 11-bit, two's complement word with a Least Significant Bit (LSB)

equal to 0.125°C. The data format is a left justified 16-bit word available in two 8-bit registers:

DIGITAL OUTPUT

TEMPERATURE BINARY HEX

+125°C 0111 1101 0000 0000 7D00

+25°C 0001 1001 0000 0000 1900

+1°C 0000 0001 0000 0000 0100

+0.125°C 0000 0000 0010 0000 0020

0°C 0000 0000 0000 0000 0000

−0.125°C 1111 1111 1110 0000 FFE0

−1°C 1111 1111 0000 0000 FF00

−25°C 1110 0111 0000 0000 E700

−55°C 1100 1001 0000 0000 C900

Local Temperature data is represented by an 8-bit, two's complement byte with an LSB equal to 1°C:

DIGITAL OUTPUT

TEMPERATURE BINARY HEX

+125°C 0111 1101 7D

+25°C 0001 1001 19

+1°C 0000 0001 01

0°C 0000 0000 00

−1°C 1111 1111 FF

−25°C 1110 0111 E7

−55°C 1100 1001 C9

OPEN-DRAIN OUTPUTS

The SMBDAT, ALERT, and PWM outputs are open-drain outputs and do not have internal pullups. A “High” level

will not be observed on these pins until pullup current is provided by an internal source, typically through a pullup

resistor. Choice of resistor value depends on several factors but, in general, the value should be as high as

possible consistent with reliable operation. This will lower the power dissipation of the LM63 and avoid

temperature errors caused by self-heating of the device. The maximum value of the pullup resistor to provide the

2.1 V high level is 88.7 kΩ.

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DIODE FAULT DETECTION

The LM63 can detect fault conditions caused by the remote diode. If the D+ pin is detected to be shorted to VDD,

or open: (1) the Remote Temperature High Byte (RTHB) register is loaded with 127°C, (2) the Remote

Temperature Low Byte (RTLB) register is loaded with 0, and (3) the OPEN bit (D2) in the status register is set.

Therefore, if the Remote T_CRIT setpoint register (RCS): (1) is set to a value less than +127°C and (2) the

ALERT Mask is disabled, then the ALERT output pin will be pulled low. If the Remote High Setpoint High Byte

(RHSHB) is set to a value less than +127°C and (2) the ALERT Mask is disabled, then the ALERT will be pulled

low. The OPEN bit by itself will not trigger an ALERT.

If the D+ pin is shorted to either ground or D−, then the Remote Temperature High Byte (RTHB) register is

loaded with −128°C (1000 0000) and the OPEN bit in the ALERT Status Register will not be set. A temperature

reading of −128°C indicates that D+ is shorted to either ground or D-. If the value in the Remote Low Setpoint

High Byte (RLSHB) Register is more than −128°C and the ALERT Mask is Disabled, ALERT will be pulled low.

COMMUNICATING WITH THE LM63

Each data register in the LM63 falls into one of four types of user accessibility:

1. Read Only

2. Write Only

3. Read/Write same address

4. Read/Write different address

A Write to the LM63 is comprised of an address byte and a command byte. A write to any register requires one

data byte.

Reading the LM63 Registers can take place after the requisite register setup sequence takes place. See

REQUIRED INITIAL FAN CONTROL REGISTER SEQUENCE.

The data byte has the Most Significant Bit (MSB) first. At the end of a read, the LM63 can accept either

Acknowledge or No-Acknowledge from the Master. Note that the No-Acknowledge is typically used as a signal

for the slave indicating that the Master has read its last byte.

DIGITAL FILTER

The LM63 incorporates a user-configured digital filter to suppress erroneous Remote Temperature readings due

to noise. The filter is accessed in the Remote Diode Temperature Filter and Comparator Mode Register. The

filter can be set according to Table 2.

Level 2 is maximum filtering.

Table 2. Digital Filter Selection Table

D2 D1 FILTER

0 0 No Filter

0 1 Level 1

1 0 Level 1

1 1 Level 2

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0 50 100 150 200

SAMPLE NUMBER

TEMPERATURE (oC)

LM63

with

Filter On

LM63

with

Filter Off

0 5 10 15 20 25

TEMPERATURE (°C)

NUMBER OF SAMPLES

No Filter

Filter Level 1

Filter Level 2

0 5 10 15 20 25

TEMPERATURE (°C)

NUMBER OF SAMPLES

No Filter

Filter Level 1

Filter Level 2

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Figure 10. Step Response of the Digital Filter

Figure 11. Impulse Response of the Digital Filter

Figure 12. Digital Filter Response in an Intel Pentium 4 processor System. The Filter on and off curves

were purposely offset to better show noise performance.

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TEMPERATURE

nn+1 n+2 n+3 n+4 n+5

SAMPLE NUMBER

RDTS Measurement

Status Register: RTDS High

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FAULT QUEUE

The LM63 incorporates a Fault Queue to suppress erroneous ALERT triggering. The Fault Queue prevents false

triggering by requiring three consecutive out-of-limit HIGH, LOW, or T_CRIT temperature readings. See

Figure 13. The Fault Queue defaults to OFF upon power-up and may be activated by setting the RDTS Fault

Queue bit in the Configuration Register to a 1.

Figure 13. Fault Queue Temperature Response Diagram

ONE-SHOT REGISTER

The One-Shot Register is used to initiate a single conversion and comparison cycle when the device is in

standby mode, after which the data returns to standby. This is not a data register. A write operation causes the

one-shot conversion. The data written to this address is irrelevant and is not stored. A zero will always be read

from this register.

SERIAL INTERFACE RESET

In the event that the SMBus Master is reset while the LM63 is transmitting on the SMBDAT line, the LM63 must

be returned to a known state in the communication protocol. This may be done in one of two ways:

1. When SMBDAT is Low, the LM63 SMBus state machine resets to the SMBus idle state if either SMBData or

SMBCLK are held Low for more than 35 ms (tTIMEOUT). All devices are to timeout when either the SMBCLK or

SMBDAT lines are held Low for 25 ms – 35 ms. Therefore, to insure a timeout of all devices on the bus,

either the SMBCLK or the SMBData line must be held Low for at least 35 ms.

2. With both SMBDAT and SMBCLK High, the master can initiate an SMBus start condition with a High to Low

transition on the SMBDAT line. The LM63 will respond properly to an SMBus start condition at any point

during the communication. After the start the LM63 will expect an SMBus Address address byte.

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LM63 REGISTERS

This section includes the following subsections: REGISTER MAP IN HEXADECIMAL ORDER, which shows a

summary of all registers and their bit assignments; REGISTER MAP IN FUNCTIONAL ORDER; and REGISTER

DESCRIPTIONS IN FUNCTIONAL ORDER, which provides a detailed explanation of each register. Do not

address the unused or manufacturer’s test registers.

Table 3 is a Register Map grouped in hexadecimal address order. Some address locations have been left blank

to maintain compatibility with LM86. Addresses in parenthesis are mirrors of “Same As” address for backwards

compatibility with some older software. Reading or writing either address will access the same 8-bit register.

Table 3. Register Map Grouped in Hexadecimal Address Order

DATA BITS

0x[HEX] NAME D7 D6 D5 D4 D3 D2 D1 D0

00 Local LT7 LT6 LT5 LT4 LT3 LT2 LT1 LT0

Temperature

01 Rmt Temp MSB RTHB± RTHB14 RTHB13 RTHB12 RTHB11 RTHB10 RTHB9 RTHB8

02 ALERT Status BUSY LHIGH 0 RHIGH RLOW RDFA RCRIT TACH

03 Configuration ALTMSK STBY PWMDIS 0 0 ALT/TCH TCRITOV FLTQUE

04 Conversion 0 0 0 0 CONV3 CONV2 CONV1 CONV0

Rate

05 Local High LHS7 LHS6 LHS5 LHS4 LHS3 LHS2 LHS1 LHS0

Setpoint

06 [Reserved] Not Used

07 Rmt High RHSHB15 RHSHB14 RHHBS13 RHSHB12 RHSHB11 RHSHB10 RHSHB9 RHSHB8

Setpoint MSB

08 Rmt Low RLSHB15 RLSHB14 RLSHB13 RLSHB12 RLHBS11 RLSHB10 RLSHB9 RLSHB8

Setpoint MSB

(09) Same as 03

(0A) Same as 04

(0B) Same as 05

0C [Reserved] Not Used

(0D) Same as 07

(0E) Same as 08

0F One Shot Write Only. Write command triggers one temperature conversion cycle.

10 Rmt Temp LSB RTLB7 RTLB6 RTLB5 0 0 0 0 0

11 Rmt Temp RTOHB15 RTOHB14 RTOHB13 RTOHB12 RTOHB11 RTOHB10 RTOHB9 RTOHB8

Offset MSB

12 Rmt Temp RTOLB7 RTOLB6 RTOLB5 0 0 0 0 0

Offset LSB

13 Rmt High RHSLB7 RHSLB6 RHSLB5 0 0 0 0 0

Setpoint LSB

14 Rmt Low RLSLB7 RLSLB6 RLSLB5 0 0 0 0 0

Setpoint LSB

15 [Reserved] Not Used

16 ALERT Mask 1 ALTMSK6 1 ALTMSK4 ALTMSK3 1 ALTMSK1 ALTMSK0

17 [Reserved] Not Used

18 [Reserved] Not Used

19 Rmt TCRIT RCS7 RCS6 RCS5 RCS4 RCS3 RCS2 RCS1 RCS0

Setpoint

1A–1F [Reserved] Not Used

20 [Reserved] Not Used

21 Rmt TCRIT RTH7 RTH6 RTH5 RTH4 RTH3 RTH2 RTH1 RTH0

Hysteresis

22–2F [Reserved] Not Used

30–3F [Reserved] Not Used

40–45 [Reserved] Not Used

46 Tach Count LSB TCLB5 TCLB4 TCLB3 TCLB2 TCLB1 TCLB0 TEDGE1 TEDGE0

47 Tach Count TCHB13 TCHB12 TCHB11 TCHB10 TCHB9 TCHB8 TCHB7 TCHB6

MSB

48 Tach Limit LSB TLLB7 TLLB6 TLLB5 TLLB4 TLLB3 TLLB2 Not Used Not Used

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Table 3. Register Map Grouped in Hexadecimal Address Order (continued)

DATA BITS

0x[HEX] NAME D7 D6 D5 D4 D3 D2 D1 D0

49 Tach Limit MSB TLHB15 TLHB14 TLHB13 TLHB12 TLHB11 TLHB10 TLHB9 TLHB8

4A PWM and RPM 0 0 PWPGM PWOUT± PWCKSL 0 TACH1 TACH0

4B Fan Spin-Up 0 0 SPINUP SPNDTY1 SPNDTY0 SPNUPT2 SPNUPT1 SPNUPT0

Config

4C PWM Value 0 0 PWVAL5 PWVAL4 PWVAL3 PWVAL2 PWVAL1 PWVAL0

4D PWM 0 0 0 PWMF4 PWMF3 PWMF2 PWMF1 PWMF0

Frequency

4E [Reserved] Not Used

4F Lookup Table 0 0 0 LOOKH4 LOOKH3 LOOKH2 LOOKH1 LOOKH0

Hystersis

50–5F Lookup Table Lookup Table of up to 8 PWM and Temp Pairs in 8-bit Registers

60–BE [Reserved] Not Used

BF Rmt Diode 0 0 0 0 0 RDTF1 RDTF0 ALTCOMP

Temp Filter

C0–FD [Reserved] Not Used

FE Manufacturer’s 0 0 0 0 0 0 0 1

FF Stepping/Die 0 1 0 0 0 0 0 1

Rev. ID

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Table 4 is a Register Map grouped in Functional Order. Some address locations have been left blank to maintain

compatibility with LM86. Addresses in parenthesis are mirrors of named address. Reading or writing either

address will access the same 8-bit register. The Fan Control and Configuration Registers are listed first, as there

is a required order to setup these registers first and then setup the others (see REQUIRED INITIAL FAN

CONTROL REGISTER SEQUENCE). The detailed explanations of each register will follow the order shown in

Table 4.

Note: POR = Power-On-Reset.

Table 4. Register Map Grouped in Functional Order

[HEX] [HEX]

FAN CONTROL REGISTERS

4A PWM and RPM R/W 20

4B Fan Spin-Up Configuration R/W 3F

4D PWM Frequency R/W 17

Read Only

4C PWM Value 00

(R/W if Override Bit is Set)

50–5F Lookup Table R/W See Table

4F Lookup Table Hysteresis R/W 04

CONFIGURATION REGISTER

03 (09) Configuration R/W 00

TACHOMETER COUNT AND LIMIT REGISTERS

46 Tach Count LSB Read Only N/A

47 Tach Count MSB Read Only N/A

48 Tach Limit LSB R/W FF

49 Tach Limit MSB R/W FF

LOCAL TEMPERATURE AND LOCAL SETPOINT REGISTERS

00 Local Temperature Read Only N/A

05 (0B) Local High Setpoint R/W 46 (70°)

REMOTE DIODE TEMPERATURE AND SETPOINT REGISTERS

01 Remote Temperature MSB Read Only N/A

10 Remote Temperature LSB Read Only N/A

11 Remote Temperature Offset MSB R/W 00

12 Remote Temperature Offset LSB R/W 00

07 (0D) Remote High Setpoint MSB R/W 46 (70°C)

13 Remote High Setpoint LSB R/W 00

08 (0E) Remote Low Setpoint MSB R/W 00 (0°C)

14 Remote Low Setpoint LSB R/W 00

19 Remote TCRIT Setpoint R/W 55 (85°C)

21 Remote TCRIT Hys R/W 0A (10°C)

BF Remote Diode Temperature Filter R/W 00

CONVERSION AND ONE-SHOT REGISTERS

04 (0A) Conversion Rate R/W 08

0F One-Shot Write Only N/A

ALERT STATUS AND MASK REGISTERS

02 ALERT Status Read Only N/A

16 ALERT Mask R/W A4

ID AND TEST REGISTERS

FF Stepping/Die Rev. ID Read Only 41

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Table 4. Register Map Grouped in Functional Order (continued)

[HEX] [HEX]

[RESERVED] REGISTERS—NOT USED

06 Not Used N/A N/A

0C Not Used N/A N/A

15 Not Used N/A N/A

17 Not Used N/A N/A

18 Not Used N/A N/A

1A–1F Not Used N/A N/A

20 Not Used N/A N/A

22–2F Not Used N/A N/A

30–3F Not Used N/A N/A

40–45 Not Used N/A N/A

4E Not Used N/A N/A

60–BE Not Used N/A N/A

C0–FD Not Used N/A N/A

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The REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER section shows a Register Map grouped in functional

order. Some address locations have been left blank to maintain compatibility with LM86. Addresses in

parenthesis are mirrors of named address for backwards compatibility with some older software. Reading or

writing either address will access the same 8-bit register.

Table 5. Fan Control Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

4AHEX FAN PWM AND TACHOMETER CONFIGURATION REGISTER

7:6 00 These bits are unused and always set to 0.

0: the PWM Value (register 4C) and the Lookup Table (50–5F) are read-

only. The PWM value (0 to 100%) is determined by the current remote

diode temperature and the Lookup Table, and can be read from the

PWM PWM value register.

Program

5 1 1: the PWM value (register 4C) and the Lookup Table (Register 50–5F)

are read/write enabled. Writing the PWM Value register will set the PWM

output. This is also the state during which the Lookup Table can be

written.

PWM 0: the PWM output pin will be 0 V for fan OFF and open for fan ON.

4 0 Output 1: the PWM output pin will be open for fan OFF and 0 V for fan ON.

Polarity

PWM Clock if 0, the master PWM clock is 360 kHz

3 0

4A R/W Select if 1, the master PWM clock is 1.4 kHz.

2 0 [Reserved] Always write 0 to this bit.

00: Traditional tach input monitor, false readings when under minimum

detectable RPM.

01: Traditional tach input monitor, FFFF reading when under minimum

detectable RPM.

10: Most accurate readings, FFFF reading when under minimum

Tachometer detectable RPM. Smart-tach mode enabled. Use with direct PWM drive

1:0 00 Mode of fan power.

11: Least effort on programmed PWM of fan, FFFF reading when under

minimum detectable RPM. Smart-tach mode enabled. Use with direct

PWM drive of fan power.

Note: If the PWM Clock is 360 kHz, mode 00 is used regardless of the

setting of these two bits.

4BHEX FAN PWM AND TACHOMETER CONFIGURATION REGISTER

7:6 0 These bits are unused and always set to 0

If 0, the fan spin-up uses the duty cycle and spin-up time, bits 0–4.

If 1, the LM63 sets the PWM output to 100% until the spin-up times out

(per bits 0–2) or the minimum desired RPM has been reached (per the

Fast Tachometer Setpoint setting) using the tachometer input, whichever

Tachometer

5 1 happens first. This bit overrides the PWM Spin-Up Duty Cycle register

Spin-Up (bits 4:3)—PWM output is always 100%. Register x03, bit 2 = 1 for

Tachometer mode.

If PWM Spin-Up Time (bits 2:0) = 000, the Spin-Up cycle is bypassed,

regardless of the state of this bit.

00: Spin-Up cycle bypassed (no Spin-Up), unless Fast Tachometer

Terminated Spin-Up (bit 5) is set.

4B R/W PWM 01: 50%

4:3 11 Spin-Up 10: 75%–81% Depends on PWM Frequency. See the APPLICATION

Duty Cycle NOTES section at the end of this datasheet.

11: 100%

000: Spin-Up cycle bypassed (No Spin-Up)

001: 0.05 seconds

010: 0.1 s

PWM 011: 0.2 s

2:0 111 Spin-Up 100: 0.4 s

Time 101: 0.8 s

110: 1.6 s

111: 3.2 s

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Table 5. Fan Control Registers (continued)

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

4DHEX FAN PWM FREQUENCY REGISTER

7:5 000 These bits are unused and always set to 0

The PWM Frequency = PWM_Clock / 2n, where PWM_Clock = 360 kHz

PWM or 1.4 kHz (per the PWM Clock Select bit in Register 4A), and n = value

4D R/W Frequency of the register.

4:0 10111 Note: n = 0 is mapped to n = 1. See the APPLICATION NOTES section

at the end of this datasheet.

4CHEX PWM VALUE REGISTER

7:6 00 These bits are unused and always set to 0

If PWM Program (register 4A, bit 5) = 0 this register is read only and

reflects the LM63’s current PWM value from the Lookup Table.

Read If PWM Program (register 4A, bit 5) = 1, this register is read/write and the

(Write only PWM

4C desired PWM value is written directly to this register, instead of from the

if reg 4A Value

5:0 000000 Lookup Table, for direct fan speed control.

bit 5 = 1.) This register will read 0 during the Spin-Up cycle.

See the APPLICATION NOTES section at the end of this datasheet for

more information regarding the PWM Value and Duty Cycle in %.

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Table 5. Fan Control Registers (continued)

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

50HEX to 5FHEX LOOKUP TABLE (7 Bits for Temperature and 6 Bits for PWM for each Temperature/PWM Pair)

7 0 This bit is unused and always set to 0.

Lookup Table

50 Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 1 be the value in Register 51.

7:6 00 These bits are unused and always set to 0.

Lookup Table

51 PWM Entry 1

5:0 0x3F The PWM value corresponding to the temperature limit in register 50.

7 0 This bit is unused and always set to 0.

Lookup Table

52 Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 2 be the value in Register 53.

7:6 00 These bits are unused and always set to 0.

Lookup Table

53 PWM Entry 2

5:0 0x3F The PWM value corresponding to the temperature limit in register 52.

7 0 This bit is unused and always set to 0.

Lookup Table

54 Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 3 be the value in Register 55.

7:6 00 These bits are unused and always set to 0.

Lookup Table

55 PWM Entry 3

5:0 0x3F The PWM value corresponding to the temperature limit in register 54.

7 0 This bit is unused and always set to 0.

Lookup Table

56 Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 4 be the value in Register 57.

7:6 00 These bits are unused and always set to 0.

Lookup Table

Read.

57 PWM Entry 4

5:0 0x3F The PWM value corresponding to the temperature limit in register 56.

(Write only

if reg 4A 7 0 This bit is unused and always set to 0.

Lookup Table

bit 5 = 1.)

58 Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 5 be the value in Register 59.

7:6 00 These bits are unused and always set to 0.

Lookup Table

59 PWM Entry 5

5:0 0x3F The PWM value corresponding to the temperature limit in register 58.

7 0 This bit is unused and always set to 0.

Lookup Table

5A Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 6 be the value in Register 5B.

7:6 00 These bits are unused and always set to 0.

Lookup Table

5B PWM Entry 6

5:0 0x3F The PWM value corresponding to the temperature limit in register 5A.

7 0 This bit is unused and always set to 0.

Lookup Table

5C Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 7 be the value in Register 5D.

7:6 00 These bits are unused and always set to 0.

Lookup Table

5D PWM Entry 7

5:0 0x3F The PWM value corresponding to the temperature limit in register 5C.

7 0 This bit is unused and always set to 0.

Lookup Table

5E Temperature If the remote diode temperature exceeds this value, the PWM output will

6:0 0x7F Entry 8 be the value in Register 5F.

7:6 00 These bits are unused and always set to 0.

Lookup Table

5F PWM Entry 8

5:0 0x3F The PWM value corresponding to the temperature limit in register 5E.

4FHEX LOOKUP TABLE HYSTERESIS

7:5 000 Lookup These bits are unused and always set to 0

4F R/W Table

4:0 00100 The amount of hysteresis applied to the Lookup Table. (1 LSB = 1°C).

Hysteresis

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Table 6. Configuration Register

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

03 (09)HEX CONFIGURATION REGISTER

When this bit is a 0, ALERT interrupts are enabled.

ALERT

7 0 When this bit is set to a 1, ALERT interrupts are masked, and the

Mask ALERT pin is always in a high-impedance (open) state.

When this bit is a 0, the LM63 is in operational mode, converting,

comparing, and updating the PWM output continuously.

When this bit is a 1, the LM63 enters a low-power standby mode.

6 0 STANDBY In STANDBY, continuous conversions are stopped, but a

conversion/comparison cycle may be initiated by writing any value to

on the setting of bit 5 in this register.

When this bit is a 0, the LM63’s PWM output continues to output the

PWM Disable current fan control signal while in STANDBY.

5 0 in STANDBY When this bit is a 1, the PWM output is disabled (as defined by the

PWM polarity bit) while in STANDBY.

4:3 00 These bits are unused and always set to 0.

When this bit is a 0, the ALERT/Tach pin is an open drain ALERT

03 (09) R/W output.

ALERT/Tach When this bit is a 1, the ALERT/Tach pin is a high-impedance

2 0 Select Tachometer input.

Note that if this bit is set, the function of the ALERT/Tach pin must be

Tach input, so an external ALERT condition will not occur.

The T_CRIT limit for the remote diode is nominally 85°C. This value

can be changed once after power-up by first setting this bit to a 1,

T_CRIT Limit

1 0 then programming a new T_CRIT value into the Remote Diode

Override T_CRIT Limit (register 0x19). The T_CRIT value can not be changed

again except by cycling power to the LM63.

0: an ALERT will be generated if any Remote Diode conversion result

is above the Remote High Set Point or below the Remote Low

RDTS Fault Setpoint.

0 0 Queue 1: an ALERT will be generated only if three consecutive Remote

Diode conversions are above the Remote High Set Point or below

the Remote Low Setpoint.

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Table 7. Tachometer Count And Limit Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

47HEX TACHOMETER COUNT (MSB) and 46HEX TACHOMETER COUNT (LSB) REGISTERS (16 bits: Read LSB first to lock MSB and

ensure MSB and LSB are from the same reading)

Tachometer These registers contain the current 16-bit Tachometer

47 Read Only 7:0 N/A Count (MSB) Count, representing the period of time between tach pulses.

Note that the 16-bit tachometer MSB and LSB are reversed

Tachometer

Read Only 7:2 N/A from the 16-bit temperature readings.

Count (LSB)

Bits Edges Used Tach_Count_Multiple

00: Reserved - do not use

01: 2 4

Tachometer 10: 3 2

46 Read Only 1:0 00 Edge Count 11: 5 1

Note: If PWM_Clock_Select = 360 kHz, then

Tach_Count_Multiple = 1 regardless of the setting of these

bits.

49HEX TACHOMETER LIMIT (MSB) and 48HEX TACHOMETER LIMIT (LSB) REGISTERS

Tachometer These registers contain the current 16-bit Tachometer

49 R/W 7:0 0xFF Limit MSB) Count, representing the period of time between tach pulses.

Fan RPM = (f * 5,400,000) / (Tachometer Count), where f =

1 for 2 pulses/rev fan; f = 2 for 1 pulse/rev fan; and f = 2/3

for 3 pulses/rev fan. See the APPLICATION NOTES section

Tachometer

R/W 7:2 0xFF at the end of this datasheet for more tachometer

Limit (LSB)

48 information. Note that the 16-bit tachometer MSB and LSB

are reversed from the 16 bit temperature readings.

R/W 1:0 [Reserved] Not Used.

Table 8. Local Temperature And Local High Setpoint Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

00HEX LOCAL TEMPERATURE REGISTER (8-bits)

Local Temperature

00 Read Only 7:0 N/A 8-bit integer representing the temperature of the LM63 die.

Reading (8-bit)

05 (0B)HEX LOCAL HIGH SETPOINT REGISTER (8-bits)

05 R/W 7:0 0x46 (70°) Local HIGH Setpoint High Setpoint for the internal diode.

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Table 9. Remote Diode Temperature, Offset And Setpoint Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

This is the MSB of the 2’s complement value, representing the

Remote Diode temperature of the remote diode connected to the LM63. Bit 7 is the

01 Read Only 7:0 N/A Temperature sign bit, bit 6 has a weight of 0x40 (64°), and bit 0 has a weight of 1°C.

Reading (MSB) This byte to be read first. The LM63C and LM63D will report the actual

thermal diode temperature.

This is the LSB of the 2’s complement value, representing the

temperature of the remote diode connected to the LM63. Bit 7 has a

Remote Diode

7:5 N/A weight 0.5°C, bit 6 has a weight of 0.25°C, and bit 5 has a weight of

10 Read Only Temperature 0.125°C.

Reading (MSB)

4:0 00 Always 00.

Remote These registers contain the value added to or subtracted from the

11 R/W 7:5 00 Temperature remote diode’s reading to compensate for the different non-ideality

OFFSET (MSB) factors of different processors, diodes, etc. The 2’s complement value,

in these registers is added to the output of the LM63’s ADC to form the

Remote

7:5 00 temperature reading contained in registers 01 and 10.

12 R/W Temperature

4:0 00 OFFSET (LSB) Always 00.

0x46 Remote HIGH

07 (0D) R/W 7:0 High setpoint temperature for remote diode. Same format as Remote

(70°C) Setpoint (MSB) Temperature Reading (registers 01 and 10).

7:5 00 Remote HIGH

13 R/W Setpoint (LSB)

4:0 00 Always 00.

00 Remote LOW

08 (0E) R/W 7:0 Low setpoint temperature for remote diode. Same format as Remote

(0°C) Setpoint (MSB) Temperature Reading (registers 01 and 10).

7:5 00 Remote LOW

14 R/W Setpoint (LSB)

4:0 00 Always 00.

This 8-bit integer storing the T_CRIT limit is nominally 85°C. This value

can be changed once after power-up by setting T_CRIT Limit Override

0x55 Remote Diode

19 R/W 7:0 (bit 1) in the Configuration register to a 1, then programming a new

(85°C) T_CRIT Limit T_CRIT value into this register. The T_CRIT Limit can not be changed

again except by cycling power to the LM63.

Remote Diode 8-bit integer storing T_CRIT hysteresis. T_CRIT stays activated until

0x0A

21 R/W 7:0 T_CRIT the remote diode temperature goes below [(T_CRIT Limit)—(T_CRIT

(10°C) Hysteresis Hysteresis)].

7:3 00000 These bits are unused and should always set to 0.

00: Filter Disabled

Remote Diode 01: Filter Level 1 (minimal filtering, same as 10)

2:1 00 Temperature 10: Filter Level 1 (minimal filtering, same as 01)

Filter

BF R/W 11: Filter Level 2 (maximum filtering)

0: the ALERT/Tach pin functions normally.

Comparator 1: the ALERTTach pin behaves as a comparator, asserting itself when

0 0 Mode an ALERT condition exists, de-asserting itself when the ALERT

condition goes away.

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Table 10. ALERT Status and Mask Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

02HEX ALERT STATUS REGISTER (8-bits) (All Alarms are latched until read, then cleared if alarm condition was removed at the

time of the read.)

When this bit is a 0, the ADC is not converting.

7 0 Busy When this bit is set to a 1, the ADC is performing a conversion. This bit

does not affect ALERT status.

When this bit is a 0, the internal temperature of the LM63 is at or below

Local the Local High Setpoint.

6 0 High Alarm When this bit is a 1, the internal temperature of the LM63 is above the

Local High Setpoint, and an ALERT is triggered.

5 0 This bit is unused and always read as 0.

When this bit is a 0, the temperature of the Remote Diode is at or

Remote below the Remote High Setpoint.

4 0 High Alarm When this bit is a 1, the temperature of the Remote Diode is above the

Remote High Setpoint, and an ALERT is triggered.

When this bit is a 0, the temperature of the Remote Diode is at or

Remote above the Remote Low Setpoint.

3 0 Low Alarm When this bit is a 1, the temperature of the Remote Diode is below the

Remote Low Setpoint, and an ALERT is triggered.

0x02 Read Only When this bit is a 0, the Remote Diode appears to be correctly

Remote Diode connected.

2 0 Fault Alarm When this bit is a 1, the Remote Diode may be disconnected or

shorted. This Alarm does not trigger an ALERT.

When this bit is a 0, the temperature of the Remote Diode is at or

Remote below the T_CRIT Limit.

1 0 T_CRIT Alarm When this bit is a 1, the temperature of the Remote Diode is above the

T_CRIT Limit, and an ALERT is triggered..

When this bit is a 0, the Tachometer count is lower than or equal to the

Tachometer Limit (the RPM of the fan is greater than or equal to the

minimum desired RPM).

When this bit is a 1, the Tachometer count is higher than the

0 0 Tach Alarm Tachometer Limit (the RPM of the fan is less than the minimum

desired RPM), and an ALERT is triggered. Note that if this bit is set,

the function of the ALERT/Tach pin must be Tach input, so an external

ALERT condition will not be generated. The user may read the status

16HEX ALERT MASK REGISTER (8-bits)

7 1 This bit is unused and always read as 1.

Local High When this bit is a 0, a Local High Alarm event will generate an ALERT.

6 0 Alarm Mask When this bit is a 1, a Local High Alarm will not generate an ALERT

5 1 This bit is unused and always read as 1.

When this bit is a 0, Remote High Alarm event will generate an

Remote ALERT.

4 0 High Alarm Mask When this bit is a 1, a Remote High Alarm event will not generate an

ALERT.

When this bit is a 0, a Remote Low Alarm event will generate an

16 R/W Remote ALERT.

3 0 Low Alarm When this bit is a 1, a Remote Low Alarm event will not generate an

Mask ALERT.

2 1 This bit is unused and always read as 1.

Remote When this bit is a 0, a Remote T_CRIT event will generate an ALERT.

1 0 T_CRIT When this bit is a 1, a Remote T_CRIT event will not generate an

Alarm Mask ALERT.

Tach When this bit is a 0, a Tach Alarm event will generate an ALERT.

0 0 Alarm Mask When this bit is a 1, a Tach Alarm event will not generate an ALERT.

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Table 11. Conversion Rate And One-Shot Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

04 (0A)HEX CONVERSION RATE REGISTER (8-bits)

Sets the conversion rate of the LM63.

00000000 = 0.0625 Hz

00000001 = 0.125 Hz

00000010 = 0.25 Hz

00000011 = 0.5 Hz

Conversion 00000100 = 1 Hz

04 (0A) R/W 7:0 0x08 Rate 00000101 = 2 Hz

00000110 = 4 Hz

00000111 = 8 Hz

00001000 = 16 Hz

00001001 = 32 Hz

All other values = 32 Hz

04 (0A)HEX ONE-SHOT REGISTER (8-bits)

Write One Shot With the LM63 in the STANDBY mode a single write to this register will

0F 7:0 N/A

Only Trigger initiate one complete temperature conversion cycle.

Table 12. ID Registers

ADDRESS READ/ POR

BITS NAME DESCRIPTION

HEX WRITE VALUE

FFHEX STEPPING / DIE REVISION ID REGISTER (8-bits)

Read Stepping/Die

FF 7:0 0x41 Version of LM63

Only Revision ID

FEHEX MANUFACTURER’S ID REGISTER (8-bits)

Read

FE 7:0 0x01 Manufacturer’s ID 0x01 = Texas Instruments

Only

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%100

%100___ _

_(%) u=forValuePWM ValuePWM

DutyCycle

LM63

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APPLICATION NOTES

FAN CONTROL DUTY CYCLE VS. REGISTER SETTINGS AND FREQUENCY

ACTUAL

PWM PWM

PWM PWM PWM DUTY

PWM STEP FREQ AT FREQ AT

VALUE VALUE VALUE CYCLE, %

FREQ RESOLUTION, 360 kHz 1.4 kHz

4D [5:0] 4C [5:0] FOR 4C [5:0] WHEN

4D [4:0] % INTERNAL INTERNAL

FOR 100% ABOUT 75% FOR 50% 75% IS

CLOCK, kHz CLOCK, Hz SELECTED

0 Address 0 is mapped to Address 1

1 50 2 1 1 180.0 703.1 50.0

2 25 4 3 2 90.00 351.6 75.0

3 16.7 6 5 3 60.00 234.4 83.3

4 12.5 8 6 4 45.00 175.8 75.0

5 10.0 10 8 5 36.00 140.6 80.0

6 8.33 12 9 6 30.00 117.2 75.0

7 7.14 14 11 7 25.71 100.4 78.6

8 6.25 16 12 8 22.50 87.9 75.0

9 5.56 18 14 9 20.00 78.1 77.8

10 5.00 20 15 10 18.00 70.3 75.0

11 4.54 22 17 11 16.36 63.9 77.27

12 4.16 24 18 12 15.00 58.6 75.00

13 3.85 26 20 13 13.85 54.1 76.92

14 3.57 28 21 14 12.86 50.2 75.00

15 3.33 30 23 15 12.00 46.9 76.67

16 3.13 32 24 16 11.25 43.9 75.00

17 2.94 34 26 17 10.59 41.4 76.47

18 2.78 36 27 18 10.00 39.1 75.00

19 2.63 38 29 19 9.47 37.0 76.32

20 2.50 40 30 20 9.00 35.2 75.00

21 2.38 42 32 21 8.57 33.5 76.19

22 2.27 44 33 22 8.18 32.0 75.00

23 2.17 46 35 23 7.82 30.6 76.09

24 2.08 48 36 24 7.50 29.3 75.00

25 2.00 50 38 25 7.20 28.1 76.00

26 1.92 52 39 26 6.92 27.0 75.00

27 1.85 54 41 27 6.67 26.0 75.93

28 1.79 56 42 28 6.42 25.1 75.00

29 1.72 58 44 29 6.21 24.2 75.86

30 1.67 60 45 30 6.00 23.4 75.00

31 1.61 62 47 31 5.81 22.7 75.81

COMPUTING DUTY CYCLES FOR A GIVEN FREQUENCY

Select a PWM Frequency from the first column corresponding to the desired actual frequency in columns 6 or 7.

Note the PWM Value for 100% Duty Cycle.

Find the Duty Cycle by taking the PWM Value of Register 4C and computing:

(1)

Example: For a PWM Frequency of 24, a PWM Value at 100% = 48 and PWM Value actual = 28, then the Duty

Cycle is (28/48) × 100% = 58.3%.

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RPMRPMFan _2723

1983

000,400,51

_ =

)_(__

000,400,5

_DecimalCountTachTotal

RPMFan u

LM63

SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

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REQUIRED INITIAL FAN CONTROL REGISTER SEQUENCE

Important! The BIOS must follow the sequence listed in Table 13 to configure the following Fan Registers for the

LM63 before using any of the Fan or Tachometer or PWM registers.

Table 13. [Register]HEX and Setup Instructions

STEP [Register]HEX AND SETUP INSTRUCTIONS(1)

[4A] Write bits 0 and 1; 3 and 4. This includes tach settings if used, PWM internal clock select (1.4 kHz or 360 kHz) and PWM

1Output Polarity.

2 [4B] Write bits 0 through 5 to program the spin-up settings.

3 [4D] Write bits 0 through 4 to set the frequency settings. This works with the PWM internal clock select.

Choose, then write, only one of the following:

4 A. [4F–5F] the Lookup Table, or

B. [4C] the PWM value bits 0 through 5.

5 If Step 4A, Lookup Table, was chosen and written then write [4A] bit 5 = 0.

(1) All other registers can be written at any time after the above sequence.

COMPUTING RPM OF THE FAN FROM THE TACH COUNT

The Tach Count Registers 46HEX and 47HEX count the number of periods of the 90 kHz tachometer clock in the

LM63 for the tachometer input from the fan assuming a 2 pulse per revolution fan tachometer, such as the fans

supplied with the Pentium 4 boxed processors. The RPM of the fan can be computed from the Tach Count

Registers 46HEX and 47HEX. This can best be shown through an example.

EXAMPLE:

Given: the fan used has a tachometer output with 2 per revolution.

Let:

• Register 46 (LSB) is BFHEX = Decimal (11 x 16) + 15 = 191 and

• Register 47 (MSB) is 7HEX = Decimal (7 x 256) = 1792.

The total Tach Count, in decimal, is 191 + 1792 = 1983.

The RPM is computed using the formula

where

• f = 1 for 2 pulses/rev fan tachometer output;

• f = 2 for 1 pulse/rev fan tachometer output, and

• f = 2 / 3 for 3 pulses/rev fan tachometer output (2)

For our example

(3)

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2.2 nF

PROCESSOR

ICIR

IE = IF

D+

D-

LM63

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USE OF THE LOOKUP TABLE FOR NON-LINEAR PWM VALUES VS TEMPERATURE

The Lookup Table, Registers 50 through 5F, can be used to create a non-linear PWM vs Temperature curve that

could be used to reduce the acoustic noise from processor fan due to linear or step transfer functions. An

example is given below.

EXAMPLE:

In a particular system it was found that the best acoustic fan noise performance was found to occur when the

PWM vs Temperature transfer function curve was parabolic in shape.

From 25°C to 105°C the fan is to go from 20% to 100%. Since there are 8 steps to the Lookup Table we will

break up the Temperature range into 8 separate temperatures. For the 80°C over 8-steps = 10°C per step. This

takes care of the x-axis.

For the PWM Value, we first select the PWM Frequency. In this example, we will make the PWM Frequency

(Register 4C) 20.

For 100% Duty Cycle then, the PWM value is 40. For 20%, the minimum is 40 x (0.2) = 8.

We can then arrange the PWM, Temperature pairs in a parabolic fashion in the form of y = 0.005 • (x −25)2+ 8

PWM VALUE CLOSEST PWM

TEMPERATURE CALCULATED VALUE

25 8.0 8

35 8.5 9

45 10.0 10

55 12.5 13

65 16.0 16

75 20.5 21

85 26.0 26

95 32.5 33

105 40.0 40

We can then program the Lookup Table with the temperature and Closest PWM Values required for the curve

required in our example.

NON-IDEALITY FACTOR AND TEMPERATURE ACCURACY

The LM63 can be applied to remote diode sensing in the same way as other integrated-circuit temperature

sensors. It can be soldered to a printed-circuit board, and because the path of best thermal conductivity is

between the die and the pins, its temperature will effectively be that of the printed-circuit board lands and traces

soldered to its pins. This presumes that the ambient air temperature is nearly the same as the surface

temperature of the printed-circuit board. If the air temperature is much higher or lower than the surface

temperature, the actual temperature of the LM63 die will be an intermediate temperature between the surface

and air temperatures. Again, the primary thermal conduction path is through the leads, so the circuit board

surface temperature will contribute to the die temperature much more than the air temperature.

To measure the temperature external to the die use a remote diode. This diode can be located on the die of the

target IC, such as a CPU processor chip as shown in Figure 14, allowing measurement of the IC’s temperature,

independent of the LM63’s temperature. The LM63 has been optimized for use with the thermal diode on the die

of an Intel Pentium 4 or a Mobile Pentium 4 Processor-M processor.

Figure 14. Processor Connection to LM63

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 

Vbe ln˜

¸¨

SF II ˜e¸

˜T

VT=q

SF II ˜e¸

˜T

1

MMBT3904

LM63

2.2 nF

D+

D-

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A discrete diode can also be used to sense the temperature of external objects or ambient air. Remember that a

discrete diode’s temperature will be affected, and often dominated by, the temperature of its leads.

Most silicon diodes do not lend themselves well to this application. It is recommended that a diode-connected

2N3904 transistor be used, as shown in Figure 15. The base of the transistor is connected to the collector and

becomes the anode. The emitter is the cathode.

Figure 15. Processor Connection to LM63

A LM63 with a diode-connected 2N3904 transistor approximates the temperature reading of the LM63 with the

Pentium 4 processor by 1°C.

T2N3904 = TPENTIUM 4 −1°C (4)

DIODE NON-IDEALITY

When a transistor is connected to a diode the following relationship holds for Vbe, T, and IF:

where (5)

• q = 1.6x10−19 Coulombs (the electron charge)

• T = Absolute Temperature in Kelvin

• k = 1.38x10−23 joules/K (Boltzmann’s constant)

•ηis the non-ideality factor of the manufacturing process used to make the thermal diode

• Is= Saturation Current and is process dependent

• If= Forward Current through the base emitter junction

• Vbe = Base Emitter Voltage Drop (6)

In the active region, the −1 term is negligible and may be eliminated, yielding the following equation

(7)

In Equation 7,ηand Isare dependent upon the process that was used in the fabrication of the particular diode.

By forcing two currents with a very controlled ratio (N) and measuring the resulting voltage difference, it is

possible to eliminate the Isterm. Solving for the forward voltage difference yields the relationship:

(8)

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The voltage seen by the LM63 also includes the IF×RSvoltage drop across the internal series resistance of the

Pentium 4 processor’s thermal diode. The non-ideality factor, η, is the only other parameter not accounted for

and depends on the diode that is used for measurement. Since ΔVbe is proportional to both ηand T, the

variations in ηcannot be distinguished from variations in temperature. Since the temperature sensor does not

control the non-ideality factor, it will directly add to the inaccuracy of the sensor.

For the Intel Pentium 4 and Mobile Pentium 4 Processor-M processors Intel specifies a ±0.1% variation in ηfrom

part to part. As an example, assume that a temperature sensor has an accuracy specification of ±1%°C at room

temperature of 25°C and process used to manufacture the diode has a non-ideality variation of ±0.1%. The

resulting accuracy will be:

TACC = ±1°C + (±0.1% of 298°K) = ±1.3°C (9)

The additional inaccuracy in the temperature measurement caused by η, can be eliminated if each temperature

sensor is calibrated with the remote diode that it will be paired with. Refer to the processor datasheet for the non-

ideality factor.

COMPENSATING FOR DIODE NON-IDEALITY

In order to compensate for the errors introduced by non-ideality, the temperature sensor is calibrated for a

particular processor. Texas Instruments temperature sensors are always calibrated to the typical non-ideality of a

particular processor type.

The LM63 is calibrated for the non-ideality of the 0.13 micron Intel Pentium 4 and Mobile Pentium 4 Processor-M

processors.

When a temperature sensor, calibrated for a specific type of processor is used with a different processor type or

a given processor type has a non-ideality that strays form the typical value, errors are introduced.

Temperature errors associated with non-ideality may be introduced in a specific temperature range of concern

through the use of the Temperature Offset Registers 11HEX and 12HEX.

The user is encouraged to send an e-mail to hardware.monitor.team@ti.com to further request information on

our recommended setting of the offset register for different processor types.

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PCB LAYOUT FOR MINIMIZING NOISE

Figure 16. Ideal Diode Trace Layout

In a noisy environment, such as a processor mother board, layout considerations are very critical. Noise induced

on traces running between the remote temperature diode sensor and the LM63 can cause temperature

conversion errors. Keep in mind that the signal level the LM63 is trying to measure is in microvolts. The following

guidelines should be followed:

1. Use a low-noise +3.3VDC power supply, and bypass to GND with a 0.1 µF ceramic capacitor in parallel with

a 100 pF ceramic capacitor. A bulk capacitance of 10 µF needs to be in the vicinity of the LM63's VDD pin.

2. Place the100 pF power supply bypass capacitor as close as possible to the VDD pin and the recommended

2.2 nF diode capacitor as close as possible to the LM63's D+ and D−pins. Make sure the traces to the

2.2 nF capacitor are matched.

3. Ideally, the LM63 should be placed within 10 cm of the Processor diode pins with the traces being as

straight, short and identical as possible. Trace resistance of 1 Ωcan cause as much as 1°C of error. This

error can be compensated by using the Remote Temperature Offset Registers, since the value placed in

these registers will automatically be subtracted from or added to the remote temperature reading.

4. Diode traces should be surrounded by a GND guard ring to either side, above and below if possible. This

GND guard should not be between the D+ and D−lines. In the event that noise does couple to the diode

lines it would be ideal if it is coupled common mode. That is equally to the D+ and D−lines.

5. Avoid routing diode traces in close proximity to power supply switching or filtering inductors.

6. Avoid running diode traces close to or parallel to high-speed digital and bus lines. Diode traces should be

kept at least 2 cm apart from the high-speed digital traces.

7. If it is necessary to cross high-speed digital traces, the diode traces and the high-speed digital traces should

cross at a 90 degree angle.

8. The ideal place to connect the LM63's GND pin is as close as possible to the Processor's GND associated

with the sense diode.

9. Leakage current between D+ and GND should be kept to a minimum. One nano-ampere of leakage can

cause as much as 1°C of error in the diode temperature reading. Keeping the printed circuit board as clean

as possible will minimize leakage current.

Noise coupling into the digital lines greater than 400 mVp-p (typical hysteresis) and undershoot less than 500 mV

below GND, may prevent successful SMBus communication with the LM63. SMBus no acknowledge is the most

common symptom, causing unnecessary traffic on the bus. Although the SMBus maximum frequency of

communication is rather low (100 kHz max), care still needs to be taken to ensure proper termination within a

system with multiple parts on the bus and long printed circuit board traces. An RC lowpass filter with a 3 dB

corner frequency of about 40 MHz is included on the LM63's SMBCLK input. Additional resistance can be added

in series with the SMBData and SMBCLK lines to further help filter noise and ringing. Minimize noise coupling by

keeping digital traces out of switching power supply areas as well as ensuring that digital lines containing high-

speed data communications cross at right angles to the SMBData and SMBCLK lines.

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SNAS190E –SEPTEMBER 2002–REVISED MAY 2013

REVISION HISTORY

Changes from Revision D (May 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 34

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM63CIMA NRND SOIC D 8 95 Non-RoHS

& Green Call TI Call TI 0 to 125 LM63

CIMA

LM63CIMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 LM63

CIMA

LM63CIMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 LM63

CIMA

LM63DIMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 LM63

DIMA

LM63DIMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 LM63

DIMA

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM63CIMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM63DIMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM63CIMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM63DIMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

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EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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