Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 TL08xx JFET-Input Operational Amplifiers 1 Features 3 Description * * The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. 1 * * * * * * * * Low Power Consumption: 1.4 mA/ch Typical Wide Common-Mode and Differential Voltage Ranges Low Input Bias Current: 30 pA Typical Low Input Offset Current: 5 pA Typical Output Short-Circuit Protection Low Total Harmonic Distortion: 0.003% Typical High Input Impedance: JFET Input Stage Latch-Up-Free Operation High Slew Rate: 13 V/s Typical Common-Mode Input Voltage Range Includes VCC+ 2 Applications * * * * Tablets White goods Personal electronics Computers Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TL084xD SOIC (14) 8.65 mm x 3.91 mm TL08xxFK LCCC (20) 8.89 mm x 8.89 mm TL084xJ CDIP (14) 19.56 mm x 6.92 mm TL084xN PDIP (14) 19.3 mm x 6.35 mm TL084xNS SO (14) 10.3 mm x 5.3 mm TL084xPW TSSOP (14) 5.0 mm x 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Schematic Symbol TL081 TL082 (EACH AMPLIFIER) TL084 (EACH AMPLIFIER) OFFSET N1 IN + + IN - - OUT IN + + IN - - OUT OFFSET N2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 8 1 1 1 2 3 5 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI ........................................................................ 6 Electrical Characteristics for TL08xM and TL084x ... 7 Operating Characteristics.......................................... 7 Dissipation Rating Table ........................................... 8 Typical Characteristics .............................................. 9 Parameter Measurement Information ................ 13 Detailed Description ............................................ 14 8.1 Overview ................................................................. 14 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 14 9 Applications and Implementation ...................... 15 9.1 Application Information............................................ 15 9.2 Typical Applications ............................................... 15 9.3 System Examples ................................................... 16 10 Power Supply Recommendations ..................... 18 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Examples................................................... 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (January 2014) to Revision I Page * Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 * Added Applications ................................................................................................................................................................. 1 * Moved Typical Characteristics into Specifications section. ................................................................................................... 9 Changes from Revision G (September 2004) to Revision H Page * Updated document to new TI data sheet format - no specification changes. ........................................................................ 1 * Deleted Ordering Information table. ....................................................................................................................................... 1 2 Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 5 Pin Configuration and Functions TL082 FK Package 20-Pin LCCC Top View NC 1OUT NC VCC+ NC TL081 and TL081x D, P, and PS Package 8-Pin SOIC, PDIP, and SO Top View NC 1IN - NC 1IN + NC 4 3 2 1 20 19 18 17 6 16 7 15 8 14 9 10 11 12 13 NC 2OUT NC 2IN - NC 1OUT 1IN - 1IN + VCC - 1IN - 1OUT NC 4OUT 4IN - TL084 FK Package 20-Pin LCCC Top View 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8 2 7 3 6 4 5 NC VCC + OUT OFFSET N2 1 8 2 7 3 6 4 5 VCC + 2OUT 2IN - 2IN + TL084 and TL084x D, J, N, NS and PW Package 14-Pin SOIC, CDIP, PDIP, SO, and TSSOP Top View 4IN + NC VCC - NC 3IN + 1OUT 1IN - 1IN + VCC + 2IN + 2IN - 2OUT 2IN - 2OUT NC 3OUT 3IN - 1IN + NC VCC + NC 2IN + 1 TL082 and TL082x D, JG, P, PS and PW Package 8-Pin SOIC, CDIP, PDIP, SO, and TSSOP Top View NC VCC - NC 2IN + NC 5 OFFSET N1 IN - IN + VCC - 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN - 4IN + VCC - 3IN + 3IN - 3OUT Pin Functions PIN TL081 TL082 TL084 SOIC, PDIP, SO SOIC, CDIP, PDIP, SO, TSSOP LCCC SOIC, CDIP, PDIP, SO, TSSOP 1IN- -- 2 5 2 3 I Negative input 1IN+ -- 3 7 3 4 I Positive input 1OUT -- 1 2 1 2 O Output 2IN- -- 6 15 6 9 I Negative input 2IN+ -- 5 12 5 8 I Positive input 2OUT -- 7 17 7 10 O Output 3IN- -- -- -- 9 13 I Negative input 3IN+ -- -- -- 10 14 I Positive input 3OUT -- -- -- 8 12 O Output 4IN- -- -- -- 13 19 I Negative input 4IN+ -- -- -- 12 18 I Positive input 4OUT -- -- -- 14 20 O Output NAME Copyright (c) 1977-2015, Texas Instruments Incorporated I/O LCCC DESCRIPTION Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 3 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com Pin Functions (continued) PIN TL081 TL082 TL084 SOIC, PDIP, SO SOIC, CDIP, PDIP, SO, TSSOP LCCC SOIC, CDIP, PDIP, SO, TSSOP LCCC IN- 2 -- -- -- -- I Negative input IN+ 3 -- -- -- -- I Positive input NAME 1 4 5 6 8 8 -- 9 DESCRIPTION 1 3 NC I/O -- 11 7 -- Do not connect 11 13 14 15 16 18 17 OFFSET N1 1 -- -- -- -- -- Input offset adjustment OFFSET N2 5 -- -- -- -- -- Input offset adjustment OUT 6 -- -- -- -- O Output VCC- 4 4 10 11 16 -- Power supply VCC+ 7 8 20 4 6 -- Power supply 4 Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VCC+ MAX Supply voltage (2) VCC- VID Differential input voltage VI Input voltage (2) (4) Operating free-air temperature 0 (2) (3) (4) (5) V 70 C TL08_I -40 85 TL084Q -40 125 TL08_M -55 125 Operating virtual junction temperature (1) V 15 See Dissipation Rating Table TL08_C TL08_AC TL08_BC Tstg 30 Unlimited Continuous total power dissipation TC V -18 (3) Duration of output short circuit (5) TA UNIT 18 150 C Case temperature for 60 seconds FK package TL08_M 260 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds J or JG package TL08_M 300 C 150 C Storage temperature -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC-. Differential voltages are at IN+, with respect to IN-. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC- Supply voltage -5 -15 V VCM Common-mode voltage VCC- + 4 VCC+ - 4 V TL08xM -55 125 TL08xQ -40 125 TL08xI -40 85 0 70 TA Ambient temperature TL08xC Copyright (c) 1977-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B C 5 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 6.4 Thermal Information TL08xx THERMAL METRIC (1) RJA (1) (2) (3) Junction-to-ambient thermal resistance (2) (3) D (SOIC) N (PDIP) NS (SO) P (PDIP) PS (SO) 8 PINS 14 PINS 14 PINS 14 PINS {PIN COUNT} PINS {PIN COUNT} PINS 8 PINS PW (TSSOP) 14 PINS 97 86 76 80 85 95 149 113 UNIT C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / RJA. Operating at the absolute maximum TJ of 150C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. 6.5 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VO = 0, RS = 50 VIO Temperature coefficient of VO = 0, input RS = 50 offset voltage IIO Input offset current (2) VO = 0 IIB Input bias current (2) VO = 0 VICR Commonmode input voltage range VOM Maximum peak output voltage swing TA (1) TL081C, TL082C, TL084C MIN 25C RL 10 k RL 2 k TYP MAX 3 15 Full range MIN TYP MAX 3 6 20 Full range 18 25C 5 Full range 30 Full range TL081BC, TL082BC, TL084BC MIN TYP MAX 2 3 7.5 200 5 30 10 MIN 100 5 MAX 3 6 100 5 30 7 200 30 7 25C 11 -12 to 15 11 -12 to 15 11 -12 to 15 11 -12 to 15 25C 12 13.5 12 13.5 12 13.5 12 13.5 Full range 12 12 12 12 mV V/C 18 2 200 UNIT TYP 9 18 2 400 TL081I, TL082I, TL084I 5 18 2 25C RL = 10 k TL081AC, TL082AC, TL084AC 100 pA 10 nA 200 pA 20 nA V V 10 12 10 12 10 12 10 12 25C 25 200 50 200 50 200 50 200 Full range 15 AVD Large-signal differential voltage amplification B1 Unity-gain bandwidth 25C 3 3 3 3 ri Input resistance 25C 1012 1012 1012 1012 CMRR Commonmode rejection ratio VIC = VICRmin, VO = 0, RS = 50 25C 70 86 75 86 75 86 75 86 dB kSVR Supplyvoltage rejection ratio (VCC/VIO) VCC = 15 V to 9 V, VO = 0, RS = 50 25C 70 86 80 86 80 86 80 86 dB (1) (2) 6 VO = 10 V, RL 2 k 15 25 V/mV 25 MHz All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range for TA is 0C to 70C for TL08_C, TL08_AC, TL08_BC and -40C to 85C for TL08_I. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 13. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI (continued) VCC = 15 V (unless otherwise noted) TEST CONDITIONS PARAMETER TA (1) TL081C, TL082C, TL084C MIN TL081AC, TL082AC, TL084AC TYP MAX 2.8 ICC Supply current (each amplifier) VO = 0, No load 25C 1.4 VO1/VO2 Crosstalk attenuation AVD = 100 25C 120 MIN TL081BC, TL082BC, TL084BC TYP MAX 1.4 2.8 MIN 120 TL081I, TL082I, TL084I TYP MAX 1.4 2.8 MIN 120 UNIT TYP MAX 1.4 2.8 mA 120 dB 6.6 Electrical Characteristics for TL08xM and TL084x VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIO Input offset voltage VO = 0, RS = 50 VIO Temperature coefficient of input offset voltage VO = 0, RS = 50 IIO Input offset current (2) VO = 0 Input bias current (2) IIB VICR Common-mode input voltage range VOM Maximum peak output voltage swing TA TL081M, TL082M MIN TYP 25C 3 Full range Full range 18 25C 5 30 125C RL 10 k RL 2 k 25C 11 25C 12 13.5 UNIT MAX 6 3 9 mV 15 V/C 18 100 5 100 pA 20 200 30 nA 200 pA 50 nA 50 -12 to 15 Full range TYP 20 25C RL = 10 k MIN 9 125C VO = 0 TL084Q, TL084M MAX 12 11 -12 to 15 12 13.5 V 12 V 10 12 10 12 25C 25 200 25 200 Full range 15 AVD Large-signal differential voltage amplification B1 Unity-gain bandwidth 25C 3 3 MHz ri Input resistance 25C 12 12 CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 25C 80 86 80 86 dB kSVR Supply-voltage rejection ratio (VCC/VIO) VCC = 15 V to 9 V, VO = 0, RS = 50 25C 80 86 80 86 dB ICC Supply current (each amplifier) VO = 0, No load 25C 1.4 VO1/VO2 Crosstalk attenuation AVD = 100 25C 120 (1) (2) VO = 10 V, RL 2 k V/mV 15 10 10 2.8 1.4 2.8 mA 120 dB All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 13. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as possible. 6.7 Operating Characteristics VCC = 15 V, TA= 25C (unless otherwise noted) PARAMETER SR (1) Slew rate at unity gain MIN TYP VI = 10 V, RL = 2 k, CL = 100 pF, See Figure 19 TEST CONDITIONS 8 (1) 13 VI = 10 V, RL = 2 k, CL = 100 pF, TA = - 55C to 125C, See Figure 19 5 (1) MAX UNIT V/s On products compliant to MIL-PRF-38535, this parameter is not production tested. Copyright (c) 1977-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 7 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com Operating Characteristics (continued) VCC = 15 V, TA= 25C (unless otherwise noted) PARAMETER tr Rise-time TEST CONDITIONS MIN TYP 0.05 overshoot factor VI = 20 V, RL = 2 k, CL = 100 pF, See Figure 19 Vn Equivalent input noise voltage RS = 20 In Equivalent input noise current RS = 20 , THD Total harmonic distortion VIrms = 6 V, AVD = 1, RS 1 k, RL 2 k, f = 1 kHz, MAX UNIT s 20% f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz 18 nV/Hz 4 V 0.01 pA/Hz 0.003% 6.8 Dissipation Rating Table 8 PACKAGE TA 25C POWER RATING D (14 pin) FK DERATING FACTOR DERATE ABOVE TA TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING 680 mW 7.6 mW/C 60C 604 m/W 490 mW 186 mW 680 mW 11.0 mW/C 88C 680 m/W 680 mW 273 mW J 680 mW 11.0 mW/C 88C 680 m/W 680 mW 273 mW JG 680 mW 8.4 mW/C 69C 672 m/W 546 mW 210 mW Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 6.9 Typical Characteristics Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. The Figure numbers referenced in the following graphs are located in Parameter Measurement Information. Table 1. Table of Graphs Figure Maximum peak output voltage versus versus versus versus Large-signal differential voltage amplification versus Free-air temperature versus Load resistance Figure 7 Figure 8 Differential voltage amplification versus Frequency with feed-forward compensation Figure 9 PD Total power dissipation versus Free-air temperature Figure 10 ICC Supply current versus Free-air temperature versus Supply voltage Figure 11 Figure 12 IIB Input bias current versus Free-air temperature Figure 13 Large-signal pulse response versus Time Figure 14 VO Output voltage versus Elapsed time Figure 15 CMRR Common-mode rejection ratio versus Free-air temperature Figure 16 Vn Equivalent input noise voltage versus Frequency Figure 17 THD Total harmonic distortion versus Frequency Figure 18 VOM AVD Frequency Free-air temperature Load resistance Supply voltage 15 VCC = 15 V 12.5 10 RL = 10 k TA = 25C See Figure 2 VCC = 10 V 7.5 VCC = 5 V 5 2.5 0 100 1k 10 k 100 k f - Frequency - Hz 1M 10 M Figure 1. Maximum Peak Output Voltage vs Frequency Copyright (c) 1977-2015, Texas Instruments Incorporated VOM VOM - Maximum Peak Output Voltage - V 15 VOM VOM - Maximum Peak Output Voltage - V Figure 1, Figure 2, Figure 3 Figure 4 Figure 5 Figure 6 VCC = 15 V 12.5 RL = 2 k TA = 25C See Figure 2 10 VCC = 10 V 7.5 5 VCC = 5 V 2.5 0 100 1k 10 k 100 k f - Frequency - Hz 1M 10 M Figure 2. Maximum Peak Output Voltage vs Frequency Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 9 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 15 VCC = 15 V RL = 2 k See Figure 2 TA = 25C 12.5 V VOM OM - Maximum Peak Output Voltage - V 10 TA = -55C 7.5 TA = 125C 5 2.5 12.5 RL = 2 k 10 7.5 5 2.5 VCC = 15 V See Figure 2 0 10 k 40 k 100 k 400 k 1 M f - Frequency - Hz 4M 0 -75 10 M VOM VOM - Maximum Peak Output Voltage - V 7.5 5 2.5 8 0.4 0.7 1 2 4 125 7.5 5 2.5 8 0 2 4 6 8 10 12 14 16 |VCC| - Supply Voltage - V Figure 6. Maximum Peak Output Voltage vs Supply Voltage 106 AAVD - Large-Signal Differential Voltage Amplification AAVD - Large-Signal Differential Voltage Amplification - V/mV 100 10 7 10 400 200 100 40 20 10 VCC = 15 V VO = 10 V RL = 2 k VCC = 5 V to 15 V RL = 2 k TA = 25C 105 104 Differential Voltage Amplification 103 102 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Submit Documentation Feedback 0 45 90 Phase Shift 101 135 1 -50 Figure 7. Large-Signal Differential Voltage Amplification vs Free-Air Temperature 10 75 0 0.2 1000 1 -75 50 12.5 Figure 5. Maximum Peak Output Voltage vs Load Resistance 2 25 RL = 10 k TA = 25C RL - Load Resistance - k 4 0 15 VCC = 15 V TA = 25C See Figure 2 10 0 0.1 -25 Figure 4. Maximum Peak Output Voltage vs Free-Air Temperature 15 12.5 -50 TA - Free-Air Temperature - C Figure 3. Maximum Peak Output Voltage vs Frequency VOM - Maximum Peak Output Voltage - V VOM RL = 10 k Phase Shift VOM VOM - Maximum Peak Output Voltage - V 15 1 10 100 1k 10 k 100 k f - Frequency - Hz 1M 180 10 M Figure 8. Large-Signal Differential Voltage Amplification and Phase Shift vs Frequency Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 250 VCC =15 V C2 = 3 pF TA = 25C See Figure 3 105 VCC =15 V No Signal No Load 225 PD - Total Power Dissipation - mW AVD - Differential Voltage Amplification - V/mV 106 104 103 102 10 200 175 TL084, TL085 150 125 100 TL082, TL083 75 TL081 50 25 1 100 1k 10 k 100 k 1M 0 -75 10 M -50 25 50 75 100 125 2 2 VCC = 15 V No Signal No Load 1.8 1.6 ICC - Supply Current Per Amplifier - mA I CC ICC - Supply Current Per Amplifier - mA I CC 0 Figure 10. Total Power Dissipation vs Free-Air Temperature Figure 9. Differential Voltage Amplification vs Frequency with Feed-Forward Compensation 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 TA = 25C No Signal No Load 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 0 125 2 4 6 8 10 12 14 16 TA - Free-Air Temperature - C |VCC| - Supply Voltage - V Figure 11. Supply Current per Amplifier vs Free-Air Temperature Figure 12. Supply Current per Amplifier vs Supply Voltage 100 6 VI and VO - Input and Output Voltages - V V CC =15 V I IB - Input Bias Current - nA -25 TA - Free-Air Temperature -C f - Frequency With Feed-Forward Compensation - Hz 10 1 0.1 0.01 - 50 4 Output 2 0 -2 Input -4 -6 - 25 0 25 50 75 100 TA - Free-Air Temperature - C Figure 13. Input Bias Current vs Free-Air Temperature Copyright (c) 1977-2015, Texas Instruments Incorporated 125 VCC = 15 V RL = 2 k CL = 100 pF TA = 25C 0 0.5 1 1.5 t - Time - s 2 2.5 3 3.5 Figure 14. Voltage-Follower Large-Signal Pulse Response Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 11 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 28 CMRR - Common-Mode Rejection Ratio - dB 89 VO - Output Voltage - mV 24 20 16 VCC =15 V RL = 2 k CL = 100 pF TA = 25C See Figure 1 12 8 4 0 -4 0.2 0.4 0.6 0.8 1.0 85 84 - 50 - 25 0 25 50 75 100 125 Figure 15. Output Voltage vs Elapsed Time Figure 16. Common-Mode Rejection Ratio vs Free-Air Temperature 40 30 20 10 40 100 400 1 k 4 k 10 k f - Frequency - Hz 40 k 100 k Figure 17. Equivalent Input Noise Voltage vs Frequency 12 86 83 - 75 1.2 VCC = 15 V AVD = 10 RS = 20 TA = 25C 10 87 TA - Free-Air Temperature -C 50 0 88 t - Elapsed Time - s Submit Documentation Feedback 1 THD - Total Harmonic Distortion - % V n - Equivalent Input Noise Voltage - nV/Hz nV/ Hz 0 VCC =15 V RL = 10 k VCC = 15 V AVD = 1 VI(RMS) = 6 V 0.4 TA = 25C 0.1 0.04 0.01 0.004 0.001 100 400 1k 4 k 10 k f - Frequency - Hz 40 k 100 k Figure 18. Total Harmonic Distortion vs Frequency Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 7 Parameter Measurement Information 10 k 1 k - - VI OUT OUT + + VI RL CL = 100 pF Figure 19. Test Figure 1 Figure 20. Test Figure 2 100 k TL081 - IN - C2 OUT C1 500 pF N2 + IN + - IN - CL = 100 pF RL = 2 k N1 100 k N1 OUT 1.5 k + VCC - Figure 21. Test Figure 3 Copyright (c) 1977-2015, Texas Instruments Incorporated Figure 22. Test Figure 4 Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 13 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 8 Detailed Description 8.1 Overview The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates wellmatched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. Offset adjustment and external compensation options are available within the TL08xx family. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from -40C to 85C. The Q-suffix devices are characterized for operation from -40C to +125C. The M-suffix devices are characterized for operation over the full military temperature range of -55C to +125C. 8.2 Functional Block Diagram VCC + IN + 64 IN - OUT 128 64 C1 1080 1080 VCC - OFFSET N1 OFFSET N2 TL081 Only 8.3 Feature Description 8.3.1 Total Harmonic Distortion Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when used in audio signal applications. 8.3.2 Slew Rate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 13-V/s slew rate. 8.4 Device Functional Modes These devices are powered on when the supply is connected. This device can be operated as a single-supply operational amplifier or dual-supply amplifier depending on the application. 14 Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TL08x series of operational amplifiers can be used in countless applications. The few applications in this section show principles used in all applications of these parts. 9.2 Typical Applications 9.2.1 Inverting Amplifier Application A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative voltages positive. RF RI Vsup+ VOUT VIN + Vsup- Figure 23. Schematic for Inverting Amplifier Application 9.2.1.1 Design Requirements The supply voltage must be chosen such that it is larger than the input voltage range and output range. For instance, this application will scale a signal of 0.5 V to 1.8 V. Setting the supply at 12 V is sufficient to accommodate this application. 9.2.1.2 Detailed Design Procedure Determine the gain required by the inverting amplifier: (1) (2) Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the k range is desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much current. This example will choose 10 k for RI which means 36 k will be used for RF. This was determined by Equation 3. (3) Copyright (c) 1977-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 15 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com Typical Applications (continued) 9.2.1.3 Application Curve 2 VIN 1.5 VOUT 1 Volts 0.5 0 -0.5 -1 -1.5 -2 0 0.5 1 Time (ms) 1.5 2 Figure 24. Input and output voltages of the inverting amplifier 9.3 System Examples 9.3.1 General Applications RF = 100 k VCC + - Output R1 Input - C3 TL081 + CF = 3.3 F TL081 R2 + 15 V 3.3 k Output VCC - 1 k -15 V R1 = R2 = 2(R3) = 1.5 M R3 C1 C2 C1 = C2 = C3 = 110 pF 2 1 fo = = 1 kHz 2 R1 C1 3.3 k 9.1 k Figure 25. 0.5-Hz Square-Wave Oscillator Figure 26. High-Q Notch Filter - 15 V 18 pF - TL084 VCC + 18 pF Output A + + TL084 - VCC + 88.4 k - 100 k VCC - 6 cos t 1 k 15 V 1N4148 88.4 k VCC + 18 k (see Note A) A. These resistor values may be adjusted for a symmetrical output. VCC + 100 k VCC - - 100 F VCC+ Output B + 100 k 18 k (see Note A) 1/2 TL082 18 pF TL084 100 k 88.4 k 1/2 TL082 + Input 1 k VCC + - 1 F 1N4148 6 sin t VCC + 1 M + 1 2 RF CF - f= TL084 Output C + Figure 27. Audio-Distribution Amplifier 16 Submit Documentation Feedback Figure 28. 100-kHz Quadrature Oscillator Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 System Examples (continued) 16 k 16 k 220 pF 220 pF VCC + 43 k 43 k 1/4 TL084 VCC + VCC + 43 k 1/4 TL084 1/4 TL084 + + + 1.5 k + - 1/4 TL084 220 pF VCC + - Input 220 pF 30 k - 43 k 43 k 30 k 1.5 k VCC - - 43 k VCC - VCC - Output B VCC - Output A Output A Output B 2 kHz/div Second-Order Bandpass Filter fo = 100 kHz, Q = 30, GAIN = 4 2 kHz/div Cascaded Bandpass Filter fo = 100 kHz, Q = 69, GAIN = 16 Figure 29. Positive-Feedback Bandpass Filter Copyright (c) 1977-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 17 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 10 Power Supply Recommendations CAUTION Supply voltages larger than 36 V for a single-supply or outside the range of 18 V for a dual-supply can permanently damage the device (see the Absolute Maximum Ratings ). Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: * Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. - Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. * Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089). * To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. * Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Examples. * Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. * Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 18 Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B www.ti.com SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 11.2 Layout Examples Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF NC NC IN1i VCC+ IN1+ OUT VCCi NC VS+ Use low-ESR, ceramic bypass capacitor RG GND VIN RIN GND Only needed for dual-supply operation GND VS(or GND for single supply) VOUT Ground (GND) plane on another layer Figure 30. Operational Amplifier Board Layout for Noninverting Configuration VIN RIN RG + VOUT RF Figure 31. Operational Amplifier Schematic for Noninverting Configuration Copyright (c) 1977-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B 19 TL081, TL081A, TL081B, TL082, TL082A TL082B, TL084, TL084A, TL084B SLOS081I - FEBRUARY 1977 - REVISED MAY 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For more information, see the following: * Circuit Board Layout Techniques, SLOA089. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TL081 Click here Click here Click here Click here Click here TL081A Click here Click here Click here Click here Click here TL081B Click here Click here Click here Click here Click here TL082 Click here Click here Click here Click here Click here TL082A Click here Click here Click here Click here Click here TL082B Click here Click here Click here Click here Click here TL084 Click here Click here Click here Click here Click here TL084A Click here Click here Click here Click here Click here TL084B Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 1977-2015, Texas Instruments Incorporated Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-9851501Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629851501Q2A TL082MFKB 5962-9851501QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA TL082M 5962-9851503Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629851503Q2A TL084 MFKB 5962-9851503QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL081ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081AC TL081ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081AC TL081ACP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081ACP TL081BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081BC TL081BCDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081BC TL081BCP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081BCP TL081BCPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081BCP TL081CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C TL081CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C TL081CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP TL081CPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL081CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I TL081IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I TL081IP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL081IP TL082ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082ACP TL082ACPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082A TL082BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082BCP Addendum-Page 2 T081 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL082BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082BCP TL082CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL082CP TL082CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL082IP Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL082IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL082IP TL082IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z082 TL082MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629851501Q2A TL082MFKB TL082MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL082MJG TL082MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA TL082M TL084ACD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084ACN TL084ACNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A TL084BCD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084BCN TL084BCNE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084BCN TL084CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL084CDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084CN TL084CNE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084CN TL084CNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084 TL084CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084 TL084CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084 TL084CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084 TL084ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN TL084INE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN TL084MFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TL084MFK Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL084MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629851503Q2A TL084 MFKB TL084MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL084MJ TL084MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL084QD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 6 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M : * Catalog: TL082, TL084 * Automotive: TL082-Q1, TL082-Q1 * Military: TL082M, TL084M NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Military - QML certified for Military and Defense Applications Addendum-Page 7 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL081ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TL081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TL082BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TL082CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2016 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL084ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TL084BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TL084IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084QDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL081ACDR SOIC D 8 2500 340.5 338.1 20.6 TL081BCDR SOIC D 8 2500 340.5 338.1 20.6 TL081CDR SOIC D 8 2500 340.5 338.1 20.6 TL081CPSR SO PS 8 2000 367.0 367.0 38.0 TL081IDR SOIC D 8 2500 340.5 338.1 20.6 TL082ACDR SOIC D 8 2500 367.0 367.0 35.0 TL082ACDR SOIC D 8 2500 340.5 338.1 20.6 TL082ACPSR SO PS 8 2000 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2016 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL082BCDR SOIC D 8 2500 340.5 338.1 20.6 TL082CDR SOIC D 8 2500 340.5 338.1 20.6 TL082CDR SOIC D 8 2500 367.0 367.0 35.0 TL082CPSR SO PS 8 2000 367.0 367.0 38.0 TL082CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL082IDR SOIC D 8 2500 367.0 367.0 35.0 TL082IDR SOIC D 8 2500 340.5 338.1 20.6 TL082IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL084ACDR SOIC D 14 2500 367.0 367.0 38.0 TL084ACDR SOIC D 14 2500 333.2 345.9 28.6 TL084ACNSR SO NS 14 2000 367.0 367.0 38.0 TL084BCDR SOIC D 14 2500 333.2 345.9 28.6 TL084CDR SOIC D 14 2500 367.0 367.0 38.0 TL084CDR SOIC D 14 2500 333.2 345.9 28.6 TL084CDRG4 SOIC D 14 2500 333.2 345.9 28.6 TL084CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TL084IDR SOIC D 14 2500 333.2 345.9 28.6 TL084QDR SOIC D 14 2500 367.0 367.0 38.0 TL084QDRG4 SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 3 PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. 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