+
−
+
−
OFFSET N1
IN +
IN −
OUT IN +
IN −
OUT
TL082 (EACH AMPLIFIER)
TL084 (EACH AMPLIFIER)
TL081
OFFSET N2
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
TL08xx JFET-Input Operational Amplifiers
1 Features 3 Description
The TL08xx JFET-input operational amplifier family is
1• Low Power Consumption: 1.4 mA/ch Typical designed to offer a wider selection than any
• Wide Common-Mode and Differential Voltage previously developed operational amplifier family.
Ranges Each of these JFET-input operational amplifiers
• Low Input Bias Current: 30 pA Typical incorporates well-matched, high-voltage JFET and
bipolar transistors in a monolithic integrated circuit.
• Low Input Offset Current: 5 pA Typical The devices feature high slew rates, low input bias
• Output Short-Circuit Protection and offset currents, and low offset-voltage
• Low Total Harmonic Distortion: 0.003% Typical temperature coefficient.
• High Input Impedance: JFET Input Stage Device Information(1)
• Latch-Up-Free Operation PART NUMBER PACKAGE BODY SIZE (NOM)
• High Slew Rate: 13 V/μs Typical TL084xD SOIC (14) 8.65 mm × 3.91 mm
• Common-Mode Input Voltage Range TL08xxFK LCCC (20) 8.89 mm × 8.89 mm
Includes VCC+ TL084xJ CDIP (14) 19.56 mm × 6.92 mm
TL084xN PDIP (14) 19.3 mm × 6.35 mm
2 Applications TL084xNS SO (14) 10.3 mm × 5.3 mm
• Tablets TL084xPW TSSOP (14) 5.0 mm × 4.4 mm
• White goods (1) For all available packages, see the orderable addendum at
• Personal electronics the end of the data sheet.
• Computers
Schematic Symbol
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
Table of Contents
8.2 Functional Block Diagram....................................... 14
1 Features.................................................................. 18.3 Feature Description................................................. 14
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 14
3 Description............................................................. 19 Applications and Implementation ...................... 15
4 Revision History..................................................... 29.1 Application Information............................................ 15
5 Pin Configuration and Functions......................... 39.2 Typical Applications ............................................... 15
6 Specifications......................................................... 59.3 System Examples ................................................... 16
6.1 Absolute Maximum Ratings ..................................... 510 Power Supply Recommendations ..................... 18
6.2 ESD Ratings.............................................................. 511 Layout................................................................... 18
6.3 Recommended Operating Conditions....................... 511.1 Layout Guidelines ................................................. 18
6.4 Thermal Information.................................................. 611.2 Layout Examples................................................... 19
6.5 Electrical Characteristics for TL08xC, TL08xxC, and
TL08xI........................................................................ 612 Device and Documentation Support................. 20
6.6 Electrical Characteristics for TL08xM and TL084x... 712.1 Documentation Support ........................................ 20
6.7 Operating Characteristics.......................................... 712.2 Related Links ........................................................ 20
6.8 Dissipation Rating Table........................................... 812.3 Community Resources.......................................... 20
6.9 Typical Characteristics.............................................. 912.4 Trademarks........................................................... 20
12.5 Electrostatic Discharge Caution............................ 20
7 Parameter Measurement Information ................ 13 12.6 Glossary................................................................ 20
8 Detailed Description............................................ 14 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 14 Information........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2014) to Revision I Page
• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description
section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
• Added Applications................................................................................................................................................................. 1
• Moved Typical Characteristics into Specifications section. ................................................................................................... 9
Changes from Revision G (September 2004) to Revision H Page
• Updated document to new TI data sheet format - no specification changes......................................................................... 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
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3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4IN +
NC
VCC −
NC
3IN +
1IN +
NC
VCC +
NC
2IN +
1IN −
1OUT
NC
3OUT
3IN −
4OUT
4IN −
2IN −
2OUT
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN −
1IN +
VCC +
2IN +
2IN −
2OUT
4OUT
4IN −
4IN +
VCC −
3IN +
3IN −
3OUT
1
2
3
4
8
7
6
5
1OUT
1IN −
1IN +
VCC −
VCC +
2OUT
2IN −
2IN +
1
2
3
4
8
7
6
5
OFFSET N1
IN −
IN +
VCC −
NC
VCC +
OUT
OFFSET N2
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
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SLOS081I –FEBRUARY 1977–REVISED MAY 2015
5 Pin Configuration and Functions
TL082 FK Package TL081 and TL081x D, P, and PS Package
20-Pin LCCC 8-Pin SOIC, PDIP, and SO
Top View Top View
TL082 and TL082x D, JG, P, PS and PW Package
8-Pin SOIC, CDIP, PDIP, SO, and TSSOP
Top View
TL084 FK Package
20-Pin LCCC
Top View
TL084 and TL084x D, J, N, NS and PW Package
14-Pin SOIC, CDIP, PDIP, SO, and TSSOP
Top View
Pin Functions
PIN
TL081 TL082 TL084
SOIC, I/O DESCRIPTION
SOIC,
NAME SOIC, PDIP, CDIP,
CDIP, PDIP, LCCC LCCC
SO PDIP, SO,
SO, TSSOP TSSOP
1IN– — 2 5 2 3 I Negative input
1IN+ — 3 7 3 4 I Positive input
1OUT — 1 2 1 2 O Output
2IN– — 6 15 6 9 I Negative input
2IN+ — 5 12 5 8 I Positive input
2OUT — 7 17 7 10 O Output
3IN– — — — 9 13 I Negative input
3IN+ — — — 10 14 I Positive input
3OUT — — — 8 12 O Output
4IN– — — — 13 19 I Negative input
4IN+ — — — 12 18 I Positive input
4OUT — — — 14 20 O Output
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,
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,
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,
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,
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TL082B
,
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,
TL084A
,
TL084B
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Pin Functions (continued)
PIN
TL081 TL082 TL084
SOIC, I/O DESCRIPTION
SOIC,
NAME SOIC, PDIP, CDIP,
CDIP, PDIP, LCCC LCCC
SO PDIP, SO,
SO, TSSOP TSSOP
IN– 2 — — — — I Negative input
IN+ 3 — — — — I Positive input
11
3
45
6
87
NC 8 — 9 — — Do not connect
11 11
13
14 15
16
18 17
OFFSET 1 — — — — — Input offset adjustment
N1
OFFSET 5 — — — — — Input offset adjustment
N2
OUT 6 — — — — O Output
VCC– 4 4 10 11 16 — Power supply
VCC+ 7 8 20 4 6 — Power supply
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,
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,
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,
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SLOS081I –FEBRUARY 1977–REVISED MAY 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC+ 18
Supply voltage(2) V
VCC– –18
VID Differential input voltage(3) ±30 V
VIInput voltage(2)(4) ±15 V
Duration of output short circuit(5) Unlimited
Continuous total power dissipation See Dissipation Rating Table
TL08_C
TL08_AC 0 70
TL08_BC
TAOperating free-air temperature °C
TL08_I –40 85
TL084Q –40 125
TL08_M –55 125
Operating virtual junction temperature 150 °C
TCCase temperature for 60 seconds FK package TL08_M 260 °C
Lead temperature 1,6 mm (1/16 J or JG package TL08_M 300 °C
inch) from case for 10 seconds
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
(3) Differential voltages are at IN+, with respect to IN−.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- 1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC+ Supply voltage 5 15 V
VCC– Supply voltage –5 –15 V
VCM Common-mode voltage VCC– + 4 VCC+ – 4 V
TL08xM –55 125
TL08xQ –40 125
TAAmbient temperature °C
TL08xI –40 85
TL08xC 0 70
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TL081
,
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,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
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6.4 Thermal Information TL08xx
D (SOIC) N (PDIP) NS (SO) P (PDIP) PS (SO) PW (TSSOP)
THERMAL METRIC(1) UNIT
8 PINS 14 14 PINS 14 PINS {PIN {PIN 8 PINS 14
PINS COUNT} COUNT} PINS
PINS PINS
Junction-to-ambient
RθJA 97 86 76 80 85 95 149 113 °C/W
thermal resistance(2)(3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJof 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI
VCC± = ±15 V (unless otherwise noted) TL081C, TL082C, TL081AC, TL082AC, TL081BC, TL082BC, TL081I, TL082I,
TEST TL084C TL084AC TL084BC TL084I
PARAMETER TA(1) UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
25°C 3 15 3 6 2 3 3 6
Input offset VO= 0,
VIO mV
Full
voltage RS= 50 Ω20 7.5 5 9
range
Temperature
coefficient of VO= 0, Full
αVIO input 18 18 18 18 μV/°C
RS= 50 Ωrange
offset
voltage
25°C 5 200 5 100 5 100 5 100 pA
Input offset
IIO VO= 0 Full
current(2) 2 2 2 10 nA
range
25°C 30 400 30 200 30 200 30 200 pA
Input bias
IIB VO= 0 Full
current(2) 10 7 7 20 nA
range
Common- –12 –12 –12 –12
mode
VICR 25°C ±11 to ±11 to ±11 to ±11 to V
input voltage 15 15 15 15
range
Maximum RL= 10 kΩ25°C ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 ±12 ±13.5
peak RL≥10 kΩ±12 ±12 ±12 ±12
VOM output V
Full
voltage range
RL≥2 kΩ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12
swing
Large-signal 25°C 25 200 50 200 50 200 50 200
differential VO= ±10 V,
AVD V/mV
Full
voltage RL≥2 kΩ15 15 25 25
range
amplification
Unity-gain
B125°C 3 3 3 3 MHz
bandwidth
Input
ri25°C Ω
1012 1012 1012 1012
resistance
Common- VIC = VICRmin,
mode
CMRR VO= 0, 25°C 70 86 75 86 75 86 75 86 dB
rejection RS= 50 Ω
ratio
Supply- VCC = ±15 V to
voltage ±9 V,
kSVR rejection 25°C 70 86 80 86 80 86 80 86 dB
VO= 0,
ratio RS= 50 Ω
(ΔVCC±/ΔVIO)
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range for
TAis 0°C to 70°C for TL08_C, TL08_AC, TL08_BC and –40°C to 85°C for TL08_I.
(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 13. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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,
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,
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,
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,
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,
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,
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SLOS081I –FEBRUARY 1977–REVISED MAY 2015
Electrical Characteristics for TL08xC, TL08xxC, and TL08xI (continued)
VCC± = ±15 V (unless otherwise noted) TL081C, TL082C, TL081AC, TL082AC, TL081BC, TL082BC, TL081I, TL082I,
TEST TL084C TL084AC TL084BC TL084I
PARAMETER TA(1) UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Supply
current VO= 0,
ICC 25°C 1.4 2.8 1.4 2.8 1.4 2.8 1.4 2.8 mA
(each No load
amplifier)
Crosstalk
VO1/VO2 AVD = 100 25°C 120 120 120 120 dB
attenuation
6.6 Electrical Characteristics for TL08xM and TL084x
VCC± = ±15 V (unless otherwise noted) TL081M, TL082M TL084Q, TL084M
PARAMETER TEST CONDITIONS(1) TAUNIT
MIN TYP MAX MIN TYP MAX
25°C 3 6 3 9
VIO Input offset voltage VO= 0, RS= 50 ΩmV
Full range 9 15
Temperature
αVIO coefficient of input VO= 0, RS= 50 ΩFull range 18 18 μV/°C
offset voltage
25°C 5 100 5 100 pA
IIO Input offset current(2) VO= 0 125°C 20 20 nA
25°C 30 200 30 200 pA
IIB Input bias current(2) VO= 0 125°C 50 50 nA
–12 –12
Common-mode
VICR 25°C ±11 to ±11 to V
input voltage range 15 15
RL= 10 kΩ25°C ±12 ±13.5 ±12 ±13.5
Maximum peak
VOM RL≥10 kΩ±12 ±12 V
output voltage swing Full range
RL≥2 kΩ±10 ±12 ±10 ±12
25°C 25 200 25 200
Large-signal differential
AVD VO= ±10 V, RL≥2 kΩV/mV
voltage amplification Full range 15 15
B1Unity-gain bandwidth 25°C 3 3 MHz
riInput resistance 25°C Ω
1012 1012
Common-mode VIC = VICRmin,
CMRR 25°C 80 86 80 86 dB
rejection ratio VO= 0, RS= 50 Ω
Supply-voltage VCC = ±15 V to ±9 V,
kSVR rejection ratio 25°C 80 86 80 86 dB
VO= 0, RS= 50 Ω
(ΔVCC±/ΔVIO)
Supply current
ICC VO= 0, No load 25°C 1.4 2.8 1.4 2.8 mA
(each amplifier)
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB
(1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.
(2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown
in Figure 13. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as possible.
6.7 Operating Characteristics
VCC± = ±15 V, TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI= 10 V, RL= 2 kΩ, CL= 100 pF, 8(1) 13
See Figure 19
SR Slew rate at unity gain V/μs
VI= 10 V, RL= 2 kΩ, CL= 100 pF,
TA=−55°C to 125°C, 5(1)
See Figure 19
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
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TL081
,
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,
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,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
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Operating Characteristics (continued)
VCC± = ±15 V, TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trRise-time 0.05 μs
VI= 20 V, RL= 2 kΩ, CL= 100 pF,
See Figure 19
overshoot factor 20%
f = 1 kHz 18 nV/√Hz
Equivalent input noise
VnRS= 20 Ω
voltage f = 10 Hz to 10 kHz 4 μV
Equivalent input noise
InRS= 20 Ω, f = 1 kHz 0.01 pA/√Hz
current VIrms = 6 V, AVD = 1, RS≤1 kΩ, RL≥2 kΩ,
THD Total harmonic distortion 0.003%
f = 1 kHz,
6.8 Dissipation Rating Table
TA≤25°C DERATING DERATE TA= 70°C TA= 85°C TA= 125°C
PACKAGE POWER RATING FACTOR ABOVE TAPOWER RATING POWER RATING POWER RATING
D (14 pin) 680 mW 7.6 mW/°C 60°C 604 m/W 490 mW 186 mW
FK 680 mW 11.0 mW/°C 88°C 680 m/W 680 mW 273 mW
J 680 mW 11.0 mW/°C 88°C 680 m/W 680 mW 273 mW
JG 680 mW 8.4 mW/°C 69°C 672 m/W 546 mW 210 mW
8Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
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10 M1 M100 k10 k1 k100
f − Frequency − Hz
VOM − Maximum Peak Output V
oltage − V
0
±2.5
±5
±7.5
±10
±12.5
±15
See Figure 2
TA= 25°C
RL= 2 kΩ
VCC±=±10 V
VCC±=±5 V
V
OM
VCC±=±15 V
RL= 10 kΩ
TA= 25°C
See Figure 2
±15
±12.5
±10
±7.5
±5
±2.5
0
VOM −Maximum Peak Output V
oltage −V
f−Frequency −Hz
100 1 k 10 k 100 k 1 M 10 M
V
OM
VCC±=±5 V
VCC±=±10 V
VCC±=±15 V
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
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,
TL084B
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SLOS081I –FEBRUARY 1977–REVISED MAY 2015
6.9 Typical Characteristics
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices. The Figure numbers referenced in the following graphs are located in Parameter Measurement Information.
Table 1. Table of Graphs
Figure
versus Frequency Figure 1,Figure 2,Figure 3
versus Free-air temperature Figure 4
VOM Maximum peak output voltage versus Load resistance Figure 5
versus Supply voltage Figure 6
Large-signal differential voltage versus Free-air temperature Figure 7
amplification versus Load resistance Figure 8
AVD versus Frequency with feed-forward
Differential voltage amplification Figure 9
compensation
PDTotal power dissipation versus Free-air temperature Figure 10
versus Free-air temperature Figure 11
ICC Supply current versus Supply voltage Figure 12
IIB Input bias current versus Free-air temperature Figure 13
Large-signal pulse response versus Time Figure 14
VOOutput voltage versus Elapsed time Figure 15
CMRR Common-mode rejection ratio versus Free-air temperature Figure 16
VnEquivalent input noise voltage versus Frequency Figure 17
THD Total harmonic distortion versus Frequency Figure 18
Figure 1. Maximum Peak Output Voltage Figure 2. Maximum Peak Output Voltage
vs vs
Frequency Frequency
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−75
1
Voltage Amplification − V/mV
TA− Free-Air Temperature − °C
125
1000
−50 −25 0 25 50 75 100
2
4
10
20
40
100
200
400
VCC±=±15 V
VO=±10 V
RL= 2 kΩ
A− Large-Signal Differential
AVD
0°
45°
180°
135°
90°
1
1
f − Frequency − Hz
10 M
106
10 100 1 k 10 k 100 k 1 M
101
102
103
104
105
Differential
Voltage
Amplification
VCC±=±5 V to ±15 V
RL= 2 kΩ
TA= 25°C
Phase Shift
Voltage Amplification
A
–Large-Signal Differential
AVD
Phase Shift
0.1
0
RL− Load Resistance − kΩ
10
±15
±2.5
±5
±7.5
±10
±12.5
VCC±=±15 V
TA= 25°C
See Figure 2
0.2 0.4 0.7 1 2 4 7
VOM − Maximum Peak Output V
oltage − V
V
OM
8
0
0
VOM − Maximum Peak Output V
oltage − V
|VCC±| − Supply Voltage − V
16
±15
2 4 6 8 10 12 14
±2.5
±5
±7.5
±10
±12.5
RL= 10 kΩ
TA= 25°C
V
OM
8
0
±2.5
±5
±7.5
±10
±12.5
±15
10 k 40 k 100 k 400 k 1 M 4 M 10 M
f − Frequency − Hz
VOM − Maximum Peak Output V
oltage − V
V
OM
VCC±=±15 V
RL= 2 kΩ
See Figure 2
TA= −55°C
TA= 25°C
TA= 125°C
−75
0
VOM − Maximum Peak Output V
oltage − V
TA− Free-Air Temperature − °C
125
±15
−50 −25 0 25 50 75 100
±2.5
±5
±7.5
±10
±12.5
RL= 10 kΩ
VCC±=±15 V
See Figure 2
V
OM
RL= 2 kΩ
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
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Figure 4. Maximum Peak Output Voltage
Figure 3. Maximum Peak Output Voltage vs
vs Free-Air Temperature
Frequency
Figure 6. Maximum Peak Output Voltage
Figure 5. Maximum Peak Output Voltage vs
vs Supply Voltage
Load Resistance
Figure 8. Large-Signal Differential Voltage Amplification and
Figure 7. Large-Signal Differential Voltage Amplification Phase Shift
vs vs
Free-Air Temperature Frequency
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− 50
0.01
− Input Bias Current − nA
TA− Free-Air Temperature − C°
125
100
− 25 0 25 50 75 100
0.1
1
10
VCC±= 15 V±
IIB
−6
t − Time − µs
3.5
6
0 0.5 1 1.5 2 2.5 3
−4
−2
0
2
4
Output
Input
VCC±=±15 V
RL= 2 kΩ
TA= 25°C
CL= 100 pF
VO
VI− Input and Output V
oltages − V
and
−75
0
TA− Free-Air Temperature − °C
125
2
−50 −25 0 25 50 75 100
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VCC±=±15 V
No Signal
No Load
ICC − Supply Current Per Amplifier − mA
CC±
I
0
0
|VCC±|− Supply Voltage − V
16
2
2 4 6 8 10 12 14
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8 TA= 25°C
No Signal
No Load
ICC − Supply Current Per Amplifier − mA
CC±
I
See Figure 3
TA= 25 C°
C2 = 3 pF
VCC±= 15 V±
105
104
103
102
10
1 M100 k10 k1 k
106
10 M
f − Frequency With Feed-Forward Compensation − Hz
1
100
− Differential Voltage Amplification − V/mV
AVD
−75
0
− Total Power Dissipation − mW
TA− Free-Air Temperature −C°
125
250
−50 −25 0 25 50 75 100
25
50
75
100
125
150
175
200
225
VCC±= 15 V±
No Signal
No Load
TL084, TL085
TL082, TL083
TL081
PD
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
www.ti.com
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
Figure 10. Total Power Dissipation
Figure 9. Differential Voltage Amplification vs
vs Free-Air Temperature
Frequency with Feed-Forward Compensation
Figure 11. Supply Current per Amplifier Figure 12. Supply Current per Amplifier
vs vs
Free-Air Temperature Supply Voltage
Figure 14. Voltage-Follower Large-Signal Pulse Response
Figure 13. Input Bias Current
vs
Free-Air Temperature
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
10
0
− Equivalent Input Noise V
oltage − nV/Hz
f − Frequency − Hz
100 k
50
10
20
30
40
VCC±=±15 V
AVD = 10
RS= 20 Ω
TA= 25°C
40 100 400 1 k 4 k 10 k 40 k
nV/ Hz
Vn
0.001
THD − T
otal Harmonic Distortion − %
1
40 k10 k4 k1 k400 100 k
f − Frequency − Hz
100
0.004
0.01
0.04
0.1
0.4
VCC±=±15 V
AVD = 1
VI(RMS) = 6 V
TA= 25°C
RL= 10 kΩ
VCC±= 15 V±
88
87
86
85
84
1007550250− 25− 50
89
125
TA− Free-Air Temperature −C°
CMRR − Common-Mode Rejection Ratio − dB
83
− 75
− 4
− Output Voltage − mV
t − Elapsed Time – sµ
1.2
28
0 0.2 0.4 0.6 0.8 1.0
0
4
8
12
16
20
24
VO
VCC±= 15 V±
RL= 2 kΩ
CL= 100 pF
TA= 25 C°
See Figure 1
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
Figure 15. Output Voltage Figure 16. Common-Mode Rejection Ratio
vs vs
Elapsed Time Free-Air Temperature
Figure 17. Equivalent Input Noise Voltage Figure 18. Total Harmonic Distortion
vs vs
Frequency Frequency
12 Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
100 kΩ
C2
C1
N1
500 pF
+
−
OUT
IN −
TL081
N2
N1
100 kΩ
1.5 kΩ
VCC −
+
−
OUT
IN −
IN +
VI
CL= 100 pF RL= 2 kΩ
+
−
OUT
VI
10 kΩ
1 kΩ
RLCL= 100 pF
+
−
OUT
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
www.ti.com
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
7 Parameter Measurement Information
Figure 19. Test Figure 1 Figure 20. Test Figure 2
Figure 21. Test Figure 3 Figure 22. Test Figure 4
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
C1
VCC +
IN +
VCC −
OFFSET N1
1080Ω1080Ω
IN −
TL081 Only
64Ω
128Ω
64Ω
OUT
OFFSET N2
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
8 Detailed Description
8.1 Overview
The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously
developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-
matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high
slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. Offset adjustment
and external compensation options are available within the TL08xx family.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to +125°C. The
M-suffix devices are characterized for operation over the full military temperature range of −55°C to +125°C.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices
have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when used in
audio signal applications.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 13-V/μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
14 Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
Vsup+
+VOUT
RF
VIN
RI
Vsup-
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
www.ti.com
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TL08x series of operational amplifiers can be used in countless applications. The few applications in this
section show principles used in all applications of these parts.
9.2 Typical Applications
9.2.1 Inverting Amplifier Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
Figure 23. Schematic for Inverting Amplifier Application
9.2.1.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.1.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩrange is desirable
because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much
current. This example will choose 10 kΩfor RI which means 36 kΩwill be used for RF. This was determined by
Equation 3.
(3)
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
Input −
+
+
−
TL084 Output C
Output BTL084
−
+
VCC +
Output ATL084
−
+
VCC +
TL084
VCC +
100 kΩ
100 µF
1µF
1 MΩ
100 kΩ
100 kΩ100 kΩ
VCC +
VCC +
+
−
+
−
88.4 kΩ
18 pF
VCC +
VCC −
18 pF
18 pF
88.4 kΩ
88.4 kΩ
1N4148
1N4148
VCC −
VCC+
1 kΩ
− 15 V
6 cos ωt
15 V
18 kΩ
(see Note A)
1 kΩ
6 sin ωt
1/2
TL082 1/2
TL082
18 kΩ
(see Note A)
+
−
−15 V
15 V
Output
1 kΩ
9.1 kΩ
3.3 kΩ
CF= 3.3 µF
RF= 100 kΩ
3.3 kΩ
TL081
f = 2πRFCF
1
+
−
R1
C1 C2
R3
C3 VCC −
VCC +
TL081
OutputInput R2
R1 = R2 = 2(R3) = 1.5 MΩ
fo=2πR1 C1
1= 1 kHz
C1 = C2 = = 110 pF
C3
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 0.5 1 1.5 2
Volts
Time (ms)
VIN
VOUT
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
Typical Applications (continued)
9.2.1.3 Application Curve
Figure 24. Input and output voltages of the inverting amplifier
9.3 System Examples
9.3.1 General Applications
Figure 25. 0.5-Hz Square-Wave Oscillator Figure 26. High-Q Notch Filter
A. These resistor values may be adjusted for a symmetrical output.
Figure 27. Audio-Distribution Amplifier Figure 28. 100-kHz Quadrature Oscillator
16 Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
Output BOutput A
+
−
1.5 kΩVCC −
43 kΩ
220 pF
43 kΩ
VCC +
30 kΩ
VCC +
43 kΩ
VCC −
+
−
16 kΩ
43 kΩ
Input
220 pF 220 pF
16 kΩ
+
−
VCC −
VCC +
30 kΩ
VCC +
43 kΩ
220 pF
43 kΩ
VCC −
+
−
1.5 kΩ
1/4
TL084
2 kHz/div
Second-Order Bandpass Filter
fo= 100 kHz, Q = 30, GAIN = 4
2 kHz/div
Cascaded Bandpass Filter
fo= 100 kHz, Q = 69, GAIN = 16
Output A
Output
B
1/4
TL084
1/4
TL084
1/4
TL084
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
www.ti.com
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
System Examples (continued)
Figure 29. Positive-Feedback Bandpass Filter
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum
Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques,(SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Examples.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
18 Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
+
RIN
RG RF
VOUT
VIN
NC
VCC+
IN1í
IN1+
VCCí
NC
OUT
NC
RG
RIN
RF
GND
VIN
VS-GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply) Ground (GND) plane on another layerVOUT
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
www.ti.com
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
11.2 Layout Examples
Figure 30. Operational Amplifier Board Layout for Noninverting Configuration
Figure 31. Operational Amplifier Schematic for Noninverting Configuration
Copyright © 1977–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
TL081
,
TL081A
,
TL081B
,
TL082
,
TL082A
TL082B
,
TL084
,
TL084A
,
TL084B
SLOS081I –FEBRUARY 1977–REVISED MAY 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For more information, see the following:
•Circuit Board Layout Techniques,SLOA089.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TL081 Click here Click here Click here Click here Click here
TL081A Click here Click here Click here Click here Click here
TL081B Click here Click here Click here Click here Click here
TL082 Click here Click here Click here Click here Click here
TL082A Click here Click here Click here Click here Click here
TL082B Click here Click here Click here Click here Click here
TL084 Click here Click here Click here Click here Click here
TL084A Click here Click here Click here Click here Click here
TL084B Click here Click here Click here Click here Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20 Submit Documentation Feedback Copyright © 1977–2015, Texas Instruments Incorporated
Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9851501Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9851501Q2A
TL082MFKB
5962-9851501QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA
TL082M
5962-9851503Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9851503Q2A
TL084
MFKB
5962-9851503QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC
A
TL084MJB
TL081ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081AC
TL081ACDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081AC
TL081ACP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081ACP
TL081BCD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081BC
TL081BCDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 081BC
TL081BCP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081BCP
TL081BCPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081BCP
TL081CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C
TL081CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C
TL081CP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP
TL081CPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL081CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T081
TL081ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I
TL081IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I
TL081IP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL081IP
TL082ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC
TL082ACP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082ACP
TL082ACPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082A
TL082BCD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC
TL082BCDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC
TL082BCDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC
TL082BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC
TL082BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC
TL082BCP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082BCP
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL082BCPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL082BCP
TL082CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C
TL082CDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C
TL082CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C
TL082CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C
TL082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C
TL082CP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL082CP
TL082CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082
TL082CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082
TL082CPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082
TL082CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082
TL082CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082
TL082ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I
TL082IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I
TL082IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I
TL082IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I
TL082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I
TL082IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL082IP
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL082IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL082IP
TL082IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z082
TL082MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9851501Q2A
TL082MFKB
TL082MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL082MJG
TL082MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA
TL082M
TL084ACD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC
TL084ACDE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC
TL084ACDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC
TL084ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC
TL084ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC
TL084ACN ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084ACN
TL084ACNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A
TL084BCD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC
TL084BCDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC
TL084BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC
TL084BCN ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084BCN
TL084BCNE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084BCN
TL084CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 5
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL084CDE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
TL084CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
TL084CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
TL084CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
TL084CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C
TL084CN ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084CN
TL084CNE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL084CN
TL084CNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084
TL084CPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084
TL084CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084
TL084CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084
TL084ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I
TL084IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I
TL084IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I
TL084IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I
TL084IN ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN
TL084INE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN
TL084MFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TL084MFK
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 6
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL084MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9851503Q2A
TL084
MFKB
TL084MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL084MJ
TL084MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC
A
TL084MJB
TL084QD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q
TL084QDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q
TL084QDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q
TL084QDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 7
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M :
•Catalog: TL082, TL084
•Automotive: TL082-Q1, TL082-Q1
•Military: TL082M, TL084M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL081ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL081BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL081CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082ACPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL082BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL082CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL082IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL084ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TL084BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL084IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL084QDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL081ACDR SOIC D 8 2500 340.5 338.1 20.6
TL081BCDR SOIC D 8 2500 340.5 338.1 20.6
TL081CDR SOIC D 8 2500 340.5 338.1 20.6
TL081CPSR SO PS 8 2000 367.0 367.0 38.0
TL081IDR SOIC D 8 2500 340.5 338.1 20.6
TL082ACDR SOIC D 8 2500 367.0 367.0 35.0
TL082ACDR SOIC D 8 2500 340.5 338.1 20.6
TL082ACPSR SO PS 8 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL082BCDR SOIC D 8 2500 340.5 338.1 20.6
TL082CDR SOIC D 8 2500 340.5 338.1 20.6
TL082CDR SOIC D 8 2500 367.0 367.0 35.0
TL082CPSR SO PS 8 2000 367.0 367.0 38.0
TL082CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL082IDR SOIC D 8 2500 367.0 367.0 35.0
TL082IDR SOIC D 8 2500 340.5 338.1 20.6
TL082IPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL084ACDR SOIC D 14 2500 367.0 367.0 38.0
TL084ACDR SOIC D 14 2500 333.2 345.9 28.6
TL084ACNSR SO NS 14 2000 367.0 367.0 38.0
TL084BCDR SOIC D 14 2500 333.2 345.9 28.6
TL084CDR SOIC D 14 2500 367.0 367.0 38.0
TL084CDR SOIC D 14 2500 333.2 345.9 28.6
TL084CDRG4 SOIC D 14 2500 333.2 345.9 28.6
TL084CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TL084IDR SOIC D 14 2500 333.2 345.9 28.6
TL084QDR SOIC D 14 2500 367.0 367.0 38.0
TL084QDRG4 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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