1
PF1245-01
Micro MINI S1C60N08/60R08
4-bit Single Chip Microcomputer
● S1C6200C Core CPU
● Built-in LCD Driver
● Serial Interface
■DESCRIPTION
The S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM (4,096
words × 12 bits), RAM (832 words × 4 bits), LCD driver, serial interface, event counter with dial input function,
watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consump-
tion, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems.
The S1C60R08 is a microcomputer with a CMOS 4-bit core CPU S1C6200C as main component, and a built-in
programmable RAM (ROM emulator). The S1C60R08 has almost the same functions as the S1C60N08/60A08.
The mask ROM in the S1C60N08/60A08 has been changed to a ROM emulator that allows the user to rewrite
programs using a Serial EEPROM.
■CONFIGULATION
The S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits.
Model
Supply voltage
Oscillation
circuit
Evaluation tool
S1C60N08
3.0 V
OSC1 only
(Single clock) S1C60R08
S1C60A08
3.0 V
OSC1 and OSC3
(Twin clock)
S1C60L08
1.5 V
OSC1 only
(Single clock)
–
■FEATURES
● OSC1 oscillation circuit................... Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.)
● OSC3 oscillation circuit................... CR o r ceramic oscillation circuit (∗1) 500 kHz (Typ.)
...S1C60A08/60R08 only
● Instruction set.................................. 108 types
● Instruction execution time............... CLK = 32.768 kHz: 153 µsec, 214 µsec, 366 µsec
(differs depending on instruction) CLK = 38.400 kHz: 130 µsec, 182 µsec, 313 µsec
(CLK: CPU operation frequency) CLK = 500 kHz: 10 µsec, 14 µsec, 24 µsec...S1C60A08/60R08 only
● ROM capacity ................................. 4,096 words × 12 bits
● Serial EEPROM interface ............... Built-in (Microchip 24AA65 two wire bus protocol interfaces
...S1C60R08 only
● RAM capacity.................................. 832 words × 4 bits
● Input ports ....................................... 9 bits (pull-down resistor can be added ∗1)
● Output ports .................................... 8 bits (BZ, BZ, FOUT and SIOF outputs are available ∗1)
● I/O ports .......................................... 8 bits (pull-down resistor is added during input data read-out)
● Serial interface................................ 1 port (8-bit clock synchronous system)
● LCD driver....................................... 48 segments × 4, 3, or 2 commons (∗1)
V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in)
● Time base counter .......................... Two types (timer and stopwatch)
● Watchdog timer............................... Built-in (∗1)
Low Voltage
Operation
Products
2
S1C60N08/60R08
● Event counter.................................. Two 8-bit inputs (dial input evaluation or independent)
● Sound generator ............................. Programmable in 8 sounds (8 frequencies)
Digital envelope built-in (∗1)
● Analog comparator.......................... Inverted input × 1, non-inverted input × 1
● Battery low detection circuit (BLD) .. Dual system (programmable in 8 values and a fixed value)
2.4 V, 2.2–2.55 V ...S1C60N08/60A08/60R08
1.2 V, 1.05–1.4 V ...S1C60L08
● External interrupt ............................ Input interrupt: 3 systems
● Internal interrupt.............................. Time base counter interrupt: 2 systems
Serial interface interrupt: 1 system
● Supply voltage ................................ 3.0 V (1.8–3.5 V) ...S1C60N08/60A08/60R08
1.5 V (0.9–1.7 V) ...S1C60L08
● Current consumption ...................... S1C60N08
Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.)
Run state:2.2 µA when CLK = 32.768 kHz (Typ.)
S1C60L08
Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.)
Run state:2.2 µA when CLK = 32.768 kHz (Typ.)
S1C60A08
Halt state: 1.1 µA when CLK = 32.768 kHz (Typ.)
Run state:3.0 µA when CLK = 32.768 kHz (Typ.)
Run state:50 µA when CLK = 500 kHz (Typ.)
S1C60R08
Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.)...Target for S1C60N08
1.1 µA when CLK = 32.768 kHz (Typ.)...Target for S1C60A08
Run state:6.5 µA when CLK = 32.768 kHz (Typ.)...Target for S1C60N08
7.5 µA when CLK = 32.768 kHz (Typ.)...Target for S1C60A08
Run state: 115 µA when CLK = 500 kHz (Typ.)...Target for S1C60A08 only
● Package .......................................... QFP5-100pin, QFP15-100pin (plastic) or chip
∗1: Can be selected with mask option
3
S1C60N08/60R08
■BLOCK DIAGRAM
S1C60R08
OSC1
OSC2
OSC3
OSC4
AMPP
AMPM
COM0–3
SEG0–47
V
DD
V
L1
V
L2
V
L3
CA
CB
V
S1
V
SS
K00–K03, K10
K20–K23
TEST
P00–P03
P10–P13
R00–R03
R10–R13
OTPRST
RESET
SIN
SOUT
SCLK
ERROUT
SDA
SCL
Core CPU S1C6200C
ROM Emulator
4,096 words × 12 bits
Interrupt
Generator
RAM
832 words × 4 bits
LCD Driver
48 SEG × 4 COM
Power
Controller
OSC
SVD
Event
Counter
Comparator
Sound
Generator
Serial I/F
Timer
Stopwatch
Input Port
I/O Port
Output Port
Serial EEPROM
Interface
System Reset
Control
Error Detecting
Circuit
OSC1
OSC2
∗ OSC3
∗ OSC4
AMPP
AMPM
COM0–3
SEG0–47
V
DD
V
L1
V
L2
V
L3
CA
CB
V
S1
V
SS
K00–K03, K10
K20–K23
TEST
RESET
P00–P03
P10–P13
R00–R03
R10–R13
SIN
SOUT
SCLK
Core CPU S1C6200C
ROM
4,096 words × 12 bits
System Reset
Control
Interrupt
Generator
RAM
832 words × 4 bits
LCD Driver
48 SEG × 4 COM
Power
Controller
OSC
SVD
Event
Counter
Comparator
Sound
Generator
Serial I/F
Timer
Stopwatch
Input Port
I/O Port
Output Port
S1C60N08/60L08/60A08
∗: S1C60A08 only
4
S1C60N08/60R08
■PIN CONFIGURATION
●S1C60N08/60L08/60A08 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COM1
COM0
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
No. Pin name 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
No. Pin name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
No. Pin name 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
K01
K00
SIN
SOUT
N.C.
SCLK
P03
P02
P01
P00
N.C.
N.C.
P13
P12
P11
P10
R03
R02
R01
R00
N.C. = No Connection
No. Pin name 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R12
R11
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V
L3
V
L2
V
L1
CA
CB
N.C.
COM3
COM2
No. Pin name
5180
31
50
INDEX
301
100
81
S1C60N08/60L08/60A08
QFP5-100pin
5175
26
50
INDEX
251
100
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
No. Pin name 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
K01
No. Pin name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
N.C.
SEG11
SEG10
No. Pin name 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
K00
SIN
SOUT
N.C.
SCLK
N.C.
P03
P02
P01
P00
P13
P12
P11
P10
R03
R02
R01
R00
R12
R11
N.C. = No Connection
No. Pin name 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V
L3
V
L2
V
L1
CA
CB
N.C.
COM3
COM2
COM1
COM0
No. Pin name
S1C60N08/60L08/60A08
QFP15-100pin
5
S1C60N08/60R08
●S1C60N08/60L08/60A08 Pin Description
Pin name
VDD
VSS
VS1
VL1
VL2
VL3
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–K03
K10
K20–K23
P00–P03
P10–P13
R00–R03
R10
R13
R11
R12
SIN
SOUT
SCLK
AMPP
AMPM
SEG0–47
COM0–3
RESET
TEST
Pin No. Function
Power supply pin (+)
Power supply pin (-)
Oscillation and internal logic system voltage output pin
LCD drive voltage output pin (approx. -1.05 V or 1/2·VL2)
LCD drive voltage output pin (2·VL1 or approx. -2.10 V)
LCD drive voltage output pin (3·VL1 or 3/2·VL2)
Boost capacitor connecting pin
Cryctal oscillation input pin
Crystal oscillation output pin
CR or ceramic oscillation input pin ∗ (N.C. for S1C60N08 and S1C60L08)
CR or ceramic oscillation output pin ∗ (N.C. for S1C60N08 and S1C60L08)
Input port pin
Input port pin
Input port pin
I/O port pin
I/O port pin
Output port pin
Output port pin or BZ output pin ∗
Output port pin or BZ output pin ∗
Output port pin or SIOF output pin ∗
Output port pin or FOUT output pin ∗
Serial interface data input pin
Serial interface data output pin
Serial interface clock input/output pin
Analog comparator non-inverted input pin
Analog comparator inverted input pin
LCD segment output pin
or DC output pin ∗
LCD common output pin (1/2, 1/3 or 1/4 duty are selectable ∗)
Initial reset input pin
Input pin for test
QFP5-100
92
85
89
95
94
93
96, 97
91
90
88
87
62–59
58
57–54
70–67
76–73
80–77
83
84
82
81
63
64
66
52
53
51–28, 26–3
2, 1, 100, 99
86
27
QFP15-100
90
83
87
93
92
91
94, 95
89
88
86
85
61–58
57
56–53
70–67
74–71
78–75
81
82
80
79
62
63
65
51
52
50–39, 37–26,
24–1
100–97
84
25
I/O
(I)
(I)
–
–
–
–
–
I
O
I
O
I
I
I
I/O
I/O
O
O
O
O
O
I
O
I/O
I
I
O
O
I
I
∗ Can be selected by mask option
6
S1C60N08/60R08
●S1C60R08 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COM1
COM0
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
No. Pin name 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
No. Pin name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
No. Pin name 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
K01
K00
SIN
SOUT
OTPRST
SCLK
P03
P02
P01
P00
SCL
SDA
P13
P12
P11
P10
R03
R02
R01
R00
No. Pin name 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R12
R11
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V
L3
V
L2
V
L1
CA
CB
ERROUT
COM3
COM2
No. Pin name
5180
31
50
INDEX
301
100
81
S1C60R08
QFP5-100pin
5175
26
50
INDEX
251
100
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
No. Pin name 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
K01
K00
No. Pin name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
No. Pin name 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SIN
SOUT
OTPRST
SCLK
P03
P02
P01
P00
SCL
SDA
P13
P12
P11
P10
R03
R02
R01
R00
R12
R11
No. Pin name 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V
L3
V
L2
V
L1
CA
CB
ERROUT
COM3
COM2
COM1
COM0
No. Pin name
S1C60R08
QFP15-100pin
7
S1C60N08/60R08
●S1C60R08 Pin Description
Pin name
V
DD
V
SS
V
S1
V
L1
V
L2
V
L3
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–K03
K10
K20–K23
P00–P03
P10–P13
R00–R03
R10
R11
R12
R13
SIN
SOUT
SCLK
AMPP
AMPM
SEG0–47
COM0–3
RESET
TEST
SCL
SDA
ERROUT
OTPRST
Pin No. Function
Power supply pin (+)
Power supply pin (-)
Oscillation and internal logic system voltage output pin
LCD drive voltage output pin (approx. -1.05 V or 1/2·V
L2
)
LCD drive voltage output pin (2·V
L1
or approx. -2.10 V)
LCD drive voltage output pin (3·V
L1
or 3/2·V
L2
)
Boost capacitor connecting pin
Crystal oscillation input pin
Crystal oscillation output pin
CR or ceramic oscillation input pin *
CR or ceramic oscillation output pin *
Input port pin
Input port pin
Input port pin
I/O port pin
I/O port pin
Output port pin
Output port pin or BZ output pin *
Output port pin or SIOF output pin *
Output port pin or FOUT output pin *
Output port pin or BZ output pin *
Serial interface data input pin
Serial interface data output pin
Serial interface clock input/output pin
Analog comparator non-inverted input pin
Analog comparator inverted input pin
LCD segment output pin or DC output pin *
LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *)
Initial reset input pin
Input pin for test
Serial EEPROM clock output pin
Serial EEPROM data input/output pin
Errout detecting singnal output for download program
Cold reset pin for re-start download program from EEPROM
QFP5-100
92
85
89
95
94
93
96, 97
91
90
88
87
62–59
58
57–54
70–67
76–73
80–77
83
82
81
84
63
64
66
52
53
51–28, 26–3
2, 1, 100, 99
86
27
71
72
98
65
QFP15-100
90
83
87
93
92
91
94, 95
89
88
86
85
60–57
56
55–52
68–65
74–71
78–75
81
80
79
82
61
62
64
50
51
49–26, 24–1
100–97
84
25
69
70
96
63
I/O
(I)
(I)
–
–
–
–
–
I
O
I
O
I
I
I
I/O
I/O
O
O
O
O
O
I
O
I/O
I
I
O
O
I
I
O
I/O
O
I
∗ Can be selected by mask option
8
S1C60N08/60R08
■OPTION LIST
1. DEVICE TYPE
• DEVICE TYPE ................................... ■■ 1. S1C60N08 (Normal Type)
■■ 2. S1C60L08 (Low Power Type) (Note)
■■ 3. S1C60A08 (Twin Clock Type)
• CLOCK TYPE (for Evaluation board) ■■ 1. 32 kHz ■■ 2. 38 kHz
2. OSC3 SYSTEM CLOCK (only for S1C60A08)
■■ 1. CR ■■ 2. Ceramic
3. MULTIPLE KEY ENTRY RESET
• COMBINATION.................................. ■■ 1. Not Use
■■ 2. Use K00, K01
■■ 3. Use K00, K01, K02
■■ 4. Use K00, K01, K02, K03
• TIME AUTHORIZE............................. ■■ 1. Use ■■ 2. Not Use
4. WATCHDOG TIMER ■■ 1. Use ■■ 2. Not Use
5. INPUT INTERRUPT NOISE REJECTOR
• K00–K03 ............................................ ■■ 1. Use ■■ 2. Not Use
• K10 ..................................................... ■■ 1. Use ■■ 2. Not Use
• K20–K23 ............................................ ■■ 1. Use ■■ 2. Not Use
6. INPUT PORT PULL DOWN RESISTOR
• K00 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K01 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K02 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K03 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K10 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K20 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K21 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K22 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
• K23 ..................................................... ■■ 1. With Resistor ■■ 2. Gate Direct
7. OUTPUT PORT SPECIFICATION (R00–R03)
• R00..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R01..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R02..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R03..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
8. R10 SPECIFICATION
• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• OUTPUT TYPE.................................. ■■ 1. DC Output ■■ 2. Buzzer Output
9. R11 SPECIFICATION
• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• OUTPUT TYPE.................................. ■■ 1. DC Output ■■ 2. SIO Flag
10.R12 SPECIFICATION
• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• OUTPUT TYPE.................................. ■■ 1. DC Output
■■ 2. FOUT 32768 or 38400 [Hz]
■■ 3. FOUT 16384 or 19200 [Hz]
■■ 4. FOUT 8192 or 9600 [Hz]
■■ 5. FOUT 4096 or 4800 [Hz]
■■ 6. FOUT 2048 or 2400 [Hz]
■■ 7. FOUT 1024 or 1200 [Hz]
■■ 8. FOUT 512 or 600 [Hz]
■■ 9. FOUT 256 or 300 [Hz]
9
S1C60N08/60R08
11.R13 SPECIFICATION
• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• OUTPUT TYPE.................................. ■■ 1. DC Output
■■ 2. Buzzer Inverted Output (R13 Control)
■■ 3. Buzzer Inverted Output (R10 Control)
12.I/O PORT SPECIFICATION
• P00 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P01 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P02 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P03 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P10 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P11 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P12 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P13 ..................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
13.SIN PULL DOWN RESISTOR ■■ 1. With Resistor ■■ 2. Gate Direct
14.SOUT SPECIFICATION ■■ 1. Complementary ■■ 2. Pch-OpenDrain
15.SCLK SPECIFICATION
• PULL DOWN RESISTOR .................. ■■ 1. With Resistor ■■ 2. Gate Direct
• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• LOGIC ................................................ ■■ 1. Positive ■■ 2. Negative
16.SIO DATA PERMUTATION ■■ 1. MSB First ■■ 2. LSB First
17.EVENT COUNTER NOISE REJECTOR
■■ 1. 2048 or 2400 [Hz] ■■ 2. 256 or 300 [Hz]
18.LCD SPECIFICATION
• BIAS SELECTION
S1C60N08.......................................... ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V
■■ 2. 1/3 Bias, Regulator Not Used, LCD 3 V
■■ 3. 1/2 Bias, Regulator Not Used, LCD 3 V
■■ 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V
S1C60L08 (Note) ............................... ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V
■■ 2. 1/2 Bias, Regulator Not Used, LCD 3 V
■■ 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V
S1C60A08 .......................................... ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V
■■ 2. 1/3 Bias, Regulator Not Used, LCD 3 V
■■ 3. 1/2 Bias, Regulator Not Used, LCD 3 V
■■ 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V
• DUTY SELECTION............................ ■■ 1. 1/4 Duty
■■ 2. 1/3 Duty
■■ 3. 1/2 Duty
19.SEGMENT MEMORY ADDRESS ■■ 1. 0 Page (040–06F) ■■ 2. 2 Page (240–26F)
Note: The S1C60R08 does not support the S1C60L08.
10
S1C60N08/60R08
■S1C60R08 ROM EMULATOR/ROM EMULATOR PROGRAMMER
The S1C60R08 has a built-in ROM emulator, which is constructed by RAM, to emulate mask ROM. The ROM
emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read
by the CPU. This chapter explain the ROM emulator and the Programmer circuit.
●Configuration of ROM Emulator
The built-in ROM emulator is the same structure with the mask ROM built-in S1C60N08. And used for loading the
user-program. That has a capacity of 4,096 steps × 12 bits. The program area consists of 16 (0–15) pages × 256
(00H–FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The
interrupt vector is allocated to page 1, steps 01H–0FH.
Step 00H
Step 0FH
Step 10H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Page 0
Page 1
Page 2
Page 3
Page 15
Step 01H
The ROM emulator data is downloaded from an external Serial EEPROM through the Programmer circuit. After
power on or a HIGH pulse is input to the OTPRST pin, the ROM emulator data is initialized and downloading will
be started.
●Configuration of ROM Emulator Programmer
The ROM emulator data is written through the Programmer. The Programmer supports data transmit/receive
communication with Serial EEPROM, interface data error check and system reset signal generation.
V
SS
CPU
V
DD
OTPRST
SDA
SCL
ERROUT
Error Detect
Circuit
OSC1 RESET
S1C60R08
System reset
Configuration
flag
CPU and
peripheral circuit
ROM Emulator
4,096 × 12 bits
EEPROM
Interface Circuit
A2
A1
A0
Serial
EEPROM
Terminals
The Programmer uses the following input/output terminals.
SCL: Serial EEPROM control clock output terminal
SDA: Serial EEPROM data transmit/receive terminal
ERROUT: Data check result output terminal
OTPRST: Data re-loading start input terminal
11
S1C60N08/60R08
●Operation
The S1C60R08 has two operation modes,
• Programming mode: Load the data from the Serial EEPROM
• Normal mode: Work as if the mask ROM type
The following describes how to operate the S1C60R08.
1) Make an application software.
2) Convert the software to the Serial EEPROM format with winedg in the S1C60R08 package.
3) Write the program which is converted to the Serial EEPROM format to the Serial EEPROM.
4) Set up the S1C60R08, the Serial EEPROM and the other peripheral components on the user target
application. (The example is described in "BASIC EXTERNAL CONNECTION DIAGRAM".)
5) The application power on.
6) The S1C60R08 enters to the Programming mode, and starts data loading from the Serial EEPROM to the
built-in ROM emulator automatically. In the loading, internal circuit is kept as system reset condition ex-
cept the Programmer. And data error checking is done at the same time.
7) If the data error happens, the ERROUT pin goes HIGH level and data loading is terminated.
8) If the data has loaded without any error, the S1C60R08 enters to the Normal mode automatically. Then
the CPU read the ROM emulator data as the instruction and start to run as if the mask ROM type.
9) If you want to re-load the data, input a HIGH pulse to the OTPRST pin. Then the S1C60R08 enters to
Programming mode and starts re-loading.
■SUMMARY OF NOTES
●Target Type for S1C60N08 Series
The S1C60N08 has 3 types (S1C60N08, S1C60A08 and S1C60L08).
In these models, the S1C60R08 supports the following 2 types as the ROM emulator model.
S1C60N08 VDD = 3.0 V (Typ.), OSC1
S1C60A08 VDD = 3.0 V (Typ.), OSC1/OSC3
Refer the "S1C60N08/60R08 Technical Manual".
●Mask/Segment Option
The S1C60R08 can load ROM emulator data. But cannot load the mask option and segment option. Therefore
customer must make the function option data and segment option data by the S1C60R08 development tool at
first. Then send the data to SEIKO EPSON and order the mask. SEIKO EPSON makes the S1C60R08 with a
customized option according to this request.
●Serial EEPROM
The external Serial EEPROM is necessary for programming the ROM emulator data, and this component
is recommended.
Recommended component: AK6010A/12A (AKM)
M24C64/32 (SGS-THOMSON)
BR24C64 (ROHM)
24AA64 (Microchip)
Note: Use larger EEPROM than program memory size.
12
S1C60N08/60R08
■ELECTRICAL CHARACTERISTICS
●Absolute Maximum Ratings
S1C60N08/60A08/60R08
Rating
Supply voltage
Input voltage (1)
Input voltage (2)
Permissible total output current
∗1
Operating temperature
Storage temperature
Soldering temperature / time
Permissible dissipation ∗2
(VDD=0V)
Symbol
VSS
VI
VIOSC
ΣIVSS
Topr
Tstg
Tsol
PD
Value
-5.0 to 0.5
VSS-0.3 to 0.5
VS1-0.3 to 0.5
10
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
∗1:
∗2:
The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
In case of plastic package.
S1C60L08
Rating
Supply voltage
Input voltage (1)
Input voltage (2)
Permissible total output current
∗1
Operating temperature
Storage temperature
Soldering temperature / time
Permissible dissipation ∗2
(VDD=0V)
Symbol
VSS
VI
VIOSC
ΣIVSS
Topr
Tstg
Tsol
PD
Value
-2.0 to 0.5
VSS-0.3 to 0.5
VS1-0.3 to 0.5
10
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
∗1:
∗2:
The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
In case of plastic package.
●Recommended Operating Conditions
S1C60N08
Condition
Supply voltage
Oscillation frequency
(Ta=-20 to 70°C)
Symbol
VSS
fOSC1
Unit
V
kHz
kHz
Max.
-1.8
–
–
Typ.
-3.0
32.768
38.400
Min.
-3.5
–
–
Remark
VDD=0V
Either one is selected
S1C60L08
Condition
Supply voltage
Oscillation frequency
∗1:
∗2:
(Ta=-20 to 70°C)
Symbol
VSS
fOSC1
Unit
V
V
V
kHz
kHz
Max.
-1.1
-0.9 ∗2
-1.2
–
–
Typ.
-1.5
-1.5
-1.5
32.768
38.400
Min.
-1.7
-1.7
-1.7
–
–
When switching to heavy load protection mode.
The possibility of LCD panel display differs depending on the characteristics of the LCD panel.
Remark
VDD=0V
VDD=0V, with software control ∗1
VDD=0V, when analog comparator is used
Either one is selected
S1C60A08/60R08
Condition
Supply voltage
Oscillation frequency (1)
Oscillation frequency (2)
(Ta=-20 to 70°C)
Symbol
V
SS
f
OSC1
f
OSC3
Unit
V
kHz
kHz
kHz
Max.
-2.2
∗1
–
–
600
Typ.
-3.0
32.768
38.400
500
Min.
-3.5
–
–
50
Remark
V
DD
=0V
Either one is selected
duty 50±5%, V
SS
=-2.2 to -3.5V
∗1: -1.8V when the S1C60R08 is used as the S1C60N08.
13
S1C60N08/60R08
●DC Characteristics
S1C60N08/60A08/60R08
Characteristic
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
High level output current (1)
High level output current (2)
Low level output current (1)
Low level output current (2)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C5=0.1µF)
Symbol
VIH1
VIH2
VIL1
VIL2
IIH1
IIH2
IIH3
IIL
IOH1
IOH2
IOL1
IOL2
IOH3
IOL3
IOH4
IOL4
IOH5
IOL5
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Max.
0
0
0.8·VSS
0.9·VSS
0.5
16
100
0
-1.8
-0.9
-3
-3
-200
Typ.Min.
0.2·VSS
0.1·VSS
VSS
VSS
0
4
25
-0.5
6.0
3.0
3
3
200
Condition
K00–03, K10, K20–23, P00–03, P10–13
SIN, (SDA) ∗1
SCLK, RESET, TEST, (OTPRST) ∗1
K00–03, K10, K20–23, P00–03, P10–13
SIN, (SDA) ∗1
SCLK, RESET, TEST, (OTPRST) ∗1
VIH1=0V K00–03, K10, K20–23, P00–03, P10–13
No pull-down SIN, SCLK, AMPP, AMPM
(SDA) ∗1
VIH2=0V K00–03, K10, K20–23
With pull-down SIN, SCLK
VIH3=0V P00–03, P10–13, RESET, TEST
With pull-down (OTPRST) ∗1
VIL=VSS K00–03, K10, K20–23, P00–03, P10–13
SIN, SCLK, AMPP, AMPM, RESET, TEST
(OTPRST), (SDA) ∗1
VOH1=0.1·VSS R10, R11, R13
VOH2=0.1·VSS R00–03, R12, P00–03, P10–13, SOUT
SCLK, (SDA), (ERROUT), (SCL) ∗1
VOL1=0.9·VSS R10, R11, R13
VOL2=0.9·VSS R00–03, R12, P00–03, P10–13, SOUT
SCLK, (SDA), (ERROUT), (SCL) ∗1
VOH3=-0.05V COM0–3
VOL3=VL3+0.05V
VOH4=-0.05V SEG0–47
VOL4=VL3+0.05V
VOH5=0.1·VSS SEG0–47
VOL5=0.9·VSS
∗1: ( ) indicate the S1C60R08 pins.
S1C60L08
Characteristic
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
High level output current (1)
High level output current (2)
Low level output current (1)
Low level output current (2)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C5=0.1µF)
Symbol
VIH1
VIH2
VIL1
VIL2
IIH1
IIH2
IIH3
IIL
IOH1
IOH2
IOL1
IOL2
IOH3
IOL3
IOH4
IOL4
IOH5
IOL5
Unit
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Max.
0
0
0.8·VSS
0.9·VSS
0.5
10
60
0
-300
-150
-3
-3
-100
Typ.Min.
0.2·VSS
0.1·VSS
VSS
VSS
0
2
12
-0.5
1400
700
3
3
100
Condition
K00–03, K10, K20–23, P00–03, P10–13
SIN
SCLK, RESET, TEST
K00–03, K10, K20–23, P00–03, P10–13
SIN
SCLK, RESET, TEST
VIH1=0V K00–03, K10, K20–23, P00–03, P10–13
No pull-down SIN, SCLK
AMPP, AMPM
VIH2=0V K00–03, K10, K20–23
With pull-down SIN, SCLK
VIH3=0V P00–03, P10–13
With pull-down RESET, TEST
VIL=VSS K00–03, K10, K20–23, P00–03, P10–13
SIN, SCLK, AMPP, AMPM
RESET, TEST
VOH1=0.1·VSS R10, R11, R13
VOH2=0.1·VSS R00–03, R12, P00–03, P10–13
SOUT, SCLK
VOL1=0.9·VSS R10, R11, R13
VOL2=0.9·VSS R00–03, R12, P00–03, P10–13
SOUT, SCLK
VOH3=-0.05V COM0–3
VOL3=VL3+0.05V
VOH4=-0.05V SEG0–47
VOL4=VL3+0.05V
VOH5=0.1·VSS SEG0–47
VOL5=0.9·VSS
14
S1C60N08/60R08
●Analog Circuit Characteristics and Current Consumption
S1C60N08 (Normal Operating Mode)
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
Max.
1/2·V
L2
×0.9
-1.90
3/2·V
L2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
2.0
4.0
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
1.0
2.2
Min.
1/2·V
L2
- 0.1
-2.30
3/2·V
L2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
S1C60N08 (Heavy Load Protection Mode)
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
Max.
1/2·V
L2
×0.9
-1.90
3/2·V
L2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
20
25
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
10
12
Min.
1/2·V
L2
- 0.1
-2.30
3/2·V
L2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
15
S1C60N08/60R08
S1C60L08 (Normal Operating Mode)
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-1.5V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
Max.
-0.95
2·V
L1
×0.9
3·V
L1
×0.9
-0.95
-1.00
-1.05
-1.10
-1.15
-1.20
-1.25
-1.30
100
-1.10
100
V
DD
-0.9
20
3
2.0
4.0
Typ.
-1.05
-1.05
-1.10
-1.15
-1.20
-1.25
-1.30
-1.35
-1.40
-1.20
1.0
2.2
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-1.15
-1.20
-1.25
-1.30
-1.35
-1.40
-1.45
-1.50
-1.30
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.1V
V
IM
=V
IP
±30mV
During HALT Without
During operation
∗2
panel load
S1C60L08 (Heavy Load Protection Mode)
Max.
-0.95
2·V
L1
×0.85
3·V
L1
×0.85
-0.95
-1.00
-1.05
-1.10
-1.15
-1.20
-1.25
-1.30
100
-1.10
100
V
DD
-0.9
20
3
10
15
Typ.
-1.05
-1.05
-1.10
-1.15
-1.20
-1.25
-1.30
-1.35
-1.40
-1.20
6.5
8.5
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-1.15
-1.20
-1.25
-1.30
-1.35
-1.40
-1.45
-1.50
-1.30
V
SS
+0.3
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-1.5V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.1V
V
IM
=V
IP
±30mV
During HALT Without
During operation
∗2
panel load
16
S1C60N08/60R08
S1C60A08 (Normal Operating Mode)
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
tB
V
BS
tBS
V
IP
V
IM
V
OF
tAMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
µA
Max.
-0.95
2·V
L1
×0.9
3·V
L1
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
2.0
5.0
70
Typ.
-1.05
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
1.1
3.0
50
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
During operation at 500kHz
∗2
S1C60A08 (Heavy Load Protection Mode)
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
tB
V
BS
tBS
V
IP
V
IM
V
OF
tAMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
µA
Max.
-0.95
2·V
L1
×0.9
3·V
L1
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
10
15
75
Typ.
-1.05
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
6.5
8.5
55
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
During operation at 500kHz
∗2
17
S1C60N08/60R08
S1C60R08 (Normal Operating Mode) Target: S1C60N08
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
Max.
1/2·V
L2
×0.9
-1.90
3/2·V
L2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
2.0
9.0
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
1.0
6.5
Min.
1/2·V
L2
- 0.1
-2.30
3/2·V
L2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
S1C60R08 (Heavy Load Protection Mode) Target: S1C60N08
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
t
B
V
BS
t
BS
V
IP
V
IM
V
OF
t
AMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
Max.
1/2·V
L2
×0.9
-1.90
3/2·V
L2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
10
20
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
6.5
11.5
Min.
1/2·V
L2
- 0.1
-2.30
3/2·V
L2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
18
S1C60N08/60R08
S1C60R08 (Normal Operating Mode) Target: S1C60A08
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
tB
V
BS
tBS
V
IP
V
IM
V
OF
tAMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
µA
Max.
-0.95
2·V
L1
×0.9
3·V
L1
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
2.0
10
150
Typ.
-1.05
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
1.1
7.5
115
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
During operation at 500kHz
∗2
S1C60R08 (Heavy Load Protection Mode) Target: S1C60A08
Characteristic
LCD drive voltage
BLD voltage
∗1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
∗1:
∗2:
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, f
OSC1
=32.768kHz, Ta=25°C, C
G
=25pF, V
S1
/V
L1
–V
L3
are internal voltage, C
1
–C
5
=0.1µF)
Symbol
V
L1
V
L2
V
L3
V
B0
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B7
tB
V
BS
tBS
V
IP
V
IM
V
OF
tAMP
I
OP
Unit
V
V
V
V
V
V
V
V
V
V
V
µsec
V
µsec
V
mV
msec
µA
µA
µA
Max.
-0.95
2·V
L1
×0.9
3·V
L1
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
V
DD
-0.9
10
3
10
20
160
Typ.
-1.05
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
6.5
12.5
120
Min.
-1.15
2·V
L1
- 0.1
3·V
L1
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
V
SS
+0.3
The relationships among V
B0
–V
B7
are V
B0
>V
B1
>V
B2
>...V
B5
>V
B6
>V
B7
.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 MΩ load resistor between V
DD
and V
L1
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L2
(without panel load)
Connect 1 MΩ load resistor between V
DD
and V
L3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
V
IP
=-1.5V
V
IM
=V
IP
±15mV
During HALT Without
During operation
∗2
panel load
During operation at 500kHz
∗2
19
S1C60N08/60R08
●Oscillation Characteristics
Oscillation characteristics will vary according to different conditions (elements used, boad pattern). Use the following char-
acteristics are as reference values.
S1C60N08/60R08 (OSC1 Crystal Oscillation)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
C
D
∆f/∆V
∆f/∆IC
∆f/∆C
G
V
hho
R
leak
Unit
V
V
pF
ppm
ppm
ppm
V
MΩ
Max.
5
10
-3.5
Typ.
20
45
Min.
-1.8
-1.8
-10
35
200
Condition
t
sta≤5sec (V
SS
)
t
stp≤10sec (V
SS
)
Including the parasitic capacitance inside the chip
V
SS
=-1.8 to -3.5V
C
G
=5 to 25pF
(V
SS
)
Between OSC1 and V
DD
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, Crystal: Q13MC146, C
G
=25pF, C
D
=built-in, Ta=25°C)
S1C60L08 (OSC1 Crystal Oscillation)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
∗1:
Symbol
Vsta
Vstp
CD
∆f/∆V
∆f/∆IC
∆f/∆CG
Vhho
Rleak
Unit
V
V
pF
ppm
ppm
ppm
V
MΩ
Max.
5
10
-1.7
Typ.
20
45
Min.
-1.1
-1.1
(-0.9)∗1
-10
35
200
Parentheses indicate value for operation in heavy load protection mode.
Condition
tsta≤5sec (VSS)
tstp≤10sec (VSS)
Including the parasitic capacitance inside the chip
VSS=-1.1 (-0.9)∗1 to -1.7V
CG=5 to 25pF
(VSS)
Between OSC1 and VDD
(Unless otherwise specified: VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25°C)
S1C60A08 (OSC1 Crystal Oscillation)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
C
D
∆f/∆V
∆f/∆IC
∆f/∆C
G
V
hho
R
leak
Unit
V
V
pF
ppm
ppm
ppm
V
MΩ
Max.
5
10
-3.5
Typ.
20
45
Min.
-2.2
-2.2
-10
35
200
Condition
t
sta≤5sec (V
SS
)
t
stp≤10sec (V
SS
)
Including the parasitic capacitance inside the chip
V
SS
=-2.2 to -3.5V
C
G
=5 to 25pF
(V
SS
)
Between OSC1 and V
DD
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, Crystal: Q13MC146, C
G
=25pF, C
D
=built-in, Ta=25°C)
S1C60A08/60R08 (OSC3 CR Oscillation)
Characteristic
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
f
OSC3
Vsta
t
sta
Vstp
Unit
%
V
msec
V
Max.
30
3
Typ.
480kHz
Min.
-30
-2.2
-2.2
Condition
(V
SS
)
V
SS
=-2.2 to -3.5V
(V
SS
)
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, R
CR
=82kΩ, Ta=25°C)
S1C60A08/60R08 (OSC3 Ceramic Oscillation)
Characteristic
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
Vsta
t
sta
Vstp
Unit
V
msec
V
Max.
5
Typ.Min.
-2.2
-2.2
Condition
(V
SS
)
V
SS
=-2.2 to -3.5V
(V
SS
)
(Unless otherwise specified: V
DD
=0V, V
SS
=-3.0V, Ceramic oscillator: 500kHz, C
GC
=C
DC
=100pF, Ta=25°C)
20
S1C60N08/60R08
■BASIC EXTERNAL CONNECTION DIAGRAM
S1C60N08 and S1C60L08
K00
:
K03
K10
K20
:
K23
P00
:
P03
P10
:
P13
SIN
SOUT
SCLK
AMPM
AMPP
R00
:
R03
R11 (LAMP)
R12 (FOUT)
SEG0
SEG47
COM0
COM3
R10 (BZ)
R13 (BZ)
CB
CA
VL1
VL2
VL3
VDD
OSC1
OSC2
VS1
OSC3
OSC4
RESET
TEST
VSS
+
Lamp Piezo
C1
C5
N.C. 3.0 V (S1C60N08)
or
1.5 V (S1C60L08)
N.C.
CP
CGX
X'tal
S1C60N08
S1C60L08
LCD panel
I/O
SIO
O
I
X'tal
CGX
C1
C2
C3
C4
C5
CP
RA1
RA2
Crystal oscillator
Trimmer capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistor
Protection resistor
32.768 kHz or 38.400 kHz,
CI = 35 kΩ
5–25 pF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
100 Ω
100 Ω
R13 (BZ)
R10 (BZ)
RA2
When the piezoelectric buzzer is driven directly
RA1
Piezo
[The potential of the substrate
(back of the chip) is VDD.]
Capacitors (C2–C4) are connected.
Connection depending on power supply
and LCD panel specification.
Note: The above tables are simply an example, and are not guaranteed to work.
21
S1C60N08/60R08
S1C60A08
K00
:
K03
K10
K20
:
K23
P00
:
P03
P10
:
P13
SIN
SOUT
SCLK
AMPM
AMPP
R00
:
R03
R11 (LAMP)
R12 (FOUT)
SEG0
SEG47
COM0
COM3
R10 (BZ)
R13 (BZ)
CB
CA
V
L1
V
L2
V
L3
V
DD
OSC1
OSC2
V
S1
OSC3
OSC4
RESET
TEST
V
SS
+
Lamp Piezo
C
1
C
5
CR
C
GC
R
CR
C
DC
3.0 V
C
P
C
GX
X'tal
S1C60A08
LCD panel
I/O
SIO
O
I
X'tal
C
GX
CR
C
GC
C
DC
R
CR
C
1
C
2
C
3
C
4
C
5
C
P
R
A1
R
A2
Crystal oscillator
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for CR oscillation
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistor
Protection resistor
32.768 kHz or 38.400 kHz,
C
I
= 35 kΩ
5–25 pF
500 kHz
100 pF
100 pF
82 kΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
100 Ω
100 Ω
R13 (BZ)
R10 (BZ)
R
A2
When the piezoelectric buzzer
is driven directly
R
A1
Piezo
∗1
∗1 Ceramic oscillation
∗2 CR oscillation
∗2
[The potential of the substrate
(back of the chip) is VDD.]
Capacitors (C
2
–C
4
) are connected.
Connection depending on power supply
and LCD panel specification.
Note: The above tables are simply an example, and are not guaranteed to work.
22
S1C60N08/60R08
S1C60R08 (Target for S1C60N08)
K00
:
K03
K10
K20
:
K23
P00
:
P03
P10
:
P13
SIN
SOUT
SCLK
OTPRST
AMPM
AMPP
R11 (LAMP)
R12 (FOUT)
SEG0
SEG47
COM0
COM3
R10 (BZ)
R13 (BZ)
CB
CA
V
L1
V
L2
V
L3
V
DD
OSC1
OSC2
V
S1
OSC3
OSC4
RESET
TEST
V
SS
+
Lamp Piezo
C
1
C
5
N.C.
N.C.
C
P
C
GX
X'tal
S1C60R08
LCD panel
3.0 V
I/O
SIO
I
X'tal
C
GX
C
1
C
2
C
3
C
4
C
5
C
P
R
A1
R
A2
IC1
Crystal oscillator
Trimmer capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistor
Protection resistor
Serial EEPROM
32.768 kHz or 38.400 kHz
5–25 pF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
100 Ω
100 Ω
∗
R13 (BZ)
R10 (BZ)
R
A2
R
A1
Piezo
ERROUT
SCL
SDA
A0
A1
A2
V
SS
V
CC
NC
SCL
SDA
IC1
When the piezoelectric buzzer
is driven directly
∗: See "Serial EEPROM"
[The potential of the substrate
(back of the chip) is VDD.]
Capacitors (C
2
–C
4
) are connected.
Connection depending on power supply
and LCD panel specification.
Note: The above tables are simply an example, and are not guaranteed to work.
23
S1C60N08/60R08
S1C60R08 (Target for S1C60A08)
K00
:
K03
K10
K20
:
K23
P00
:
P03
P10
:
P13
SIN
SOUT
SCLK
OTPRST
AMPM
AMPP
SEG0
SEG47
COM0
COM3
CB
CA
VL1
VL2
VL3
VDD
OSC1
OSC2
VS1
OSC3
OSC4
RESET
TEST
VSS
+
C1
C5
CR
CGC RCR
CDC
3.0 V
CP
CGX
X'tal
S1C60R08
LCD panel
I/O
SIO
I
R13 (BZ)
R10 (BZ)
RA2RA1
Piezo
∗1
∗1 Ceramic oscillation
∗2 CR oscillation
∗2
R11 (LAMP)
R12 (FOUT)
R10 (BZ)
R13 (BZ)
Lamp Piezo
ERROUT
SCL
SDA
A0
A1
A2
VSS
VCC
NC
SCL
SDA
IC1
X'tal
CGX
CR
CGC
CDC
RCR
C1
C2
C3
C4
C5
CP
RA1
RA2
IC1
Crystal oscillator
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for CR oscillation
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistor
Protection resistor
Serial EEPROM
32.768 kHz or 38.400 kHz
5–25 pF
500 kHz
100 pF
100 pF
82 kΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
100 Ω
100 Ω
∗
When the piezoelectric buzzer
is driven directly
∗: See "Serial EEPROM"
[The potential of the substrate
(back of the chip) is VDD.]
Capacitors (C2–C4) are connected.
Connection depending on power supply
and LCD panel specification.
Note: The above tables are simply an example, and are not guaranteed to work.
24
S1C60N08/60R08
■PACKAGE
Plastic QFP5-100pin
20±0.1
25.6±0.4
5180
14±0.1
19.6±0.4
31
50
INDEX
0.3±0.1 301
100
81
2.7±0.1
0.26
3.4max
2.8
1.5
0°
12°
0.15±0.05
0.65
Plastic QFP15-100pin
14±0.1
16±0.4
5175
14±0.1
16±0.4
26
50
INDEX
0.18 251
100
76
1.4±0.1
0.1
1.7max
1
0.5±0.2
0°
10°
0.125
0.5 +0.1
–0.05
+0.05
–0.025
Unit: mm
25
S1C60N08/60R08
■PAD LAYOUT
●S1C60N08/60L08/60A08 Diagram of Pad Layout
X
(0, 0)
Die No.
Y
3.73 mm
3.74 mm
15101520
25
30
35
40
45
50 55 60 65 70
75
80
85
90
95
Chip thickness:400 µm
Pad opening: 95 µm
●S1C60N08/60L08/60A08 Pad Coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pad name
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
K01
K00
SIN
SOUT
SCLK
P03
P02
P01
P00
P13
P12
P11
P10
R03
R02
R01
R00
R12
R11
R10
R13
VSS
RESET
X
1,294
1,164
1,034
904
774
644
514
384
254
124
-7
-137
-267
-397
-527
-657
-787
-917
-1,048
-1,178
-1,308
-1,438
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
Y
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,699
1,686
1,556
1,426
1,296
1,166
1,036
812
682
457
327
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pad name
OSC4 *
OSC3 *
VS1
OSC2
OSC1
VDD
VL3
VL2
VL1
CA
CB
COM3
COM2
COM1
COM0
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
X
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,704
-1,415
-1,285
-1,155
-1,025
-895
-765
-635
-505
-375
-245
-115
15
145
275
405
535
665
Y
176
46
-84
-214
-344
-503
-633
-763
-893
-1,022
-1,153
-1,283
-1,413
-1,543
-1,673
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Pad name
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
X
795
925
1,055
1,185
1,315
1,445
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
1,704
Y
-1,699
-1,699
-1,699
-1,699
-1,699
-1,699
-1,621
-1,465
-1,310
-1,180
-1,050
-920
-790
-660
-530
-400
-270
-140
-10
120
250
380
510
640
770
900
1,030
1,160
1,290
1,420
1,550
1,680
Unit: µm
∗: S1C60A08 only
26
S1C60N08/60R08
●S1C60R08 Diagram of Pad Layout
Y
X
(0, 0)
7.00 mm
8.35 mm
1
5
1015
20
25 Die No.
30
35
40
45
50
55 60 65 70 75
80
85
90
95
100
Chip thickness:400 µm
Pad opening: 95 µm
●S1C60R08 Pad Coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pad name
AMPP
AMPM
K23
K22
K21
K20
K10
K03
K02
K01
K00
SIN
SOUT
OTPRST
SCLK
P03
P02
P01
P00
SCL
SDA
P13
P12
P11
P10
R03
R02
R01
R00
R12
R11
R10
R13
V
SS
X
2,893
2,638
2,382
2,127
1,871
1,616
1,360
1,105
849
594
339
83
-85
-260
-438
-683
-863
-1,064
-1,275
-1,566
-1,821
-2,126
-2,405
-2,685
-2,978
-3,686
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
Y
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,330
3,090
2,787
2,657
2,527
2,288
2,064
1,599
1,470
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pad name
REST
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V
L3
V
L2
V
L1
CA
CB
ERROUT
COM3
COM2
COM1
COM0
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
X
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-4,005
-3,420
-3,116
-2,811
-2,507
-2,203
-1,899
-1,595
-1,290
-986
-682
-378
-74
230
534
838
1,142
1,446
Y
1,340
733
517
300
-576
-793
-958
-1,174
-1,391
-1,607
-1,824
-2,040
-2,241
-2,429
-2,645
-2,862
-3,088
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad name
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
TEST
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
X
1,751
2,055
2,359
2,663
2,967
3,272
3,661
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
4,005
Y
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,330
-3,049
-2,590
-2,355
-2,119
-1,883
-1,647
-1,411
-1,175
-939
-703
-467
-231
4
240
476
712
948
1,184
1,420
1,656
1,892
2,128
2,364
2,600
2,836
Unit: µm
27
S1C60N08/60R08
THIS PAGE IS BLANK.
S1C60N08/60R08
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
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© Seiko Epson Corporation 2001 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department Europe & U.S.A.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
ED International Marketing Department Asia
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5814 FAX : 042-587-5110
http://www.epson.co.jp/device/
■ EPSON Electronic Devices Website
Issue August, 2001
Printed in Japan L
