1 TO 4 CLOCK BUFFER
MDS 551 G 4Revision 091004
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS551
VDD = 5 V ±5% , Ambient temperature -40 to +85 °C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Notes: 1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
4. With external series resistor of 33Ω positioned close to each output pin.
Input Capacitance CIN OE pin 5 pF
CIN ICLK TBD pF
Short Circuit Current IOS ±50 mA
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 4.75 5.25 V
Input High Voltage, ICLK VIH Note 1 VDD/2+1 5.5 V
Input Low Voltage, ICLK VIL Note 1 VDD/2-1 V
Input High Voltage, OE VIH 2VDDV
Input Low Voltage, OE VIL 0.8 V
Output High Voltage VOH IOH = -35 mA 2.4 V
Output Low Voltage VOL IOL = 35 mA 0.4 V
Output High Voltage (CMOS
Level)
VOH IOH = -12 mA VDD-0.4 V
Operating Supply Current IDD No load, 135 MHz 35 mA
Nominal Output Impedance ZO20 Ω
Internal Pull-up Resistor RPU ICLK TBD kΩ
Input Capacitance CIN OE pin 5 pF
CIN ICLK TBD pF
Short Circuit Current IOS ±80 mA
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 160 MHz
Output Frequency, 3.3 V 15 pF load. Note 4 160 MHz
Output Frequency, 5 V 15 pF load. Note 4 135 MHz
Output Clock Rise Time tOR 0.8 to 2.0 V 1.5 ns
Output Clock Fall Time tOF 2.0 to 0.8 V 1.5 ns
Propagation Delay, 3.3 V Note 1 135 MHz 2 4 8 ns
Propagation Delay, 5 V Note 1 135 MHz 1.5 3 6 ns
Output to Output Skew Note 2 Rising edges at VDD/2 250 ps
Parameter Symbol Conditions Min. Typ. Max. Units