MT48LC2M32B2TG-6AIT:J - Micron Technology, Inc.

Automotive SDR SDRAM

MT48LC2M32B2 – 512K x 32 x 4 Banks

Features

• PC100-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 4096-cycle, 15.6µs/row (commercial and

industrial)

– 16ms, 4096-cycle, 3.9µs/row (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

• AEC-Q100

• PPAP submission

• 8D response time

Options Marking

• Configuration

– 2 Meg x 32 (512K x 32 x 4 banks) 2M32B2

• Plastic package – OCPL on page

– 86-pin TSOP II (400 mil) standard TG

– 86-pin TSOP II (400 mil) Pb-free P

– 90-ball VFBGA (8mm x 13mm) Pb-

free

• Timing – cycle time

– 5ns (200 MHz) -5

– 5.5ns (183 MHz) -552

– 6ns (167 MHz) -62

– 6ns (167 MHz) -6A3

– 7ns (143 MHz) -72

• Automotive certified

– Automotive A

• Operating temperature range

– Industrial (–40˚C to +85˚C) IT

– Automotive (–40˚C to +105˚C) AT4

• Revision :G/:J

Notes: 1. Off-center parting line.

2. Available only on revision G.

3. Available only on revision J.

4. Contact Micron for availability.

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

Clock

Frequency (MHz) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-5 200 3-3-3 15 15 15

-55 183 3-3-3 16.5 16.5 16.5

-6 167 3-3-3 18 18 18

-6A 167 3-3-3 18 18 18

-7 143 3-3-3 20 20 20

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Address Table

Parameter 2 Meg x 32

Configuration 512K x 32 x 4 banks

Refresh count 4K

Row addressing 2K A[10:0]

Bank addressing 4 BA[1:0]

Column addressing 256 A[7:0]

Table 3: 64Mb (x32) SDR Part Numbering

Part Numbers Architecture Package

MT48LC2M32B2TG 2 Meg x 32 86-pin TSOP II

MT48LCM32B2P 2 Meg x 32 86-pin TSOP II

MT48LC2M3B2B512 Meg x 32 90-ball VFBGA

Note: 1. FBGA Device Decoder: www.micron.com/decoder.

64Mb: x32 Automotive SDRAM

Features

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Contents

General Description ......................................................................................................................................... 7

Automotive Industrial Temperature ............................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ....................................................................................................... 9

Package Dimensions ....................................................................................................................................... 12

Temperature and Thermal Impedance ............................................................................................................ 14

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – IDD Parameters ........................................................................................................ 19

Electrical Specifications – AC Operating Conditions ......................................................................................... 21

Functional Description ................................................................................................................................... 24

Commands .................................................................................................................................................... 25

COMMAND INHIBIT .................................................................................................................................. 25

NO OPERATION (NOP) ............................................................................................................................... 26

LOAD MODE REGISTER (LMR) ................................................................................................................... 26

ACTIVE ...................................................................................................................................................... 26

READ ......................................................................................................................................................... 27

WRITE ....................................................................................................................................................... 28

PRECHARGE .............................................................................................................................................. 29

BURST TERMINATE ................................................................................................................................... 29

Truth Tables ................................................................................................................................................... 30

Initialization .................................................................................................................................................. 35

Mode Register ................................................................................................................................................ 37

Burst Length .............................................................................................................................................. 39

Burst Type .................................................................................................................................................. 39

CAS Latency ............................................................................................................................................... 41

Operating Mode ......................................................................................................................................... 41

Write Burst Mode ....................................................................................................................................... 41

Bank/Row Activation ...................................................................................................................................... 42

READ Operation ............................................................................................................................................. 43

WRITE Operation ........................................................................................................................................... 52

Burst Read/Single Write .............................................................................................................................. 59

PRECHARGE Operation .................................................................................................................................. 60

Auto Precharge ........................................................................................................................................... 60

AUTO REFRESH Operation ............................................................................................................................. 72

SELF REFRESH Operation ............................................................................................................................... 74

Power-Down .................................................................................................................................................. 76

Clock Suspend ............................................................................................................................................... 77

Revision History ............................................................................................................................................. 80

Rev. B – 10/13 ............................................................................................................................................. 80

Rev. A – 8/12 ............................................................................................................................................... 80

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List of Figures

Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8

Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9

Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 13

Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15

Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16

Figure 8: ACTIVE Command .......................................................................................................................... 26

Figure 9: READ Command ............................................................................................................................. 27

Figure 10: WRITE Command ......................................................................................................................... 28

Figure 11: PRECHARGE Command ................................................................................................................ 29

Figure 12: Initialize and Load Mode Register .................................................................................................. 36

Figure 13: Mode Register Definition ............................................................................................................... 38

Figure 14: CAS Latency .................................................................................................................................. 41

Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 42

Figure 16: Consecutive READ Bursts .............................................................................................................. 44

Figure 17: Random READ Accesses ................................................................................................................ 45

Figure 18: READ-to-WRITE ............................................................................................................................ 46

Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 47

Figure 20: READ-to-PRECHARGE .................................................................................................................. 47

Figure 21: Terminating a READ Burst ............................................................................................................. 48

Figure 22: Alternating Bank Read Accesses ..................................................................................................... 49

Figure 23: READ Continuous Page Burst ......................................................................................................... 50

Figure 24: READ – DQM Operation ................................................................................................................ 51

Figure 25: WRITE Burst ................................................................................................................................. 52

Figure 26: WRITE-to-WRITE .......................................................................................................................... 53

Figure 27: Random WRITE Cycles .................................................................................................................. 54

Figure 28: WRITE-to-READ ............................................................................................................................ 54

Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 55

Figure 30: Terminating a WRITE Burst ............................................................................................................ 56

Figure 31: Alternating Bank Write Accesses ..................................................................................................... 57

Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 58

Figure 33: WRITE – DQM Operation ............................................................................................................... 59

Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 61

Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 62

Figure 36: READ With Auto Precharge ............................................................................................................ 63

Figure 37: READ Without Auto Precharge ....................................................................................................... 64

Figure 38: Single READ With Auto Precharge .................................................................................................. 65

Figure 39: Single READ Without Auto Precharge ............................................................................................. 66

Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 67

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 67

Figure 42: WRITE With Auto Precharge ........................................................................................................... 68

Figure 43: WRITE Without Auto Precharge ..................................................................................................... 69

Figure 44: Single WRITE With Auto Precharge ................................................................................................. 70

Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 71

Figure 46: Auto Refresh Mode ........................................................................................................................ 73

Figure 47: Self Refresh Mode .......................................................................................................................... 75

Figure 48: Power-Down Mode ........................................................................................................................ 76

Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 77

Figure 50: Clock Suspend During READ Burst ................................................................................................. 78

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Figure 51: Clock Suspend Mode ..................................................................................................................... 79

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List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Address Table ..................................................................................................................................... 2

Table 3: 64Mb (x32) SDR Part Numbering ......................................................................................................... 2

Table 4: Pin and Ball Descriptions .................................................................................................................. 11

Table 5: Temperature Limits .......................................................................................................................... 14

Table 6: Thermal Impedance Simulated Values ............................................................................................... 15

Table 7: Absolute Maximum Ratings .............................................................................................................. 17

Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 17

Table 9: Capacitance ..................................................................................................................................... 18

Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 19

Table 11: IDD Specifications and Conditions – Revision J ................................................................................. 20

Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 21

Table 13: AC Functional Characteristics ......................................................................................................... 22

Table 14: Truth Table – Commands and DQM Operation ................................................................................. 25

Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 30

Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 32

Table 17: Truth Table – CKE ........................................................................................................................... 34

Table 18: Burst Definition Table ..................................................................................................................... 40

64Mb: x32 Automotive SDRAM

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General Description

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous in-

terface (all signals are registered on the positive edge of the clock signal, CLK). Each of

the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each

of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the

bank; A[10:0] select the row). The address bits registered coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-

so allows the column address to be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank while accessing one of the other

three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-

dom-access operation.

The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided, along with a power-saving, power-down mode. All inputs and out-

puts are LVTTL-compatible.

SDRAM devices offer substantial advances in DRAM operating performance, including

the ability to synchronously burst data at a high data rate with automatic column-ad-

dress generation, the ability to interleave between internal banks to hide precharge

time, and the capability to randomly change column addresses on each clock cycle dur-

ing a burst access.

Automotive Industrial Temperature

The automotive industrial temperature (AIT) device requires that the case temperature

not exceed –40°C or +95°C. JEDEC specifications require the refresh rate to double when

TC exceeds +85°C; this also requires use of the high-temperature self refresh option. Ad-

ditionally, ODT resistance and the input/output impedance must be derated when TC is

<0°C or >+95°C.

Automotive Temperature

The automotive temperature (AAT) device requires that the case temperature not ex-

ceed –40°C or +105°C. JEDEC specifications require the refresh rate to double when TC

exceeds +85°C; this also requires use of the high-temperature self refresh option. Addi-

tionally, ODT resistance and the input/output impedance must be derated when TC is

<0°C or >+105°C.

64Mb: x32 Automotive SDRAM

General Description

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Functional Block Diagrams

Figure 1: 2 Meg x 32 Functional Block Diagram

RAS#

CAS#

CLK

CS#

WE#

CKE

A[10:0],

BA[1:0]

DQM[3:0]

256

(x32)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(2048 x 256 x 32)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

2048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ[31:0]

DATA

INPUT

DATA

OUTPUT

BANK 1

BANK 0

BANK 2

BANK 3

4 4

REFRESH

COUNTER

MODE REGISTER

CONTROL

LOGIC

COMMAND

DECODE

ROW-

ADDRESS

MUX

ADDRESS

COLUMN-

ADDRESS

COUNTER/

LATCH

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Functional Block Diagrams

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Pin and Ball Assignments and Descriptions

Figure 2: 86-Pin TSOP (Top View)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

DQM0

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

DQM2

VDD

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQM1

CLK

CKE

DQM3

VSS

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

Note: 1. Package may or may not be assembled with a location notch.

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Pin and Ball Assignments and Descriptions

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Figure 3: 90-Ball VFBGA (Top View)

1 2 3 4 6 7 8 95

DQ26

DQ28

VSSQ

VDDQ

VSS

CLK

DQM1

VDDQ

VSSQ

DQ11

DQ13

DQ24

VDDQ

DQ27

DQ29

DQ31

DQM3

CKE

DQ8

DQ10

DQ12

VDDQ

DQ15

VSS

VSSQ

DQ25

DQ30

VSS

DQ9

DQ14

VSSQ

VSS

VDD

VDDQ

DQ22

DQ17

A10

BA0

CAS#

VDD

DQ6

DQ1

VDDQ

VDD

DQ21

DQ19

VDDQ

VSSQ

VDD

RAS#

DQM0

VSSQ

VDDQ

DQ4

DQ2

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

VSSQ

DQ0

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Pin and Ball Assignments and Descriptions

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Table 4: Pin and Ball Descriptions

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides precharge power-down and SELF REFRESH operation (all banks idle), active

power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-

gress). CKE is synchronous except after the device enters power-down and self refresh modes,

where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-

cluding CLK, are disabled during power-down and self refresh modes, providing low standby

power. CKE may be tied HIGH.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-

coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already

in progress will continue, and DQM operation will retain its DQ mask capability while CS# is

HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-

ered part of the command code.

CAS#, RAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-

tered.

DQM[3:0] Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked during a WRITE cycle. The

output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0

corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and

DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as

DQM.

BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-

CHARGE command is being applied.

A[10:0] Input Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and

READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select

one location out of the memory array in the respective bank. A10 is sampled during a PRE-

CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-

ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE

DQ[31:0] I/O Data input/output: Data bus.

VDDQ Supply DQ power supply: DQ power to the die for improved noise immunity.

VSSQ Supply DQ ground: DQ ground to the die for improved noise immunity.

VDD Supply Power supply: 3.3V ±0.3V.

VSS Supply Ground.

NC – No connect: These pins/balls should be left unconnected.

NU – Not used.

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Pin and Ball Assignments and Descriptions

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Package Dimensions

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P

See Detail A

2X R 1.00

2X R 0.75

0.50

TYP

0.61

10.16 ±0.08

0.50 ±0.10

11.76 ±0.20

Pin #1 ID

Detail A

22.22 ±0.08

0.20 +0.07

-0.03

0.15 +0.03

-0.02

0.10 +0.10

-0.05

1.20 MAX

0.10

0.25

Gage

plane

0.80

TYP

2X 0.10

2X 2.80

Plastic package material: Epoxy novolac

Plated lead finish:

TG (90% Sn, 10% Pb) or P (100% Sn) 0.01 ±0.005 thick per side

Package width and length do not include

mold protrusion. Allowable protrusion is

0.25 per side.

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is

0.25mm per side.

3. "2X" means the notch is present in two locations (both ends of the device).

4. Package may or may not be assembled with a location notch.

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Package Dimensions

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Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5

Ball A1 ID

1.00 MAX

Mold compound:

Epoxy novolac

Substrate material:

Plastic laminate

Solder ball material:

62% Sn, 36% Pb, 2% Ag or

96.5% Sn, 3%Ag, 0.5% Cu

13.00 ±0.10

Ball A1

Ball A9

Ball A1 ID

0.80 TYP

6.50 ±0.05

8.00 ±0.10

4.00 ±0.053.20 ±0.05

5.60 ±0.05

0.65 ±0.05

Seating plane

11.20 ±0.10

6.40

0.12 A

90X Ø0.45

Dimensions apply

to solder balls post

reflow. The pre-reflow

diameter is 0.42 on a

0.40 SMD ball pad.

0.80 TYP

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is

0.25mm per side.

3. Recommended pad size for PCB is 0.33mm ±0.025mm.

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Package Dimensions

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Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Temper-

ature Limits below, be maintained to ensure the junction temperature is in the proper

operating range to meet data sheet specifications. An important step in maintaining the

proper junction temperature is using the device’s thermal impedances correctly. The

thermal impedances are listed in Table 6 (page 15) for the applicable die revision and

packages being made available. These thermal impedance values vary according to the

density, package, and particular design used for each device.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-

ces listed in Table 6 (page 15). To ensure the compatibility of current and future de-

signs, contact Micron Applications Engineering to confirm thermal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the TC

specification is not exceeded. In applications where the device’s ambient temperature

is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-

perature specifications.

Table 5: Temperature Limits

Parameter Symbol Min Max Unit Notes

Operating case temperature Commercial TC0 80 °C 1, 2, 3, 4

Industrial –40 90

Automotive –40 105

Junction temperature Commercial TJ0 85 °C 3

Industrial –40 95

Automotive –40 110

Ambient temperature Commercial TA0 70 °C 3, 5

Industrial –40 85

Automotive –40 105

Peak reflow temperature TPEAK – 260 °C

Notes: 1. MAX operating case temperature TC is measured in the center of the package on the

top side of the device, as shown in Figure 6 (page 15) and Figure 7 (page 16).

2. Device functionality is not guaranteed if the device exceeds maximum TC during opera-

tion.

3. All temperature specifications must be satisfied.

4. The case temperature should be measured by gluing a thermocouple to the top-center

of the component. This should be done with a 1mm bead of conductive epoxy, as de-

fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple

bead is touching the case.

5. Operating ambient temperature surrounding the package.

64Mb: x32 Automotive SDRAM

Temperature and Thermal Impedance

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Table 6: Thermal Impedance Simulated Values

Die

Revision Package Substrate

ΘJA (°C/W)

Airflow =

0m/s

ΘJA (°C/W)

Airflow =

1m/s

ΘJA (°C/W)

Airflow =

2m/s ΘJB (°C/W) ΘJC (°C/W)

G 86-pin TSOP Low Con-

ductivity

95.2 75.3 69.0 66.5 12.7

High Con-

ductivity

66.6 57.7 54.6 53.6

90-ball VFBGA Low Con-

ductivity

70.6 57.6 69.5 35.7 7.95

High Con-

ductivity

54 47.3 52.7 35.2

J 86-pin TSOP Low Con-

ductivity

122.3 105.6 98.1 89.5 20.7

High Con-

ductivity

101.9 93.5 88.8 87.6

90-ball VFBGA Low Con-

ductivity

76.8 63.1 63.1 50.1 10.4

High Con-

ductivity

56.3 49.6 46.9 43.5

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

2. Thermal resistance data is sampled from multiple lots, and the values should be viewed

as typical.

3. These are estimates; actual results may vary.

Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View)

22.22mm

11.11mm

Test point

10.16mm

5.08mm

Note: 1. Package may or may not be assembled with a location notch.

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Temperature and Thermal Impedance

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Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View)

Test point

6.50mm

13.00mm

4.00mm

8.00mm

64Mb: x32 Automotive SDRAM

Temperature and Thermal Impedance

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 7: Absolute Maximum Ratings

Voltage/Temperature Symbol Min Max Unit

Voltage on VDD, VDDQ supply relative to VSS VDD, VDDQ –1 4.6 V

Voltage on inputs, NC, or I/O pins relative to VSS VIN –1 4.6 V

Storage temperature (plastic) TSTG –55 150 °C

Power dissipation – – 1 W

Table 8: DC Electrical Characteristics and Operating Conditions

Notes 1–3 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V

Parameter/Condition Symbol Min Max Unit Notes

Supply voltage VDD, VDDQ 3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 4

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 4

Output high voltage: IOUT = –4mA VOH 2.4 – V

Output low voltage: IOUT = 4mA VOL – 0.4 V

Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other pins

not under test = 0V)

IL–5 5 μA

Output leakage current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ IOZ –5 5 μA

Operating temperature: Commercial TA0 70 °C

Industrial TA–40 85 °C

Automotive TA–40 105 °C

Notes: 1. All voltages referenced to VSS.

2. An initial pulse of 100µs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured (VDD and VDDQ must be powered

up simultaneously. VSS and VSSQ must be at same potential). The two AUTO REFRESH

command wake-ups should be repeated any time the tREF refresh requirement is excee-

ded.

3. VDD,min = 3.135V for -6, -55, and -5 speed grades.

4. VIH overshoot: VIH,max = VDDQ + 1.2V for a pulse width ≤ 3ns, and the pulse width cannot

be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –1.2V for a pulse

width ≤3ns, and the pulse width cannot be greater than one-third of the cycle rate.

64Mb: x32 Automotive SDRAM

Electrical Specifications

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Table 9: Capacitance

Note 1 applies to all parameters and conditions

Package Parameter Min Max Unit

TSOP Package Input capacitance: CLK 2.5 4.0 pF

Input capacitance: All other input-only

balls/pins

2.5 4.0 pF

Input/output capacitance: DQ 4.0 6.5 pF

VFBGA Package Input capacitance: CLK 1.5 4.0 pF

Input capacitance: All other input-only

balls/pins

1.5 4.0 pF

Input/output capacitance: DQ 3 6.5 pF

Note: 1. This parameter is sampled. VDD, VDDQ = 3.3V; f = 1 MHz, TA = 25°C; pin under test biased

at 1.4V. AC can range from 0pF to 6pF.

64Mb: x32 Automotive SDRAM

Electrical Specifications

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Electrical Specifications – IDD Parameters

Table 10: IDD Specifications and Conditions – Revision G

Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V

Parameter/Condition Symbol

Max

Unit Notes-5 -55 -6 -7

Operating current: Active mode; Burst = 2; READ or WRITE; tRC ≥ tRC

(MIN); CL = 3

IDD1 200 190 150 130 mA 6, 7, 8, 9

Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2 2 2 2 mA

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac-

tive after tRCD met; No accesses in progress

IDD3 80 70 60 50 mA 6, 8, 9, 10

Operating current: Burst mode; Continuous burst; READ or WRITE;

All banks active; CL = 3

IDD4 280 260 180 160 mA 6, 7, 8, 9

Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 225 225 225 225 mA 6, 7, 8, 9,

Self refresh current: CKE ≤ 0.2V IDD6 2 2 2 2 mA 11

64Mb: x32 Automotive SDRAM

Electrical Specifications – IDD Parameters

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Table 11: IDD Specifications and Conditions – Revision J

Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V

Parameter/Condition Symbol

Max

Unit Notes-6A

Operating current: Active mode; Burst = 2; READ or WRITE; tRC ≥ tRC (MIN); CL = 3 IDD1 120 mA 6, 7, 8, 9

Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2.5 mA

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD

met; No accesses in progress

IDD3 45 mA 6, 8, 9, 10

Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active;

CL = 3

IDD4 120 mA 6, 7, 8, 9

Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 180 mA 6, 7, 8, 9, 10

Self refresh current: CKE ≤ 0.2V IDD6 3 mA 11

Notes: 1. All voltages referenced to VSS.

2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (VDD and VDDQ must be powered

up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH

command wake-ups should be repeated any time the tREF refresh requirement is excee-

ded.

3. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V

crossover point.

4. IDD specifications are tested after the device is properly initialized.

5. VDD = 3.135V for -6, -55, and -5 speed grades.

6. IDD is dependent on output loading and cycle rates. Specified values are obtained with

minimum cycle time and the outputs open.

7. The IDD current will decrease as the CL is reduced. This is due to the fact that the maxi-

mum cycle rate is slower as the CL is reduced.

8. Address transitions average one transition every two clocks.

9. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.

10. Other input signals are allowed to transition no more than once in any two-clock period

and are otherwise at valid VIH or VIL levels.

11. Enables on-chip refresh and address counters.

64Mb: x32 Automotive SDRAM

Electrical Specifications – IDD Parameters

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Electrical Specifications – AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions

Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V

Parameter Symbol

-5 -55 -6A6-6 -7

Unit NotesMin Max Min Max Min Max Min Max Min Max

Access time from CLK

(positive edge)

CL = 3 tAC(3) – 4.5 – 5 – 5.4 – 5.5 – 5.5 ns

CL = 2 tAC(2) – – – – – 7.5 – 7.5 – 8 ns

CL = 1 tAC(1) – – – – – 17 – 17 – 17 ns

Address hold time tAH 1 – 1 – 0.8 – 1 – 1 – ns

Address setup time tAS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns

CLK high-level width tCH 2 – 2 – 2.5 – 2.5 – 2.75 – ns

CLK low-level width tCL 2 – 2 – 2.5 – 2.5 – 2.75 – ns

Clock cycle time CL = 3 tCK(3) 5 – 5.5 – 6 – 6 – 7 – ns 7

CL = 2 tCK(2) – – – – 10 – 10 – 10 – ns 7

CL = 1 tCK(1) – – – – 20 – 20 – 20 – ns 7

CKE hold time tCKH 1 – 1 – 0.8 – 1 – 1 – ns

CKE setup time tCKS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns

CS#, RAS#, CAS#, WE#, DQM

hold time

tCMH 1 – 1 – 0.8 – 1 – 1 – ns

CS#, RAS#, CAS#, WE#, DQM

setup time

tCMS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns

Data-in hold time tDH 1 – 1 – 0.8 – 1 – 1 – ns

Data-in setup time tDS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns

Data-out High-Z time CL = 3 tHZ(3) 4.5 – 5 – – 5.4 – 5.5 – 5.5 ns 8

CL = 2 tHZ(2) – – – – – 7.5 – 7.5 – 8 ns 8

CL = 1 tHZ(1) – – – – – 17 – 17 – 17 ns 8

Data-out Low-Z time tLZ 1 – 1 – 1 – 1 – 1 – ns

Data-out hold time tOH 1.5 – 2 – 3 – 2 – 2.5 – ns

ACTIVE-to-PRECHARGE com-

mand

tRAS 38.7 120k 38.7 120k 42 120k 42 120k 42 120k ns

ACTIVE-to-ACTIVE command

period

tRC 55 – 55 – 60 – 60 – 70 – ns 9

AUTO REFRESH period tRFC 60 – 60 – 60 – 60 – 70 – ns

ACTIVE-to-READ or WRITE

delay

tRCD 15 – 16.5 – 18 – 18 – 20 – ns

Refresh period (4096 rows) tREF – 64 – 64 – 64 – 64 – 64 ms

Refresh period – automotive

(4096 rows)

tREFAT – 16 – 16 – 16 – 16 – 16 ms

PRECHARGE command peri-

tRP 15 – 16.5 – 18 – 18 – 20 – ns

ACTIVE bank a to ACTIVE

bank b command

tRRD 10 – 11 – 12 – 12 – 14 – ns 10

64Mb: x32 Automotive SDRAM

Electrical Specifications – AC Operating Conditions

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Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)

Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V

Parameter Symbol

-5 -55 -6A6-6 -7

Unit NotesMin Max Min Max Min Max Min Max Min Max

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 ns 11

WRITE recovery time tWR 2 – 2 – 1

CLK

6ns

– 1

CLK

6ns

– 1

CLK

7ns

–tCK 12

12 – 12 – 14 – ns 13

Exit SELF REFRESH-to-ACTIVE

command

tXSR 55 – 55 – 67 – 70 – 70 – ns 14

Table 13: AC Functional Characteristics

Notes 2–5 apply to all parameters and conditions

Parameter Symbol -5 -55 -6/6A -7 Unit Notes

READ/WRITE command to READ/WRITE command tCCD 1 1 1 1 tCK 15

CKE to clock disable or power-down entry mode tCKED 1 1 1 1 tCK 16

CKE to clock enable or power-down exit setup mode tPED 1 1 1 1 tCK 16

DQM to input data delay tDQD 0 0 0 0 tCK 15

DQM to data mask during WRITEs tDQM 0 0 0 0 tCK 15

DQM to data High-Z during READs tDQZ 2 2 2 2 tCK 15

WRITE command to input data delay tDWD 0 0 0 0 tCK 15

Data-in to ACTIVE command CL = 3 tDAL(3) 5 5 5 5 tCK 17, 18

CL = 2 tDAL(2) – – 4 4 tCK 17, 18

CL = 1 tDAL(1) – – 3 3 tCK 17, 18

Data-in to PRECHARGE command tDPL 2 2 2 2 tCK 18, 19

Last data-in to burst STOP command tBDL 1 1 1 1 tCK 15

Last data-in to new READ/WRITE command tCDL 1 1 1 1 tCK 15

Last data-in to PRECHARGE command tRDL 2 2 2 2 tCK 18, 19

LOAD MODE REGISTER command to ACTIVE or REFRESH

command

tMRD 2 2 2 2 tCK 20

Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 3 3 tCK 15

CL = 2 tROH(2) – – 2 2 tCK 15

CL = 1 tROH(1) – – 1 1 tCK 15

Notes: 1. Minimum specifications are used only to indicate the cycle time at which proper opera-

tion over the full temperature range is ensured:

0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ TA ≤ +85˚C (industrial)

–40˚C ≤ TA ≤ +105˚C (automotive)

2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (VDD and VDDQ must be powered

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Electrical Specifications – AC Operating Conditions

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up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH

command wake-ups should be repeated any time the tREF refresh requirement is excee-

ded.

3. In addition to meeting the transition rate specification, the clock and CKE must transit

between VIH and VIL (or between VIL and VIH) in a monotonic manner.

4. Outputs measured at 1.5V with equivalent load:

50pF

5. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V

crossover point.

6. Not applicable for revision G.

7. The clock frequency must remain constant (stable clock is defined as a signal cycling

within timing constraints specified for the clock pin) during access or precharge states

(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce

the data rate.

8. tHZ defines the time at which the output achieves the open circuit condition; it is not a

reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.

9. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in reduction of the product lifetime.

10. JEDEC and PC100 specify three clocks.

11. AC characteristics assume tT = 1ns.

12. Auto precharge mode only.

13. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1

tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge.

14. CLK must be toggled a minimum of two times during this period.

15. Required clocks are specified by JEDEC functionality and are not dependent on any tim-

ing parameter.

16. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.

17. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-

cle rate.

18. Based on tCK = 143 MHz for -7, 166 MHz for -6, 183 MHz for -55, and 200 MHz for -5.

19. Timing is specified by tWR.

20. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.

64Mb: x32 Automotive SDRAM

Electrical Specifications – AC Operating Conditions

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Functional Description

In general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM that

operates at 3.3V and include a synchronous interface. All signals are registered on the

positive edge of the clock signal, CLK. Each of the 16,777,216-bit banks is organized as

2048 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, followed by a

READ or WRITE command. The address bits registered coincident with the ACTIVE

command are used to select the bank and row to be accessed (BA0 and BA1 select the

bank, A[10:0] select the row). The address bits (A[7:0]) registered coincident with the

READ or WRITE command are used to select the starting column location for the burst

access.

Prior to normal operation, the device must be initialized. The following sections provide

detailed information covering device initialization, register definition, command de-

scriptions, and device operation.

64Mb: x32 Automotive SDRAM

Functional Description

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Commands

The following table provides a quick reference of available commands, followed by a

written description of each command. Additional Truth Tables (Table 15 (page 30), Ta-

ble 16 (page 32), and Table 17 (page 34)) provide current state/next state informa-

tion.

Table 14: Truth Table – Commands and DQM Operation

Note 1 applies to all parameters and conditions

Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (select bank and activate row) L L H H X Bank/row X 2

READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3

WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3

BURST TERMINATE L H H L X X Active 4

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 6, 7

LOAD MODE REGISTER L L L L X Op-code X 8

Write enable/output enable X X X X L X Active 9

Write inhibit/output High-Z X X X X H X High-Z 9

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1

determine which bank is made active.

3. A[0:i] provide column address (where i = the most significant column address for a given

device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which

bank is being read from or written to.

4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-

mand could coincide with data on the bus. However, the DQ column reads a “Don’t

Care” state to illustrate that the BURST TERMINATE command can occur when there is

no data present.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-

charged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-

cept for CKE.

8. A[11:0] define the op-code written to the mode register.

9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock

delay).

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by

the device, regardless of whether the CLK signal is enabled. The device is effectively de-

selected. Operations already in progress are not affected.

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Commands

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NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to the selected device

(CS# is LOW). This prevents unwanted commands from being registered during idle or

wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-

dress term), BA0, and BA1(see Mode Register (page 37)). The LOAD MODE REGISTER

command can only be issued when all banks are idle and a subsequent executable com-

mand cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to activate a row in a particular bank for a subsequent

access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-

lects the row. This row remains active for accesses until a PRECHARGE command is is-

sued to that bank. A PRECHARGE command must be issued before opening a different

row in the same bank.

Figure 8: ACTIVE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

Address Row address

Don’t Care

HIGH

BA0, BA1 Bank address

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Commands

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READ

The READ command is used to initiate a burst read access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the READ

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Read data appears on the DQ subject to the logic level on the DQM inputs two clocks

earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-

Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.

Figure 9: READ Command

CS#

WE#

CAS#

RAS#

CKE

CLK

Column address

A101

BA0, BA1

Don’t Care

HIGH

EN AP

DIS AP

Bank address

Address

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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Commands

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WRITE

The WRITE command is used to initiate a burst write access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the write

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Input data appearing on the DQ is written to the memory array, subject to the DQM in-

put logic level appearing coincident with the data. If a given DQM signal is registered

LOW, the corresponding data is written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that

byte/column location.

Figure 10: WRITE Command

DIS AP

EN AP

CS#

WE#

CAS#

RAS#

CKE

CLK

Column address

Don’t Care

HIGH

Bank address

Address

BA0, BA1

Valid address

A101

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

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Commands

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PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specified time (tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the case where only one bank is

precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as

“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands are issued to that bank.

Figure 11: PRECHARGE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

Don’t Care

HIGH

All banks

Bank selected

Address

BA0, BA1 Bank address

Valid address

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or continu-

ous page bursts. The most recently registered READ or WRITE command prior to the

BURST TERMINATE command is truncated.

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Commands

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Truth Tables

Table 15: Truth Table – Current State Bank n, Command to Bank n

Notes 1–6 apply to all parameters and conditions

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle L L H H ACTIVE (select and activate row)

L L L H AUTO REFRESH 7

L L L L LOAD MODE REGISTER 7

L L H L PRECHARGE 8

Row active L H L H READ (select column and start READ burst) 9

L H L L WRITE (select column and start WRITE burst) 9

L L H L PRECHARGE (deactivate row in bank or banks) 10

Read

(auto precharge disabled)

L H L H READ (select column and start new READ burst) 9

L H L L WRITE (select column and start WRITE burst) 9

L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10

L H H L BURST TERMINATE 11

Write

(auto precharge disabled)

L H L H READ (select column and start READ burst) 9

L H L L WRITE (select column and start new WRITE burst) 9

L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10

L H H L BURST TERMINATE 11

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17 (page 34))

and after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (for example, the current state is for a

specific bank and the commands shown can be issued to that bank when in that state).

Exceptions are covered below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

COMMAND INHIBIT or NOP commands, or supported commands to the other bank

should be issued on any clock edge occurring during these states. Supported commands

to any other bank are determined by the bank’s current state and the conditions descri-

bed in this and the following table.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is

met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD is

met. After tRCD is met, the bank will be in the row active state.

64Mb: x32 Automotive SDRAM

Truth Tables

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64mb_x32_aat-ait_sdram.pdf - Rev. B 10/13 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Read with auto precharge enabled: Starts with registration of a READ command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Write with auto precharge enabled: Starts with registration of a WRITE command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these

states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

tRFC is met. After tRFC is met, the device will be in the all banks idle state.

Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-

mand and ends when tMRD has been met. After tMRD is met, the device will be in the

all banks idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. After tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank specific; requires that all banks are idle.

8. Does not affect the state of the bank and acts as a NOP to that bank.

9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

10. May or may not be bank specific; if all banks need to be precharged, each must be in a

valid state for precharging.

11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-

gardless of bank.

64Mb: x32 Automotive SDRAM

Truth Tables

PDF: 09005aef84d5580d

64mb_x32_aat-ait_sdram.pdf - Rev. B 10/13 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 16: Truth Table – Current State Bank n, Command to Bank m

Notes 1–6 apply to all parameters and conditions

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle X X X X Any command otherwise supported for bank m

Row activating, active, or

precharging