K6T4016V4C, K6T4016U4C Family CMOS SRAM Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Date Remark Initial draft - UB/LB power control Errata correction July 4, 1998 Preliminary 0.1 Revise - Add 3,3V product : K6T4016V4C September 11, 1998 Preliminary 1.0 Revise - Specified CSP type. November 16, 1998 Final 0.0 0.01 August 17, 1998 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM 256Kx16 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology: TFT * Organization: 256K x16 * Power Supply Voltage K6T4016V4C Family: 3.0~3.6V K6T4016U4C Family: 2.7~3.3V * Low Data Retention Voltage: 2.0V(Min) * Three state output and TTL Compatible * Package Type: 48-BGA-6.10x8.90 The K6T4016V4C, K6T4016U4C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature K6T4016V4C-F Vcc Range 3.0~3.6V Industrial(-40~85C) K6T4016U4C-F Speed Standby (ISB1, Max) Operating (ICC2, Max) 20A 45mA 701)/85/100ns PKG Type 48-BGA 2.7~3.3V 1. The parameter is measured with 30pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 1 2 3 4 5 6 Clk gen. A LB OE A0 A1 A2 Precharge circuit. N.C Vcc Vss B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vcc I/O13 N.C A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 N.C A12 A13 WE I/O8 Row Addresses I/O1~I/O 8 Row select Data cont Memory array 1024 rows 256x16 columns I/O Circuit Column select Data cont I/O9~I/O16 Data cont Column Addresses H N.C A8 A9 A10 A11 N.C CS 48-ball CSP - Top View (Ball Down) OE WE Name Function Name Function CS Chip Select Inputs Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) LB Lower Byte(I/O1~8) NC No Connection A0~A17 Address Inputs I/O 1~I/O16 Data Inputs/Outputs Control Logic UB LB SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name Function K6T4016V4C-ZF70 K6T4016V4C-ZF85 K6T4016V4C-ZF10 48-BGA with 0.75mm ball pitch, 70ns, 3.3V, LL 48-BGA with 0.75mm ball pitch, 85ns, 3.3V, LL 48-BGA with 0.75mm ball pitch, 100ns, 3.3V, LL K6T4016U4C-ZF70 K6T4016U4C-ZF85 K6T4016U4C-ZF10 48-BGA with 0.75mm ball pitch, 70ns, 3.0V, LL 48-BGA with 0.75mm ball pitch, 85ns, 3.0V, LL 48-BGA with 0.75mm ball pitch, 100ns, 3.0V, LL FUNCTIONAL DESCRIPTION CS OE WE LB UB 1) 1) I/O1~8 I/O9~16 Mode Power H X X X X High-Z High-Z Deselected Standby X1) X1) X1) H H High-Z High-Z Deselected Standby L H H L X High-Z High-Z Output Disabled Active L H H X L High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active 1) 1) 1) 1) L 1) X L L H Din High-Z Lower Byte Write Active L X1) L H L High-Z Din Upper Byte Write Active L 1) L L L Din Din Word Write Active X 1. X means dont care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit VIN,VOUT -0.5 to VCC+0.5 V Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V Power Dissipation PD 1.0 W TSTG -65 to 150 C TA -40 to 85 C Voltage on any pin relative to Vss Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Item Symbol Supply voltage Vcc Product Min Typ Max K6T4016V4C Family 3.0 3.3 3.6 K6T4016U4C Family 2.7 3.0 3.3 0 Ground Vss K6T4016V4C, K6T4016U4C Family 0 0 Input high voltage VIH K6T4016V4C, K6T4016U4C Family 2.2 - Input low voltage VIL K6T4016V4C, K6T4016U4C Family -0.3 3) Unit V V Vcc+0.3 - V 2) 0.6 V Note: 1. TA=-40 to 85C, otherwise specified 2. Overshoot: VCC+2.0V in case of pulse width 30ns. 3. Undershoot: -2.0V in case of pulse width 30ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Symbol Test Condition Min Max Unit Input capacitance Item C IN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIL=Vss to Vcc -1 - 1 A Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH - - 4 mA ICC1 Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V - - 6 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 45 mA Input leakage current Average operating current Symbol Test Conditions Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS=VIH or LB=UB=VIH, Other inputs=VIH or VIL - - 0.3 mA Standby Current(CMOS) ISB1 CSVcc-0.2V or LB=UBVcc-0.2V, CS0.2V, Other inputs=0~Vcc - - 20 A 4 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL C L=30pF+1TTL CL1) 1.Including scope and jig capacitance AC CHARACTERISTICS (TA=-40 to 85C, K6T4016V4C Family: Vcc=3.0~3.6V, K6T4016U4C Family:Vcc=2.7~3.3V) Speed Bins Parameter List Symbol Read cycle time Read Write 70ns tRC 85ns Units 100ns Min Max Min Max Min Max 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns LB, UB valid to data output tBA - 70 - 85 - 100 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns LB, UB enable to low-Z output tBLZ 10 - 10 - 10 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 15 - ns OE disable to high-Z output tOHZ 0 25 0 25 0 30 ns UB, LB disable to high-Z output tBHZ 0 25 0 25 0 30 ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 55 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns LB, UB valid to end of write tBW 60 - 70 - 80 - ns Typ Max Unit 2.0 - 3.6 V - 0.5 20 A 0 - - 5 - - DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CSVcc-0.2V Data retention current IDR Vcc=3.0V, CSVcc-0.2V 1) Data retention set-up time tSDR Recovery time tRDR 1) See data retention waveform Min ms 1. CSVcc-0.2V(CS controlled) or LB=UBVcc-0.2V, CS0.2V(LB, UB controlled) 5 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS or LB/UB controlled VCC tSDR Data Retention Mode tRDR 3.0/ 2.7V 2.0V VDR CS or LB/UB GND CSVCC - 0.2V or LB=UBVcc-0.2V 8 Revision 1.0 November 1998 K6T4016V4C, K6T4016U4C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters 48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch Top View Bottom View Ball #A1 B B 6 5 4 3 2 1 C/2 C/2 A B Ball #A1 C C C C1 D E F G H B1 B/2 B/2 SRAM Die Elastomer Detail A Detail A 0.25/Typ. Side View E2 D A Y Min Typ Max A - 0.75 - B 6.00 6.10 6.20 B1 - 3.75 - C 8.80 8.90 9.00 C1 - 5.25 - D 0.30 0.35 0.40 E - 0.93 0.94 E1 - 0.68 - E2 - 0.25 - Y - - 0.08 0.45/Typ. 0.68/Typ. E1 E C Elastomer Die 0.3/Typ. Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) 9 Revision 1.0 November 1998