K6T4016V4C, K6T4016U4C FAMILY - Samsung Electronics

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

Document Title

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

0.0

0.01

0.1

1.0

Remark

Preliminary

Final

History

Initial draft

- UB/LB power control

Errata correction

Revise

- Add 3,3V product : K6T4016V4C

Revise

- Specified CSP type.

Draft Date

July 4, 1998

August 17, 1998

September 11, 1998

November 16, 1998

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6T4016V4C, K6T4016U4C families are fabricated by

SAMSUNG′s advanced CMOS process technology. The fami-

lies support industrial operating temperature ranges and have

chip scale package for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 256K x16

• Power Supply Voltage

K6T4016V4C Family: 3.0~3.6V

K6T4016U4C Family: 2.7~3.3V

• Low Data Retention Voltage: 2.0V(Min)

• Three state output and TTL Compatible

• Package Type: 48-µBGA-6.10x8.90

Name Function Name Function

CS Chip Select Inputs Vcc Power

OE Output Enable Input Vss Ground

WE Write Enable Input UB Upper Byte(I/O9~16)

A0~A17 Address Inputs LB Lower Byte(I/O1~8)

I/O1~I/O16 Data Inputs/Outputs NC No Connection

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.

Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

K6T4016V4C-F Industrial(-40~85°C) 3.0~3.6V 701)/85/100ns 20µA45mA 48-µBGA

K6T4016U4C-F 2.7~3.3V

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Row

select

I/O1~I/O8Data

cont

Data

cont

Data

cont

I/O9~I/O16

Vcc

Vss

Precharge circuit.

Memory array

1024 rows

256×16 columns

I/O Circuit

Column select

PIN DESCRIPTION

48-ball CSP - Top View (Ball Down)

LB OE A0 A1 A2 N.C

I/O9 UB A3 A4 CS I/O1

I/O10 I/O11 A5 A6 I/O2 I/O3

Vss I/O12 A17 A7 I/O4 Vcc

Vcc I/O13 N.C A16 I/O5 Vss

I/O15 I/O14 A14 A15 I/O6 I/O7

I/O16 N.C A12 A13 WE I/O8

N.C A8 A9 A10 A11 N.C

1 23456

Control Logic

Row

Addresses

Column Addresses

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name Function

K6T4016V4C-ZF70

K6T4016V4C-ZF85

K6T4016V4C-ZF10

K6T4016U4C-ZF70

K6T4016U4C-ZF85

K6T4016U4C-ZF10

48-µBGA with 0.75mm ball pitch, 70ns, 3.3V, LL

48-µBGA with 0.75mm ball pitch, 85ns, 3.3V, LL

48-µBGA with 0.75mm ball pitch, 100ns, 3.3V, LL

48-µBGA with 0.75mm ball pitch, 70ns, 3.0V, LL

48-µBGA with 0.75mm ball pitch, 85ns, 3.0V, LL

48-µBGA with 0.75mm ball pitch, 100ns, 3.0V, LL

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V

Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V

Power Dissipation PD1.0 W

Storage temperature TSTG -65 to 150 °C

Operating Temperature TA-40 to 85 °C

FUNCTIONAL DESCRIPTION

1. X means don′t care. (Must be low or high state)

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

HX1) X1) X1) X1) High-Z High-Z Deselected Standby

X1) X1) X1) H H High-Z High-Z Deselected Standby

LH H LX1) High-Z High-Z Output Disabled Active

LH H X1) LHigh-Z High-Z Output Disabled Active

L L HLHDout High-Z Lower Byte Read Active

L L H H LHigh-Z Dout Upper Byte Read Active

L L HL L Dout Dout Word Read Active

LX1) L L HDin High-Z Lower Byte Write Active

LX1) LHLHigh-Z Din Upper Byte Write Active

LX1) L L L Din Din Word Write Active

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+2.0V in case of pulse width ≤30ns.

3. Undershoot: -2.0V in case of pulse width ≤30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Product Min Typ Max Unit

Supply voltage Vcc K6T4016V4C Family 3.0 3.3 3.6 V

K6T4016U4C Family 2.7 3.0 3.3

Ground Vss K6T4016V4C, K6T4016U4C Family 000V

Input high voltage VIH K6T4016V4C, K6T4016U4C Family 2.2 -Vcc+0.32) V

Input low voltage VIL K6T4016V4C, K6T4016U4C Family -0.33) -0.6 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIL=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 -1µA

Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH - - 4mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V - - 6mA

ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 45 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.2 - - V

Standby Current(TTL) ISB CS=VIH or LB=UB=VIH, Other inputs=VIH or VIL - - 0.3 mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V or LB=UB≥Vcc-0.2V, CS≤0.2V, Other inputs=0~Vcc - - 20 µA

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

CL1)

1.Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

CL=30pF+1TTL

DATA RETENTION CHARACTERISTICS

1. CS≥Vcc-0.2V(CS controlled) or LB=UB≥Vcc-0.2V, CS≤0.2V(LB, UB controlled)

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V1) 2.0 -3.6 V

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V1) -0.5 20 µA

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

AC CHARACTERISTICS (TA=-40 to 85°C, K6T4016V4C Family: Vcc=3.0~3.6V, K6T4016U4C Family:Vcc=2.7~3.3V)

Parameter List Symbol Speed Bins Units

70ns 85ns 100ns

Min Max Min Max Min Max

Read

Read cycle time tRC 70 -85 -100 -ns

Address access time tAA -70 -85 -100 ns

Chip select to output tCO -70 -85 -100 ns

Output enable to valid output tOE -35 -40 -50 ns

LB, UB valid to data output tBA -70 -85 -100 ns

Chip select to low-Z output tLZ 10 -10 -10 -ns

Output enable to low-Z output tOLZ 5-5-5-ns

LB, UB enable to low-Z output tBLZ 10 -10 -10 -ns

Chip disable to high-Z output tHZ 025 025 030 ns

Output hold from address change tOH 10 -10 -15 -ns

OE disable to high-Z output tOHZ 025 025 030 ns

UB, LB disable to high-Z output tBHZ 025 025 030 ns

Write

Write cycle time tWC 70 -85 -100 -ns

Chip select to end of write tCW 60 -70 -80 -ns

Address set-up time tAS 0-0-0-ns

Address valid to end of write tAW 60 -70 -80 -ns

Write pulse width tWP 55 -55 -70 -ns

Write recovery time tWR 0-0-0-ns

Write to output high-Z tWHZ 025 025 030 ns

Data to write time overlap tDW 30 -35 -40 -ns

Data hold from write time tDH 0-0-0-ns

End write to output low-Z tOW 5-5-5-ns

LB, UB valid to end of write tBW 60 -70 -80 -ns

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

Address

Data Out Previous Data Valid Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

tRC

Address

UB, LB

Data out

tAA

tRC

tOH

tAA

tCO

tBA

tOE

tOLZ

tBLZ

tLZ tOHZ

tBHZ

tHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

Data Undefined

UB, LB

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

tWC

tCW(2) tWR(4)

tAWtBW

tWP(1)

tAS(3) tDH

tDW

tWHZ tOW

tWC

tCW(2)

tAW tBW

tWP(1)

tDH

tDW

tWR(4)

High-Z High-Z

Data Valid

tAS(3)

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS or LB/UB controlled

VCC

3.0/ 2.7V

2.0V

VDR

CS or LB/UB

GND

Data Retention Mode

CS≥VCC - 0.2V or LB=UB≥Vcc-0.2V

tSDR tRDR

tAS(3)

K6T4016V4C, K6T4016U4C Family CMOS SRAM

Revision 1.0

November 1998

PACKAGE DIMENSIONS

654321

C/2

B/2

Ball #A1

B/2

Elastomer

SRAM Die

Ball #A1

C/2

Bottom ViewTop View

Detail A

Side View

0.68/Typ.

0.45/Typ. 0.25/Typ.

Elastomer

0.3/Typ.

Die

Detail A

Notes.

1. Bump counts: 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

4. Typ : Typical

5. Y is coplanarity: 0.08(Max)

Min Typ Max

A-0.75 -

B6.00 6.10 6.20

B1 -3.75 -

C8.80 8.90 9.00

C1 -5.25 -

D0.30 0.35 0.40

E-0.93 0.94

E1 -0.68 -

E2 -0.25 -

Y- - 0.08

Units: millimeters

48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch