LF256H - Texas Instruments High-Performance Analog

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers

Check for Samples: LF155,LF156,LF355,LF356,LF357

1FEATURES DESCRIPTION

These are the first monolithic JFET input operational

23Advantages amplifiers to incorporate well matched, high voltage

• Replace Expensive Hybrid and Module FET Op JFETs on the same chip with standard bipolar

Amps transistors ( BI-FET™ Technology). These amplifiers

• Rugged JFETs Allow Blow-Out Free Handling feature low input bias and offset currents/low offset

voltage and offset voltage drift, coupled with offset

Compared with MOSFET Input Devices adjust which does not degrade drift or common-mode

• Excellent for Low Noise Applications Using rejection. The devices are also designed for high slew

Either High or Low Source Impedance—Very rate, wide bandwidth, extremely fast settling time, low

Low 1/f Corner voltage and current noise and a low 1/f noise corner.

• Offset Adjust Does Not Degrade Drift or

Common-Mode Rejection as in Most Common Features

Monolithic Amplifiers • Low Input Bias Current: 30pA

• New Output Stage Allows Use of Large • Low Input Offset Current: 3pA

Capacitive Loads (5,000 pF) without Stability • High Input Impedance: 1012Ω

Problems • Low Input Noise Current: 0.01 pA/√Hz

• Internal Compensation and Large Differential • High Common-Mode Rejection Ratio: 100 dB

Input Voltage Capability • Large DC Voltage Gain: 106 dB

APPLICATIONS Table 1. Uncommon Features

• Precision High Speed Integrators LF155/ LF156/ LF257/ Units

LF355 LF256/ LF357

• Fast D/A and A/D Converters LF356 (AV=5)

• High Impedance Buffers Extremely fast 4 1.5 1.5 μs

settling time to 0.01%

• Wideband, Low Noise, Low Drift Amplifiers Fast slew rate 5 12 50 V/µs

• Logarithmic Amplifiers Wide gain bandwidth 2.5 5 20 MHz

• Photocell Amplifiers Low input noise 20 12 12 nV / √Hz

• Sample and Hold Circuits voltage

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2BI-FET is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Simplified Schematic

*3pF in LF357 series.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Absolute Maximum Ratings(1)(2)

LF155/6 LF256/7/LF356B LF355/6/7

Supply Voltage ±22V ±22V ±18V

Differential Input Voltage ±40V ±40V ±30V

Input Voltage Range (3) ±20V ±20V ±16V

Output Short Circuit Duration Continuous Continuous Continuous

TJMAX

LMC Package 150°C 115°C 115°C

P Package 100°C 100°C

D Package 100°C 100°C

Power Dissipation at TA= 25°C (1) (4)

LMC Package (Still Air) 560 mW 400 mW 400 mW

LMC Package (400 LF/Min Air Flow) 1200 mW 1000 mW 1000 mW

P Package 670 mW 670 mW

D Package 380 mW 380 mW

Thermal Resistance (Typical) θJA

LMC Package (Still Air) 160°C/W 160°C/W 160°C/W

LMC Package (400 LF/Min Air Flow) 65°C/W 65°C/W 65°C/W

P Package 130°C/W 130°C/W

D Package 195°C/W 195°C/W

(Typical) θJC

LMC Package 23°C/W 23°C/W 23°C/W

Storage Temperature Range −65°C to +150°C −65°C to +150°C −65°C to +150°C

Soldering Information (Lead Temp.)

TO-99 Package

Soldering (10 sec.) 300°C 300°C 300°C

PDIP Package

Soldering (10 sec.) 260°C 260°C 260°C

SOIC Package

Vapor Phase (60 sec.) 215°C 215°C

Infrared (15 sec.) 220°C 220°C

ESD tolerance

(100 pF discharged through 1.5kΩ) 1000V 1000V 1000V

(1) The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the

ambient temperature, TA. The maximum available power dissipation at any temperature is PD=(TJMAX−TA)/θJA or the 25°C PdMAX,

whichever is less.

(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.

(3) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

(4) Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the

part to operate outside specified limits.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

DC Electrical Characteristics

LF256/7

LF155/6 LF355/6/7

LF356B

Symbol Parameter Conditions Units

Min Typ Max Min Typ Max Min Typ Max

VOS Input Offset Voltage RS=50Ω, TA=25°C 3 5 3 5 3 10 mV

Over Temperature 7 6.5 13 mV

ΔVOS/ΔT Average TC of Input RS=50Ω5 5 5 μV/°C

Offset Voltage

ΔTC/ΔVOS Change in Average TC RS=50Ω,(2) μV/°C

0.5 0.5 0.5

with VOS Adjust per mV

IOS Input Offset Current TJ=25°C, (1) (3) 3 20 3 20 3 50 pA

TJ≤THIGH 20 1 2 nA

IBInput Bias Current TJ=25°C, (1) (3) 30 100 30 100 30 200 pA

TJ≤THIGH 50 5 8 nA

RIN Input Resistance TJ=25°C 1012 1012 1012 Ω

AVOL Large Signal Voltage VS=±15V, TA=25°C 50 200 50 200 25 200 V/mV

Gain VO=±10V, RL=2k

Over Temperature 25 25 15 V/mV

VOOutput Voltage Swing VS=±15V, RL=10k ±12 ±13 ±12 ±13 ±12 ±13 V

VS=±15V, RL=2k ±10 ±12 ±10 ±12 ±10 ±12 V

VCM Input Common-Mode VS=±15V +15.1 ±15.1 +15.1 V

±11 ±11 +10

Voltage Range −12 −12 −12 V

CMRR Common-Mode 85 100 85 100 80 100 dB

Rejection Ratio

PSRR Supply Voltage Rejection (4) 85 100 85 100 80 100 dB

Ratio

(1) Unless otherwise stated, these test conditions apply:

LF155/156 LF256/257 LF356B LF355/6/7

Supply Voltage, VS±15V ≤VS≤±20V ±15V ≤VS≤±20V ±15V ≤VS±20V VS= ±15V

TA−55°C ≤TA≤ −25°C ≤TA≤+85°C 0°C ≤TA≤+70°C 0°C ≤TA≤+70°C

+125°C

THIGH +125°C +85°C +70°C +70°C

and VOS, IBand IOS are measured at VCM = 0.

(2) The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5μV/°C typically) for each mV of

adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset

adjustment.

(3) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature,

TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the

junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ= TA+θJA Pd where θJA is

the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.

(4) Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common

practice.

DC Electrical Characteristics

TA= TJ= 25°C, VS= ±15V

LF155 LF355 LF156/256/257/356B LF356 LF357

Parameter Units

Typ Max Typ Max Typ Max Typ Max Typ Max

Supply 2 4 2 4 5 7 5 10 5 10 mA

Current

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

AC Electrical Characteristics

TA= TJ= 25°C, VS= ±15V LF155/355 LF156/256/ LF156/256/356/ LF257/357

356B LF356B

Symbol Parameter Conditions Units

Typ Min Typ Typ

SR Slew Rate LF155/6: AV=1, 5 7.5 12 V/μs

LF357: AV=5 50 V/μs

GBW Gain Bandwidth Product 2.5 5 20 MHz

tsSettling Time to 0.01% (1) 4 1.5 1.5 μs

enEquivalent Input Noise RS=100Ω

Voltage f=100 Hz 25 15 15 nV/√Hz

f=1000 Hz 20 12 12 nV/√Hz

inEquivalent Input Current f=100 Hz 0.01 0.01 0.01 pA/√Hz

Noise f=1000 Hz 0.01 0.01 0.01 pA/√Hz

CIN Input Capacitance 3 3 3 pF

(1) Settling time is defined here, for a unity gain inverter connection using 2 kΩresistors for the LF155/6. It is the time required for the error

voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is

applied to the inverter. For the LF357, AV=−5, the feedback resistor from output to input is 2kΩand the output step is 10V (See Settling

Time Test Circuit).

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Typical DC Performance Characteristics

Curves are for LF155 and LF156 unless otherwise specified.

Input Bias Current Input Bias Current

Figure 1. Figure 2.

Input Bias Current Voltage Swing

Figure 3. Figure 4.

Supply Current Supply Current

Figure 5. Figure 6.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Typical DC Performance Characteristics (continued)

Curves are for LF155 and LF156 unless otherwise specified.

Negative Current Limit Positive Current Limit

Figure 7. Figure 8.

Positive Common-Mode Negative Common-Mode

Input Voltage Limit Input Voltage Limit

Figure 9. Figure 10.

Open Loop Voltage Gain Output Voltage Swing

Figure 11. Figure 12.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Typical AC Performance Characteristics

Gain Bandwidth Gain Bandwidth

Figure 13. Figure 14.

Normalized Slew Rate Output Impedance

Figure 15. Figure 16.

Output Impedance

Figure 17.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Typical AC Performance Characteristics (continued)

LF155 Small Signal Pulse Response, AV= +1 LF156 Small Signal Pulse Response, AV= +1

Figure 18. Figure 19.

LF156 Large Signal Puls

LF155 Large Signal Pulse Response, AV= +1 Response, AV= +1

Figure 20. Figure 21.

Inverter Settling Time Inverter Settling Time

Figure 22. Figure 23.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Typical AC Performance Characteristics (continued)

Open Loop Frequency Response Bode Plot

Figure 24. Figure 25.

Bode Plot Bode Plot

Figure 26. Figure 27.

Common-Mode Rejection Ratio Power Supply Rejection Ratio

Figure 28. Figure 29.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Typical AC Performance Characteristics (continued)

Power Supply Rejection Ratio Undistorted Output Voltage Swing

Figure 30. Figure 31.

Equivalent Input Noise

Equivalent Input Noise Voltage Voltage (Expanded Scale)

Figure 32. Figure 33.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

DETAILED SCHEMATIC

*C = 3pF in LF357 series.

Connection Diagrams

(Top Views)

*Available per JM38510/11401 or

JM38510/11402

Figure 34. TO-99 Package (LMC) Figure 35. SOIC and PDIP Package (D and P)

See Package Number LMC (O-MBCY-W8) See Package Number

D (R-PDSO-G8) or P (R-PDIP-T8)

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

APPLICATION HINTS

These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to

source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can

easily be accommodated without a large increase in input current. The maximum differential input voltage is

independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the

negative supply as this will cause large currents to flow which can result in a destroyed unit.

Exceeding the negative common-mode limit on either input will force the output to a high state, potentially

causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force

the amplifier output to a high state. In neither case does a latch occur since raising the input back within the

common-mode range again puts the input stage and thus the amplifier in a normal operating mode.

Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if

both inputs exceed the limit, the output of the amplifier will be forced to a high state.

These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the

common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage

and over the full operating temperature range. The positive supply can therefore be used as a reference on an

input as, for example, in a supply current monitor and/or limiter.

Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in

polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through

the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed

unit.

All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers

are therefore essentially independent of supply voltage.

As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in

order to ensure stability. For example, resistors from the output to an input should be placed with the body close

to the input to minimize “pickup” and maximize the frequency of the feedback pole by minimizing the capacitance

from the input to ground.

A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and

capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.

In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop

gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than

approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the

input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor

and the resistance it parallels is greater than or equal to the original feedback pole time constant.

Typical Circuit Connections

Figure 36. VOS Adjustment

• VOS is adjusted with a 25k potentiometer

• The potentiometer wiper is connected to V+

• For potentiometers with temperature coefficient of 100 ppm/°C or less the additional drift with adjust is ≈

0.5μV/°C/mV of adjustment

• Typical overall drift: 5μV/°C ±(0.5μV/°C/mV of adj.)

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

*LF155/6 R = 5k, LF357 R = 1.25k

Figure 37. Driving Capacitive Loads

Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still

maintain stability. CL(MAX) ≃0.01μF.

Overshoot ≤20%, Settling time (ts)≃5μs

For distortion ≤1% and a 20 Vp-p VOUT swing, power bandwidth is: 500kHz.

Figure 38. LF357 - A Large Power BW Amplifier

Typical Applications

Figure 39. Settling Time Test Circuit

• Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV=−5

• FET used to isolate the probe capacitance

• Output = 10V step

• AV=−5 for LF357

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Large Signal Inverter Output, VOUT (from Settling Time Circuit)

Figure 40. LF355

Figure 41. LF356

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Figure 42. LF357

Figure 43. Low Drift Adjustable Voltage Reference

•ΔVOUT/ΔT = ±0.002%/°C

• All resistors and potentiometers should be wire-wound

• P1: drift adjust

• P2: VOUT adjust

• Use LF155 for

– Low IB

– Low drift

– Low supply current

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Figure 44. Fast Logarithmic Converter

• Dynamic range: 100μA≤Ii≤1mA (5 decades), |VO| = 1V/decade

• Transient response: 3μs for ΔIi= 1 decade

• C1, C2, R2, R3: added dynamic compensation

• VOS adjust the LF156 to minimize quiescent error

• RT: Tel Labs type Q81 + 0.3%/°C

Figure 45. Precision Current Monitor

• VO= 5 R1/R2 (V/mA of IS)

• R1, R2, R3: 0.1% resistors

• Use LF155 for

– Common-mode range to supply range

– Low IB

– Low VOS

– Low Supply Current

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Figure 46. 8-Bit D/A Converter with Symmetrical Offset Binary Operation

• R1, R2 should be matched within ±0.05%

• Full-scale response time: 3μs

EOB1 B2 B3 B4 B5 B6 B7 B8 Comments

+9.920 1 1 1 1 1 1 1 1 Positive Full-Scale

+0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale

−0.040 0 1 1 1 1 1 1 1 (−) Zero-Scale

−9.920 0 0 0 0 0 0 0 0 Negative Full-Scale

Figure 47. Wide BW Low Noise, Low Drift Amplifier

• Parasitic input capacitance C1 ≃(3pF for LF155, LF156 and LF357 plus any additional layout capacitance)

interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such

that: R2 C2 ≃R1 C1.

Figure 48. Boosting the LF156 with a Current Amplifier

• IOUT(MAX)≃150mA (will drive RL≥100Ω)

•

• No additional phase shift added by the current amplifier

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

R1, R4 matched. Linearity 0.1% over 2 decades.

Figure 49. Decades VCO

Figure 50. Isolating Large Capacitive Loads

• Overshoot 6%

• ts10μs

• When driving large CL, the VOUT slew rate determined by CLand IOUT(MAX):

Figure 51. Low Drift Peak Detector

• By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf.

• Leakage of circuit is essentially Ib(LF155, LF156) plus capacitor leakage of Cp.

• Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2.

• Maximum input frequency should be << ½πRfCD2 where CD2 is the shunt capacitance of D2.

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Figure 52. Non-Inverting Unity Gain Operation for LF157

Figure 53. Inverting Unity Gain for LF157

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Figure 54. High Impedance, Low Drift Instrumentation Amplifier

• System VOS adjusted via A2 VOS adjust

• Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best

accuracy and lowest drift

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

Figure 55. Fast Sample and Hold

• Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)

• Acquisition time TA, estimated by:

• LF156 develops full Sroutput capability for VIN ≥1V

• Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop

• Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

Figure 56. High Accuracy Sample and Hold

• By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.

– No VOS adjust required for A2.

• TAcan be estimated by same considerations as previously but, because of the added

– propagation delay in the feedback loop (A2) the overshoot is not negligible.

• Overall system slower than fast sample and hold

• R1, CC: additional compensation

• Use LF156 for

– Fast settling time

– Low VOS

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

www.ti.com

SNOSBH0C –MAY 2000–REVISED MARCH 2013

Figure 57. High Q Band Pass Filter

• By adding positive feedback (R2)

• Q increases to 40

• fBP = 100 kHz

• Clean layout recommended

• Response to a 1Vp-p tone burst: 300μs

Figure 58. High Q Notch Filter

• 2R1 = R = 10MΩ

– 2C = C1 = 300pF

• Capacitors should be matched to obtain high Q

• fNOTCH = 120 Hz, notch = −55 dB, Q > 100

• Use LF155 for

– Low IB

– Low supply current

Product Folder Links: LF155 LF156 LF355 LF356 LF357

LF155, LF156, LF355, LF356, LF357

SNOSBH0C –MAY 2000–REVISED MARCH 2013

www.ti.com

REVISION HISTORY

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 23

Product Folder Links: LF155 LF156 LF355 LF356 LF357

PACKAGE OPTION ADDENDUM

www.ti.com 1-Nov-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LF156H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 LF156H

LF156H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS

& no Sb/Br) POST-PLATE Level-1-NA-UNLIM -55 to 125 LF156H

LF256H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -25 to 85 LF256H

LF256H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS

& no Sb/Br) POST-PLATE Level-1-NA-UNLIM -25 to 85 LF256H

LF356H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI 0 to 70 LF356H

LF356H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS

& no Sb/Br) POST-PLATE Level-1-NA-UNLIM 0 to 70 LF356H

LF356M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LF356

LF356M/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LF356

LF356MX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LF356

LF356MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LF356

LF356N NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LF

356N

LF356N/NOPB ACTIVE PDIP P 8 40 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF

356N

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

PACKAGE OPTION ADDENDUM

www.ti.com 1-Nov-2013

Addendum-Page 2

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LF356MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LF356MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LF356MX SOIC D 8 2500 367.0 367.0 35.0

LF356MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265