DS89C386
Twelve Channel CMOS Differential Line Receiver
General Description
The DS89C386 is a high speed twelve channel CMOS dif-
ferential receiver that meets the requirements of TIA/EIA-
422-B. The DS89C386 features low power dissipation of 240
mW typical.
Each TRI-STATE®enable, EN, allows the receiver output to
be active or in a Hi-impedance off state. Each enable is
common to only two receivers for flexibility and multiplexing
of receiver outputs.
The receiver output (RO) is guaranteed to be High when the
inputs are left open and unterminated. The receiver can
detect signals as low and including ±200 mV over the com-
mon mode range of ±7V. The receiver outputs (RO) are
compatible with both TTL and CMOS levels.
Features
nLow power design — 240 mW typical
nMeets TIA/EIA-422-B (RS-422)
nReceiver OPEN input failsafe feature
nGuaranteed AC parameters:
— Maximum receiver skew −4 ns
— Maximum transition time −9 ns
nHigh Output Drive Capability: ±6mA
nAvailable in SSOP packaging:
— Requires 30% less PCB space than 3 DS34C86TMs
Connection Diagram
48L SSOP
DS89C386
01208501
Order Number DS89C386TMEA
See NS Package Number MS48A
Function Diagram
01208502
1/6 of package
Truth Table
Enable Inputs Output
EN RI–RI* RO
LXZ
H≥200 mV or OPEN†H
H≤−200 mV L
H +200 mV >and >−200 mV X
†Not terminated.
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
October 2001
DS89C386 Twelve Channel CMOS Differential Line Receiver
© 2004 National Semiconductor Corporation DS012085 www.national.com
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5 to 7V
Input Common Mode Range (V
CM
)±14V
Differential Input Voltage (V
DIFF
)±14V
Enable Input Voltage (V
IN)
7V
Storage Temperature Range (T
STG
) −65˚C to
+150˚C
Lead Temperature (Soldering 4 sec) 260˚C
Maximum Power Dissipation at 25˚C (Note 4)
SSOP Package 1359 mW
Current Per Output ±25 mA
This device does not meet 2000V ESD rating. (Note 5)
Operating Conditions
Min Max Unit
Supply Voltage (V
CC
) 4.50 5.50 V
Operating Temperature Range (T
A
)
DS89C386T −40 +85 ˚C
Enable Input Rise or Fall Times 500 ns
DC Electrical Characteristics (Note 3)
V
CC
=5V±10% (unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
V
TH
Differential Input Voltage V
OUT
=V
OH
or V
OL
−200 ±35 +200 mV
−7V <V
CM
<+7V
V
HYST
Input Hysteresis V
CM
=0V 70 mV
R
IN
Input Resistance V
IN
= −7V, +7V 5.0 6.8 10 kΩ
(Other Input = GND)
I
IN
Input Current V
IN
= +10V, Other Input = GND +1.1 +1.5 mA
(Under Test) V
IN
= −10V, Other Input = GND −2.0 −2.5 mA
V
OH
High Level Output Voltage V
CC
= Min., V
(DIFF)
= +1V 3.8 4.2 V
I
OUT
= −6.0 mA
V
OL
Low Level Output Voltage V
CC
= Max., V
(DIFF)
= −1V 0.2 0.3 V
I
OUT
= 6.0 mA
V
IH
Enable High Input Level Voltage 2.0 V
CC
V
V
IL
Enable Low Input Level Voltage GND 0.8 V
I
OZ
TRI-STATE Output Leakage Current V
OUT
=V
CC
or GND, EN = V
IL
±0.5 ±5.0 µA
I
I
Enable Input Current V
IN
=V
CC
or GND ±1.0 µA
I
CC
Quiescent Power Supply Current V
CC
= Max., V
(DIFF)
= +1V 48 69 mA
DS89C386
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AC Electrical Characteristics (Note 3)
V
CC
=5V±10% (Figures 1, 2, 3)
Symbol Parameter Conditions Min Typ Max Units
t
PLH
, Propagation Delay C
L
=50pF
t
PHL
Input to Output V
DIFF
= 2.5V 10 19 30 ns
V
CM
=0V
t
SK
Skew C
L
=50pF
V
DIFF
= 2.5V 0 2 4 ns
V
CM
=0V
t
RISE
, Output Rise and C
L
=50pF
t
FALL
Fall Times V
DIFF
= 2.5V 4 9 ns
V
CM
=0V
t
PLZ
, Propagation Delay C
L
=50pF
t
PHZ
ENABLE to Output R
L
= 1000Ω13 18 ns
V
DIFF
= 2.5V
t
PZL
, Propagation Delay C
L
=50pF
t
PZH
ENABLE to Output R
L
= 1000Ω13 21 ns
V
DIFF
= 2.5V
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: Unless otherwise specified, all voltages are referenced to ground.
Note 3: Unless otherwise specified, Min/Max limits apply across the operating temperature range. All typicals are given for VCC = 5V and TA= 25˚C.
Note 4: Ratings apply to ambient temperature at 25˚C. Above this temperature derate SSOP (MEA) Package 10.9 mW/˚C.
Note 5: ESD Rating: HEM (1.5 kΩ, 100 pF)
Inputs ≥2000V
Outputs ≥1000V
EIAJ (0Ω, 200 pF)
All Pins ≥350V
DS89C386
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Logic Diagram
01208503
Parameter Measurement Information
01208504
FIGURE 1. Propagation Delays
DS89C386
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Parameter Measurement Information (Continued)
Application Information
SKEW
Skew may be thought of in a lot of different ways, the next
few paragraphs should clarify what is represented by t
SK
in
this datasheet and how it is determined. Skew, as used in
this databook, is the absolute value of a mathematical differ-
ence between two propagation delays. This is commonly
accepted throughout the semiconductor industry. However,
there is no standardized method of measuring propagation
delay, from which skew is calculated, of differential line re-
ceivers. Elucidating, the voltage level, at which propagation
delays are measured, on both input and output waveforms
are not always consistant. Therefore, skew calculated in this
datasheet, may not be calculated the same as skew defined
in another. This is important to remember whenever making
a skew comparison.
Skew may be calculated for the DS89C386, from many
different propagation delay measurements. They may be
classified into two categories, single-ended and differential.
Single-ended skew is calculated from t
PHL
and t
PLH
propa-
01208505
CLIncludes load and test jig capacitance.
S1=V
CC for tPZL, and tPLZ measurements.
S1 = GND for tPZH, and tPHZ measurements.
S1 = Open for tPLH,t
PHL, and tSK.
FIGURE 2. Test Circuit for Switching Characteristics
01208506
FIGURE 3. TRI-STATE Output Enable and Disable Waveforms
01208507
*R
Tis optional although highly recommended to reduce reflections.
FIGURE 4. Two-Wire Balanced System, RS-422
DS89C386
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Application Information (Continued)
gation delay measurements (see Figures 5, 6). Differential
skew is calculated from t
PHLD
and t
PLHD
differential propa-
gation delay measurements (see Figures 7, 8).
In Figure 6, VX, where X is a number, is the waveform
voltage level at which the propagation delay measurement
either starts or stops. Furthermore, V1 and V2 are normally
identical. The same is true for V3 and V4. However, as
mentioned before, these levels are not standardized and
may vary, even with similar devices from other companies.
Also note, V
REF
in Figure 1 should equal V1 and V2 in Figure
6.
The single-ended skew provides information about the pulse
width distortion of the output waveform. The lower the skew,
the less the output waveform will be distorted. For best case,
skew would be zero, and the output duty cycle would be
50%, assuming the input has a 50% duty cycle.
For differential propagation delays, V1 may not equal V2.
Furthermore, the crossing point of RI and RI* corresponds to
zero volts on the differential waveform. (See middle wave-
form in Figure 8.) This is true whether V1 equals V2 or not.
However, if V1 and V2 are specified voltages, then V1 and
(Circuit 1)
01208508
(Circuit 2)
01208509
FIGURE 5. Circuits for Measuring Single-Ended Propagation Delays (See Figure 6)
Waveforms for Circuit 1
01208510
Waveforms for Circuit 2
01208511
FIGURE 6. Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 5)
(Circuit 3)
01208512
FIGURE 7. Circuit for Measuring Differential
Propagation Delays (See Figure 8)
Waveforms for Circuit 3
01208513
FIGURE 8. Propagation Delay Waveforms
for Circuit 3 (see Figure 7)
DS89C386
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Application Information (Continued)
V2 are less likely to be equal to the crossing point voltage.
Thus, the differential propagation delays will not be mea-
sured from zero volts on the differential waveform.
The differential skew also provides information about the
pulse width distortion of the output waveform relative to the
differential input waveform. The higher the skew, the greater
the distortion of the output waveform. Assuming the differen-
tial input has a 50% duty cycle, the output will have a 50%
duty cycle if skew equals zero and less than a 50% duty
cycle if skew is greater than zero.
Only t
SK
is specified in this datasheet for the DS89C386. t
SK
is measured singIe-endedly but corresponds to differential
skew. Because, for single-ended skew, when V
REF
equals
V1 and V2, t
PHL
equals t
PHLD
when t
PHLD
is measured from
the crossing point.
More information can be calculated from the propagation
delays. The channel to channel and device to device skew
may be calculated in addition to the types of skew mentioned
previously. These parameters provide timing performance
information beneficial when designing. The channel to chan-
nel skew is calculated from the variation in propagation delay
from receiver to receiver within one package. The device to
device skew is calculated from the variation in propagation
delay from one DS89C386 to another DS89C386.
For the DS89C386, the maximum channel to channel skew
is 20 ns (t
p
max—t
p
min) where t
p
is the low to high or high
to low propagation delay. The minimum channel to channel
skew is 0 ns since it is possible for all 12 receivers to have
identical propagation delays. Note, this is best and worst
case calculations used whenever t
SK
(channel) is not inde-
pendently characterized and specified in the datasheet. The
device to device skew may be calculated in the same way
and the results are identical. Therefore, the device to device
skew is 20 ns and 0 ns maximum and minimum respectively.
TABLE 1. DS89C386 Skew Table
Parameter Min Typ Max Units
t
SK
(diff.) 0 2 4 ns
t
SK
(channel) 0 20 ns
t
SK
(device) 0 20 ns
Note t
SK
(diff.) in Table 1 is the same as t
SK
in the datasheet.
Also, t
SK
(channel) and t
SK
(device) are calculations, but are
guaranteed by the propagation delay tests. Both t
SK
(chan-
nel) and t
SK
(device) would normally be tighter whenever
specified from characterization data.
The information in this section of the datasheet is to help
clarify how skew is defined in this datasheet. This should
help when designing the DS89C386 into most applications.
Typical Performance Characteristics
Receiver Input Voltage vs
Receiver Input Current
(Notes 6, 7)
01208514
Note 6: The DS89C386 is V.11 compatible. IIN (RI input) is not ≥0 when VIN= 3V due to internal failsafe bias resistors (see Figure 6). See ITU V.11 for complete
conditions.
Note 7: Failsafe (open inputs) is maintained over entire common mode range and operating range ±10V.
DS89C386
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DS89C386 Equivalent Input/Output
Circuits
01208515
FIGURE 9. Receiver Input Equivalent Circuit
01208516
FIGURE 10. Receiver Output Equivalent Circuit
01208517
FIGURE 11. Receiver Enable Equivalent Circuit
DS89C386
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Pin Descriptions
TABLE 2. Device Pin Names and Descriptions
Pin # Pin Name Pin Description
2, 4, 9, 11, 17, 19, 26, RO TTL/CMOS Compatible Receiver Output Pin
28, 33, 35, 41, 43
5, 8, 12, 16, 20, 23, 29, RI Non-Inverting Signal Receiver Input Pin
32, 36, 40, 44, 47
6, 7, 13, 15, 21, 22, 30, RI* Inverting Signal Receiver Input Pin
31, 37, 39, 45, 46
3, 10, 18, 27, 34, 42 EN Active High Dual Receiver Enabling Pin
38 V
CC
Positive Power Supply Pin +5 ±10%
14, 24 GND Device Ground Pin
1, 25, 48 NC Unused Pin (NOT CONNECTED)
DS89C386
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Physical Dimensions inches (millimeters)
unless otherwise noted
48-Lead (0.300" Wide) Molded Shrink Small Outline Package, JEDEC
Order Number DS89C386TMEA
NS Package Number MS48A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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DS89C386 Twelve Channel CMOS Differential Line Receiver
