ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 1 -
AK93C45C/55C/65C
1K/2K/4Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION : VCC = 1.5V to 5.5V(READ)
VCC = 1.6V to 5.5V(WRITE/WRAL/PAGE WRITE)
AK93C45C ・・1024 bits, 64 x 16 organization
AK93C55C ・・2048 bits, 128 x 16 organization
AK93C65C ・・4096 bits, 256 x 16 organization
SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
-1.0MHz(1.5V≤VCC<2.5V), 4.0MHz(2.5V≤VCC≤5.5V)
LOW POWER CONSUMPTION
- 0.8µA Max. Standby
High Reliability
- Endurance : 1000K E/W cycles / Address
- Data Retention : 10 years
Automatic address increment (READ)
Automatic write cycle time-out with auto-ERASE
Busy/Ready status signal
Software and Hardware controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (TMSOP, SON, USON)
Block Diagram
93C45C=1024bit
93C55C=2048bit
93C65C=4096bit
VPP
GENERATOR
DATA
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
INSTRUCTION
REGISTER EEPROM
DI
CS
SK
ADD.
BUFFERS
VREF
VPP SW
DECODER
R/ W AM PS
AND
AUTO ERASE
DO
16
16
PE
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 2 -
General Description
The AK93C45C/55C/65C is a 1024/2048/4096-bit serial CMOS EEPROM divided into 64/128/256
registers of 16 bits each. The AK93C45C/55C/65C has 6 instructions such as READ, WRITE,
PAGE WRITE, EWEN, EWDS and WRAL. Those instructions control the AK93C45C/55C/65C.
The AK93C45C/55C/65C can operate full function under wide operating voltage range. The
charge up circuit is integrated for high voltage generation that is used for write operation.
A serial interface of AK93C45C/55C/65C, consisting of chip select (CS), serial clock (SK), data-in
(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C45C/55C/65C takes in the write data from data input pin (DI) to a register
synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK93C45C/55C/65C takes out the read data from a register to data output pin (DO) synchronously
with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction
is disabled. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must
be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or
VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE,
PAGE WRITE, WRAL, EWEN and EWDS instructions.
x Busy/Ready status signal
After a WRITE, PAGE WRITE, WRAL instruction, the DO output serves as a Busy/Ready status
indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 3 -
Type of Products
Model Memory size Temp. Range VCC Package
AK93C45CT -40°C to +85° C 1.5V to 5.5V 8pin Plastic TMSOP
AK93C45CL -40°C to +85° C 1.5V to 5.5V 8pin Plastic SON
AK93C45CU 1K bits -40°C to +85° C 1.5V to 5.5V 8pin Plastic USON
AK93C55CT -40°C to +85° C 1.5V to 5.5V 8pin Plastic TMSOP
AK93C55CL -40°C to +85° C 1.5V to 5.5V 8pin Plastic SON
AK93C55CU 2K bits -40°C to +85° C 1.5V to 5.5V 8pin Plastic USON
AK93C65CT -40°C to +85° C 1.5V to 5.5V 8pin Plastic TMSOP
AK93C65CL -40°C to +85° C 1.5V to 5.5V 8pin Plastic SON
AK93C65CU 4K bits -40°C to +85° C 1.5V to 5.5V 8pin Plastic USON
Pin Arrangement
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
PE Program Enable
VCC Power Supply
GND Ground
NC Not Connected *1
(note) The PE is internally pulled up to VCC ( R = typ.2.5MΩ, VCC=5V ).
*1: Please Open NC pin.
SK NC
VCC
PE
GND DO
DI
CS 18
2
3
4
7
6
5
AK93C45CL/55CL/65CL
8pi n SO N
AK93C45CT/55CT/65CT
8pin TMSOP
NCS
K
CS
DI
DO
1
2
3
4
8
7
6
5 GND
PE
VCC
1
2
3
4
SKNC
VCC
PE
GND DO
DI
CS
8
7
6
5
AK93C45CU/55CU/65CU
8pi n USON
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 4 -
Functional Description
The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS
and WRAL. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the
desired memory Address location.
The CS pin must be brought low for a minimum of ‘tCS’ between each instruction when the
instruction is continuously executed.
Instruction Start
Bit Op
Code Address Data Comments
READ 1 10 A5-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 1 01 A5-A0 D15-D0 Writes register.
PAGE WRITE 1 11 A5-A0 D15-D0 Page Write register.
EWEN 1 00 11XXXX Write enable must precede all programm ing modes.
EWDS 1 00 00XXXX Disables all programming instructions.
WRAL 1 00 010000 D15-D0 Writes all registers. X: Don't care
table1. Instruction Set for the AK93C45C
Instruction Start
Bit Op
Code Address Data Comments
READ 1 10 XA6-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 1 01 XA6-A0 D15-D0 Writes register.
PAGE WRITE 1 11 XA6-A0 D15-D0 Page Write register.
EWEN 1 00 11XXXXXX Write enable must precede all programm ing modes.
EWDS 1 00 00XXXXXX Disables all programming instructions.
WRAL 1 00 010000000 D15-D0 Writes all registers. X: Don't care
table2. Instruction Set for the AK93C55C
Instruction Start
Bit Op
Code Address Data Comments
READ 1 10 A7-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 1 01 A7-A0 D15-D0 Writes register.
PAGE WRITE 1 11 A7-A0 D15-D0 Page Write register.
EWEN 1 00 11XXXXXX Write enable must precede all programm ing modes.
EWDS 1 00 00XXXXXX Disables all programming instructions.
WRAL 1 00 010000000 D15-D0 Writes all registers. X: Don't care
table3. Instruction Set for the AK93C65C
(Note) x The AK93C45C/55C/65C perceives the start bit in the logic"1" and also "01".
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 5 -
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the
last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the
SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
WRITE (AK93C45C)
WRITE (AK93C55C)
WRITE (AK93C65C)
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
tCS
Busy Ready
A
K93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, P AGE WRITE, WRAL.
D0
1 2 3 4 5 8 9 10
11
23 24 25
D1
D2
D14
D15
A0
A1
A4
1
0
1
0 A5
PE
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
tCS
Busy Ready
A
K93C55C output a logic "1" (Ready status),
if previous instruction is WRITE, P AGE WRITE, WRAL.
D0
1 2 3 4 5 10
11
12
13
25 26 27
D1
D2
D14
D15
A0
A1
A6
1
0
1
0
X: Don't care
X
PE
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
tCS
Busy Ready
A
K93C65C output a logic "1" (Ready status),
if previous instruction is WRITE, P AGE WRITE, WRAL.
D0
1 2 3 4 5 10
11
12
13
25 26 27
D1
D2
D14
D15
A0
A1
A6
1
0
1
0 A7
PE
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 6 -
PAGE WRITE
AK93C45C/55C/65C has Page Write mode, which can write the data within 4 words with one
programming cycle. The input data sent to the shift register within 4 words. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
After the receipt of each word, the two lower order address pointer bits internally incremented by
one. The higher order six bits of the word address remains constant. When the highest address
is reached ”XXXX XX11”, the address counter rolls over to address ”XXXX XX00” allowing the page
write cycle to be continued indefinitely.
If AK93C45C/55C/65C is transmitted more than 4 words, the address counter will ”roll over” and the
previously written data will be overwritten. When AK93C45C/55C/65C is transmitted 6 words, fifth
word will be overwritten to first word, and sixth word will be overwritten to second word.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
PAGE WRITE (AK93C45C)
A3
D2
D1
D0
D15
D14
D15
D0
Hi-Z
D15
D14
D2
D1
D0
D0
25
9
11
12
23
26
27
39
40
41
Hi-Z
D14
D13
D2
A2
A1
A0
0
1
1
1
A5
A4
SK
CS
DI
DO
SK
CS
DI
DO
Read
y
0
1
2
3
4
5
6
7
8
10
D15
Data(n)
Data(n+1) Data(n+3)
24
D1
tCS
Bus
y
tE/W
PE
PE
A
K93C45C output a logic "1" (Ready status),
if previ ous instru ct i on is WR ITE, PA G E WR IT E , WR A L.
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 7 -
PAGE WRITE (AK93C55C)
PAGE WRITE (AK93C65C)
A5
D2
D1
D0
D15
D14
D15
D0
Hi-Z
D15
D14
D2
D1
D0
D0
27
9
11
12
25
28
29
41
42
43
Hi-Z
A0
D15
D2
A4
A3
A2
0
1
1
1
X
A6
SK
CS
DI
DO
SK
CS
DI
DO
Read
y
0
1
2
3
4
5
6
7
8
10
A1
Data(n)
Data(n+1) Data(n+3)
26
D1
tCS
Bus
y
tE/W
PE
PE
A
K93C55C output a logic "1" (Ready status),
if previ ous instru ct i on is WR ITE, PA G E WR IT E , WR A L.
X: Don't care
A5
D2
D1
D0
D15
D14
D15
D0
Hi-Z
D15
D14
D2
D1
D0
D0
27
9
11
12
25
28
29
41
42
43
Hi-Z
A0
D15
D2
A4
A3
A2
0
1
1
1
A7
A6
SK
CS
DI
DO
SK
CS
DI
DO
Read
y
0
1
2
3
4
5
6
7
8
10
A1
Data(n)
Data(n+1) Data(n+3)
26
D1
tCS
Bus
y
tE/W
PE
PE
A
K93C65C output a logic "1" (Ready status),
if previ ous instru ct i on is WR ITE, PA G E WR IT E , WR A L.
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 8 -
Hi-Z
0
CS
SK
DI
DO
Sta rt Bit
A
K9 3C 45C outpu t a log ic "1" (Ready st atus),
if previous instruction is WRITE, PAGE WRITE, WRAL.
1 2 3 4 5
tE/W
tCS
Busy Ready
10
11
12 13 25
D0
D12
D13
D14
D15
1
0
0
0
1
0
6 7 8 9
0
0 0
0
PE
Hi-Z
0
CS
SK
DI
DO
Sta rt Bit
A
K9 3C 55C outpu t a log ic "1" (Ready st atus),
if previous instruction is WRITE, PAGE WRITE, WRAL.
1 2 3 4 5
tE/W
tCS
Busy Ready
10
11
12 13 27
D0
D14
D15
0
0
1
0
0
0
1
0
6 7 8 9
0
0 0
0
PE
Hi-Z
0
CS
SK
DI
DO
Sta rt Bit
A
K9 3C 65C outpu t a log ic "1" (Ready st atus),
if previous instruction is WRITE, PAGE WRITE, WRAL.
1 2 3 4 5
tE/W
tCS
Busy Ready
10
11
12 13 27
D0
D14
D15
0
0
1
0
0
0
1
0
6 7 8 9
0
0 0
0
PE
WRAL
The write instruction is followed by 16 bits of data to be written into all address. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0"
indicates that programming is still in progress. DO=logical "1" indicates that the register at the
address specified in the instruction has been written with the new data pattern contained in the
instruction and the part is ready for a next instruction.
WRAL (AK9 3C45C)
WRAL (AK9 3C55C)
WRAL (AK9 3C65C)
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 9 -
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
Following the Start bit, first Op code and address are decoded, then the data from the selected
memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from
the selected memory location. The output data changes are synchronized with the rising edges of
the serial clock (SK).
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
When the highest address is reached, the address counter rolls over to address 00h allowing the
read cycle to be continued indefinitely.
READ (AK93C45C)
READ (AK93C55C)
READ (AK93C65C)
A
K93C45C output a logic "1" (Ready status),
if previ ous ins t r uc tion is WR ITE, PAG E WR IT E ,
WRAL.
address[A5–A0]+1
Hi-Z
Hi-Z
Dummy
Bit addre ss[A5–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
1 2 3 4 5 10
11
D14
D15
A0
A1
A4
0
1
1
0
25 26 40 41
D15 D1 D0
0
8 9
A5
A
K93C55C output a logic "1" (Ready status),
if previ ous ins t r uc tion is WR ITE, PAG E WR IT E ,
WRAL.
address[A6–A0]+1
Hi-Z
Hi-Z
Dummy
Bit addre ss[A6–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
1 2 3 4 5 12
13
D14
D15
A0
A1
A6
0
1
1
0
27 28 42 43
D15 D1 D0
0
X: Don't care
10
11
X
A
K93C65C output a logic "1" (Ready status),
if previ ous ins t r uc tion is WR ITE, PAG E WR IT E ,
WRAL.
address[A7–A0]+1
Hi-Z
Hi-Z
Dummy
Bit addre ss[A7–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
1 2 3 4 5 12
13
D14
D15
A0
A1
A6
0
1
1
0
27 28 42 43
D15 D1 D0
0
10
11
A7
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 10 -
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction
is disable. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must
be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or
VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
EWEN / EWDS (AK93C45C)
EWEN / EWDS (AK93C55C)
EWEN / EWDS (AK93C65C)
A
K93C45C output a logic "1" (Ready status),
if previous instruction is WRITE P AGE WRITE, WRAL.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
1 2 3 4 5
0
0
1
0
6 7
X X
EWEN=11
X X
8 9
PE
A
K93C55C output a logic "1" (Ready status),
if previous instruction is WRITE P AGE WRITE, WRAL.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
1 2 3 4 5 10 11
0
0
1
0
6 7
X X
X X
EWEN=11
X X
8 9
PE
A
K93C65C output a logic "1" (Ready status),
if previous instruction is WRITE P AGE WRITE, WRAL.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
1 2 3 4 5 10 11
0
0
1
0
6 7
X X
X X
EWEN=11
X X
8 9
PE
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 11 -
Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Power Supply VCC -0.6 +6.5 V
All Input Voltages
with Respect to Ground VIO
-0.6
VCC+0.6
V
Ambient storage temperature Tst -65 +150 °C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Symbol Min Max Unit
Power Supply 1(Except READ) VCC1 1.6 5.5 V
Power Supply 2(READ) VCC2 1.5 5.5 V
Ambient Operating Temperature Ta -40 +85 °C
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 12 -
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.5V
≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
ICC1 VCC=5.5V, tSKP=250ns, *1 2.5 mA
Current Dissipation
(WRITE) ICC2 VCC=1.8V, tSKP=1.0µs, *1 1.5 mA
ICC3 VCC=5.5V, tSKP=250ns, *1 2.5 mA
Current Dissipation
(WRAL) ICC4 VCC=1.8V, tSKP=1.0µs, *1 1.5 mA
ICC5 VCC=5.5V, tSKP=250ns, *1 1.5 mA
Current Dissipation
(READ) ICC6 VCC=1.5V, tSKP=1.0µs, *1 0.1 mA
Current Dissipation
(Standby) ICCSB
VCC=5.5V *2
0.8
µA
VIH1 VCC=5.0V±10% 2.0 VCC + 0.5 V
Input High Voltage
VIH2 2.5V ≤ VCC ≤ 5.5V 0.8 x VCC VCC + 0.5 V
VIH3
1.5V ≤ VCC < 2.5V 0.8 x VCC VCC + 0.5 V
VIL1 VCC=5.0V±10% -0.1 0.8 V
Input Low Voltage
VIL2 1.8V ≤ VCC ≤ 5.5V -0.1 0.15 x VCC V
VIL3
1.5V ≤ VCC < 1.8V -0.1 0.1 x VCC V
Output High Voltage
VOH1
VCC=5.0V±10%
IOH=-0.4mA 2.2
V
VOH2
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA 0.8 x VCC
V
VOH3
1.5V ≤ VCC < 2.5V
IOH=-0.1mA 0.8 x VCC
V
Output Low Voltage
VOL1
VCC=5.0V±10%
IOL=1.5mA
0.4
V
VOL2
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
VOL3
1.5V ≤ VCC < 2.5V
IOL=0.1mA
0.4
V
Input Leakage
ILI
VCC=5.5V, VIN=5.5V *3
±1.0
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
±1.0
µA
*1 : VIN=VIH/VIL, DO=Open
*2 : VIN=VCC/GND, CS=GND, DO=Open, PE=VCC/Open
*3 : CS, SK, DI pin
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 13 -
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.5V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
SK Cycle Time tSKP1 2.5V ≤ VCC ≤ 5.5V 250 ns
tSKP2
1.5V ≤ VCC < 2.5V 1.0 µs
SK Pulse Width tSKW1 2.5V ≤ VCC ≤ 5.5V 100 ns
tSKW2
1.5V ≤ VCC < 2.5V 400 ns
tCSS1 2.5V ≤ VCC ≤ 5.5V 80 ns
CS Setup Time tCSS2 1.5V ≤ VCC < 2.5V 200 ns
CS Hold Time tCSH 0 ns
tDIS1 2.5V ≤ VCC ≤ 5.5V 50 ns
Data Setup Time tDIS2 1.5V ≤ VCC < 2.5V 100 ns
tDIH1 2.5V ≤ VCC ≤ 5.5V 50 ns
Data Hold Time tDIH2 1.5V ≤ VCC < 2.5V 100 ns
tPD1 2.5V ≤ VCC ≤ 5.5V 60 ns
Output delay *4
tPD2 1.5V ≤ VCC < 2.5V 300 ns
Selftimed
Programming T ime tE/W 1.6V ≤ VCC ≤ 5.5V 5 ms
tCS1 2.5V ≤ VCC ≤ 5.5V 60 ns
Min CS Low Time tCS2 1.5V ≤ VCC < 2.5V 200 ns
tCCH1 2.5V ≤ VCC ≤ 5.5V 60 ns
SK HOLD Time tCCH2 1.5V ≤ VCC < 2.5V 200 ns
CS to Status Valid tSV1 2.5V ≤ VCC ≤ 5.5V 125 ns
tSV2
1.6V ≤ VCC < 2.5V 300 ns
tOZ1 2.5V ≤ VCC ≤ 5.5V 75 ns
CS to Output High-Z
tOZ2 1.5V ≤ VCC < 2.5V 100 ns
Endurance *5 5.5V, 25°C, PA GE WRITE 1,000,000 E/W
cycles/
A
ddress
*4 : CL=100pF
*5 : This parameter is not tested to all samples.
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 14 -
Synchronous Data timing
The Start of Instruction
The End of Instruction
Hi-Z
CS
DI
DO
SK
tCSH
tPD tPD tPD tOZ
D2D3 D1 D0
Hi-Z
CS tCSS
tDIS tDIH
1
DI
DO
SK
tSKW tSKW
0
tSKP
tSV
A
K93C45C/55C/65C output a logical "1" (Ready stat us),
if previous instruction is WRITE, PAGE W RITE, WRAL.
ASAHI KASEI [AK93C45C/55C/65C]
DAM06E-01 2005/10
- 15 -
Busy/Ready Signal Output
Hi-Z
CS tCSH
tDIS tDIH
D1
DI
DO
SK
D0
tSV
tCS
tE/W
Busy Ready
tCCH
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