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Publication# 21028 Rev: BAmendment/0
Issue Date: December 1998
Élan™SC400 and ÉlanSC410
Single-Chip, Low-Power,
PC/AT-Compatible Microcontrollers
DISTINCTIVE CHARACTERISTICS
Élan™SC400 and ÉlanSC410
Microcontrollers
■E86TM family of x86 embedded processors
– Offers improved time-to-market, software
migration, and field-proven development tools
■Highly integrated single-chip CPU with a complete
set of common peripherals
– Accelerates time-to-market with simplified
hardware
– Low-power 0.35-micron process technology
– Single chip delivers smallest system form fact or
– 33-MHz, 66- MHz, and 100- M Hz oper at ing
frequencies
■Am486® CPU core
– Robust Microsoft® Windows® compatible CPU
– 8-Kbyte write-back cache for enhanced
performance
– Fully static design with System Management
Mode (SMM) for power savings
■Comprehensive power management unit
– Seven modes of operation allow fine-tuning of
power requirements for maximum battery life
– Provides a superset of APM 1.2 features
■Glueless burst-mode
ROM/Flash memory/SRAM interface
– Reduces system cost by allowing mask ROM and
Flash memory at the same time with three ROM/
Flash memory/SRAM chip selects
■Glueless DRAM controller
– Allows mixed DRAM types on a per-bank basis to
reduce system cost
■VESA Local (VL) bus and ISA bus interface
– Reduces time-to-market with a wide variety of off-
the-shelf companion chips
■Standard PC/AT system logic
(PICs, DMACs, timer, RTC)
– DOS, ROM-DO S, Wi ndo ws, and indus try-
standard BIOS support
– Leverages the benefits of desktop computing
environment at embedded price points
■Bidirectional parallel port with Enhanced
Parallel Port (EPP) mode
■16550-compatible UART
■Infrared port for wireless communication
– Standard and high-speed
■Keyboard interface
– Matrix keyboard support with up to 15 rows and 8
columns
– SCP-emulation mode for PC/AT and XT
keyboar d su ppor t
ÉlanSC400 Microcontroller Only
The ÉlanSC400 microcontroller includes the following
additional features designed specifically for mobile
computin g applic ations. The É lanSC410 microcon trol-
ler does not include these features.
■Dual PC Card (PCMCIA Version 2.1) controller
supports 8- or 16-bit data bus
– End-user (after-market) system expansion
– ExCA-compliant, 82365-register set compatible
– Leverages off-the-shelf card and socket services
– Supports DMA transfers between I/O PC cards
and system DRAM
■LCD graphics controller
– Suppo rts monochro me and 4- bit colo r S up er
Twisted Nematic (STN) LCDs
– Unified Memory Architecture (UMA) eliminates
separate video memory
2Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
GENERAL DESCRIPTION
The Élan™SC400 and ÉlanSC410 microcontrollers
are the among the latest in a series of E86™ family
microcontrollers, which integrate proven x86 CPU
cores wi th a co mpr eh ens ive s e t of on- chi p pe ri ph erals
in a 0.35-micr on process.
The ÉlanSC400 and ÉlanSC410 microcontrollers
combine a 32-bit, low-voltage Am486 CPU with a
complete set of PC/AT-compatible peripherals, along
with the power management features required for
battery operation.
Leveraging the benefits of the x86 desktop computing
environment, the ÉlanSC400 and ÉlanSC410 microcon-
trollers integrate all of the common logic and I/O func-
tionalit y associat ed with a PC/AT computing syste m into
a single device , elimin ating t he ne ed for mu ltip le peri ph-
eral chips. Fully integrated PC/AT-compatible peripher-
als include two 8259A-compatible programmable
interrupt controllers (P ICs), two 8237A-compatible DMA
controllers, an 8254-compatible timer, a 16550 UART,
an IrDA controller, VL-bus and ISA bus controllers, a
real-time clock (RTC), and Enhanced Parallel Port
(EPP) mo de fo r th e pa ral l e l po rt.
With its low-voltage Am486® CPU core and ultra-small
form factor , the ÉlanSC400 microcontroll er is hi ghly op-
timized for mobile computing applications. The
ÉlanSC410 microcontroller is targeted specifically for
embedded systems.
A feature comparison of the two microcontrollers is
shown in Table 1 on page 3.
The ÉlanSC400 and ÉlanSC410 microcontrollers use
the industry-standard 486 microprocessor instruction
set. All software written for the x86 architecture family
is compatible with the ÉlanSC400 and ÉlanSC410
microcontrollers.
The ÉlanSC400 and ÉlanSC410 microcontrollers are
based on a fully static design and include an advanced
power management unit. Operating voltages are
2.7 V–3.3 V with 5-V-tolerant I/O pads. Orderable in
both 33-MHz, 66-MHz, and 100-MHz peak processor
speeds, the product is available in the ultra-small
292 ball grid array (BGA) package.
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid
combinations and to check on newly released
combinations.
–33 A C TEMPERATURE RANGE
C = Commercial
For 33 and 66 MHz: TCASE = 0°C to +95°C
For 100 MHz: TCASE = 0°C to +85°C
I = Industrial
For 33 and 66 MHz, TCASE = – 40°C to +95°C
PACKAGE TYPE
A = 292-pin BGA (Ball Grid Array)
SPEED OPTION
–33 = 33 MHz
–66 = 66 MHz
–100 = 100 MH z
ELANSC400
DEVICE NUMBER/DESCRIPTION
ÉlanSC4 00 mic roc on trol ler
ÉlanSC4 10 mic roc on trol ler
Valid Combinations
ELANSC400–33 AC, AI
ELANSC400–66
ELANSC400–100 AC
ELANSC410–33 AC, AI
ELANSC410–66
ELANSC410–100 AC
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 3
Table 1. Product Comparison—ÉlanSC400 and ÉlanSC410 Microcontrollers
Feature ÉlanSC410 ÉlanSC400
Core CPU
L1 Cache
System management mode (SMM)
Floating-point unit
Am486 CPU
8-Kbyte Write-Back
Yes
No
Am486 CPU
8-Kbyte Write-Back
Yes
No
Data Bus 16, 32 bit 16, 32 bit
ISA Interface
ISA bus mastering 8, 16 bit
No 8, 16 bit
No
VESA Local Bus
VL bus mastering 32 bit
No 32 bit
No
Power Management
Mode timers
Activity detection
SMI/NMI generation
Battery monitoring
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
On-Chip ROM Interface
Width
Size (total ROM space)
ROM chip selects
Burst-mode su ppo rt
Support for SRAM as ROM address space
8, 16, 32 bit
3 x 64 Mbyte
3
Yes
Yes
8, 16, 32 bit
3 x 64 Mbyte
3
Yes
Yes
On-Chip DRAM Controller
Banks
Width
Size (total of all banks)
EDO support
Support for SRAM as main memory
4
16, 32 bit
64 Mbyte
Yes
ROM-mappable
4
16, 32 bit
64 Mbyte
Yes
ROM-mappable
Integrated PC/AT-Compatible Peripherals
Programmable timer (8254-compatible)
Real-time clock (146818A-compatible)
Port B and Port 92h I/O registers
Cascaded DMA Controllers (8237A)
Width
Total numbe r of chann els
External channels
Cascaded Interrupt Controllers (8259)
External IRQ signals
Yes
Yes
Yes
2
8, 16 bit
7
2
2
8
Yes
Yes
Yes
2
8, 16 bit
7
2
2
8
Bidirectional Parallel Port with EPP Mode Yes Yes
Serial Port (UART) 16550-compatible 16550-compatible
Keyboard Interface
Support for external 8042 SCP
XT interface
Matrix scanned with SCP emulation
Yes
Yes
Yes
Yes
Yes
Yes
General-Purpose Input/Output Signals 32 32
Infrared (IrDA) Port Yes Yes
PC Card Controller
Sockets
PCM CIA 2.1-compliant
82365-compatible
No Yes
2
Yes
Yes
LCD Graphics Controller
Programmable clock frequency
Unified memory architecture (UMA)
No Yes
Yes
Yes
JTAG Support Yes Yes
Pin Count and Package 292 BGA 292 BGA
VCC: CPU core
On-chip peri pheral logic
I/O tolerance (designated pins)
2.7–3.3 V
3.3 V
5 V
2.7–3.3 V
3.3 V
5 V
Processor Clock Rate 33, 66, 100 MHz 33, 66, 100 MHz
4Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
BLOCK DIAGRAM—ÉlanSC400 MICROCONTROLLER
Serial Port
Infrared
Graphics or
Local Bus C ontr oll er
Socket A Ctrl
GPIOs or
Parallel Port or
PC Card Socket B
32-kHz Crystal
Clock I/O
GPIOs
GPIOs
Columns or
XT Keyboard
DRAM Control
Addr
Addr
GPIOs
GPIOs
Internal
Bus
System Address Bus
Data
ROM Control
Data Bus
GPIOs or
Keyboard Rows
DRAM Control or
Keyboard Rows
ISA Control or
Keyboard Rows
ISA Control
ISA Control or
GPIOs
GPIOs
Am486®
CPU
Dual DMA
Controllers
8237
Power
Management
Unit
Clock
Generation
Real-Time
Clock
Boundary
Scan
AT P ort
Logic
Timer
8254
Dual Interrupt
Controllers
8259
PC Card
Controller
EPP
Parallel
Port
UART
16550
Infrared
Port
Memory
Management
Unit
Address
Decoder
Data
Steering
LCD
Graphics
Controller
Local Bus
Controller
System
Arbiter
Memory
Controller
Keyboard
Interface:
Matrix/XT/SCP
ISA Bus
Controller
ÉlanSC400 Microcontroller
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 5
BLOCK DIAGRAM—ÉlanSC410 MICROCONTROLLER
System
Arbiter
Serial Port
Infrared
Local Bus Cont roll er
GPIOs or
Parallel Port
32-kHz Crystal
Clock I/O
GPIOs
GPIOs
Columns or
XT Keyboard
DRAM Control
Addr
Addr
GPIOs
GPIOs
Internal
Bus
System Address Bus
Data
ROM Control
Data Bus
GPIOs or
Keyboard Rows
DRAM Control or
Keyboard Rows
ISA Control or
Keyboard Rows
ISA Control
ISA Control or
GPIOs
GPIOs
Am486®
CPU
Dual DMA
Controllers
8237
Power
Management
Unit
Clock
Generation
Real-Time
Clock
Boundary
Scan
AT Port
Logic
Timer
8254
Dual Interrupt
Controllers
8259
EPP
Parallel
Port
UART
16550
Infrared
Port
Memory
Management
Unit
Address
Decoder
Data
Steering
Local Bus
Controller
Memory
Controller
Keyboard
Interface:
Matrix/XT/SCP
ISA Bus
Controller
ÉlanSC410 Microcontroller
6Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
LOGIC SYMBOL—ÉlanSC400 MICROCONTROLLER
DRAM, VL, ROM, ISA
and PC Card Data
Scan Keyboard
Rows/ISA Interface
GPIO/I SA
Interface
GPIO/External
Buffer Control
SA25–SA0
SD15–SD0 [D31–D16]
ROMRD
ROMCS1–ROMCS0
IOR
IOW
MEMR
MEMW
RSTDRV
LCDD0 [VL_RST]
M [VL_BE2]
LC [VL_BE1]
SCK [VL_BE0]
FRM [VL_LCLK]
LVEE [VL_BRDY]
LVDD [VL_BLAST]
DTR, RTS, SOUT
CTS, DCD, DSR
RIN, SIN
SIROUT
SIRIN
ACIN
BL2–BL1
BL0 [CLK_IO]
GPIO_CS0
GPIO_CS1
GPIO_CS2 [[DBUFRDL]]
GPIO_CS3 [[DBUFRDH]]
GPIO_CS4 [[DBUFOE]]
GPIO_CS5 [IOCS16]
GPIO_CS6 [IOCHRDY]
GPIO_CS7 [PIRQ1]
GPIO_CS8 [PIRQ0]
MA11–MA5
D15–D0
RAS1–RAS0
CASL/H1–CASL/H0
MWE
RST_A [[BNDSCN_TDI]]
REG_A [[BNDSCN_TDO]]
CD_A
RDY_A
BVD1_A, BVD2_A
WAIT_AB
OE
WE
ICDIR
WP_A
GPIO31 [STRB] [MCEL_B]
GPIO30 [AFDT] [MCEH_B]
GPIO29 [SLCTIN] [RST_B]
GPIO28 [INIT] [REG_B]
GPIO27 [ERROR] [CD_B]
GPIO26 [PE] [RDY_B]
GPIO25 [ACK] [BVD1_B]
GPIO24 [BUSY] [BVD2_B]
GPIO23 [SLCT] [WP_B]
GPIO22 [PPOEN]
GPIO21 [PPDWE]
32KXTAL1, 32KXTAL2
LF_INT, LF_LS
RESET
BBATSEN
SPKR
BNDSCN_EN
VCC_RTC
GPIO_CS9 [TC]
GPIO_CS10 [AEN]
GPIO_CS11 [PDACK0]
LCDD1 [VL_ADS]
LCDD2 [VL_W/R]
LCDD3 [VL_M/IO]
LCDD4 [VL_LRDY]
LCDD5 [VL_D/C]
LCDD6 [VL_LDEV]
LCDD7 [VL_BE3]
SUS_RES / KBD_ROW14
GPIO_CS12 [PDRQ0]
MA4
MA3 {CFG3}
MA2 {CFG2}
MA1 {CFG1}
MA0 {CFG0}
KBD COL1-0 [XT_CLK/DATA]
KBD_ROW13 [[R32BFOE]]
ROMWR
MCEL_A [[BNDSCN_TCK]]
MCEH_A [[BNDSCN_TMS]]
LF_VID, LF_HS
GPIO_CS13 [PCMA_VCC]
GPIO_CS14 [PCMA_VPP1]
GPIO15 [PCMA_VPP2]
GPIO16 [PCMB_VCC]
GPIO17 [PCMB_VPP1]
GPIO18 [PCMB_VPP2]
GPIO19 [LBL2]
GPIO20 [CD_A2]
KBD_COL7
KBD_COL6-2 / PIRQ7-3
KBD_ROW12 [MCS16]
KBD_ROW11 [SBHE]
KBD_ROW10 [BALE]
KBD_ROW9 [PIRQ2]
KBD_ROW8 [PDRQ1]
KBD_ROW7 [PDACK1]
KBD_ROW6 [MA12]
KBD_ROW5 [RAS3]
KBD_ROW4 [RAS2]
KBD_ROW3 [CASH3]
KBD_ROW2 [CASH2]
KBD_ROW1 [CASL3]
KBD_ROW0 [CASL2]
LCD Graphics
Controller or
VESA Local Bus
8-Pin Serial Port
DRAM Interface
and Feature
Confi g ur a tion Pins
Infrared Interface
Boundary Scan
Enable
Speaker
RTC
Reset
Loop Filters
Power
Management
Interface
GPIOs
GPIO/PC Card
Power Control
Scan Keyboard
Columns/IRQs/XT
Keyboard Interface
Scan Keyboard
Rows/DRAM
Interface
VL, ROM, ISA, and
PC Card Address
ROM/Flash Memory
Control
PC Card Command
ISA Bus Command
and Reset
Dedicated Single
Slot PC Card and
Boundary Scan
Interface
Parallel Port or
Second PC Card or
GPIOs
32-kHz Crystal
ÉlanSC400
Microcontroller
292 BGA
Notes:
/
=Two functions available on the pin at the same time.
{ }
= Function during hardware reset.
[ ]
= Alternative function selected by
firmwar e co nf ig ur at i on.
[[ ]]
= Alternate function selected by a hardware configuration pin state at power-on reset. This does not apply
to [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These alternate functions are enabled by the
BNDSCN_EN signal.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 7
LOGIC SYMBOL—ÉLANSC 410 MICROCONTROLLER
DRAM, VL, ROM,
and ISA Data
Scan Keyboard
Rows/ISA Interface
GPIO/I SA
Interface
GPIO/External
Buffer Control
SA25–SA0
SD15–SD0 [D31–D16]
ROMRD
ROMCS1–ROMCS0
IOR
IOW
MEMR
MEMW
RSTDRV
VL_RST
VL_BE2
VL_BE1
VL_BE0
VL_LCLK
VL_BRDY
VL_BLAST
DTR, RTS, SOUT
CTS, DCD, DSR
RIN, SIN
SIROUT
SIRIN
ACIN
BL2–BL1
BL0 [CLK_IO]
GPIO_CS0
GPIO_CS1
GPIO_CS2 [[DBUFRDL]]
GPIO_CS3 [[DBUFRDH]]
GPIO_CS4 [[DBUFOE]]
GPIO_CS5 [IOCS16]
GPIO_CS6 [IOCHRDY]
GPIO_CS7 [PIRQ1]
GPIO_CS8 [PIRQ0]
MA11–MA5
D15–D0
RAS1–RAS0
CASL/H1–CASL/H0
MWE
[[BNDSCN_TDI]]
[[BNDSCN_TDO]]
GPIO31 [STRB]
GPIO30 [AFDT]
GPIO29 [SLCTIN]
GPIO28 [INIT]
GPIO27 [ERROR]
GPIO26 [PE]
GPIO25 [ACK]
GPIO24 [BUSY]
GPIO23 [SLCT]
GPIO22 [PPOEN]
GPIO21 [PPDWE]
32KXTAL1, 32KXTAL2
LF_INT, LF_LS
RESET
BBATSEN
SPKR
BNDSCN_EN
VCC_RTC
GPIO_CS9 [TC]
GPIO_CS10 [AEN]
GPIO_CS11 [PDACK0]
VL_ADS
VL_W/R
VL_M/IO
VL_LRDY
VL_D/C
VL_LDEV
VL_BE3
SUS_RES / KBD_ROW14
GPIO_CS12 [PDRQ0]
MA4
MA3 {CFG3}
MA2
MA1 {CFG1}
MA0 {CFG0}
KBD COL1-0 [XT_CLK/DATA]
KBD_ROW13 [[R32BFOE]]
ROMWR
[[BNDSCN_TCK]]
[[BNDSCN_TMS]]
LF_HS
GPIO_CS13
GPIO_CS14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19 [LBL2]
GPIO20
KBD_COL7
KBD_COL6-2 / PIRQ7-3
KBD_ROW12 [MCS16]
KBD_ROW11 [SBHE]
KBD_ROW10 [BALE]
KBD_ROW9 [PIRQ2]
KBD_ROW8 [PDRQ1]
KBD_ROW7 [PDACK1]
KBD_ROW6 [MA12]
KBD_ROW5 [RAS3]
KBD_ROW4 [RAS2]
KBD_ROW3 [CASH3]
KBD_ROW2 [CASH2]
KBD_ROW1 [CASL3]
KBD_ROW0 [CASL2]
VESA Local Bus
8-Pin Serial Port
DRAM Interface
and Feature
Confi g ur a tion Pins
Infrared Interface
Boundary Scan
Enable
Speaker
RTC
Reset
Loop Filters
Power
Management
Interface
GPIOs
GPIO/
Power Control
Scan Keyboard
Columns/IRQs/XT
Keyboard Interface
Scan Keyboard
Rows/DRAM
Interface
VL, ROM, and ISA
Address
ROM/Flash Memory
Control
ISA Bus Command
and Reset
Boundary Scan
Interface
Parallel Port or
GPIOs
32-kHz Crystal
ÉlanSC410
Microcontroller
292 BGA
Notes:
/
=Two functions available on the pin at the same time.
{ }
= Function during hardware reset.
[ ]
= Alternative function selected
by firmw ar e configur at i on .
[[ ]]
= Alterna te fun ct ion selected by a hard w ar e configur at ion pin state at pow er-on reset. This does not
apply to [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These functions are enabled by the
BNDSCN_EN signal.
8Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
Élan™SC400 and ÉlanSC410 Microcontrollers ...................................................................... 1
ÉlanSC400 Microcontroller Only ....................... ......... ......... ......... ......... .......................... ........ 1
General Description ..................................................................................................................... 2
Block Diagram—ÉlanSC400 Microcontr oller ...... ....... ......... .......................... ......... ......... ......... ... 4
Block Diagram—ÉlanSC410 Microcontr oller ...... ....... ......... .......................... ......... ......... ......... ... 5
Logic Symbol—ÉlanSC400 Microcontroller ............. ......... ......... ................ ......... ................... ...... 6
Logic Symbol—ÉlanSC410 Microcontroller ............. ......... ......... ................ ......... ................... ...... 7
Related AMD Products .............................................................................................................. 12
E86™ Fa m ily D e vi c es ... .. ....... ........... ...... ........... ........... ........... ........... ............ ...... ........... ..... 12
Related Documents ............................................................................................................... 12
Élan™SC 40 0 Mic r o co n t ro ll e r E va l u at io n B oar d ......... ........... ........... ........... ....... ........... ....... 13
Third-Party Development Support Products .. ..... ... .. ..... ... ..... ... ... ..... .. ...... .. ... ..... ... ..... ... .. ...... .. ...... ..13
Customer Service .................................................................................................................. 13
Architectural Overview ............................................................................................................... 13
Low-Voltage Am486 CPU Core ....... .. ......... ......... .......................... ......... ......... ......... ............ 14
Power Management .............................................................................................................. 14
Clock Generati on .................... ......... .......................... ......... ......... ......... ......... .......... ............. 14
ROM/Flash Memory Interface ............................................................................................... 15
DRAM Controller ................................................................................................................... 15
Integrated Standard PC/AT Peripherals ................................................................................ 15
PC/AT Support Features ....................................................................................................... 16
Bidirectional Enhanced Parallel Port (EPP) .......................................................................... 16
Serial Port .............................................................................................................................. 17
Keyboard Interfaces .............................................................................................................. 17
Programmable General-Purpose Inputs and Outputs ............. ......... ......... ......... ......... ......... . 17
Infrared Port for Wireless Communication ............................................................................ 17
Dual PC Card Controll er (ÉlanSC400 Microcontroller Only) ........ ......... ......... ................... .... 17
Graphics Controller for CGA-Compatible Text and Graphics (ÉlanSC400 Microcontroller Only) .. 17
JTAG Test Features ... .. ......... .......... ......... ......... .. ......... ................ ......... ......... ................... .... 18
System Interfaces ................................................................................................................. 18
System Considerations .............................................................................................................. 20
Connection Diagr am—ÉlanSC400 and ÉlanSC410 Microcontrollers ........ .. .. .. .. ............ .. .. .. .. .. .. 24
Pin Designations ........................................................................................................................ 25
Pin Na min g .. ....... ...... ........... ........... ............ ........... ........... ...... ........... ........... ........... .............. 25
Pin Changes for the ÉlanSC410 Microcontroller ....................................................................... 25
Pin Designations (Pin Nu mber) —ÉlanSC400 Micr ocontroller ... .. .. ............ .. .. .. .. ....................... . 26
Pin Designations (Pin Name)—ÉlanSC400 Microcont roller .... ............... ......... ......... ......... ........ 29
Pin Designations (Pin Nu mber) —ÉlanSC410 Micr ocontroller ... .. .. ............ .. .. .. .. ....................... . 33
Pin Designations (Pin Name)—ÉlanSC410 Microcont roller ................... ......... ......... ......... ........ 36
Pin State Tables ........................................................................................................................ 40
Pin Ch ar a c te ristic s ...... ........... ........... ........... ........... ...... ........... ........... ............ ........... ........... 40
Using the Pin State Tables .................................................................................................... 41
Signal Descriptions .................................................................................................................... 62
Multiplexed Pin Function Options ...................... ................ ......... ................... ......... ......... ...... 70
Using the Configuration Pins to Select Pin Functions.............. ......... ......... ......... ......... ......... . 74
Clocking ..................................................................................................................................... 76
Clock Generati on .................... ......... .......................... ......... ......... ......... ......... .......... ............. 76
Integrated Peripheral Clock Sources .................................................................................... 77
32-kHz Crystal Oscillator ....................................................................................................... 79
Loop F ilt e rs ...... ........... ........... ........... ........... ...... ........... ........... ........... ............ ........... ...... .. ... 79
Intermedi ate and Low-Speed PLLs ................. .. .. ....................... .. .. .. .. .. ............ .. .. .. .. ............ . 79
Graphics Dot Clock PLL (ÉlanSC400 Microcontroll er Only) .............. ......... ......... ......... ........ 80
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 9
High-Speed PLL .................................................................................................................... 81
Band Gap Block ......... .. ......... .......... ......... ......... .. ......... ................ ......... ......... ....................... 81
RTC Voltage Monitor ................... ......... ......... ......... ......... .......... ......... .. ......... ......... ............... 81
Clock Specifications .............................................................................................................. 83
Absolute Maximum Ratings .......................................................................................................86
Operating Ranges ...... ..... ........ ....... ............. ............................................ ............ ........ ............... 86
DC Characteristics Over Commerci al and Industrial Operating Ranges............. .. .. .. .. .. ............ . 86
Capacitance ............................................................................................................................... 87
Typical Power Numbers ............................................................................................................. 88
Power Requirements Under Different Power Management Modes ........ .. .. .. ............ .. .. .. .. .. .. 88
Derating Curves ............................................................................................................... .......... 89
AC Switching Characteristics and Waveforms ............................ ......... ................ ......... ............ 91
Key to Switching Waveforms ................................................................................................ 91
AC Switching Test Waveforms .................................................................................................. 91
AC Switching Characteristics over Commercial and Industrial Operating Ranges ............... 92
Thermal Charact eristics ........ ......... ......... ......... ......... ................... ................ ......... ......... .......... 130
Physical Dimensions—BGA 292—Plastic Ball Grid Array ...................................................... 131
LIST OF FIGURES
Figure 1. Typical Mobile Terminal Design ............................................................................. 21
Figure 2. System Diagr am with Trade-offs —Él anSC400 Microcontroll er ............ .. ......... ...... 22
Figure 3. System Design with Trade-offs—ÉlanSC410 Microcont roller .......... ......... ............ 23
Figure 4. Clock Generation Block Diagram ........................................................................... 76
Figure 5. Clock Source Block Diagram ................................................................................. 78
Figure 6. 32-kHz Crystal Circuit ............................................................................................ 79
Figure 7. 32-kHz Oscillator Circuit ........................................................................................ 79
Figure 8. Intermediate and Low-Speed PLLs Block Diagram ............................................... 80
Figure 9. Graphics Dot Clock PLL Block Diagram ................................................................ 81
Figure 10. High-Speed PLL Block Diagram ............................................................................ 82
Figure 11. RTC Voltage Monitor Circui t .......... .. ................ ................... ......... ......... ......... ........ 82
Figure 12. Timing Diagram for RTC-On Power-Down Sequence ........................................... 83
Figure 13. PLL Enabling Timing Sequence ............................................................................ 85
Figure 14. 3.3-V I/O Drive Type A Rise Time ......................................................................... 89
Figure 15. 3.3-V I/O Drive Type A Fall Time ........................................................................... 89
Figure 16. 3.3-V I/O Drive Type B Rise Time ......................................................................... 89
Figure 17. 3.3-V I/O Drive Type B Fall Time ........................................................................... 89
Figure 18. 3.3-V I/O Drive Type C Rise Time ......................................................................... 90
Figure 19. 3.3-V I/O Drive Type C Fall Time ........................................................................... 90
Figure 20. 3.3-V I/O Drive Type D Rise Time ......................................................................... 90
Figure 21. 3.3-V I/O Drive Type D Fall Time ........................................................................... 90
Figure 22. 3.3-V I/O Drive Type E Rise Time ......................................................................... 90
Figure 23. 3.3-V I/O Drive Type E Fall Time ........................................................................... 90
Figure 24. Power-Up Timing Sequence ............................ .. .. .. .. .. ............ .. .. .. .. ....................... . 92
Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle .................................... 94
Figure 26. Fast Mode CPU Read of Three Consecuti ve Bytes from 8-Bit ROM/Flash Memory .. 95
Figure 27. Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles ............................................ 95
Figure 28. Fast Mode 16-Bit Burst ROM Read Cycles ........................................................... 96
Figure 29. Fast Mode CPU Burst Read from 32-Bit Burst Mode ROM/Flash Memory ........... 96
Figure 30. Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles .................................... 97
Figure 31. Normal Mode 8-/16-Bit Flash Memory Write Cycles .............................................. 97
Figure 32. DRAM Page Hit Read, Interleaved ........... .......................... ......... ......... ......... ........ 99
Figure 33. DRAM Page Hit Write, Interleaved ........................................................................ 99
Figure 34. DRAM Page Miss Read, Interleaved ................................................................... 100
10 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 35. DRAM Page Hit Read, Non-Interl eaved .................. .. ....................... .. .. .. .. ........... 100
Figure 36. DRAM Page Hit Write, Non-Interleaved .............................................................. 101
Figure 37. DRAM Page Miss Read, Non-Interleaved ........................................................... 101
Figure 38. EDO DRAM Page Hit Read, Non-Interleaved ..................................................... 102
Figure 39. EDO DRAM Page Miss Read, Non-Interleaved .................................................. 102
Figure 40. DRAM CAS-Before-RAS Refresh ........................................................................ 103
Figure 41. DRAM Self-Refresh ............................................................................................. 103
Figure 42. DRAM Slow Refresh ............................................................................................ 104
Figure 43. 8-Bit ISA Bus Cycles ............................................................................................ 107
Figure 44. 16-Bit ISA Bus Cycles .......................................................................................... 108
Figure 45. ISA DMA Read Cycle .......................................................................................... 109
Figure 4 6 . ISA DM A Wr ite C y cl e .. ........... ........... ........... ........... ........... ....... ........... ........... ..... 110
Figure 47. VESA Local Bus Cycles ....................................................................................... 112
Figure 48. EPP Parallel Port Write Cycle .............................................................................. 114
Figure 49. EPP Parallel Port Read Cycle ............................................................................. 115
Figure 50. I/O Decode (R/W), Address Decode Only .................... .......................... ......... .... 116
Figure 51. I/O Decode (R/W), Command Qualified ................................ .. .. .. .. ...................... 116
Figure 52. I/O Decode (R/W), GPIO_CSx as 8042CS Timin g ... ... ........... ........... ...... ........... . 117
Figure 53. Memory CS Decode (R/W), Address Decode Only .............. ............ .. .. .. .. ........... 117
Figure 54. Memory CS Decode (R/W), Command Qualif ied ........... ......... .......................... .. 118
Figure 55. PC Card Attribute Memory Read Cycle (ÉlanSC400 Microcontroll er Only) ........ 120
Figure 56. PC Card Attribute Memory Write Cycle (ÉlanSC400 Microcontroller Only) ......... 121
Figure 57. PC Card Common Memory Read Cycle (ÉlanSC400 Microc ontroller Only) ....... 122
Figure 58. PC Card Common Memory Write Cycle (ÉlanSC400 Microcont roller Only) ....... 123
Figure 59. PC Card I/O Read Cycle .................... .. ....................... .. .. .. .. .. ............ .. .. .. .. ........... 124
Figure 60. PC Card I/O Write Cycle ...................................................................................... 125
Figure 61. PC Card DMA Read Cycle (Memory Read to I/O Write) ........... .. ................ ........ 126
Figure 62. PC Card DMA Write Cycle (I/O Read to Memory Write) ..................................... 127
Figure 63. Graphics Panel Interface Timing (ÉlanSC400 Microcontroller Only) ................... 128
Figure 64. Graphics Panel Power Sequencing (ÉlanSC400 Microcon troller Only) .............. 129
LIST OF TABLES
Table 1. Product Comparison—ÉlanSC400 and ÉlanSC410 Microcontroller s .......... .. .. .. .. .... 3
Table 2. Drive Output Descr iption ............................. ................ ................... ......... ......... ...... 40
Table 3. Pin Type Abbreviations .......................................................................................... 40
Table 4. Power Pin Type Abbreviatio ns .............. .. .. .. .. .. ....................... .. .. .. .. ............ .. .. .. .. .. .. 41
Table 5. Power-Down Groups ................ ....................... .. .. .. .. .. ............ .. .. .. .. ....................... . 41
Table 6. Pin State Table—System Interface ........................................................................ 42
Table 7. Pin State Table—Memory Interface ....................................................................... 44
Table 8. Pin State Table—GPIOs/Paralle l Port /PC Card Socket B .............. .. .. .. .. .. ............. 47
Table 9. Pin State Table—GPIOs/ISA Bus .......................................................................... 49
Table 10. Pin State Table—GPIOs/System Data (SD) Buffe r Contr ol .................. .. .. ............ . 51
Table 11. Pin State Table—GPIOs ........................................................................................ 52
Table 12. Pin State Table—Serial Port .................................................................................. 52
Table 13. Pin State Table—Infrared Interface ....................................................................... 52
Table 14. Pin State Table—Keyboard Interface .................................................................... 53
Table 15. Pin State Table—PC Card Socket A ..................................................................... 55
Table 16. Pin State Table—Graphics Controller/VESA Local Bus Control ....... .. .. .. .. ............ . 56
Table 17. Pin State Table—Miscellaneous ............................................................................ 58
Table 18. Pin State Table—Power and Ground ......................... .. .. .. .. .. .......... .. .. .. .. .. ............ . 59
Table 19. Signal Description Table ............................... ......... ......... ................ ................... .... 62
Table 20. Multiplexed Pin Configuration Options ............... ......... ................... ......... ......... ...... 70
Table 21. Pinstrap Bus Buffer Options ........ ......... ................... ................ ......... ......... ............ 74
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 11
Table 22. CFG0 and CFG1 Configuration ....................... .. .. .. .. .. ....................... .. .. .. .. ............ . 74
Table 23. CFG2 Configuration (ÉlanSC400 microcontroller only) .................. ................... .... 74
Table 24. CFG3 Configuration .................. ............ .. .. .. .. .. ....................... .. .. .. .. ............ .. .. .. .. .. .. 75
Table 25. BNDSCN_EN Configuration ............ .. .. ............ .. .. .. .. .. ....................... .. .. .. .. ............ . 75
Table 26. Integ rat ed Pe ripheral Clock Sources .......... .. ......... ......... ......... .......................... .... 77
Table 27. Frequency Select ion Control for Graphi cs Dot Clock PLL ......... .. ......... ......... ........ 80
Table 28. Loop-Filter Component Specification for PLLs ............... .. ......... ................ ............ 84
Table 29. Analog VCC (VCCA) Specification ......................................................................... 84
Table 30. 32.768-kHz Crystal Characteristics ................. ................... ......... ......... ......... ........ 84
Table 31. Start-Up Time Specifications PLLs ....... ................... ......... ......... ......... ......... .......... 84
Table 32. PLL Jitter Speci fication ........... ................ ......... ................... ......... ......... ................ . 85
Table 33. Operating Volt age (Commercial and Industrial) ......... ......... ......... ......... ......... ........ 87
Table 34. Power Estimates .......... .. .. .......... .. .. .. .. .. ............ .. .. .. .. .. ....................... .. .. .. .. ............ . 88
Table 35. Power-On Reset Cycle ........... .. ....................... .. .. .. .. .. ............ .. .. .. .. ....................... . 92
Table 36. ROM/Flash Memory Cycles ......... .. ......... .......................... ......... ......... ......... ......... . 93
Table 37. DRAM Cycles ................... .. .. .. .. ....................... .. .. .. .. .. ............ .. .. .. .. ....................... . 98
Table 38. ISA Cycles ........................ .. .. .. .. ............ .. .. .. .. .. ....................... .. .. .. .. ............ .. .. .. .. ..105
Table 39. VESA Local Bus Cycles ....................................................................................... 111
Table 40. Parallel Po rt Cycles .......... .......................... ......... ......... ......... ......... .......... ......... .. 113
Table 41. General-Purpose Input/Output Cycles .......... .. ............ .. .. .. .. .. .......... .. .. .. .. .. ........... 115
Table 42. PC Card Cycles—ÉlanSC400 Microcontroller Only ................ .. .. .. ...................... 119
Table 43. PC Card Attribut e Memory Read Functi on (ÉlanSC400 Microcontroller Only) .... 120
Table 44. PC Card Attribut e Memory Writ e Function (ÉlanSC400 Microcont roller Only) .... 121
Table 45. PC Card Common Memory Read Function (ÉlanSC400 Microcontr oller Only) .. 122
Table 46. PC Card Common Memory Write Function (ÉlanSC400 Microc ontroller Only) ... 123
Table 47. PC Card I/O Read Function (ÉlanSC400 Microcontroller Only) ....... ......... .......... 124
Table 48. PC Card I/O Write Functi on (ÉlanSC400 Microcontroller Only) ....... .. ......... ........ 125
Table 49. PC Card DMA Read Function (ÉlanSC400 Microcontroller Only) ................... .. .. 126
Table 50. PC Card DMA Write Function (ÉlanSC400 Microcontroller Only) ................... .. .. 127
Table 51. LCD Graphics Control ler Cycles—ÉlanSC400 Microcontroller Only ................... 128
Table 52. Thermal Resist ance ΨJ-T and θJA (°C/W) for the 292-BGA Packag e ) ............... .. 130
Table 53. Maximum TA at Various Airflows in °C ................................................................ 130
12 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
RELATED AMD PRODUCTS
E86™ Family Devices
Device Description
80C186 16-bit microcontroller
80C188 16-bit microcontroller with 8-bit external data bus
80L186 Low-voltage, 16-bit microcontroller
80L188 Low-voltage, 16-bit microcontroller with 8-bit external data bus
Am186™EM High-per fo rmanc e, 80C1 86- comp ati ble , 16-b it emb edde d mic roco ntrol le r
Am188™EM High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
Am186EMLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
Am188EMLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ES High-perfo rm anc e, 80C1 86-c omp ati ble , 16-b it emb edde d micro co ntrol le r
Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or
16-bit external data bus
Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte
of internal RAM
Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus and 32 Kbyte of internal RAM
Am186CC High-performance, 80C186-compatible 16-bit embedded communications controller
Am186CH High-performance, 80C186-compatible 16-bit embedded HDLC microcontroller
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Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller
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ÉlanSC410 Single-chip, PC/AT-compatible microcontroller
Am386®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am386®SX High-performance, 32-bit embedded microprocessor with 16-bit external data bus
Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Related Documents
The following documents provide additional
informat ion regardin g the ÉlanS C400 and Él anSC410
microcontrollers.
■
ÉlanSC400 and ÉlanSC410 User’s Manual
,
order #21030
■
ÉlanSC400 Register Set Reference Manual
,
order #21032
■
ÉlanSC400 Register Set Reference Manual
Amendment
, order #21032A/1
■
ÉlanSC400 Evaluation Board User’s Manual
,
order #21906
■
ÉlanSC400 Microcontroller and Windows CE
µ
forCE Demonstration System User’s Manual
,
order #21892
■
ROMCS0 Redire ction to PC Car d Socket A on th e
ÉlanSC4 00 Mic roc ontr olle r App lica tio n Note
,
order #21643
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 13
ÉlanSC400 Microcontroller
Evaluation Board
The Élan™SC400 microcontroller evaluation board is a
stand-alone evaluation platform for the ÉlanSC400 and
Éla nSC410 microcont rollers.
As a tes t and dev el opm ent pla tform for desi gns ba se d
on the ÉlanSC400 and ÉlanSC410 microcontrollers,
this AMD product is used by system designers to ex-
periment with design trade-offs, make power measure-
ments, and devel op software . Contac t your loc al AM D
sales office for more information on evaluation board
availability and pricing.
Third-Party Development Support Products
The FusionE86SM Program of Partnerships for
Application Solutions provides the customer with an
array of products designed to meet critical time-to-
market needs. Products and solutions available from
the AMD FusionE86 partners include protocol stacks,
emulators, hardware and software debuggers, board-
level products, and software development tools,
among others .
In addition, mature development tools and applications
for the x86 platform are widely available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S.
offices, international offices, and a customer training
center. Expert technical assistance is available from
the AMD w orldwide staff of fiel d applicat ion engi neers
and factory support staff to answer E86™ and
Comm86™ family hardware and software
development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail support as well as a toll-free number for direct
access to our corporate applications hotline.
The AMD World Wide Web home page provides the
latest product information, including technical
information and data on upcoming product releases. In
addition, EPD CodeKit software on the Web site
provides tested source code example applications.
Additional contact information is listed on the back of
this datasheet. For technical support questions on all
E86 and Comm86 products, send e-mail to
epd.support@amd.com.
World Wide Web Home Page
To access the AMD home page, go to: www.amd.com.
Then follow the Embedded Processors link for
information about E86 and Comm86 products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to
webmaster@amd.com.
Documentation and Literature
Free informa tion suc h as data book s, user ’s manua ls,
data sheets, application notes, the
E86™ Family
Products and Development Tools CD
, order #21058,
and other literature is available with a simple phone
call. Internationally , contact your local AMD sales office
for product literature. Additional contact information is
listed on the back of this data sheet.
ARCHITECTURAL OVERVIEW
The architectural goals of the ÉlanSC400 and
ÉlanSC4 10 microc ontrollers included a focus on CPU
performance, CPU-to-memory performance, and inter-
nal graphics controller (ÉlanSC400 microcontroller
only) pe rforman ce. The res ultin g arch itectu re inc ludes
several distinguishing features of interest to the system
designer:
■The main system DRAM is shared between the
CPU and graphics controller, so that the graphics
cont roller can be serviced quickl y to maintain vid eo
display performance at higher panel resolutions.
The internal unified memory architecture (UMA)
implemented on the ÉlanSC400 and ÉlanSC410
microcontrollers means lower cost and less
complication for the system designer, with only one
DRAM interface, fewer pins, and a much smaller
board for many designs.
■CPU-to-memory performance is critical for both
DRAM and ROM accesses. The CPU on the
ÉlanSC400 microcontroller has a concurrent path to
the ROM/Fl ash memory interface an d can exe cute
code out of ROM/Flash memory at the same time
as the grap hics co ntrol ler is ac cess ing DRA M for a
screen refresh. Many system designs can take
advantage of this concurrency without sacrificing
performance.
Corporate Applications Hotline
(800) 222-9323 Toll-free for U.S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
Literature Ordering
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(512) 602-5651 Direct dial worldwide
(512) 602-7639 Fax
14 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
■The ROM/Flash memory interface provides the flex-
ibility to optimize the performance of ROM cycles,
includi ng the support of b urst-mode ROM s. This is
beneficial because products based on the
ÉlanSC400 and ÉlanSC410 microcontrollers may
be impl emented suc h that the operating sy stem or
application programs are executed from ROM.
■Becaus e the m icroco ntroller s supp ort a large nu m-
ber of external buses and interfaces, the address
and data buses are sha re d betw een the vari ous in-
terfaces to reduce pin count on the chip.
These features result in a versatile architecture that
can use various combinations of data bus sizes to
achieve cost an d perfo rman ce goa ls. The ar chite cture
provides maximum performance and flexibility for high-
end vertical applications, but contain s functionality for
a wider horizontal market that may demand less
performance.
■A typical lower performance/lower cost system
might implement 16-bit DRAM banks, an 8-bit ISA
bus, an 8/1 6-bit PC Card bus, and use the in ternal
graphic controller.
■A higher performance, full-featured system might
include 32-bi t DRAM, VL- bus to a n externa l graph-
ics controller, and a 16-bit ISA/PC Card bus.
The followin g bas i c da ta bus confi gur at ion ru les app ly.
(A complete list of feature trade-offs to be considered
in system design can be found in “System Consider-
ations” on page 20.)
■When the internal graphics controller on the
ÉlanSC400 microcontroller is enabled, DRAM is al-
ways 16 bits wide, and no 32-bit targets are sup-
ported. This is because the graphics controller
needs a guaranteed short latency for adequate
video performance. If either 32-bit DRAMs, 32-bit
ROMs, or the VL-bus is enabled, the internal graph-
ics controller is unavailable.
Note that, as a derivative of the original ÉlanSC400 mi-
crocontroller, the ÉlanSC410 microcontroller shares
the primary architectural characteristics of the
ÉlanSC400 microcontroller described above, minus
the graphics controller and PCMCIA interfaces.
The following sections provide an overview of the fea-
tures of th e ÉlanSC400 and Éla nSC410 microcontrolle rs,
including on -chip pe riph erals an d system in te rfac es.
Low-Voltage Am486 CPU Core
The ÉlanSC400 and ÉlanSC410 microcontrollers are
based on the low-v oltage Am 486 CPU c ore. The co re
include s t he foll owing features:
■2.7–3.3-V operation reduces power consumption
■Industry-standard 8-Kbyte unified code and data
write-back cache improves both CPU and total sys-
tem performance by significantly reducing traffic on
the DRAM bus.
■System management mode (SMM) facilitates de-
signs requiring power management by providing a
mechanism to control power to unneeded peripher-
als transparently to application software.
To reduce power consumption, the floating-point unit
has been removed from the Am486 CPU core. Float-
ing-point instructions are not supported on the
ÉlanSC400 and ÉlanSC410 microcontrollers, although
normal software emulation can be easily implemented.
The ÉlanSC400 and ÉlanSC410 microcontrollers use
the industry-standard 486 instruction set. Software
written for the 486 microprocessor and previous mem-
bers of the x86 architecture family can run on the
ÉlanSC400 and ÉlanSC410 microcontrollers.
Power Management
Power management on the ÉlanSC400 and
ÉlanSC410 microcontrollers includes a dedicated
power management unit and additional power man-
agement features built into each integrated peripheral.
The ÉlanSC400 and ÉlanSC410 microcontrollers can
use the following techniques to conserve power:
■Slow down clocks when the system is not in active use
■Shut off clocks to parts of the chip that are idle
■Switch off power to parts of the system that are idle
■Automatically reduce power use when batteries are low
The power man agement unit (PMU) controls stoppin g
and changing clocks, SMI generation, timers, activities,
and battery-level monitoring. It provides:
■Hyper-Speed, High-Speed, Low-Speed, Temporary
Low-Speed, Standby, Suspend, and Critical
Suspend modes
■Dynamically adjusted clock speeds for power
reduction
■Programmable activity and wake-up monitoring
■General-purpose I/O signals to control external
devices and external power management
■Battery low and AC power monitoring
■SMI/NMI synchronization and generation
Clock Generation
The ÉlanSC400 and ÉlanSC410 microcontrollers re-
quire only one 32.768-kHz crystal to generate all the
other clock frequencies required by the system. The
output of the on-chi p cr yst a l osci ll ato r ci rcu it is use d to
generate the various frequencies by utilizing four
Phase-Locked Loop (PLL) circuits (three for the
ÉlanSC410 microcontroller). An additional PLL in the
CPU is used for Hyper-Speed mode.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 15
ROM/Flash Memory Interface
The integra ted ROM/ Flash me mory inte rface sup ports
the following features:
■8-, 16-, and 32-bit ROM/Flash memory interfaces
■Three ROM/Flash memory chip selects
■Burst-mode ROMs
■ROM accesses at both ISA and CPU speeds
(normal and fast-speed modes)
■Dedicated ROM Read and ROM Write signals for
better performance
Each ROM space can accommodate up to 64 Mbyte of
ROM. The three ROM spaces can be individually write-
protected. This is useful for protecting code residing in
Flash memor y devic es.
Two of the three RO M/Flash memory chip s elec ts ca n
be remapp ed to a PC Ca r d so cket v i a pi nst ra p or so ft-
ware control. This feature supports reprogramming of
soldered-down Flash memory boot devices and also
simplifies testing of BIOS/XIP OS code.
Three ROM access modes are supported: Normal
mode, Fast mode, and Burst mode. A different set of
timings is us ed in e ach mo de. In Nor mal RO M ac cess
mode, the bus cycles follow ISA-like timings. In Fast
ROM ac ce ss mode, th e bus c y cle tim ing o cc urs at th e
CPU clock rate with controls for wait-state insertion.
Burst ROM access timing is used when the ROM/Flash
memory interface is fu lfilling an int ernal CPU b urst r e-
quest to support a cache line refill.
W ait states are supported for all ROM and Flash mem-
ory accesses, including Burst mode. Burst-mode
(page-mode) ROM reads are supported for either a
16- or 32-bit ROM interface running in Fast mode.
DRAM Controller
The integrated DRAM controller provides the signals and
associated timing necessary to support an external
DRAM array with minimal software programming and
overhead. Internal programmable registers are provided
to select the DRAM type and operating mode, as well as
refresh options. A wide variety of comm odity DRAMs ar e
supported, and substantial flexibility is built into the DRAM
controller to optimize performance of the CPU and (on the
ÉlanSC40 0 m icrocon tr oller ) t he in tern al grap hics cont rol-
ler, which uses system DRAM f or its buffers.
The DRAM controller supports the following features:
■3.3-V, 70-ns DRAMs
■Up to four banks
■16-bit or 32-bit banks
■Up to 64 Mbyte of total memory
■Self-refresh DRAMs
■Fast page and Extended Data Out (EDO) DRAMs
■Two-way interleaved operation among identically
populated banks using fast-page mode devices
■Mixed depth and width of DRAM banks in non-inter-
leaved mode
■Symmetrical and asymmetrical DRAM support
Integrated Standard PC/AT Peripherals
The ÉlanSC400 and ÉlanSC410 microcontrollers in-
clude a ll the standa rd p eripher al cont roll ers tha t m ake
up a PC/AT system.
Dual DMA Controllers
Dual, cascaded, 8237A-compatible DMA controllers
provide seven user-definable DMA channels. Of the
seven internal channels, four are 8-bit channels and
three a re 16-bit chan nels. Channel 4 is use d for the cas-
cade fu nct i on .
Any t wo of the sev en channe ls can b e mapped s imul-
taneously to external DMA request/acknowledge lines.
The DMA controller on the ÉlanSC400 and ÉlanSC410
microcontrollers is software compatible with the PC/AT
cascaded 8237 controller pair. Its features include:
■Single, block, and demand transfer modes
■Enable/disable channel controller
■Addres s inc reme nt o r decr eme nt
■Software priority
■64-Mbyte system address space for increased
performance
■Dynamic clock-enable design fo r reducing cl ocked
elements during DMA inactivity
■Programmable clock frequency for performance
Dual Interrupt Controllers
Dual, cascaded, 8259-compatible programmable
interrupt controllers support 15 user-definable interrupt
levels. Eight external interrupt requests can be mapped
to any of the 15 internal IRQ inputs.
The interrupt controller block includes these features:
■Software-compatibility with PC/AT interrupt controllers
■15-lev el prior i ty co ntr ol ler
■Programmable interrupt modes
■Individual interrupt request mask capability
■Accepts requests from peripherals
■Resolves priority on pending interrupts and
interrupts in service
■Issues interrupt request to processor
■Provides interrupt vectors for interrupt service routines
■Tied into the PMU for power management
16 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
The interrupt controller block is functionally compatible
with the standard cascaded 8259A controller pair as
implemented in the PC/A T system. The master control-
ler drives the CPU’s interrupt input signal based on the
highest priority interrupt request pending at the master
control ler’s IRQ7–IRQ0 inputs . The mas ter I RQ2 inpu t
is configured for Cascade mode and is driven only by
the slave co ntroller’s interrupt output sign al. The high-
est pending interrupt at the slave’s IRQ inputs will
therefore drive the IRQ2 input of the master.
The interru pt contr oller has programm able so urce s for
interrupts that are contr olled throu gh extende d config-
uration registe rs and, o n th e ÉlanSC4 00 mic rocont rol-
ler, through PC Card controller configuration registers.
Programmable Interval Timer (PIT)
The programmable interval timer (PIT) on the
ÉlanSC400 and ÉlanSC410 microcontrollers is soft-
ware-comp atible with P C/AT 8254 syste m timers. The
PIT provides three 16-bit counters that can be operated
independently in six different modes. The PIT is gener-
ally used for timing external events, counting, and pro-
ducing repetitive waveforms. The PIT can be
programme d to count in bin ar y or in BCD.
Real-Time Clock (RTC)
The RTC designed into the ÉlanSC400 and
ÉlanSC410 microcontrollers is compatible with the
MC146818A dev ic e u se d in PC/AT system s. The RTC
cons i st s of a ti me - of - day cl oc k wi t h a l ar m i n te rrupt and
a 100-year calendar. The clock/calendar has a pro-
grammable periodic interrupt, 114 bytes of static user
RAM, and can be represented in either binary or BCD.
The RTC includes the following features:
■Counts seconds, minutes, and hours of the day
■Counts days of the week, date, month, and year
■12–24 hour clock with AM and PM indication in
12-hour mode
■14 clock, status, and control registers
■114 bytes of general-purpose RAM
■Three separately software-maskable and testable
interrupts
– Time-of-day alarm is programmable to occur
from once-per -s ec ond to once -per -day
– Periodic interrupts can be continued to oc cur at
rates from 122 µs to 500 ms
– Update-ended interrupt provides cycle status
■Dedicated power pin directly supports lithium
backup battery when the rest of the chip is com-
pletely powered down (RTC-only mode)
■Voltage monitor circuit checks the voltage level of
the lithium backup battery and sets a bit when the
battery is below specification.
■Internal RTC reset signal performs a reset when
power is applied to the RTC core.
PC/AT Support Features
The ÉlanSC400 and ÉlanSC410 microcontrollers
provide all of the support functions found in the original
IBM PC/A T. These include the Port B status and control
bits, speaker control, CPU-core reset based on the
system control processor (SCP), and A20 gate control,
as well as extensions for fast CPU core reset. In
addition , a CPU shutdown c ycle (e.g., as a result of a
triple fault) generates a CPU core reset.
Bidirectional Enhanced Parallel Port (EPP)
The parallel port on the ÉlanSC400 and ÉlanSC410
microcontrollers is functionally compatible with IBM
PC/A T and PS/2 systems, with an added EPP mode for
faster transfers. The microcontroller’s parallel port in-
terface provides all the status inputs, control outputs,
and the control si gna ls n ec es sary for t he ex terna l par -
allel port data buffers.
The parallel port interface on both microcontrollers is
shared with some of the GPIO signals and, on the
ÉlanSC400 microcontroller, with the second PC Card
socket interface. Only one of these interfaces can be
enabled at one time.
The parallel port interface can be configured to operate
in one of three different modes of operation:
■PC/AT Compatible mode: This mode provides a
byte-wi de fo rwar d ( host- to-pe ri ph eral) c han nel wit h
data and status lines used according to their original
(Centro nics ) defini tio ns in the IBM PC/AT.
■Bidirectional mode: This mode offers byte-wide bi-
directional parallel data transfers between host and
peripheral, equivalent to the parallel interface on the
IBM PS/2.
■Enhanced Parallel Port (EPP) mode: This mode
provides a byte-wide bidirectional channel con-
trolled by the microcontroller. It provides separate
address and data cycles over the eight data lines of
the interface with an automatic address and data
strobe for the address and data cycles, respectively .
EPP mode offers wider system bandwidth and in-
creased performance over both the PC/A T Compat-
ible and Bidirectional modes.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 17
Serial Port
The ÉlanSC400 and ÉlanSC410 microcontrollers in-
clude an industry-standard 16550A UART. The UART
can be used to drive a standard 8-pin serial interface or
a 2-pin infrared interface. The serial interface and infra-
red interface signals are available on the ÉlanSC400
and ÉlanSC410 microcontrollers at all times, though
only one is available at any given time.
The UART powers up as a 16450-compatible device. It
can be switched to and from the FIFO (16550) mode
under so ftware contro l. In the FIFO mode, the receive
and the transmi t ci r cuitr y ar e e ach e nha nc ed by sep a-
rate 16-byte FIFOs to off-load the CPU from repetiti ve
service routines.
The serial port includes the following features:
■Eight-p in inte rface: s erial in , serial out, two m odem
control lines, and four modem status lines
■Separately enabled receiver line status, receiver
data, character timeout, transmitter holding register ,
and modem status interrupts
■Baud-rate generator provides input clock divisor
from 1 to 65535 to create 16x clock
■5-, 6-, 7-, or 8-bit data
■Even, odd, stick, or no parity generation and
checking
■1, 1-1/2 or 2 stop-bit generation
■Break generation/detection
Keyboard Interfaces
The integrated keyboard controller has the following
features:
■Matrix keyboard support with up to 15 rows and 8
columns
■Hardware support for software emulation of the
System Control Processor (SCP) emulation logic
■XT keyboard interface
Programmable General-Purpose
Inputs and Outputs
The chip supports several general-purpose I/O signals
(GPIOs) that can be us ed on the sy stem board . The r e
are two classifications of GPIO available: the GPIOx
signals , which are progra mmable as inputs or outputs
only, and the GPIO_CSx signals.
The GPIO_ CSx si gna ls h ave many prog ra mma bl e op-
tions. They can be c onfigure d as chip se lects. A s out-
puts, these signals are individually programmable to be
High or Low for the following PMU modes: Hyper , High-
Speed, Low-Speed, Standby, and Suspend. As inputs,
they can be programmed to cause System Manage-
ment Interrupts (SMIs), Non-Maskable Interrupts
(NMIs), wak e-ups, or activiti es for the p ower mana ge-
ment unit. They can also be used as I/O or memory
chip selects.
Infrared Port for Wireless Communication
The ÉlanSC4 00 and Él anSC41 0 microc ontroll ers sup-
port infrared data transfer. This support consists of
adding additional transmit and receive serializers as
well as a con troll ing s tate ma chine an d DMA interf ace
to the internal UART.
The integrated infrared port includes these features:
■Low-spe ed mode supp orts all bit rat es from UART,
up to 115 Kbit/s
■High-speed mode transfers 1.152 Mbit/s using DMA
Dual PC Card Controller
(ÉlanSC400 Microcontroller Only)
The PC Card host bus adapter included on the
ÉlanSC400 microcontroller conforms to
PCMCIA Stan-
dard Rele ase 2.1
. It provides support for two sock ets,
each implementing the PC Card memory and I/O inter-
faces. The PC Card contr oller is not supported on the
ÉlanSC410 microcontroller.
The PC Card controller includes the following features:
■ExCA-compliant, 82365-register-set compatible
■8-bit and 16-bit data bus
■DMA transfers between I/O PC cards and system
DRAM
■Ten available memory windows, five per socket
Of the two PC Card sockets supported, only one is
available in all modes of operation. The second socket
is multiplexed with the parallel port and GPIO features.
Register set compatibility with the 82365SL PC Card
Interface Controller is maintained where features are
common to both controllers.
Of the ten memory windows available, six are dedi-
cated to the PC Card controller and four are shared
with memory mapping system (MMS) Windows C–F.
Two of the three RO M/Flash m emory chip s elects can
be remapp ed to a PC C ard so ck et vi a pins tra p or s oft-
ware control. This feature supports reprogramming of
soldered down Flash memory boot devices and also
simplifies testing of BIOS/XIP OS code.
Graphics Controller for CGA-Compatible
Text and Graphics
(ÉlanSC400 Microcontroller Only)
The graphics controller included on the ÉlanSC400 mi-
crocontroller offers a low-cost integrated graphics solu-
tion for the mobile terminal market. Integration with the
main processor and system logic affords the advan-
18 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
tages of an integrated local-bus interface and frame
and font buffers that are shared with main memory . The
graphics controller is not supported on the ÉlanSC410
microcontroller.
The graphics controller includes the following features:
■Supports multiple panel resolutions
■Provides internal unified memory architecture
(UMA) with optional write-through caching of
graphics buffers
■Stores frame and font buffer data in system DRAM,
eliminates extra memory chip
■Provides software compatibility with Color Graphics
Adapter (CGA), Monochrome Display Adapter
(MDA), and Herc ules G raphics Ada pter (HGA ) tex t
and graphics
■Supports single-scan or dual-scan monochrome
LCD panels with 4-bit or 8-bit data interface
■Typical panels supported include:
– 640 x 200, 640 x 240, 640 x 480, 480 x 320,
480 x 240, 480 x 128, 320 x 200, 320 x 240
– Other resolutions can be supported
■Supports single-scan color STN panels with 8-bit
interface, same resolutions as monochrome mode
■Internal local-bus interface provides high perfor-
mance
■Logical screen can be larger than physical window .
■Supports panning and scrolling
■Supports horizontal dot doubling and vertical line
doubling
The following MDA/CGA-compatible text mode fea-
tures are supported:
■40, 64, or 80 columns with characters 16, 10, or 8
pixels wide
■Variable height characters up to 32 lines
■Variable width characters—8, 10, or 16 pixels
■MDA Monochrome, or CGA 4 gray shades, 16 gray
shade s, or 16-co lor s
■16-Kbyte downloadable font area, relocatable on
16-Kbyte boundaries within lower 16 Mbytes of
system DRAM (can be write protected)
■16-Kbyte frame buffer, relocatable on either
16-Kbyte boundaries within lower 16 Mbyte of
system DRAM (CGA-compatible mode) or 32-Kbyte
boundari es when the fr ame bu ffer is larger th an 16
Kbyte (flat-mapped mode)
The following graphics mode features are supported:
■640 x 200 1 bit-per-pixel, CGA-compatible graphics
buffer memory map
■320 x 200 2 bits-per-pixel, CGA-compatib le graph-
ics buffer memory map
■640 x 480 2 bits-per-pix el, flat m emory map ( lower
resolutions supported)
■640 x 480 1 bit-per-pixel, flat memory map
■1, 2, or 4 bits-per-pixel packed-pixel flat-mapped
graphics up to 640 x 240/480 x 320 with two map-
ping modes:
– 16-Kbyte window with bank swapping to ad-
dress up to 64 Kbyte of graphics frame buffer
while consuming only 16 Kbyte of DOS/Real-
mode CPU address space
– Direct-mapped (no bank swapping) with locat-
able base address, up to 128-Kbyte direct ad-
dressability
■Hercules Graphics mode emulation (HGA)
JTAG Test Features
The ÉlanSC400 and ÉlanSC4 10 microcontrollers pro-
vide a boundary-scan interface based on the
IEEE S td
1149.1, Standard Test Access Port and Boundary-
Scan Architecture
. The test access port provides a
scan interface for testing the microcontroller and sys-
tem hardwa re in a pr oduction e nvironm ent . It contains
extensions that allow a hardware-development system
to control and observe the microcontroller without inter-
posing hardware between the microcontroller and the
system.
System Interfaces
Data Buses
The ÉlanSC400 and ÉlanSC4 10 microcontrollers pro-
vide 32 bits of data that are divided into two separate
16-bit buses.
■System Data Bus: The system (or peripheral) data
bus (SD15–SD0) is always 16 bits wide and is
shared between ISA, 8-bit or 16-bit ROM/Flash
memory, and PC Card peripherals (ÉlanSC400
microcontroller only). It can be directly connected to
all of these devices. In addition, these signals are
the upper word of the VESA local (VL) data bus, the
32-bit DRAM interface, and the 32-bit ROM
interface.
■Data Bus: The D15–D0 data bus is used during
16-bit DRAM cycles. For 32-bit DRAM, VL-bus, and
ROM cycl es, this bus is c ombined with th e system
data bus. In other words, the data bus signals
(D31–D16) are shared with the system data bus
signals SD15–SD0.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 19
The ÉlanSC4 00 and Él anSC410 microcontr olle rs sup-
port the dat a bus configurat ions listed belo w. External
transceivers or buffers can be used to isolate the
buses.
■16-bit DRAM bus, 8-/16-bit ROM, 32-bit VL-bus
disabled, internal graphics controller enabled/
disabled
■16-/32-bit DRAM bus, 8 /16-bit ROM, 32-bit VL- bus
enabled/disabled, internal graphics controller
disabled
■16-/32-bit DRAM bus, 32-bit ROM, 32-bit VL-bus
enabled/disabled, internal graphics controller
disabled
See Figur e 2 o n page 22 and Figure 3 on page 23 for
block diag ra ms of examp le sy st ems .
The ÉlanS C400 and Él anS C41 0 mi crocontroll er s offer
flexibility in configuring the ROM and DRAM data
buses for different widths. The widths (8/16/32 bits) for
ROMCS0 are programmed during power-up through
two pinstraps, CFG0 and CFG1. The DRAM widths
(16/32 bits) are programmed through configuration
registers. Up to four 16- or 32-bit banks of DRAM are
supported.
Two of the three ROM/Flash memory chip selects
(ROMCS2–ROMCS0) c an be r ema ppe d to a P C Ca r d
socket via pinstrap or software control. This feature
supports reprogramming of soldered-down Flash
memory boot devices and also simplifies testing of
BIOS/XIP (execute in place) OS code.
Address Buses
There are two external address buses on the
ÉlanSC400 and ÉlanSC410 microcontrollers.
■System Address Bus: The SA25–SA0 system ad-
dress bus outputs the ph ysical memory or I/O port
latched addresses. These addresses are used by
all external peripheral devices other than main sys-
tem DRAM. In addition, the s ystem addres s bus is
the local address bus in VL-bus mode.
■DRAM Address Bus: DRAM row and column ad-
dresses are multiplexed onto the DRAM address
bus (MA12 –MA0). Row addresses are driven onto
this bus and are valid upon the falling edge of RAS.
Column addresses are driven onto this bus and are
valid upon the falling edge of CAS.
The SA bus is shared between the ISA bus, the
VL-bus, the ROM/Flash memory controller and, on the
ÉlanSC400 microcontroller, the PC Card controller.
The ÉlanSC400 and ÉlanSC410 microcontrollers
provide programmable drive strengths in the I/O
buffers to accommodate loading for various system
configurations.
Memory Management
The ÉlanSC400 and ÉlanSC410 microcontrollers man-
age up to nine separate physical device memory ad-
dress spaces. All but the ISA memory address space
can have a depth of up to 64 Mbyte each. The ISA bus
memory area is limited to 16 Mbyte, as defined by ISA
specific ations. The microcontro ller will dri ve all 26 ad-
dress lines on ISA cycles to allow up to 64-Mbyte ad-
dress space, as described in the memory management
section of the
ÉlanSC400 and ÉlanSC410 Microcon-
trollers User’s Manual
(order #21030)—refer to the
subsectio n on ISA bus a ddress ing). The n ine memo ry
spaces are:
■System memory address space (DRAM)
■ROM0 memory addr e ss spac e (ROMCS0 si gna l)
■ROM1 memory addr e ss spac e (ROMCS1 si gna l)
■ROM2 memory addr e ss spac e (ROMCS2 si gna l)
■PC Card Socket A memory address spaces (com-
mon and attribute) (ÉlanSC400 microcontroller only)
■PC Card Socket B memory address spaces (com-
mon and attribute) (ÉlanSC400 microcontroller only)
■External ISA/VL-bus memory address space
The system memo r y add ress sp ac e (DRAM) is ac ce s-
sible using direct-mapped CPU addresses and can
also be accessed by the CPU in an indirect method
using the Memory Mapping System (MMS). On the
ÉlanSC400 microcontroller, DRAM is also accessible
by the integrated graphics controller if enabled.
The ROM0 add ress sp ace is parti ally acce ssible v ia a
direct mapping of the CPU address bus and partially
accessible via the MMS. The ROM1 and ROM2
address spaces are only accessible indirectly using the
MMS.
On the ÉlanSC400 microcontroller, the PC Card ad-
dress spaces are accessed through a separate,
82365SL-compatible address mapping system.
The ISA/VL-bus address space is accessible as a
direct mapping of the CPU address bu s. ISA memory
cycles are generated when the CPU generates a
memory cycle that is not detected as an access to any
other memory space. An ISA bus memory cycle can
also be generated if the CPU generates a memory
address that resides in the ISA overlapping memory
region windo w. This wi ndow can be defi ned to overlay
any system memory region below 16 Mbyte.
20 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
ISA Bus Interface For External ISA Peripherals
The ISA inte rfac e con si s ts of a su bs et of ISA -com pati-
ble bus signals, allowing for the connection of 8- or
16-bit devices supporting ISA-compatible I/O, memory,
and DMA cycles. The following features are supported:
■8.2944-M Hz max im um bus clock speed
■Programmable DMA clock speed up to 16 MHz
■8-bit and 16-bit ISA I/O and memory cycles (ISA
memory is non-cacheable)
■Direct connection to 3- or 5-volt peripherals
Eight programmable IRQ input signals are available.
These interrupts can be routed via software to any
available PC/AT-compatible interrupt channel.
T wo programmable DMA channels are available for ex-
ternal DMA peripherals. These DMA channels can be
routed to software to any available ISA DMA channel.
VESA Local (VL) Bus Interface Supports 32-Bit
Memory and I/O Targets
The VESA local (VL) bus controller provides the sig-
nals and associated timing necessary to support a sin-
gle VESA compliant VL-bus target. Multiple VL-bus
targets can be supported using external circuitry to
allow multiple VL devices to share the VL_LDEV sig-
nal. This allows the ÉlanSC400 and ÉlanSC410 micro-
controllers to operate as a normal VL-bus motherboard
controller , in accordance with the
VL-Bus Standard 2.0
.
On the ÉlanSC400 microcontroller, the VL-bus is
available only when the internal graphics controller is
disable d.
The microcontroller’s VL-bus controller includes the
following features:
■33-MHz operation at 3.3 V
■32-bit data bus
■Burst-mode transfers
■Register control of local bus reset
VESA bus mastering and DMA transfers to and from
the VL-bus target are not supported. VL memory is
non-cacheable.
SYSTEM CONSIDERATIONS
Figure 1 shows the ÉlanSC400 microcontroller as it
might be used in a minimal system design.
Figure 2 and Figu re 3 sh ow m or e c om ple x syst em de-
signs for each microcontroller and the features that are
traded for others because of pin multiplexing.
■The ÉlanSC400 and ÉlanSC410 microcontrollers
support a maximum of 4 banks of 32-bit DRAM, but
because the RAS and CAS signals for the high
word and for banks 2 and 3 are traded for keyboard
row signals, the minimum system would have one
or two banks of DRAM (either Bank 0 or Bank 1)
populated wi th 1 6-bi t DRAMs . The MA 12 s ignal for
asymmetrical support is also traded with a keyboard
row signal.
■Because the VL-bus and the graphics controller
share control signal s on the ÉlanSC400 m icrocon-
troller, use of the internal graphics controller is
traded with having an external VL-bus on that mi-
crocontroller.
■If either 32-bit DRAMs, 32-bit ROMs, or the VL-bus
is enabled, the internal graphics controller on the
ÉlanSC4 00 microcontroller is unavailable be cause
of internal design constraints.
■The ÉlanSC400 and ÉlanSC410 microcontrollers
provide an absolute minimum of dedicated ISA con-
trol signals. A ny additional ISA controls are traded
with GPIOs or keyboa rd rows and columns.
■The SD buffer shares control signals with some of
the GPIOs. This buffer controls the high word of the
D data bus (D31–D16). Note that using the SD
buffer is optional . The high word of th e D data bus
can be hooke d up directly to devic es that want the
SD data bus (SD15–SD0). Buffering aids in voltage
translation or isolation for heavy loading.
■The R32BFOE signal buffers the high word of the D
data bus (D31–D16) for 32-bit ROMs. The control
signal asso ciated with the ROM 32 buffer is share d
with a keyboard row.
■On the ÉlanSC400 microcontroller, the parallel port
is traded for PC Card Socket B. It requires an exter-
nal buffer and latch.
■The ser ial and inf rared p orts share the same inter-
nal UART. Real-time switching between the two is
supported; however, only one port is available at
any given time.
■ROMCS2 is not connected to a dedicated pin. Soft-
ware can enable and map it to any of the 15
GPIO_CS signals.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 21
Figure 1. Typical Mobile Terminal Design
Column
Conn
PC Card
Socket
A
PC Card
Socket
B
LCD
Serial
Conn
Infrared
Matrix
Power
Supply
Backup
32-kHz
Crystal
Ctrl
SA25–SA0
LCD
Serial
Infrared
Columns
Rows
PC Card B Ctrl
PC Card A Ctrl
Ctrl
SD15–SD0
GPIO_CS12–GPIO_CS0
SD15–SD0
Ctrl
Ctrl Ctrl
SA
SA
Loop
Filters
High D
Bank 0 Bank 1
MA DCtrl
Low
Low
Word
SD SD
MA11–MA0
Ctrl
D15–D0
Keyboard
Row
Conn
Pwr Conn
BIOS/OS
Flash/
ROM
SA25–SA1
Ctrl
Battery
Speaker
Battery
ÉlanSC4 00 Mi cro co ntrol le r
DRAM
DRAM
Serial
Translator
22 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 2. System Diagram with Trade-offs—ÉlanSC400 Microcontroller
PC Card
Socket
A
PC Card
Socket
B
LCD
Conn
Serial
Translator
Serial
Conn
Infrared
Keyboard
Power
Supply
Battery
32-kHz
Crystal
Ctrl
SA
LCD
Serial
Infrared
Columns
Rows
PC Card B Ctrl
PC Card A Ctrl
Ctrl
Parallel Port
Connector
Buffer Latch
VL
Bus
Device
SD
Buffer
Ctrl SD SD
SA
SD
SA
High D
SA
A dashed box indicates a feature that is optional or is traded for another.
ISA
Bus
Device
Ctrl Ctrl
Ctrl
SD
Ctrl
Ctrl
Ctrl
Ctrl SA
SA
Loop
Filters
High D
Bank 0 Bank 1
MA DCtrl
DRAM
Bank 2
DRAM
Bank 3
DRAM
Ctrl
MA12
DRAM DRAM DRAM
Low
DRAM
DRAM
Low D
High
Word
Low
Word
SD SD
Ctrl
Ctrl
ROM32
Buffer
Notes:
Low D
ÉlanSC400 Microcontroller
Backup
Battery
BIOS/
OS/
Apps
Flash
ROM
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 23
Figure 3. System Design with Trade-offs—ÉlanSC410 Microcontroller
Serial
Translator
Serial
Conn
Infrared
Keyboard
Power
Supply
32-kHz
Crystal
Ctrl
SA
Serial
IrDA
Columns
Rows
Parallel Ctrl
ROM Ctrl
Parallel Port
Connector
Buffer and Latch
VL
Bus
Device
SD
Buffer
Ctrl SD SD
SA
SA
High D
SA
A dashed box indicates a feature that is optional or is traded for another.
ISA
Bus
Device
ISA Ctrl Ctrl
Ctrl
SD
Ctrl
Ctrl
Loop
Filters
High D
Bank 0 Bank 1
MA DCtrl
DRAM
Bank 2
DRAM
Bank 3
DRAM
MA12
DRAM DRAM DRAM
Low
DRAM
DRAM
Low D
High
Word
Low
Word
Ctrl
Ctrl
ROM32
Buffer
Notes:
Low D
ÉlanSC410 Microcontroller
Backup
Battery
Ctrl
DRAM
VL-Bus Ctrl
BIOS/
OS/
Apps
Flash
ROM
24 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
CONNECTION DIAGRAM—ÉlanSC400 AND ÉlanSC410 MICROCONTROLLERS
292 Ball Grid Array (BGA) Package
Top View (from component side looking through to bottom)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20
12345678910 11 12 13 14 15 16 17 18 19
20
12345678910 11 12 13 14 15 16 17 18 19
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 25
PIN DESIGNATIONS
This section identifies the pins of the ÉlanSC400 and
ÉlanSC410 microcontrollers and lists the signals asso-
ciated with each pin.
Several different tables are included in this section.
■The Pin Designations (Pin Number)—ÉlanSC400
Microcontroller table beginning on page 26 lists the
ÉlanSC400 microcontroller signals sorted by pin
number.
The Pin Designations (Pin Number)—ÉlanSC410
Microcontroller table on page 33 lists the
ÉlanSC410 microcontroller signals sorted by pin
number.
Along with the Connection Diagram on page 24,
these tables can be used to associate the complete
pin name (including all multiplexed functions) with
the physical pin on the BGA package.
■The Pin Designations (Pin Name)—ÉlanSC400
Microcontroller table on page 29 lists the
ÉlanSC400 microcontroller signals sorted in
alphabetical order.
The Pin Designations (Pin Name)—ÉlanSC410
Microcontroller table on page 36 lists the
ÉlanSC410 microcontroller signals sorted in
alphabetical order.
All multiplexed signals are included in these lists.
Note that these tables should not be used to
determine primary and secondary functions for
multiplexed pins because the ordering was
changed to alphabetize every function. Please refer
to the Pin Designations (Pin Number) table or the
Pin State tables for the definitive listing of primary
and secondary functions in the correct order for
each pin.
■The Pin State tables beginning on page 42, which
group pins alphabetically by function, show pin
states during reset, normal operation, and Suspend
mode, along with output drive strength, maximum
load, supply source, and power-down groups.
■The Signal Descr iption table beginn ing on page 62
includes complete pin descriptions in alphabetical
order by function.
■The table beginning on page 70 clarifies the
configur at ion op tio ns fo r thos e pins ha vi ng mu lti pl e
functions.
Pin Naming
The Signal Name column in the Pin Designation tables
beginning on page 26 and in the Pin State tables be-
ginning on page 40 is decoded as follows:
NAME1/NAME2 {NAME3} [NAME4] [[NAME5]]
NAME1
This is the only function for the pin.
NAME1/NAME2
The slash separates two functions that are available on
the pin at the same time (i.e., at different times in the
same design the pin is used for different functions).
{NAME3}
The name in braces is the pin function during a hard-
ware reset.
[NAME4]
The name in square brackets is the alternative function
for the pin, selected by firmware configuration. Only
one function is available for each configuration.
[[NAME5]]
The name inside double square brackets is the
alternate function for the pin, selected by a hardware
configuration pin state at power-on reset. This does not
apply to [[BNDSCN_TCK]], [[BNDSCN_TMS]],
[[BNDSCN_TDI]], and [[BNDSCN_TDO]]. These four
alternate functions are enabled by the BNDSCN_EN
signal. Only one function is available for each
configuration.
PIN CHANGES FOR THE ÉlanSC410
MICROCONTROLLER
The following signals supported on the ÉlanSC400
microcontroller are not available on the ÉlanSC410
microcontroller.
■Configuration signal: CFG2
■PC Card controller signals: MCEL_A, MCEL_B,
MCEH_A, MCEH_B, RST_A, RST_B, REG_A,
REG_B, CD_A, CD_B, CD_A2, RDY_A, RDY_B,
BVD1_A, BVD1_B, BVD2_A, BVD2_B, WP_A,
WP_B, WAIT_AB, OE, WE, ICDIR, PCMA_VCC,
PCMA_VPP1, PCMA_VPP2, PCMB_VCC,
PCMB_VPP1, PCMB_VPP2
■Graphics controller signals: LCDD7–LCDD0, M,
LC, SCK, FRM, LVEE, LVDD
■Loop filter signal: LF_VID
26 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Number)—ÉlanSC400 Microcontroller
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
A1 KBD_COL5/PIRQ6 B19 KBD_ROW0 [CASL2] D17 GPIO_CS3 [[DBUFRDH]]
A2 KBD_COL2/PIRQ3 B20 LCDD0 [VL_RST]D18 LCDD2 [VL_W/R]
A3 KBD_ROW13 [[R32BFOE]] C1 KBD_ROW11 [SBHE]D19 LCDD4 [VL_LRDY]
A4 D15 C2 KBD_ROW8 [PDRQ1] D20 LCDD7 [VL_BE3]
A5 D12 C3 KBD_COL4/PIRQ5 E1 VCC
A6 D9 C4 GPIO_CS4 [[DBUFOE]] E2 KBD_COL0 [XT_DATA]
A7 D7 C5 KBD_COL7 E3 KBD_ROW9 [PIRQ2]
A8 VCC C6 D13 E4 GND
A9 D4 C7 D10 E17 VCC
A10 D1 C8 D6 E18 LCDD5 [VL_D/C]
A11 MWE C9 D2 E19 FRM [VL_LCLK]
A12 MA2 {CFG2} C10 MA0 {CFG0} E20 LC [VL_BE1]
A13 VCC C11 MA4 F1 SD4 [D20]
A14 MA5 C12 MA7 F2 SD1 [D17]
A15 MA8 C13 MA10 F3 KBD_ROW12 [MCS16]
A16 MA11 C14 CASL1 F4 GND
A17 CASH1 C15 RAS0 F17 LCDD6 [VL_LDEV]
A18 VCC C16 KBD_ROW5 [RAS3]F18 M [VL_BE2]
A19 LVDD [VL_BLAST]C17 KBD_ROW2 [CASH2]F19 SCK [VL_BE0]
A20 LVEE [VL_BRDY]C18 GPIO_CS2 [[DBUFRDL]] F20 SA24
B1 VCC C19 LCDD1 [VL_ADS]G1 SD6 [D22]
B2 KBD_COL6/PIRQ7 C20 LCDD3 [VL_M/IO]G2 SD3 [D19]
B3 KBD_COL3/PIRQ4 D1 KBD_COL1 [XT_CLK] G3 SD0 [D16]
B4 VCC D2 KBD_ROW10 [BALE] G4 GND
B5 D14 D3 KBD_ROW7 [PDACK1]G17 VCC
B6 D11 D4 GND G18 GPIO20 [CD_A2]
B7 D8 D5 GND G19 SA22
B8 D5 D6 GND G20 SA21
B9 D3 D7 GND H1 VCC
B10 D0 D8 GND H2 SD5 [D21]
B11 MA1 {CFG1} D9 GND H3 SD2 [D18]
B12 MA3 {CFG3} D10 GND H4 GND
B13 MA6 D11 GND H8 GND
B14 MA9 D12 GND H9 GND
B15 CASL0 D13 CASH0 H10 GND
B16 VCC D14 RAS1 H11 GND
B17 KBD_ROW6 [MA12] D15 KBD_ROW4 [RAS2]H12 GND
B18 KBD_ROW3 [CASH3]D16 KBD_ROW1 [CASL3]H13 GND
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 27
PIN DESIGNATIONS (Pin Number)—ÉlanSC400 Microcontroller (Con tinued)
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
H17 SA25 L10 GND P3 RDY_A
H18 SA23 L11 GND P4 VCC_CPU
H19 SA20 L12 GND P17 VCC
H20 SA18 L13 GND P18 VCC
J1 SD10 [D26] L17 VCC P19 SA1
J2 SD7 [D23] L18 SA10 P20 SA4
J3 VCC L19 SA9 R1 RST_A [[BNDSCN_TDI]]
J4 GND L20 SA11 R2 CD_A
J8 GND M1 VCC R3 BVD2_A
J9 GND M2 REG_A [[BDNSCN_TDO]] R4 VCC_CPU
J10 GND M3 ICDIR R17 GND
J11 GND M4 VCC_CPU R18 ROMCS0
J12 GND M8 GND R19 IOW
J13 GND M9 GND R20 SA2
J17 VCC M10 GND T1 VCC
J18 SA19 M11 GND T2 WP_A
J19 SA17 M12 GND T3 GPIO22 [PPOEN]
J20 SA14 M13 GND T4 VCC_CPU
K1 SD11 [D27] M17 VCC T17 GND
K2 SD9 [D25] M18 SA7 T18 MEMW
K3 SD8 [D24] M19 VCC T19 ROMCS1
K4 VCC_CPU M20 SA8 T20 SA0
K8 GND N1 SD14 [D30] U1 WAIT_AB
K9 GND N2 WE U2 GPIO25 [ACK] [BVD1_B]
K10 GND N3 MCEH_A [[BNDSCN_TMS]] U3 GPIO24 [BUSY] [BVD2_B]
K11 GND N4 VCC_CPU U4 GPIO23 [SLCT] [WP_B]
K12 GND N8 GND U5 GND
K13 GND N9 GND U6 GND
K17 SA16 N10 GND U7 GND
K18 SA15 N11 GND U8 GND
K19 SA13 N12 GND U9 GND
K20 SA12 N13 GND U10 GND
L1 SD12 [D28] N17 VCC U11 GND
L2 SD13 [D29] N18 SA3 U12 GND
L3 SD15 [D31] N19 SA5 U13 GND
L4 VCC_CPU N20 SA6 U14 GND
L8 GND P1 OE U15 GND
L9 GND P2 MCEL_A [[BNDSCN_TCK]] U16 GND
28 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Number)—ÉlanSC400 Microcontroller (Con tinued)
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
U17 GND V19 GPIO_CS0 Y1 VCC
U18 VCC V20 ROMRD Y2 GPIO28 [INIT] [REG_B]
U19 ROMWR W1 GPIO30 [AFDT] [MCEH_B]Y3 LF_INT
U20 IOR W2 GPIO26 [PE] [RDY_B]Y4 32KXTAL2
V1 BVD1_A W3 GPIO29 [SLCTIN] [RST_B] Y5 GND_ANALOG
V2 GPIO31 [STRB] [MCEL_B]W4 LF_LS Y6 32KXTAL1
V3 GPIO21 [PPDWE]W5 LF_VID Y7 RESET
V4 GPIO27 [ERROR] [CD_B]W6 VCC_A Y8 DTR
V5 LF_HS W7 VCC_RTC Y9 SIRIN
V6 BBATSEN W8 RTS Y10 SOUT
V7 SPKR W9 VCC Y11 BNDSCN_EN
V8 SIROUT W10 DSR Y12 SUS_RES/KBD_ROW14
V9 DCD W11 SIN Y13 BL1
V10 CTS W12 ACIN Y14 GPIO18 [PCMB_VPP2]
V11 RIN W13 BL2 Y15 GPIO15 [PCMA_VPP2]
V12 RSTDRV W14 BL0 [CLK_IO] Y16 VCC
V13 VCC W15 GPIO17 [PCMB_VPP1] Y17 GPIO_CS12 [PDRQ0]
V14 GPIO19 [LBL2]W16 GPIO_CS14 [PCMA_VPP1] Y18 GPIO_CS9 [TC]
V15 GPIO16 [PCMB_VCC]W17 GPIO_CS11 [PDACK0]Y19 GPIO_CS7 [PIRQ1]
V16 GPIO_CS13 [PCMA_VCC]W18 GPIO_CS8 [PIRQ0] Y20 GPIO_CS1
V17 GPIO_CS10 [AEN] W19 GPIO_CS5 [IOCS16]
V18 GPIO_CS6 [IOCHRDY] W20 MEMR
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 29
PIN DESIGNATIONS (Pin Name)—ÉlanSC400 Microcontroller
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
ACIN W12 D2 C9 GND D4
[ACK] [BVD1_B] GPIO25 U2 D3 B9 GND D5
[AEN] GPIO_CS10 V17 D4 A9 GND D6
[AFDT] [MCEH_B] GPIO30 W1 D5 B8 GND D7
[BALE] KBD_ROW10 D2 D6 C8 GND D8
BBATSEN V6 D7 A7 GND D9
BL0 [CLK_IO] W14 D8 B7 GND D10
BL1 Y13 D9 A6 GND D11
BL2 W13 D10 C7 GND D12
BNDSCN_EN Y11 D11 B6 GND E4
[[BNDSCN_TCK]] MCEL_A P2 D12 A5 GND F4
[[BNDSCN_TDI]] RST_A R1 D13 C6 GND G4
[[BNDSCN_TDO]] REG_A M2 D14 B5 GND H4
[[BNDSCN_TMS]] MCEH_A N3 D15 A4 GND H8
[BUSY] [BVD2_B] GPIO24 U3 [D16] SD0 G3 GND H9
BVD1_A V1 [D17] SD1 F2 GND H10
[BVD1_B] GPIO25 [ACK]U2 [D18] SD2 H3 GND H11
BVD2_A R3 [D19] SD3 G2 GND H12
[BVD2_B] GPIO24 [BUSY] U3 [D20] SD4 F1 GND H13
CASH0 D13 [D21] SD5 H2 GND J4
CASH1 A17 [D22] SD6 G1 GND J8
[CASH2] KBD_ROW2 C17 [D23] SD7 J2 GND J9
[CASH3] KBD_ROW3 B18 [D24] SD8 K3 GND J10
CASL0 B15 [D25] SD9 K2 GND J11
CASL1 C14 [D26] SD10 J1 GND J12
[CASL2] KBD_ROW0 B19 [D27] SD11 K1 GND J13
[CASL3] KBD_ROW1 D16 [D28] SD12 L1 GND K8
CD_A R2 [D29] SD13 L2 GND K9
[CD_A2] GPIO20 G18 [D30] SD14 N1 GND K10
[CD_B] GPIO27 [ERROR]V4 [D31] SD15 L3 GND K11
{CFG0} MA0 C10 [[DBUFOE]] GPIO_CS4 C4 GND K12
{CFG1} MA1 B11 [[DBUFRDH]] GPIO_CS3 D17 GND K13
{CFG2} MA2 A12 [[DBUFRDL]] GPIO_CS2 C18 GND L8
{CFG3} MA3 B12 DCD V9 GND L9
[CLK_IO] BL0 W14 DSR W10 GND L10
CTS V10 DTR Y8 GND L11
D0 B10 [ERROR] [CD_B] GPIO27 V4 GND L12
D1 A10 FRM [VL_LCLK] E19 GND L13
30 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Name)—ÉlanSC400 Microcontroller (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
GND M8 GPIO_CS10 [AEN] V17 KBD_ROW0 [CASL2]B19
GND M9 GPIO_CS11 [PDACK0]W17 KBD_ROW1 [CASL3]D16
GND M10 GPIO_CS12 [PDRQ0] Y17 KBD_ROW2 [CASH2]C17
GND M11 GPIO_CS13 [PCMA_VCC]V16 KBD_ROW3 [CASH3]B18
GND M12 GPIO_CS14 [PCMA_VPP1] W16 KBD_ROW4 [RAS2]D15
GND M13 GPIO15 [PCMA_VPP2] Y15 KBD_ROW5 [RAS3]C16
GND N8 GPIO16 [PCMB_VCC]V15 KBD_ROW6 [MA12] B17
GND N9 GPIO17 [PCMB_VPP1] W15 KBD_ROW7 [PDACK1]D3
GND N10 GPIO18 [PCMB_VPP2] Y14 KBD_ROW8 [PDRQ1] C2
GND N11 GPIO19 [LBL2]V14 KBD_ROW9 [PIRQ2] E3
GND N12 GPIO20 [CD_A2]G18 KBD_ROW10 [BALE] D2
GND N13 GPIO21 [PPDWE]V3 KBD_ROW11 [SBHE]C1
GND R17 GPIO22 [PPOEN] T3 KBD_ROW12 [MCS16]F3
GND T17 GPIO23 [SLCT] [WP_B] U4 KBD_ROW13 [[R32BFOE]] A3
GND U5 GPIO24 [BUSY] [BVD2_B] U3 KBD_ROW14 / SUS_RES Y12
GND U6 GPIO25 [ACK] [BVD1_B] U2 [LBL2] GPIO19 V14
GND U7 GPIO26 [PE] [RDY_B]W2 LC [VL_BE1]E20
GND U8 GPIO27 [ERROR] [CD_B]V4 LCDD0 [VL_RST]B20
GND U9 GPIO28 [INIT] [REG_B]Y2 LCDD1 [VL_ADS]C19
GND U10 GPIO29 [SLCTIN] [RST_B] W3 LCDD2 [VL_W/R]D18
GND U11 GPIO30 [AFDT] [MCEH_B]W1 LCDD3 [VL_M/IO]C20
GND U12 GPIO31 [STRB] [MCEL_B]V2 LCDD4 [VL_LRDY]D19
GND U13 ICDIR M3 LCDD5 [VL_D/C]E18
GND U14 [INIT] [REG_B] GPIO28 Y2 LCDD6 [VL_LDEV]F17
GND U15 [IOCHRDY] GPIO_CS6 V18 LCDD7 [VL_BE3]D20
GND U16 [IOCS16] G PIO _CS5 W19 LF_HS V5
GND U17 IOR U20 LF_INT Y3
GND_ANALOG Y5 IOW R19 LF_LS W4
GPIO_CS0 V19 32KXTAL1 Y6 LF_VID W5
GPIO_CS1 Y20 32KXTAL2 Y4 LVDD [VL_BLAST]A19
GPIO_CS2 [[DBUFRDL]] C18 KBD_COL0 [XT_DATA] E2 LVEE [VL_BRDY]A20
GPIO_CS3 [[DBUFRDH]] D17 KBD_COL1 [XT_CLK] D1 M [VL_BE2]F18
GPIO_CS4 [[DBUFOE]] C4 KBD_COL2/PIRQ3 A2 MA0 {CFG0} C10
GPIO_CS5 [IOCS16]W19 KBD_COL3/PIRQ4 B3 MA1 {CFG1} B11
GPIO_CS6 [IOCHRDY] V18 KBD_COL4/PIRQ5 C3 MA2 {CFG2} A12
GPIO_CS7 [PIRQ1] Y19 KBD_COL5/PIRQ6 A1 MA3 {CFG3} B12
GPIO_CS8 [PIRQ0] W18 KBD_COL6/PIRQ7 B2 MA4 C11
GPIO_CS9 [TC] Y18 KBD_COL7 C5 MA5 A14
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 31
PIN DESIGNATIONS (Pin Name)—ÉlanSC400 Microcontroller (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
MA6 B13 RAS0 C15 SA20 H19
MA7 C12 RAS1 D14 SA21 G20
MA8 A15 [RAS2] KBD_ROW4 D15 SA22 G19
MA9 B14 [RAS3] KBD_ROW5 C16 SA23 H18
MA10 C13 RDY_A P3 SA24 F20
MA11 A16 [RDY_B] GPIO26 [PE] W2 SA25 H17
[MA12] KBD_ROW6 B17 REG_A [[BNDSCN_TDO]] M2 [SBHE] KBD_ROW11 C1
MCEH_A [[BNDSCN_TMS]] N3 [REG_B] GPIO28 [INIT]Y2 SCK [VL_BE0]F19
[MCEH_B] GPIO30 [AFDT]W1 RESET Y7 SD0 [D16] G3
MCEL_A [[BNDSCN_TCK]] P2 RIN V11 SD1 [D17] F2
[MCEL_B] GPIO31 [STRB]V2 ROMCS0 R18 SD2 [D18] H3
[MCS16] KBD_ROW12 F3 ROMCS1 T19 SD3 [D19] G2
MEMR W20 ROMRD V20 SD4 [D20] F1
MEMW T18 ROMWR U19 SD5 [D21] H2
MWE A11 RST_A [[BNDSCN_TDI]] R1 SD6 [D22] G1
OE P1 [RST_B] GPIO29 [SLCTIN]W3 SD7 [D23] J2
[PCMA_VCC] GPIO_CS13 V16 RSTDRV V12 SD8 [D24] K3
[PCMA_VPP1] GPIO_CS14 W16 RTS W8 SD9 [D25] K2
[PCMA_VPP2] GPIO15 Y15 SA0 T20 SD10 [D26] J1
[PCMB_VCC] GPIO16 V15 SA1 P19 SD11 [D27] K1
[PCMB_VPP1] GPIO17 W15 SA2 R20 SD12 [D28] L1
[PCMB_VPP2] GPIO18 Y14 SA3 N18 SD13 [D29] L2
[PDACK0] GPIO_CS11 W17 SA4 P20 SD14 [D30] N1
[PDACK1] KBD_ROW7 D3 SA5 N19 SD15 [D31] L3
[PDRQ0] GPIO_CS12 Y17 SA6 N20 SIN W11
[PDRQ1] KBD_ROW8 C2 SA7 M18 SIRIN Y9
[PE] [RDY_B] GPIO26 W2 SA8 M20 SIROUT V8
[PIRQ0] GPIO_CS8 W18 SA9 L19 [SLCT] [WP_B] GPIO23 U4
[PIRQ1] GPIO_CS7 Y19 SA10 L18 [SLCTIN] [RST_B] GPIO29 W3
[PIRQ2] KBD_ROW9 E3 SA11 L20 SOUT Y10
PIRQ3/KBD_COL2 A2 SA12 K20 SPKR V7
PIRQ4/KBD_COL3 B3 SA13 K19 [STRB] [MCEL_B] GPIO31 V2
PIRQ5/KBD_COL4 C3 SA14 J20 SUS_RES/KBD_ROW14 Y12
PIRQ6/KBD_COL5 A1 SA15 K18 [TC] GPIO_CS9 Y18
PIRQ7/KBD_COL6 B2 SA16 K17 VCC A8
[PPDWE] GPIO21 V3 SA17 J19 VCC A13
[PPOEN] GPIO22 T3 SA18 H20 VCC A18
[[R32BFOE]] KBD_ROW13 A3 SA19 J18 VCC B1
32 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Name)—ÉlanSC400 Microcontroller (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
VCC B4 VCC V13 [VL_BE3] LCDD7 D20
VCC B16 VCC W9 [VL_BLAST] LVDD A19
VCC E1 VCC Y1 [VL_BRDY] LVEE A20
VCC E17 VCC Y16 [VL_D/C] LCDD5 E18
VCC G17 VCC_A W6 [VL_LCLK] FRM E19
VCC H1 VCC_CPU K4 [VL_LDEV] LCDD6 F17
VCC J3 VCC_CPU L4 [VL_LRDY] LCDD4 D19
VCC J17 VCC_CPU M4 [VL_M/IO] LCDD3 C20
VCC L17 VCC_CPU N4 [VL_RST] LCDD0 B20
VCC M1 VCC_CPU P4 [VL_W/R] LCDD2 D18
VCC M17 VCC_CPU R4 WAIT_AB U1
VCC M19 VCC_CPU T4 WE N2
VCC N17 VCC_RTC W7 WP_A T2
VCC P17 [VL_ADS] LCDD1 C19 [WP_B] GPIO23 [SLCT] U4
VCC P18 [VL_BE0] SCK F19 [XT_CLK] KBD_COL1 D1
VCC T1 [VL_BE1] LC E20 [XT_DATA] KBD_COL0 E2
VCC U18 [VL_BE2] M F18
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 33
PIN DESIGNATIONS (Pin Number)—ÉlanSC410 MICROCONTROLLER
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
A1 KBD_COL5/PIRQ6 B19 KBD_ROW0 [CASL2] D17 GPIO_CS3 [[DBUFRDH]]
A2 KBD_COL2/PIRQ3 B20 VL_RST D18 VL_W/R
A3 KBD_ROW13 [[R32BFOE]] C1 KBD_ROW11 [SBHE]D19 VL_LRDY
A4 D15 C2 KBD_ROW8 [PDRQ1] D20 VL_BE3
A5 D12 C3 KBD_COL4/PIRQ5 E1 VCC
A6 D9 C4 GPIO_CS4 [[DBUFOE]] E2 KBD_COL0 [XT_DATA]
A7 D7 C5 KBD_COL7 E3 KBD_ROW9 [PIRQ2]
A8 VCC C6 D13 E4 GND
A9 D4 C7 D10 E17 VCC
A10 D1 C8 D6 E18 VL_D/C
A11 MWE C9 D2 E19 VL_LCLK
A12 MA2 C10 MA0 {CFG0} E20 VL_BE1
A13 VCC C11 MA4 F1 SD4 [D20]
A14 MA5 C12 MA7 F2 SD1 [D17]
A15 MA8 C13 MA10 F3 KBD_ROW12 [MCS16]
A16 MA11 C14 CASL1 F4 GND
A17 CASH1 C15 RAS0 F17 VL_LDEV
A18 VCC C16 KBD_ROW5 [RAS3]F18 VL_BE2
A19 VL_BLAST C17 KBD_ROW2 [CASH2]F19 VL_BE0
A20 VL_BRDY C18 GPIO_CS2 [[DBUFRDL]] F20 SA24
B1 VCC C19 VL_ADS G1 SD6 [D22]
B2 KBD_COL6/PIRQ7 C20 VL_M/IO G2 SD3 [D19]
B3 KBD_COL3/PIRQ4 D1 KBD_COL1 [XT_CLK] G3 SD0 [D16]
B4 VCC D2 KBD_ROW10 [BALE] G4 GND
B5 D14 D3 KBD_ROW7 [PDACK1]G17 VCC
B6 D11 D4 GND G18 GPIO20
B7 D8 D5 GND G19 SA22
B8 D5 D6 GND G20 SA21
B9 D3 D7 GND H1 VCC
B10 D0 D8 GND H2 SD5 [D21]
B11 MA1 {CFG1} D9 GND H3 SD2 [D18]
B12 MA3 {CFG3} D10 GND H4 GND
B13 MA6 D11 GND H8 GND
B14 MA9 D12 GND H9 GND
B15 CASL0 D13 CASH0 H10 GND
B16 VCC D14 RAS1 H11 GND
B17 KBD_ROW6 [MA12] D15 KBD_ROW4 [RAS2]H12 GND
B18 KBD_ROW3 [CASH3]D16 KBD_ROW1 [CASL3]H13 GND
34 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Number)—ÉlanSC410 MICROCONTROLLER (Continued)
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
H17 SA25 L10 GND P3 Reserved
H18 SA23 L11 GND P4 VCC_CPU
H19 SA20 L12 GND P17 VCC
H20 SA18 L13 GND P18 VCC
J1 SD10 [D26] L17 VCC P19 SA1
J2 SD7 [D23] L18 SA10 P20 SA4
J3 VCC L19 SA9 R1 [[BNDSCN_TDI]]
J4 GND L20 SA11 R2 Reserved
J8 GND M1 VCC R3 Reserved
J9 GND M2 [[BNDSCN_TDO]] R4 VCC_CPU
J10 GND M3 Reserved R17 GND
J11 GND M4 VCC_CPU R18 ROMCS0
J12 GND M8 GND R19 IOW
J13 GND M9 GND R20 SA2
J17 VCC M10 GND T1 VCC
J18 SA19 M11 GND T2 Reserved
J19 SA17 M12 GND T3 GPIO22 [PPOEN]
J20 SA14 M13 GND T4 VCC_CPU
K1 SD11 [D27] M17 VCC T17 GND
K2 SD9 [D25] M18 SA7 T18 MEMW
K3 SD8 [D24] M19 VCC T19 ROMCS1
K4 VCC_CPU M20 SA8 T20 SA0
K8 GND N1 SD14 [D30] U1 Reserved
K9 GND N2 Reserved U2 GPIO25 [ACK]
K10 GND N3 [[BNDSCN_TMS]] U3 GPIO24 [BUSY]
K11 GND N4 VCC_CPU U4 GPIO23 [SLCT]
K12 GND N8 GND U5 GND
K13 GND N9 GND U6 GND
K17 SA16 N10 GND U7 GND
K18 SA15 N11 GND U8 GND
K19 SA13 N12 GND U9 GND
K20 SA12 N13 GND U10 GND
L1 SD12 [D28] N17 VCC U11 GND
L2 SD13 [D29] N18 SA3 U12 GND
L3 SD15 [D31] N19 SA5 U13 GND
L4 VCC_CPU N20 SA6 U14 GND
L8 GND P1 Reserved U15 GND
L9 GND P2 [[BNDSCN_TCK]] U16 GND
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 35
PIN DESIGNATIONS (Pin Number)—ÉlanSC410 MICROCONTROLLER (Continued)
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
U17 GND V19 GPIO_CS0 Y1 VCC
U18 VCC V20 ROMRD Y2 GPIO28 [INIT]
U19 ROMWR W1 GPIO30 [AFDT]Y3 LF_INT
U20 IOR W2 GPIO26 [PE] Y4 32KXTAL2
V1 Reserved W3 GPIO29 [SLCTIN]Y5 GND_ANALOG
V2 GPIO31 [STRB]W4 LF_LS Y6 32KXTAL1
V3 GPIO21 [PPDWE]W5 Reserved Y7 RESET
V4 GPIO27 [ERROR] W6 VCC_A Y8 DTR
V5 LF_HS W7 VCC_RTC Y9 SIRIN
V6 BBATSEN W8 RTS Y10 SOUT
V7 SPKR W9 VCC Y11 BNDSCN_EN
V8 SIROUT W10 DSR Y12 SUS_RES/KBD_ROW14
V9 DCD W11 SIN Y13 BL1
V10 CTS W12 ACIN Y14 GPIO18
V11 RIN W13 BL2 Y15 GPIO15
V12 RSTDRV W14 BL0 [CLK_IO] Y16 VCC
V13 VCC W15 GPIO17 Y17 GPIO_CS12 [PDRQ0]
V14 GPIO19 [LBL2]W16 GPIO_CS14 Y18 GPIO_CS9 [TC]
V15 GPIO16 W17 GPIO_CS11 [PDACK0]Y19 GPIO_CS7 [PIRQ1]
V16 GPIO_CS13 W18 GPIO_CS8 [PIRQ0] Y20 GPIO_CS1
V17 GPIO_CS10 [AEN] W19 GPIO_CS5 [IOCS16]
V18 GPIO_CS6 [IOCHRDY] W20 MEMR
36 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Na me)— Élan SC410 MICRO CONTROLLER
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
ACIN W12 D10 C7 GND E4
[ACK] GPIO25 U2 D11 B6 GND F4
[AEN] GPIO_CS10 V17 D12 A5 GND G4
[AFDT] GPIO30 W1 D13 C6 GND H4
[BALE] KBD_ROW10 D2 D14 B5 GND H8
BBATSEN V6 D15 A4 GND H9
BL0 [CLK_IO] W14 [D16] SD0 G3 GND H10
BL1 Y13 [D17] SD1 F2 GND H11
BL2 W13 [D18] SD2 H3 GND H12
BNDSCN_EN Y11 [D19] SD3 G2 GND H13
[[BNDSCN_TCK]] P2 [D20] SD4 F1 GND J4
[[BNDSCN_TDI]] R1 [D21] SD5 H2 GND J8
[[BNDSCN_TDO]] M2 [D22] SD6 G1 GND J9
[[BNDSCN_TMS]] N3 [D23] SD7 J2 GND J10
[BUSY] GPIO24 U3 [D24] SD8 K3 GND J11
CASH0 D13 [D25] SD9 K2 GND J12
CASH1 A17 [D26] SD10 J1 GND J13
[CASH2] KBD_ROW2 C17 [D27] SD11 K1 GND K8
[CASH3] KBD_ROW3 B18 [D28] SD12 L1 GND K9
CASL0 B15 [D29] SD13 L2 GND K10
CASL1 C14 [D30] SD14 N1 GND K11
[CASL2] KBD_ROW0 B19 [D31] SD15 L3 GND K12
[CASL3] KBD_ROW1 D16 [[DBUFOE]] GPIO_CS4 C4 GND K13
{CFG0} MA0 C10 [[DBUFRDH]] GPIO_CS3 D17 GND L8
{CFG1} MA1 B11 [[DBUFRDL]] GPIO_CS2 C18 GND L9
{CFG3} MA3 B12 DCD V9 GND L10
[CLK_IO] BL0 W14 DSR W10 GND L11
CTS V10 DTR Y8 GND L12
D0 B10 [ERROR] GPIO27 V4 GND L13
D1 A10 GND D4 GND M8
D2 C9 GND D5 GND M9
D3 B9 GND D6 GND M10
D4 A9 GND D7 GND M11
D5 B8 GND D8 GND M12
D6 C8 GND D9 GND M13
D7 A7 GND D10 GND N8
D8 B7 GND D11 GND N9
D9 A6 GND D12 GND N10
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 37
PIN DESIGNATIONS (Pin Name)—Élan SC410 MICROCONTROLLER (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
GND N11 GPIO19 [LBL2]V14 KBD_ROW10 [BALE] D2
GND N12 GPIO20 G18 KBD_ROW11 [SBHE]C1
GND N13 GPIO21 [PPDWE]V3 KBD_ROW12 [MCS16]F3
GND R17 GPIO22 [PPOEN] T3 KBD_ROW13 [[R32BFOE]] A3
GND T17 GPIO23 [SLCT] U4 KBD_ROW14 / SUS_RES Y12
GND U5 GPIO24 [BUSY] U3 [LBL2] GPIO19 V14
GND U6 GPIO25 [ACK] U2 LF_HS V5
GND U7 GPIO26 [PE] W2 LF_INT Y3
GND U8 GPIO27 [ERROR]V4 LF_LS W4
GND U9 GPIO28 [INIT]Y2 MA0 {CFG0} C10
GND U10 GPIO29 [SLCTIN] W3 MA1 {CFG1} B11
GND U11 GPIO30 [AFDT]W1 MA2 A12
GND U12 GPIO31 [STRB]V2 MA3 {CFG3} B12
GND U13 [INIT] GPIO28 Y2 MA4 C11
GND U14 [IOCHRDY] GPIO_CS6 V18 MA5 A14
GND U15 [IOCS16] G PIO _CS5 W19 MA6 B13
GND U16 IOR U20 MA7 C12
GND U17 IOW R19 MA8 A15
GND_ANALOG Y5 32KXTAL1 Y6 MA9 B14
GPIO_CS0 V19 32KXTAL2 Y4 MA10 C13
GPIO_CS1 Y20 KBD_COL0 [XT_DATA] E2 MA11 A16
GPIO_CS2 [[DBUFRDL]] C18 KBD_COL1 [XT_CLK] D1 [MA12] KBD_ROW6 B17
GPIO_CS3 [[DBUFRDH]] D17 KBD_COL2/PIRQ3 A2 [MCS16] KBD_ROW12 F3
GPIO_CS4 [[DBUFOE]] C4 KBD_COL3/PIRQ4 B3 MEMR W20
GPIO_CS5 [IOCS16]W19 KBD_COL4/PIRQ5 C3 MEMW T18
GPIO_CS6 [IOCHRDY] V18 KBD_COL5/PIRQ6 A1 MWE A11
GPIO_CS7 [PIRQ1] Y19 KBD_COL6/PIRQ7 B2 [PDACK0] GPIO_CS11 W17
GPIO_CS8 [PIRQ0] W18 KBD_COL7 C5 [PDACK1] KBD_ROW7 D3
GPIO_CS9 [TC] Y18 KBD_ROW0 [CASL2]B19 [PDRQ0] GPIO_CS12 Y17
GPIO_CS10 [AEN] V17 KBD_ROW1 [CASL3]D16 [PDRQ1] KBD_ROW8 C2
GPIO_CS11 [PDACK0]W17 KBD_ROW2 [CASH2]C17 [PE] GPIO26 W2
GPIO_CS12 [PDRQ0] Y17 KBD_ROW3 [CASH3]B18 [PIRQ0] GPIO_CS8 W18
GPIO_CS13 V16 KBD_ROW4 [RAS2]D15 [PIRQ1] GPIO_CS7 Y19
GPIO_CS14 W16 KBD_ROW5 [RAS3]C16 [PIRQ2] KBD_ROW9 E3
GPIO15 Y15 KBD_ROW6 [MA12] B17 PIRQ3/KBD_COL2 A2
GPIO16 V15 KBD_ROW7 [PDACK1]D3 PIRQ4/KBD_COL3 B3
GPIO17 W15 KBD_ROW8 [PDRQ1] C2 PIRQ5/KBD_COL4 C3
GPIO18 Y14 KBD_ROW9 [PIRQ2] E3 PIRQ6/KBD_COL5 A1
38 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN DESIGNATIONS (Pin Name)—Élan SC410 MICROCONTROLLER (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
PIRQ7/KBD_COL6 B2 SA12 K20 [STRB] GPIO31 V2
[PPDWE] GPIO21 V3 SA13 K19 SUS_RES/KBD_ROW14 Y12
[PPOEN] GPIO22 T3 SA14 J20 [TC] GPIO_CS9 Y18
[[R32BFOE]] KBD_ROW13 A3 SA15 K18 VCC A8
RAS0 C15 SA16 K17 VCC A13
RAS1 D14 SA17 J19 VCC A18
[RAS2] KBD_ROW4 D15 SA18 H20 VCC B1
[RAS3] KBD_ROW5 C16 SA19 J18 VCC B4
Reserved M3 SA20 H19 VCC B16
Reserved N2 SA21 G20 VCC E1
Reserved P1 SA22 G19 VCC E17
Reserved P3 SA23 H18 VCC G17
Reserved R2 SA24 F20 VCC H1
Reserved R3 SA25 H17 VCC J3
Reserved T2 [SBHE] KBD_ROW11 C1 VCC J17
Reserved U1 SD0 [D16] G3 VCC L17
Reserved V1 SD1 [D17] F2 VCC M1
Reserved W5 SD2 [D18] H3 VCC M17
RESET Y7 SD3 [D19] G2 VCC M19
RIN V11 SD4 [D20] F1 VCC N17
ROMCS0 R18 SD5 [D21] H2 VCC P17
ROMCS1 T19 SD6 [D22] G1 VCC P18
ROMRD V20 SD7 [D23] J2 VCC T1
ROMWR U19 SD8 [D24] K3 VCC U18
RSTDRV V12 SD9 [D25] K2 VCC V13
RTS W8 SD10 [D26] J1 VCC W9
SA0 T20 SD11 [D27] K1 VCC Y1
SA1 P19 SD12 [D28] L1 VCC Y16
SA2 R20 SD13 [D29] L2 VCC_A W6
SA3 N18 SD14 [D30] N1 VCC_CPU K4
SA4 P20 SD15 [D31] L3 VCC_CPU L4
SA5 N19 SIN W11 VCC_CPU M4
SA6 N20 SIRIN Y9 VCC_CPU N4
SA7 M18 SIROUT V8 VCC_CPU P4
SA8 M20 [SLCT] GPIO23 U4 VCC_CPU R4
SA9 L19 [SLCTIN] GPIO29 W3 VCC_CPU T4
SA10 L18 SOUT Y10 VCC_RTC W7
SA11 L20 SPKR V7 VL_ADS C19
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 39
PIN DESIGNATIONS (Pin Name)—Élan SC410 MICROCONTROLLER (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
VL_BE0 F19 VL_BRDY A20 VL_M/IO C20
VL_BE1 E20 VL_D/C E18 VL_RST B20
VL_BE2 F18 VL_LCLK E19 VL_W/R D18
VL_BE3 D20 VL_LDEV F17 [XT_CLK] KBD_COL1 D1
VL_BLAST A19 VL_LRDY D19 [XT_DATA] KBD_COL0 E2
40 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
PIN STATE TABLES
The pin state tables beginning on page 42 are grouped
alphabetically by function and show pin states during
reset, normal operation, and Suspend mode, along
with output drive strength, maximum load, supply
source, and power-down groups.
Pin Characteristics
The following information describes the individual
column headings in the Pin State tables beginning on
page 42. Most abbreviations are defined in Table 3.
Drive types and power-down groups are defined in
Tables 2 and 5, respectively.
■Pin Number: The Pin Number colum n in all tables
identifies the pin number of the individual I/O signal
on the package.
■Type: The abbr eviations in the Type c olumn for all
tables are defined in Table 2.
■Output Drive: The Output Drive column designates
the output drive strength of the pin. The footnote
after the drive strength letter designates that the
drive strength is programmable. The available drive
strengths are indicated in Table 2.
■Max Load: The Max Load column designates the
load at which the I/O timing for that pin is guaran-
teed. It is also used to determine derated AC timing.
■Supply: The Supply column identifies the VCC pin
that supplies power for the specified I/O pin.The pin
state tabl e shows the pin state and termination for
each power management unit mode.
■Normal Operation: The Normal Opera tion column
covers the following power management modes:
– Hyper-Speed mode
– High-Speed mode
– Low-Speed mode
– Temporary Low-Speed mode
– Stand by mod e
■Suspend State: The letters used in the Suspend
State column are defined in Table 3. Note that in
Critical Suspend mode, pin terminations remain un-
changed from the prior mode.
Table 2. Drive Output Description
Output
Drive IohTTL/IolTTL1
Notes:
1. The cur rent out of a pin is given as a negative value.
Vcc
A -3mA/3mA 3.0 V
B -6mA/6mA 3.0 V
C2
2. Output drive is programma ble.
-12mA/12mA 3.0 V
D -18mA/18mA 3.0 V
E2-24mA/24mA 3.0 V
Table 3. Pin Type Abbreviations
Symbol Meaning
[ ] Brackets signify alternate state
{ } Reset configuration pin
- Not an output during Suspend mode
Act Pin continues to function during Suspend
mode
B Bidirectional
H Driven High (a logical 1)
I Pin is an input
IOD Input or open drain output
L Driven Low (a logical 0)
LS Last state of the pin prior to entering Suspend
mode
NA Not applicable
O Pin is an active output
OD Open drain output
OD-STI Pin is typically an open drain output, but can
be c onfigur ed as a Schmitt trigger input
PD Built-in pulldown resistor
PPD Programmable pulldown or no resistor
PPU Programmable pullup or no resistor
PPUD Programmable pullup or pulldown resistor
PU Built-in pullup resistor
S 5-V safe pin
STI Pin is a Schmitt trigger input
STI-OD Pin is typica lly a Schmitt trigge r input, bu t can
be configured as an open-drain output
TS Three-state output
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 41
■Power-Down Group: The signals on the chip are
grouped together by interface for the purpose of
powering down c hips on the s ystem board th at ar e
connecte d to these signals in Suspend mode. The
letters A–I in the Power-Down Group column indi-
cate the group with which each affected signal is as-
sociated. Only those signals that have a different
Suspend state ba sed on th e inter face poweri ng off
have a letter. The interfaces are identified in
Table 5. The extended registers have bits that allow
components connected to each interface to be pow-
ered down in Suspend mode. Care must be taken
when des igning a s ystem with s ections that power
down, because many signals are shared between
components.
■5 V: An S in the 5 V colu mn denotes pins that are
5-volt safe. This means these signals can tolerate 5
volts and the y will not be damaged. Howeve r, they
cannot drive to 5 volts.
Usi n g th e Pin S t at e Tabl es
In the following Pin State tables, multiplexed pins in-
clude v alues spec ific t o each s igna l in the row (ac ross
the table) where that signal is named. If a cell has only
one val ue l isted fo r two or three different sign als, then
this value is constant (does not change) no matter what
signal is programmed to come out on the pin.
■For example, in the table on page 47, when pin V14
is GPIO 19, it is bid irec tiona l; when pin V 14 i s L BL2,
it is an output only. Because the cell includes two
separa te li nes, the p in type is u nique for e ach si gnal .
■When the V14 pin is either GPIO19 or LBL2, the
rese t state is I-PU. Bec ause t here is o nly one v alue
shown in the ta ble, this va lue appl ies to bot h signals.
Table 4. Power Pin Type Abbreviations
Symbol Meaning
A Pin is an analog input
CPU CPU power input
RT C Real-time cl ock inpu t
VCC Power input
Table 5. Power-Down Groups
Group Interface
A DRAM
BROM
C ISA (shared ISA signals individual ly enable d)
D Serial port, serial IrDA infrared port
EGPIO Chip Selects 1–0
FVL bus
G PC Card Socket A
H PC Card Socket B and parallel port
I SD buffer control signals
42 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 6. Pin State Table—System Interface1
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
IOR U20 O C 50 VCC H O H[TS-PD][TS] C 2S
IOW R19 O C 50 VCC H O H[TS-PD][TS] C 2S
MEMR W20 O C 50 VCC H O H[TS-PD][TS] C 2S
MEMW T18 O C 50 VCC H O H[TS-PD][TS] C 2S
RSTDRV V12 O A 30 VCC H O TS-PD 3
SA0 T20 O C–E470 VCC H O TS-PD 3S
SA1 P19 O C–E470 VCC H O TS-PD 3S
SA2 R20 O C–E470 VCC H O TS-PD 3S
SA3 N18 O C–E470 VCC H O TS-PD 3S
SA4 P20 O C–E470 VCC H O TS-PD 3S
SA5 N19 O C–E470 VCC H O TS-PD 3S
SA6 N20 O C–E470 VCC H O TS-PD 3S
SA7 M18 O C–E470 VCC H O TS-PD 3S
SA8 M20 O C–E470 VCC H O TS-PD 3S
SA9 L19 O C–E470 VCC H O TS-PD 3S
SA10 L18 O C–E470 VCC H O TS-PD 3S
SA11 L20 O C–E470 VCC H O TS-PD 3S
SA12 K20 O C–E470 VCC H O TS-PD 3S
SA13 K19 O C–E470 VCC H O TS-PD 3S
SA14 J20 O C–E470 VCC H O TS-PD 3S
SA15 K18 O C–E470 VCC H O TS-PD 3S
SA16 K17 O C–E470 VCC H O TS-PD 3S
SA17 J19 O C–E470 VCC H O TS-PD 3S
SA18 H20 O C–E470 VCC H O TS-PD 3S
SA19 J18 O C–E470 VCC H O TS-PD 3S
SA20 H19 O C–E470 VCC H O TS-PD 3S
SA21 G20 O C–E470 VCC H O TS-PD 3S
SA22 G19 O C–E470 VCC H O TS-PD 3S
SA23 H18 O C–E470 VCC H O TS-PD 3S
SA24 F20 O B 50 VCC H O TS-PD 3S
SA25 H17 O B 50 VCC H O TS-PD 3S
SD0 [D16] G3 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD1 [D17] F2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD2 [D18] H3 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD3 [D19] G2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD4 [D20] F1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD5 [D21] H2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD6 [D22] G1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD7 [D23] J2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD8 [D24] K3 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD9 [D25] K2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD10 [D26] J1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 43
SD11 [D27] K1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD12 [D28] L1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD13 [D29] L2 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD14 [D30] N1 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
SD15 [D31] L3 B [B] C–E470 VCC TS-PD B-PPUD I-PD 5S
Notes:
1. Pin states for AEN, IOCHRDY, IO CS16, PDACK0, PDRQ0, TC, and PIRQ1–PIRQ0 are listed in Table 9 on page 49.
Pin states for BALE, MCS16, SBHE, PDACK1, PDRQ1 and PIRQ7–PIRQ2 are listed in Table 14 on page 53.
2. The ISA contro l sig nals have three programmable opti ons for S usp end mode:
–Driven High (inactive).
–Three-stated with no pullup or pulldown. This is useful when the ISA device is at 5 V and left powered in Suspend. The
board d esign shou ld no t d rive 3.3-V sign als i nto a 5-V de vice durin g Susp end b ecaus e thi s ca n wa ste p ower. The sys tem
designer should provide large pullup resistors to 5 V for each of these signals on the board if this configuration is
programmed.
– Three-stated with pulldown resistors when suspended with the intent of powering off the ISA device
(Power-Down Group C).
Be careful when handling IOR and IOW because they are shared with the PC Card sockets and may need to be buffered if
certain combinations of system components are powered up and off.
Summary: These pins have built-in pulldown resistors that are invoked by:
–Suspend mode and the ISA interface is programmed to be powered off in Suspend mode (Power-Down Group C).
3. The SA bus, SA25–SA0, and the RSTDRV signal are three-stated with pulldowns in Suspend mode. This accommodates
having the ISA bus, PC Card sockets, VL bus, and ROM interfaces left powered on or powered off in Suspend mode.
Summary: These pins have built-in pulldown resistors that are invoked by:
–Suspend mode.
4. C, D, and E output drives are programmable.
5. The combination of SD15–SD0 and D31–D16 on the same pins requires the signals to be pulled up in SD bus mode (for PC
compatibility) and pulled down in D bus mode (for consistency with D15–D0). Regardless of the mode the bus is in, the pins
are in the input state (i.e., they are still bidirectional and are not driven as outputs) and pulled down in Suspend mode.
These signals are pulled up or down automatically dependin g on whether the SD bu ffer is enabled or not (CFG3) , and whether
the system is in Suspend mode or not.
Summary: These pins have built-in pulldown and pullup resistors that are invoked by:
–Reset invokes the pulldown resistors.
–Suspend mode invokes the pulldown resistors.
–Operating (Hyper/High/Low/Temp Low-Speed modes): the pins will have pullups if the SD buffer control signals are
enabled, and have pulldowns otherwise.
Table 6. Pin State Table—System In terface1 (Continued)
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
44 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 7. Pin State Table—Memory Interface1
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
CASH0 D13 O D 30 VCC H O O[L][TS-PD] A 2
CASH1 A17 O D 30 VCC H O O[L][TS-PD] A 2
CASL0 B15 O D 30 VCC H O O[L][TS-PD] A 2
CASL1 C14 O D 30 VCC H O O[L][TS-PD] A 2
D0 B10 B C–E370 VCC TS-PD B-PD TS-PD 4
D1 A10 B C–E370 VCC TS-PD B-PD TS-PD 4
D2 C9 B C–E370 VCC TS-PD B-PD TS-PD 4
D3 B9 B C–E370 VCC TS-PD B-PD TS-PD 4
D4 A9 B C–E370 VCC TS-PD B-PD TS-PD 4
D5 B8 B C–E370 VCC TS-PD B-PD TS-PD 4
D6 C8 B C–E370 VCC TS-PD B-PD TS-PD 4
D7 A7 B C–E370 VCC TS-PD B-PD TS-PD 4
D8 B7 B C–E370 VCC TS-PD B-PD TS-PD 4
D9 A6 B C–E370 VCC TS-PD B-PD TS-PD 4
D10 C7 B C–E370 VCC TS-PD B-PD TS-PD 4
D11 B6 B C–E370 VCC TS-PD B-PD TS-PD 4
D12 A5 B C–E370 VCC TS-PD B-PD TS-PD 4
D13 C6 B C–E370 VCC TS-PD B-PD TS-PD 4
D14 B5 B C–E370 VCC TS-PD B-PD TS-PD 4
D15 A4 B C–E370 VCC TS-PD B-PD TS-PD 4
KBD_ROW0
[CASL2]B19 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW1
[CASL3]D16 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW2
[CASH2]C17 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW3
[CASH3]B18 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW4
[RAS2]D15 STI-OD
[O] C–E3250 VCC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW5
[RAS3]C16 STI-OD
[O] C–E3250 VCC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW6
[MA12] B17 STI-OD
[O] C–E3250 VCC I-PU IOD-PU
OI-PU
TS-PD
5
MA0 {CFG0} C10 O {I} C–E370 VCC I-PD O TS-PPD 6
MA1 {CFG1} B11 O {I} C–E370 VCC I-PD O TS-PPD 6
MA2 {CFG2} A12 O {I} C–E370 VCC I-PD O TS-PPD 6, 7
MA3 {CFG3} B12 O {I} C–E370 VCC I-PD O TS-PPD 6
MA4 C11 O C–E370 VCC I-PD O TS-PD 6, 8
MA5 A14 O C–E370 VCC L O TS-PD 8
MA6 B13 O C–E370 VCC L O TS-PD 8
MA7 C12 O C–E370 VCC L O TS-PD 8
MA8 A15 O C–E370 VCC L O TS-PD 8
MA9 B14 O C–E370 VCC L O TS-PD 8
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 45
MA10 C13 O C–E370 VCC L O TS-PD 8
MA11 A16 O C–E370 VCC L O TS-PD 8
MWE A11 O C–E370 VCC H O H[TS-PD] A 2
RAS0 C15 O C–E350 VCC H O O[L][TS-PD] A 2
RAS1 D14 O C–E350 VCC H O O[L][TS-PD] A 2
ROMCS0 R18 O B 50 VCC H O H[TS-PD][TS] B 9S
ROMCS1 T19 O B 50 VCC H O H[TS-PD][TS] B 9S
ROMRD V20 O B 50 VCC H O H[TS-PD][TS] B 9S
ROMWR U19 O B 50 VCC H O H[TS-PD][TS] B 9S
Notes:
1. Pin states for D31–D16 are lis ted in Table 6 on page 42.
2. RAS3–RAS0, CASH3–CASH0, CASL3–CASL0, and MWE Suspend state of the pins:
–The RAS and CAS sign als remain active if the DRAM interface is configured for CAS -before-RAS refresh in Sus pend mode.
–The RAS and CAS signals will be Low if the DRAM is configured for self-refresh in Suspend mode.
–Will be three-stated with a pulldown resistor if the DRAM interface is programmed to be disabled so the DRAM can be
powered down (Power-Down Group A).
–Will not be affected by this when the RAS and CAS signals that share pins with other functions (RAS3–RAS2, CASH3–
CASH2, and CASL3–CASL2) are not enabled to come out of the chip.
–The MWE signal will be driven out High (deasserted) when the DRAM is programmed to be left powered (Power-Down
Group A).
Summary: These pins have built-in pulldown resistors that are invoked by:
–Suspend mode and DRAM interface programmed for power-down in Suspend (Power-Down Group A), and the pins are
enabled as RAS/CAS for RAS3–RAS2, CASH3–CASH2, and CASL3–CASL2.
3. C, D, and E output drives are programmable.
4. The data bus D15–D0 has built-in pulldown resistors that are invoked when the data bus signals are inputs.
5. Memory Address MA12 Suspend state of the pin:
Will be three-stated with a pulldown resistor. This will work for CAS-before-RAS refresh, self-refresh, and the DRAM powered down.
Summary: This pin has a built-in pulldown resistor that is invoked by Suspend mode.
6. Memory Address MA4–M A0 pins are sha red w ith the p ower -on c onfig uration signal s so th e reset state of the pin s has a pull-
down resist or on these signals.
This default configuration will choose: not test mode and an 8-bit ROM/Flash memory accessed by ROMCS0 with the SD
buffer -cont rol sig nals d isabl ed. The p ulldown resistors are from 50 K to 150 K; they need to be ov erridde n by pullu p resis tors
on the board if other configurations are needed.
These pulldown resistors are disabled after reset; they are not active during normal chip operation.
For conf igurati on signa ls CFG0, CFG1, CF G2, and CFG3, i f the sy stem use s the defaul t conf iguration , the pull down resis tors
will b e activ e a gai n in Suspen d m ode . If ex te rnal pul lup res is tors are used on the board fo r a di ffere nt c on figu r ati on, the p in s
with external pullups will three-state in Suspend mode without pulldown resistors.
The reser ved signa l on MA4 is only u sed for AMD test ing; it shou ld not be pulle d up on the syst em design. T his pin will al ways
go to three-state with a pulldown resistor in Suspend mode.
Summary: Each pin has a built-in pulldown resistor t hat is invok ed by :
–Reset
–Suspend mode and the configuration pin being Low during reset (for CFG3–CFG0).
–Suspend mode for the reserved signal on MA4.
Table 7. Pin State Table—Memory Interface1 (Continued)
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
46 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
7. The CFG2 pin is not supported on the ÉlanSC410 microcontroller.
8. Memory Address MA11–MA4 Suspend state of the pins:
Wi ll be th ree-stated with a pulldo wn resi stor . This will work for CAS-before-RAS refresh, se lf-refresh, and the DRAM p owered
down.
Summary: These pins have built-in pulldown resistors that are invoked by Suspend mode.
9. The ROM control signals have three programmable options for Suspend mode:
–Driven High (inactive)
–Three-stated with no pullup or pulldown. This is useful when the ROM is at 5 V and left powered in Suspend. The board
design should not drive 3.3-V signals into a 5-V device during Suspend, because this can waste power. The system
designer could provide large pullup resistors to 5 V for each of these signals on the board if this configuration is
programmed.
– Three-stated with pulldown resistors when suspended with the intent of powering off the ROMs (Power-Down Group B).
Summary: These pins have built-in pulldown resistors that are invoked by:
–Suspend mode; and the ROM interface is programmed to be powered off in Suspend mode (Power-Down Group B).
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 47
Table 8. Pin State Table—GPIOs/Parallel Port/PC Card Socket B
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
GPIO15
[PCMA_VPP2] Y15 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1,2
GPIO16
[PCMB_VCC]V15 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1, 2
GPIO17
[PCMB_VPP1] W15 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1, 2
GPIO18
[PCMB_VPP2] Y14 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1, 2
GPIO19
[LBL2]V14 B
[O] B50V
CC I-PU I-PPU[O]
OI-PPU[O]
O
1
GPIO20
[CD_A2] G18 B
[I] B50V
CC I-PU I-PPU[O]
I-PPU I-PPU[O]
I-PPUD G1, 2S
GPIO21
[PPDWE]
(PC Card
Enabled)
V3 B
[O] C30V
CC I-PU I-PPU[O]
O
TS-PD
I-PPU[O]
H[TS-PD][TS]
TS-PD
H3S
GPIO22
[PPOEN]
(PC C ard
Enabled)
T3 B
[O] C30V
CC I-PU I-PPU[O]
O
TS-PD
I-PPU[O]
H[TS-PD][TS]
TS-PD
H3S
GPIO23
[SLCT]
[WP_B]
U4 B
[I]
[I]
D150V
CC I-PU I-PPU[O]
I-PU
I-PPU
I-PPU[O]
I-PU[I-PD]
I-PPUD
H2, 3S
GPIO24
[BUSY]
[BVD2_B]
U3 B
[I]
[I]
D150V
CC I-PU I-PPU[O]
I-PU
I-PPU
I-PPU[O]
I-PU[I-PD]
I-PPUD
H2, 3S
GPIO25
[ACK]
[BVD1_B]
U2 B
[I]
[I]
D150V
CC I-PU I-PPU[O]
I-PU
I-PPU
I-PPU[O]
I-PU[I-PD]
I-PPUD
H2, 3S
GPIO26
[PE]
[RDY_B]
W2 B
[I]
[I]
D150V
CC I-PU I-PPU[O]
I-PU
I-PPU
I-PPU[O]
I-PU[I-PD]
I-PPUD
H2, 3S
GPIO27
[ERROR]
[CD_B]
V4 B
[I]
[I]
D150V
CC I-PU I-PPU[O]
I-PU
I-PPU
I-PPU[O]
I-PU[I-PD]
I-PPUD
H2, 3S
GPIO28
[INIT]
[REG_B]
Y2 B
[OD][O]
[O]
D150V
CC OD-PU I-PPU[O]
OD-PU[O]
O
I-PPU[O]
OD-PU[OD-PD]
H[TS-PD][TS]
H2, 3S
GPIO29
[SLCTIN]
[RST_B]
W3 B
[OD][O]
[O]
D150V
CC OD-PU I-PPU[O]
OD-PU[O]
O
I-PPU[O]
OD-PU[OD-PD]
L[TS-PD]
H2, 3S
GPIO30
[AFDT]
[MCEH_B]
W1 B
[OD][O]
[O]
D150V
CC OD-PU I-PPU[O]
OD-PU[O]
O
I-PPU[O]
OD-PU[OD-PD]
H[TS-PD][TS]
H2, 3S
GPIO31
[STRB]
[MCEL_B]
V2 B
[OD][O]
[O]
D150V
CC OD-PU I-PPU[O]
OD-PU[O]
O
I-PPU[O]
OD-PU[OD-PD]
H[TS-PD][TS]
H2, 3S
GPIO_CS13
[PCMA_VCC]V16 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1, 2
GPIO_CS14
[PCMA_VPP1] W16 B
[O] B50V
CC I-PD I-PPD[O]
OI-PPD[O]
O
1, 2
48 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Notes:
1. The shared GPIO20–GPIO15, GPIO_CS14–GPIO_CS13, and PC Card battery signals:
As GPIO_CSxs, the signals are active in Suspend mode: that is, if they are inputs before Suspend, they are still inputs during
Suspend (the GP IO_CSs c an be u sed to wak e up the sy stem); i f they a re outputs before Suspend, they are still outputs during
Suspend (the GPIO _CSs can be programm ed to ch ange state b y mode). As inputs, the pullup or pulldown on the signal can be
disabled; if disabled, it is d isabled i n all modes. When the signal is an output, the built-in resisto rs are automatic ally dis abled.
When enab led, the Latc hed Battery Lo w Detect functi on (LBL2) that is shared on GP IO19 is an outpu t in all mode s; there ar e
no pullup or pulldown resistors active.
On the ÉlanSC400 microcontroller, the PC Card functions shared on these pins are programmable by PC Card socket; the
pin multiplexing options are explained earlier in this document. For the PC Card power control (PCMA_VCC, PCMA_VPP1,
PCMA_VPP2, PCMB_VCC, PCMB_VPP1, PCMB_VPP2), the signals are outputs for each mode.
For the second Card Detect (CD_A2):
–Reset invokes pullup.
–During normal operation, the pullup resistor can be disabled by a register bit.
–During Su sp end mo de , the in put w il l h ave a pul ldo w n i f th e PC C a rd So ck et A in terfa ce is pro gram m ed to b e p owere d o f f
in Susp end m ode (Po wer -Down Group G). I f the sock et is not p rogrammed to b e powere d off in Sus pend mode, the i nput
will have the same state as when operating: the pullup is programmable to be enabled or not.
2. The PC Card signals MCEL_B, MCEH_B, RST_B, REG_B, CD_B,
RDY_B
, BVD1_B, BVD2_B, WP_B, CD_A2,
PCMB_VPP2, PCMB_VPP1, PCMB_VCC, PCMA_VPP1, PCMA_VPP2, and PCMA_VCC are not supported on the
ÉlanSC4 10 mi cro con trol ler .
3. The shared parallel port, PC Card Socket B control, and GPIO signals:
–These signals default to the GPIO interface on reset.
–As a parallel port in Suspend mode, these signals are programmable to accommodate the parallel port powered up or
down.
–As PC Card control on the ÉlanSC400 microcontroller, these signals have the same features as the Socket A control
signals.
–As GPIOs, these signals are not handled specially in Suspend, they remain the same as they were when the chip was
active (i.e., they remain as inputs with the pullup enabled or not, or continue to drive out the same value if they were
outp uts).
Summary: Shared parallel port/PC Card Socket B/GPIO signals: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes pullups
–As parallel port signals:
•Operating: pullups are enabled if not EPP mode. Outputs without pullup or pulldowns if EPP mode.
•Suspend: p ullups a re ena bled, unles s the paral lel port is p rogramm ed to b e pow ered off in Suspend mode , in which
case pulldowns are enabled.
•If EPP mode is enabled for the parallel port, the outputs are driven out at their last value in Suspend mode.
–As PC Card Socket B signals (ÉlanSC400 microcontroller only):
•Operating: outputs have no pullups or pulldowns; inputs have pullups that can be disabled by programming a bit.
•Suspend: outp uts are driv en out ina ctive with no pullu ps or pull down s unles s the PC Card Socke t B is program med
to be powered off in Suspend mode; then the outputs go to three-state with pulldown resistors; inputs will be the
same as they were wh en operating , with a pul lup resist or that can be d isabled by programming , unless the PC Card
Socket B is pro grammed to be power ed off in Suspen d mode (Power -Down Group H), in whic h case the inputs have
pulldown resistors enabled.
–As GPIO signals:
•Operating or Suspend: as outputs they have no pullups or pulldowns; as inputs they have pullups that can be dis-
abled by programming a bit; no change of state when the system goes to Suspend.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 49
Table 9. Pin State Table—GPIOs/ISA Bus
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
GPIO_CS5
[IOCS16]W19 B
[I] B50V
CC I-PU I-PPU[O]
I-PU I-PPU[O]
I-PU[I-PD] C
1S
GPIO_CS6
[IOCHRDY] V18 B
[STI] B50V
CC I-PU I-PPU[O]
I-PU I-PPU[O]
I-PU[I-PD] C
1S
GPIO_CS7
[PIRQ1] Y19 B
[I] B50V
CC I-PU I-PPU[O]
I-PU I-PPU[O]
I-PU[I-PD] C
1S
GPIO_CS8
[PIRQ0] W18 B
[I] B50V
CC I-PU I-PPU[O]
I-PU I-PPU[O]
I-PU[I-PD] C
1S
GPIO_CS9
[TC] Y18 B
[O] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
TS-PD
1S
GPIO_CS10
[AEN] V17 B
[O] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
TS-PD
1S
GPIO_CS11
[PDACK0]W17 B
[O] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
H[TS-PD][TS] C
1S
GPIO_CS12
[PDRQ0] Y17 B
[I] B50V
CC I-PD I-PPD[O]
I-PD I-PPD[O]
I-PD
1S
50 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Notes:
1. The shared GPIO_CS12–GPIO_CS5 and ISA signals:
As GPIO _C S s ign als , t hey are ac tiv e in Susp end mode: that is, i f they are inputs be fore Sus pend, they are still in puts during
Suspend (they can be used t o wake u p the syste m); if they are output s befor e Suspend, they are s till outpu ts during Suspend
(they can be programmed to change state by mode). As inputs, the pullup or pulldown on the signal can be disabled; if
disabled, it is disabled in all modes. When the signal is an output, the built-in resistors are automatically disabled.
The ISA functi on for each pin is programma ble by funct ional group : that is, the sys tem can ch oose to use PIRQ 0 and still use
the DMA p ins a s G PIO _CSx s (the pi n m ul tip lex in g o pti ons a re e xp lai ned el se w here in th is doc um en t). As IS A signals , th es e
pins a re programm able to sup port a sy stem with ISA periphe rals powere d up or d own in Susp end mode (Power- Down Grou p
C). For those signals that are High when deasserted, there is an option to three-state them with no built-in resistors, so an
external resistor can be placed on the board to pull them up to 5 V.
Summary: GPIO_CS12: Built-in pulldown resistor that is invoked by:
–Reset
–ISA signal enabled on this pin (the pin will be PDRQ0).
–The pulldown is disabled by this pin being a GPIO_CS and an output.
–The pulldown can be programmed to be disabled when the pin is a GPIO_CS input.
Summary: GPIO_CS11: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullup.
–When enabled as the ISA signal PDACK0:
•In normal operation, this signal is an output and no pullup or pulldown is needed.
•The pulldown is invoked by Suspend mode and the ISA bus is programmed to be powered off in Suspend (Power-
Down Group C).
•If the ISA bus is programmed for 5-V us e and is not powered down in Suspe nd, then this sig nal is three-st ate without
a built-in pullup or pulldown resistor.
–When enabled as the GPIO_CS11 signal:
•As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSx signals can be active in
Suspend.
• As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all
modes, including Suspend.
Summary: GPIO_CS10–GPIO_CS9: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullups.
–When enabled as the ISA signals AEN and TC:
•In normal operation, these signals are outputs and no pullup or pulldown is needed.
•The pulldown s are inv ok ed by Sus pen d mod e.
–When enabled as the GPIO_CS10–GPIO_CS9 signals:
•As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CS signals can be active in Suspend.
• As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all
modes, including Suspend.
Summary: GPIO_CS8–GPIO_CS5: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullups.
–When enabled as PIRQ1–PIRQ0, IOCHRDY, and IOCS16:
•In normal operation and Suspend, these signals are inputs and the pullup resistors are active.
•The pulldowns are invoked by Suspend mode and the ISA bus interface programmed for power off in Suspend
(Power-Down Group C).
–When enabled as the GPIO_CS8–GPIO_CS5 signals:
•As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSx signals can be active in
Suspend.
• As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all
modes, including Suspend.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 51
Table 10. Pin State Table—GPIOs/System Data (SD) Buffer Control
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
GPIO_CS2
[[DBUFRDL]] C18 B
[[O]] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
TS-PD
1
GPIO_CS3
[[DBUFRDH]] D17 B
[[O]] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
TS-PD
1
GPIO_CS4
[[DBUFOE]] C4 B
[[O]] C50V
CC I-PU I-PPU[O]
OI-PPU[O]
H[TS-PD][TS] I1S
KBD_ROW13
[[R32BFOE]] A3 STI-OD
[O] C250V
CC I-PU IOD-PU
OI-PU
H[TS-PD][TS] I2S
Notes:
1. The data buffer control signals are shared with the GPIO_CS4–GPIO_CS2 signals and with the keyboard row signal:
When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state
without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer.
Summary: GPIO_CS4– GPIO_CS2/DBUFOE/DBUFRDH/DBUFRDL: Built-in pullup and pulldow n resistors that are invoked by:
–Reset invokes pullup.
–When buffer control is invoked by the configuration pin, these pins are outputs without any pullups or pulldowns.
–When buffer control is enabled and in Suspend mode, DBUFRDH and DBUFRDL are three-state with the pulldowns
enabled; DBUFOE has three options:
•High (inactive) with no pullup or pulldown.
•Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode (Power-Down Group I).
•Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V.
–When enabled as the GPIO_CS4–GPIO_CS2 signals:
•As an output, the p ullup and pulldown are disabled in all modes, and these GPIO_CS signals can be active in Suspend.
• As an input, the pullup can be programmed to be enabled or disabled. This will then be the state of the pin in all
modes, including Suspend.
2. This data buffer control signal (R32BFOE) is shared with the keyboard row signal:
When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state
without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer.
Summary: KBD_ROW13/R32BFOE: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullup.
–As R32BFOE , this pin is an output without a pullup or pulldown.
–When buffer control is enabled and in Suspend mode, R32BFOE has three options:
•High (inactive) with no pullup or pulldown.
•Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode.
•Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V.
–When enabled as the keyboard row signal, this signal has a pullup enabled at all times.
52 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 11. Pin State Table—GPIOs
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
GPIO_CS0 V19 B B 50 VCC I-PU I-PPU[O] I-PPU[O] E 1S
GPIO_CS1 Y20 B B 50 VCC I-PU I-PPU[O] I-PPU[O] E 1S
Notes:
1. The GPIO_CS signals become inputs in Suspend mode with either a pullup resistor for devices that are left powered, or a
pulldown resistor fo r devices that are to be powered off .
Summary: GPIO_CS1–GPIO_CS0: Built-in pullup and pulldown resistors that are invoked by:
Reset invokes pullup.
When enabl ed as the GPI O_ CS1–G PIO _CS 0 sign als :
As an output, the pullup and pulldown are disabled in all modes, and these GPIO_CSxs can be active in Suspend.
As an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all mo des,
including Suspend.
Table 12. Pi n State Table—Serial Port
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
CTS V10 I VCC I-PU I-PU [I-PD] I-PU[I-PD] D 1
Notes:
1. The serial port output signals are three-state with built-in pulldown resistors in Suspend mode. The serial port input signals
can be left as inputs with pullups for a Suspend when the serial device is left powered. Or, they can be configured as inputs
with pulldown resistors if the serial device is to be powered off (Power-Down Group D).
Summary: The serial port output pins have built-in pulldown resistors that are invoked by Suspend mode.
Summary: The serial port input pins have built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullup resistors.
–Operating: the pullup resistors are enabled.
–Suspend m ode inv okes the pul ldown re sisto rs i f the se rial int erface is prog ramme d to be p owere d off in S uspend ( Powe r-
Down Group C); otherwise there are pullup resistors in Suspend mode.
DCD V9 I VCC I-PU I-PU [I-PD] I-PU[I-PD] D 1
DSR W10 I VCC I-PU I-PU [I-PD] I-PU[I-PD] D 1
DTR Y8 O A 30 VCC H O [TS-PD] TS-PD 1
RIN V11 I VCC I-PU I-PU [I-PD] I-PU[I-PD] D 1
RTS W8 O A 30 VCC H O [TS-PD] TS-PD 1
SIN W11 I VCC I-PU I-PU [I-PD] I-PU[I-PD] D 1
SOUT Y10 O A 30 VCC H O [TS-PD] TS-PD 1
Table 13. Pin State Table—Inf rared Interface
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
SIRIN Y9 I VCC I-PD I-PPD I-PPD 1
Notes:
1. The seria l infrared interface output and input settle to Suspend states that allow the device to be powered up or off. The o utput
is three-s tate with a built-in p ulldown resistor, and t he input ha s a built-in pulldown res istor . T he pulldown resistor on the input
pin (SIRIN) can be programmed to be disabled during normal operation and Suspend mode.
Summary: The serial infrared input pin has a built-in pulldown resistor that is invoked by:
–Reset invokes the pulldown resistor.
–The pulldown resistor is then programmable to be there or not.
SIROUT V8 O A 30 VCC L O TS-PD 1
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 53
Table 14. Pin State Table—Keyboard Interface
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
KBD_COL0
[XT_DATA] E2 OD-STI
[B] D250V
CC OD-
PU IOD-PPUD
IOD-PPUD IOD-PPUD
IOD-PPUD
1S
KBD_COL1
[XT_CLK] D1 OD-STI
[B] D250V
CC OD-
PU IOD-PPUD
IOD-PPUD IOD-PPUD
IOD-PPUD
1S
KBD_COL2/
PIRQ3 A2 OD-STI
[I] D250V
CC OD-
PU IOD-PPUD
I-PPUD IOD-PPUD
I-PPUD[I-PD] C
1S
KBD_COL3/
PIRQ4 B3 OD-STI
[I] D250V
CC OD-
PU IOD-PPUD
I-PPUD IOD-PPUD
I-PPUD[I-PD] C
1S
KBD_COL4/
PIRQ5 C3 OD-STI
[I] D250V
CC OD-
PU IOD-PPUD
I-PPUD IOD-PPUD
I-PPUD[I-PD] C
1S
KBD_COL5/
PIRQ6 A1 OD-STI
[I] D250V
CC OD-
PU IOD-PPUD
I-PPUD IOD-PPUD
I-PPUD[I-PD] C
1S
KBD_COL6/
PIRQ7 B2 OD-STI
[I] D250V
CC OD-
PU IOD-PPUD
I-PPUD IOD-PPUD
I-PPUD[I-PD] C
1S
KBD_COL7 C5 OD-STI D 250 VCC OD-
PU IOD-PPUD IOD-PPUD 1
KBD_ROW0
[CASL2]B19 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW1
[CASL3]D16 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW2
[CASH2]C17 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW3
[CASH3]B18 STI-OD
[O] D250V
CC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW4
[RAS2]D15 STI-OD
[O] P-C,E 250 VCC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW5
[RAS3]C16 STI-OD
[O] P-C,E 250 VCC I-PU IOD-PU
OI-PU
O[L][TS-PD] A
2
KBD_ROW6
[MA12] B17 STI-OD
[O] P-C,E 250 VCC I-PU IOD-PU
OI-PU
TS-PD
3
KBD_ROW7
[PDACK1]D3 STI-OD
[O] C250V
CC I-PU IOD-PU
OI-PU
H[TS-PD][TS] C S
KBD_ROW8
[PDRQ1] C2 STI-OD
[I] C250V
CC I-PU IOD-PU
I-PD I-PU
I-PD S
KBD_ROW9
[PIRQ2] E3 STI-OD
[I] C250V
CC I-PU IOD-PU
I-PU I-PU
I-PU[I-PD] C S
KBD_ROW10
[BALE] D2 STI-OD
[O] C250V
CC I-PU IOD-PU
OI-PU
TS-PD S
KBD_ROW11
[SBHE]C1 STI-OD
[O] C250V
CC I-PU IOD-PU
OI-PU
H[TS-PD][TS] C S
KBD_ROW12
[MCS16]F3 STI-OD
[I] C250V
CC I-PU IOD-PU
I-PU I-PU
I-PU[I-PD] C S
KBD_ROW13
[[R32BFOE]] A3 STI-OD
[O] C250V
CC I-PU IOD-PU
OI-PU
H[TS-PD][TS] I4S
54 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Notes:
1. The keyboard column signals are shared with the programmable IRQs and XT keyboard signals.
As keyboard column signals and XT keyboard signals, they are inputs and open drain outputs with pullup or pulldown
resisto rs in no rmal opera tion and Su spend mo de. Each c olumn si gnal is i ndividua lly progra mmable fo r the pullu p or pulldo wn
in the keyboard extended registers.
As IRQs, the pins are inputs with built-in pullup or pulldown resistors (use the same registers in the keyboard controller to
enable pullups or pulldowns). During Suspend mode, they stay as inputs with the pullup or pulldown. Or, if Power-Down
Group C is enabled for the ISA bus to be powered down in Suspend mode and a bit is set identifying that these signals are
being used as IRQs, they will have pulldown resistors activated. There is no programmable bit to make these signals IRQs
beyond the extended register in the interrupt controller that maps the pin to a particular IRQ. If the system must use any of
these as IRQs, a bit must be set, notifying the chip, so that they can have the pulldown resistors invoked in Suspend mode.
Summary: As keyboard column and XT keyboard signals:
–Pullup or pulldown resistor depending on the setting of the Keyboard Column Pullup/Pulldown register in the keyboard
controller.
Summary: As programmable IRQ signals:
–Pullup or pulldown resistors during normal operation and Suspend (depending on the configuration register in the
keyboard contr oller.
–Pulldown resistors during suspend if Power-Down Group C (the ISA bus) is enabled for power-down in Suspend, and a
bit is set indicating that these signals are used as IRQs and need to be pulled down in Suspend.
2. RAS3–RAS2, CASH3–CASH2, and CASL3–CASL2 Suspend state of the pins:
–The RAS and CAS signals remain active if the DRAM interface is configured for CAS-before-RAS refresh in Suspend
mode.
–The RAS and CAS signals will be Low if the DRAM is configured for self-refresh in Suspend mode.
–Will be three-stated with a pulldown resistor if the DRAM interface is programmed to be disabled so the DRAM can be
powered down (Power-Down Group A).
–Will not be affected by this when the RAS and CAS signals that share pins with other functions are not enabled to come
out of the chip.
Summary: These pins have built-in pulldown resistors that are invoked by:
–Suspend mode and DRAM interface programmed for power-down in Suspend (Power-Down Group A), and the pins are
enabled as RAS/CAS for RAS3–RAS2, CASH3–CASH2, and CASL3–CASL2.
3. Memory Address MA12 Suspend state of the pin:
Wi ll be th ree-stated with a pulldo wn resi stor . This will work for CAS-before-RAS refresh, se lf-refresh, and the DRAM p owered
down.
Summary: This pin has a built-in pulldown resistor that is invoked by Suspend mode.
4. The data buffer control signal R32BFOE that is shared with the keyboard row signal:
When the data buffer control signals are enabled on the pins, they will drive inactive during Suspend mode, go three-state
without resistors to allow an external resistor to 5 V, or three-state with a pulldown to support powering off the data buffer.
Summary: KBD_ROW13/R32BFOE: Built-in pullup and pulldown resistors that are invoked by:
–Reset invokes the pullup.
–As R32BFOE , this pin is an output without a pullup or pulldown.
–When buffer control is enabled and in Suspend mode, R32BFOE has three options:
•High (inactive) with no pullup or pulldown.
•Three-state with a pulldown if it is programmed for the buffer to be powered off in Suspend mode.
•Three-state with no pulldown if it is programmed for the buffer to be powered on in Suspend mode and at 5 V.
–When enabled as the keyboard row signal, this signal has a pullup enabled at all times.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 55
Table 15. Pin State Table—PC Card Socket A
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
BVD1_A V1 I VCC I-PU I-PPU I-PPUD G 1,2
Notes:
1. On the ÉlanSC400 microcontroller only, the PC Card control signals for Socket A:
The pul lup resi stors for th e input si gnals are built in and can be disabled if external pullups a re necessa ry (the exte rnal pullups
can be on a different power plane).
In Suspend mode, the signals can be configured for: a card not plugged in (inputs terminated with internal resistors), a card
plugged in and powered (the output signals drive out inactive), a card plugged in and powered and at 5 V (the inactive High
output si gna ls are three - st ated and pullup res is tors sho uld be put on the board), an d a card plugge d in and power ed off (the
signals terminated with pulldown resistors) (Power-Down Group G).
Summary: The outputs are built-in pulldown resistors that are invoked by:
–Suspend and PC Card Socket A is programmed to be powered off in Suspend (Power-Down Group G).
–These are not pulldowns for normal operation. These are driven outputs.
Summary: The inputs are built-in pullup and pulldown resistors that are invoked by:
–Reset invokes pullups.
–During normal operation, the pullup resistors can be disabled by a register bit.
–During Suspend mode, the inputs will have pulldowns if the PC Card Socket A interface is programmed to be powered off
in Susp end mode (Powe r-Down G roup G). If th e socket is not programmed to be powe red off in Sus pend mode, the inputs
have the same state as when operating: the pullups are programmable to be enabled or not.
2. The PC Card signals MCEL_A, MCEH_A, RST_A, REG_A, CD_A,
RDY_A
, BVD1_A, BVD2_A, WP_A, WAIT_AB, OE, WE ,
and ICDIR are not supported on the ÉlanSC410 microcontroller.
S
BVD2_A R3 I VCC I-PU I-PPU I-PPUD G 1, 2 S
CD_A R2 I VCC I-PU I-PPU I-PPUD G 1, 2 S
ICDIR M3 O B 50 VCC L O H[TS-PD][TS] G 1, 2 S
MCEH_A
[[BNDSCN_TMS]] N3 O
[[I]] B50V
CC HO
[I-PD] H[TS-PD][TS] G 1, 2 S
MCEL_A
[[BDNSCN_TCK]] P2 O
[[I]] B50V
CC HO
[I-PD] H[TS-PD][TS] G 1, 2 S
OE P1 O B 50 VCC H O H[TS-PD][TS] G 1, 2 S
RDY_A P3 I VCC I-PU I-PPU I-PPUD G 1, 2 S
REG_A
[[BNDSCN_TDO]] M2 O
[[O]] B50V
CC HO
[O] H[TS-PD][TS] G 1, 2 S
RST_A
[[BNDSCN_TDI]] R1 O
[[I]] B50V
CC OO
[I-PD] L[TS-PD] G 1, 2 S
WAIT_AB U1 I VCC I-PU I-PPU I-PPUD G 1, 2 S
WE N2 O B 50 VCC H O H[TS-PD][TS] G 1, 2 S
WP_A T2 I VCC I-PU I-PPU I-PPUD G 1, 2 S
56 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 16. Pin St ate Table—Graphics Controller/VESA Local Bus Control
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
FRM
[VL_LCLK] E19 O
[O] E150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
TS-PD F
1,2 S
LC
[VL_BE1]E20 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD0
[VL_RST]B20 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD1
[VL_ADS]C19 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD2
[VL_W/R]D18 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD3
[VL_M/IO]C20 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD4
[VL_LRDY]D19 O
[I] D150V
CC TS-PD TS-PD[O]
ITS-PD
I[I-PD] F
1,2 S
LCDD5
[VL_D/C]E18 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LCDD6
[VL_LDEV]F17 O
[I] D150V
CC TS-PD TS-PD[O]
ITS-PD
I[I-PD] F
1,2 S
LCDD7
[VL_BE3]D20 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
LVDD
[VL_BLAST]A19 O
[O] D50V
CC TS-PU O[TS-PU]
O[TS-PU] H
H[TS-PD] F
1,2
LVEE
[VL_BRDY]A20 O
[I] D50V
CC TS-PU O[TS-PU]
IH
I[I-PD] F
1,2
M
[VL_BE2]F18 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
SCK
[VL_BE0]F19 O
[O] D150V
CC TS-PD O[TS-PD]
O[TS-PD] TS-PD
H[TS-PD] F
1,2 S
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 57
Notes:
1. The shared graphics controller interface and VESA local bus pins:
These si gnals defa ul t to three-state with pulldown res ist ors and re ma in this way until an LC D or VL -bus interface i s s ele cte d
(all except LVEE and LVDD).
When the graphics controller is enabled on the ÉlanSC400 microcontroller, the signals will be three-state with pulldowns
whenever the LCD is not enabled. This allows the LCD to be powered off in any mode, and prevents damage to the LCD by
having it powered when the timing of the signals is not correct. In Suspend these signals are three-state with pulldowns. The
LCD cannot be driven in Suspend.
When the VESA loca l bus interface i s ena bled, t he sig nals will becom e the i nputs and output s nec essary fo r VL-bus suppo rt.
In Suspend, the signals support leaving the VL device powered on or off (Power-Down Group F).
Summary: LCD control si gna ls /VESA lo cal b us control si gn als (al l e xcept LVEE and LVDD ) ha ve bu ilt-in pull down res ist ors
that are invoked by:
–Reset invokes pulldowns.
–Graphics controller disabled and VL-bus disabled invokes pulldowns.
–VL-bus enabled and VL interface programmed for power-down in Suspend mode invokes pulldowns (Power-Down Group F).
–Graphics controller enabled and LCD enabled. All pins are outputs with no termination.
–Graphics controller enabled and LCD disabled. All pins are three-state with pulldowns.
–VL-bus enabled and not Suspend mode. No pulldowns enabled.
Summary: LVEE and LVDD have built-in pullup and pulldown resistors that are invoked by:
–Reset invokes pullups.
–VL-bus enabled and VL interface programmed for power-down in Suspend mode invokes pulldowns in Suspend mode
(Power-Down Group F).
–Graphics enabled. Drive out High in Suspend.
–Graphics enabled. Both pins are outputs without pullups or pulldowns.
–VL-bus enabled. No pullups or pulldowns in normal operation.
2. The graphics controller signals LCDD7 –LCDD0, M, LC, SCK, FRM, LVEE, and LVDD are not supported on the ÉlanSC410
microcontroller.
58 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 17. Pin State Table—Miscellaneous
Signal Name
[Alternate
Function]
Pin
#Type Output
Drive
Max
Load
(pF) Supply Reset
State Normal
Operation Suspend
State
Power
Down
Group Note 5 V
32KXTAL1 Y6 VRTC 1
32KXTAL2 Y4 VRTC 1
ACIN W12 STI VCC I-PD I-PD I-PD
BBATSEN V6 A VRTC I I I 1
BL1 Y13 STI VCC II I
BL2 W13 STI VCC II I
BLO
[CLK_IO] W14 STI[B] B 50 VCC II
I[O] I
I[TS-PD]
BNDSCN_EN Y11 I VCC I-PD I-PD I-PD
LF_HS V5 A AVCC Analog Analog Analog
LF_INT Y3 A AVCC Analog Analog Analog
LF_LS W4 A AVCC Analog Analog Analog
LF_VID W5 A AVCC Analog Analog Analog 2
RESET Y7 STI VCC II I 1
SPKR V7 O B 50 VCC L O TS-PD
SUS_RES/
KBD_ROW14 Y12 STI/STI VCC II I
Notes:
1. The 32-kHz crystal signals are active in all modes.
The RESET signal is enabled as an input in all modes to reset the w hole chip.
The BBATSEN signal is active during reset to sense the state of the backup battery.
Summary: No pullups or pulldowns on these pins.
2. The LF_VID signal is not supported on the ÉlanSC410 microcontroller.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 59
Table 18. Pin State Table—Power1 and Ground
Signal Name (Alternate Function) Pin # Type
GND D4 —
GND D5 —
GND D6 —
GND D7 —
GND D8 —
GND D9 —
GND D10 —
GND D12 —
GND D11 —
GND E4 —
GND F4 —
GND G4 —
GND H4 —
GND H8 Thermal
GND H9 Thermal
GND H10 Thermal
GND H11 Thermal
GND H12 Thermal
GND H13 Thermal
GND J4 —
GND J8 Thermal
GND J9 Thermal
GND J10 Thermal
GND J11 Thermal
GND J12 Thermal
GND J13 Thermal
GND K8 Thermal
GND K9 Thermal
GND K10 Thermal
GND K11 Thermal
GND K12 Thermal
GND K13 Thermal
GND L8 Thermal
GND L9 Thermal
GND L10 Thermal
GND L11 Thermal
GND L12 Thermal
GND L13 Thermal
GND M8 Thermal
GND M9 Thermal
GND M10 Thermal
GND M11 Thermal
GND M12 Thermal
60 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
GND M13 Thermal
GND N8 Thermal
GND N9 Thermal
GND N10 Thermal
GND N11 Thermal
GND N12 Thermal
GND N13 Thermal
GND R17 —
GND T17 —
GND U5 —
GND U6 —
GND U7 —
GND U8 —
GND U9 —
GND U10 —
GND U11 —
GND U12 —
GND U13 —
GND U14 —
GND U15 —
GND U16 —
GND U17 —
GND_A Y5 Analog
VCC A8 I/O
VCC A13 I/O
VCC A18 I/O
VCC B1 I/O
VCC B4 I/O
VCC B16 I/O
VCC E1 I/O
VCC E17 I/O
VCC G17 I/O
VCC H1 I/O
VCC J17 I/O
VCC J3 I/O
VCC L17 Logic
VCC M1 I/O
VCC M17 Logic
VCC M19 I/O
VCC N17 Logic
VCC P17 Logic
VCC P18 I/O
VCC T1 I/O
VCC U18 I/O
Table 18. Pin State Table—Powe r 1 and Ground (Continued)
Signal Name (Alternate Function) Pin # Type
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 61
VCC V13 I/O
VCC_RTC W7 RTC
VCC W9 I/O
VCC Y1 I/O
VCC Y16 I/O
VCC_A W6 Analog
VCC_CPU K4 CPU
VCC_CPU L4 CPU
VCC_CPU M4 CPU
VCC_CPU N4 CPU
VCC_CPU P4 CPU
VCC_CPU R4 CPU
VCC_CPU T4 CPU
Notes:
1. See the signal descriptions under the Reset and Power subheading
in the Signal Description table beginning on page 62 for additional
information about the V
CC
pins.
Table 18. Pin State Table—Powe r 1 and Ground (Continued)
Signal Name (Alternate Function) Pin # Type
62 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
SIGNAL DESCRIPTIONS
The descriptions in Table 19 are organized in
alphabetical order within the functional group listed here.
■System Interface on page 62
■Configuration Pins on page 63
■Memory Interface on page 64
■VL-Bus Interface on page 64
■Power Management on page 65
■Clocks on page 66
■Parall el Por t on page 66
■Serial Port on page 66
■Keyboard Interfaces on page 67
■General-Purpose Input/Output on page 67
■Serial Infrared Port on page 67
■PC Card Controller (ÉlanSC400 Microcontroller
Only) on page 67
■LCD Graphics Controller (ÉlanSC400 Microcontrol-
ler Only) on page 68
■Boundary Scan Test Interface on page 69
■Reset and Power on page 69
Table 19. Signal Description Table
Signal Type Description
System Interface
AEN O DMA Address Enable indicates that the current address active on the SA25–SA0 address
bus is a memory address, and that the current cycle is a DMA cycle. All I/O devices should
use this signal in decoding their I/O addresses, and should not respond when this signal is
asserted. When AEN is asserted, the PDACK1– PDACK0 signals are use d to sele ct the
appropriate I/O device for the DMA transfer. AEN is also asserted when a DMA cycle is
occurring internal to the chip.
On the ÉlanSC4 00 microco ntroller, AEN is a lso asserted fo r all acces ses to the PC Card I/O
space to prevent ISA devices from responding to the IOR/IOW signal assertions because
these signals are shared between the PC Card and ISA interfaces.
BALE O Bus Address Latch Enable is driven at the beginning of an ISA bus cycle with a valid
address. This signal can be used by external devices to latch the address for the current
cycle. BALE is also asserted for all accesses to the PC Card interfaces (memory or I/O)
(ÉlanSC400 microcontroller only) and all DMA cycles. This prevents an ISA device from
responding to a cycle based on a previously latched address.
DBUFOE OData Buffer Outp ut Enable co ntrols th e output en able on the extern al transcei ver requi red
to drive the peripheral data bus in local bus and 32-bit DRAM modes.
DBUFRDH OHigh Byte Data Buffer Direction Control controls direction of data flow through the external
transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This
is the control signal for the upper 8 bits of the data bus.
DBUFRDL OLow Byte Data Buffer Direction Control controls direction of data flow through the external
transceiver required to drive the peripheral data bus in local bus and 32-bit DRAM mode. This
is the control signal for the lower 8 bits of the data bus.
IOCHRDY STI
PU I/O Channel Ready should be driven by open-drain devices. When pu lled Low during an ISA
access, wait state s are inserted in the current cy cle. This pin has an internal weak pullup that
should be supplemented by a stronge r external pullu p (usually 4.7 KΩ to 1 KΩ) for faster rise
time.
IOCS16 II/O Chip Select 16: The targeted I/O device drives this signal active early in the cycle to
request a 16-bit transfer.
IOR OI/O Read Command indicates that the curre nt cycle is a read from the current ly addressed
I/O devi ce. When this signal is as serted, the se lected I/O de vice can dri ve data onto th e data
bus. Thi s signal is al so shared wi th the PC Card i nterface on the Élan SC400 microco ntroller.
IOW OI/O Write Command indicates that the current cycle is a write to the currently addressed
I/O devi ce. When this signal is as serted, the se lected I/O de vice can la tch data from th e data
bus. This signal i s also share d with the PC Card interface o n the ÉlanSC40 0 microc ontroller.
MCS16 IMemory Chip Select 16 indicates to the ISA control logic that the targeted memory device
is a 16-bit-wide device.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 63
MEMR OMemory Read Command indicates that the current cycle is a read of the currently
address ed memory device. W hen this sign al is asserted, the m emory device c an drive data
onto the data bus.
MEMW OMemory Write Command indicates that the current cycle is a write of the currently
address ed mem ory dev ice . When thi s sig nal is a ss erte d, the me mory dev ic e c an latch dat a
from the data bus.
PDACK1–PDACK0 OProgrammable DMA Acknowledge signals can each be mapped to one of the seven
available DMA channels. They are driven active (Low) back to the DMA initiator to
acknowledge the corresponding DMA requests.
PDRQ1–PDRQ0 I Programmable DMA Requests can each be mapped to one of the seven available DMA
channels. They ar e asserted active (High) by a DMA initiator to request DMA ser v ic e from
the DMA controller.
PIRQ7–PIRQ0 I Programmable Interrupt Requests can each be mapped to one of the available 8259
interrupt channels. They are asserted when a peripheral requires interrupt service.
(Rising Edge/Active High Trigger)
RSTDRV O System Reset is the ISA bus reset signal. When this signal is asserted, all connected
devices reinitialize to their reset state. This signal should not be confused with the internal
CPU RESET and SRESET signals.
SA25–SA0 O System Address Bus outputs the ph ysical memory or I/O port la tched ad dresses . It is used
by all extern al peripheral dev ices other than mai n system DRAM. In additi on, this is the local
address bus in local bus mode.
SBHE OSystem Byte High Enable is driven active when the high data byte is to be transferred on
the upper 8 bits of the ISA data bus.
SD15–SD0 B System Data Bus is shared between ISA, 8- or 16-bit ROM/Flash memory, and PC Card
peripherals (on the ÉlanSC400 microcontroller only) and can be directly connected to all of
these device s. In additi on, these si gn als are the upper w o rd o f th e l oc al data bus, th e 3 2-bit
DRAM i nterface, a nd the 32-bi t ROM interfa ce. In thes e modes, t he system da ta bus can be
generated via an external buf fer conn ected to the SD bus and controlled by the bu ffer c ontrol
signals provided.
SPKR O Speaker, Digital Audio O utput controls an external spe aker driver. It is generate d from the
internal 8254-compatible timer Channel 2 output ANDed with I/O Port 0061h[1] (Speaker
Data Enable); on the ÉlanSC400 microcontroller, the PC Card speaker signals are
exclusively ORed with each other and the speaker control function of the timer to generate
the SPKR signal.
TC O Terminal Count is driven from the DMA controller pa ir to indicate that the trans fer count for
the currently active DMA channel has reached zero, and that the current DMA cycle is the
last tran sfe r.
Configuration Pins
BNDSCN_EN I Boundary Scan Enable enables the boundary scan pin functions . When this pin is High , the
boundary scan interface is enabled. When this pin is Low, the boundary scan pin functions
are disab led and the pi ns are conf igured to their d efault functi ons. This pin must be held Low
during reset for normal operation.
CFG1–CFG0 I Configuration Pins 1–0 select the data bus width for the physical device(s) selected by the
ROMCS0 pin (i.e., 8-, 16-, or 32-bit-wide). These pins are sampled at the deassertion of RESET.
CFG2 I Configuration Pin 2 selects whether or not the system will boot from PC Card Socket A
memory card or from the device attached to ROMCS0. This pin is sampled at the deassertion
of RESET. This pin is not supported on the ÉlanSC410 microcontroller.
CFG3 I Configuration Pin 3 enables the SD buffer control signals, DBUFOE, DBUFRDH, and
DBUFRDL. This pin is sampled at the deass erti on of RESET.
Table 19. Signal Description Table (Continued)
Signal Type Description
64 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Memory Interface
CASH3–CASH0 OColumn Addres s Strobe High indicates to the DRAM devices that a valid column address
is asserted on the MA lines.
These CAS s ignals are for the odd bank s (Banks 1 and 3); CASH3–CASH2 are for the high
word; and CASH1–CASH0 is for the low word.
CASL3–CASL0 OColumn Address Strobe Low indicates to the DRAM devices that a valid column address
is asserted on the MA lines.
These CAS signals are for the even banks (Banks 0 and 2); CASL1–CASL0 are for the lo w
word; CASL3–CASL2 are for the high word.
D31–D0 B Data Bus is used for DR AM an d local bu s c yc le s. T his bu s is also us ed w h en i nte rfac ing to
32-bit ROMs.
MA12–MA0 O Memory Address: The DRAM row and column addresses are multiplexed onto this bus.
Row addres ses are drive n onto this bus and are valid upo n the falling ed ge of RAS. Colu mn
addresses are driven onto this bus and are valid upon the falling edge of CAS.
MWE OWrite Enable indicates an active write cycle to the DRAM devices. This signal is also used
to three-state EDO DRAMs at the end of EDO read cycles.
R32BFOE OROM 32-Bit Buffer Output Enable provides the buffer enable signal for the external
transceivers on the low word of the ROM interface. This signal is automatically provided
when the ROMCS0 interface is configured as 32 bit (the configuration can be done using
either CFG1–CFG0 or CSC index 20h[1–0]). Once ROMCS0 is configured as 32 bit, all
accesses to 32-bit ROM devices on ROMCS2–ROMCS0 result in the assertion of the
R32BFOE signal.
RAS3–RAS0 ORow Address Strobe indicates to th e DRAM devi c es that a v alid row address is asserted
on the MA lines.
ROMCS2–ROMCS0 OROM Chip Selects are active Low outputs that provide the chip select for the BIOS ROM
and/or the ROM/Fl ash memory a rray. After p ower-on re set, the ROMCS0 chip select will go
active for accesses into the 64-Kbyte segment that contains the boot vector, at address
3FF0000h to 3FFFFFFh. ROMCS0 can be driven active during a linear (direct) address
decode of certain add resses in the hi gh memory (00 A0000h–00F FFFFh) region . By default,
direct-mapped accesses to the 64-Kbyte region from 00FFFF0h to 00FFFFFh are enabled
to suppo rt Legacy PC /AT BIOS. This area is known as the a liased b oot vecto r . It can als o be
activated by accessing a Memory Management System (MMS) page that points to the ROM0
address space. ROMC S1 is activa ted only whe n access ing an MM S page that po ints to it. A
third, MMS-mappable ROMCS2 signal is available by reconfiguring one of the chip’s General
Purpose Input Output (GPIO) pins for this function and also requires the use of MMS to
access devices connected to it.
ROMRD OROM Read indicates that the current cycle is a read of the currently selected ROM device.
When this signal is asserted, the selected ROM device can drive data onto the data bus.
ROMWR OROM Write indicates that the current cycle is a write of the currently selected ROM device.
When this signal is asserted, the selected ROM device can latch data from the data bus.
VL-Bus Interface
VL_ADS OLocal Bus Address Strobe is asserted to indicate the start of a VL-bus cycle. It is always
strobed Low for one clock period. The address and status lines are valid on the rising edge
of VL_LCLK, which samples this signal Low.
VL_BE3–VL_BE0 OLocal Bus Byte Enables indicate which byte lanes of the 32-bit data bus are involved with
the current VL-bus transfer.
VL_BLAST OLocal Bus Burst Last is asserted to indicate that the next VL_BRDY assertion will terminate
the current VL-bus transfer.
Table 19. Signal Description Table (Continued)
Signal Type Description
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 65
VL_BRDY ILocal Bus Burst Ready is asserted by the VL-bus target to indicate that it is terminating the
current burst transfer. The chip samples this signal on the rising edge of VL_LCLK.
VL_BRDY should be asserted for one VL_LCLK period per burst transfer. If VL_LRDY is
asserted at the same time as VL_BRDY, VL_BRDY is ignored and the VL-bus transfer is
terminated.
VL_D/C
VL_M/IO
VL_W/R
O
O
O
Local Bus Data/Code Status is driven Low to indicate that code is being transferred. A Hi gh
on this signal indicates that data is being transferred.
Local Bus Memory/I/O Status is driven Low to indicate an I/O tra nsfer . A High on this signal
indicates a memory transfer.
Local Bu s Write/Read S tatus is driven Low to indicate a read transfer . A High on this signal
indicates a writ e.
VL_LCLK O Local Bus Clock is the VL-bus clock. It is used by the VL-bus target for all timing references.
This signal is in phase with the internal CPU’s clock input.
(Rising Edge Active)
VL_LDEV ILocal Bu s Device S elect is as serted by the VL-bus ta rget to indi cate that i t is acce pting the
current tran sfer as indi cated by the addr ess and status lines. The VL-bus target asserts th is
signal as a function of the address and status presented on the bus.
VL_LRDY ILocal Bus Ready is asserted by the VL-bus target to indicate that it is terminating the current
bus cycle. This signal is sampled by the chip on the rising edge of VL_LCLK.
VL_RST OLocal Bus Reset is the VL-bus master reset. It is controlled with CSC index 14h[4].
Power Management
ACIN I AC Supply Active indi cates to the system that it i s being po wered from an AC source. When
asserted, this signal can disable power management functions (if configured to do so).
BL2–BL0 IBattery Low Detects indicate to the chip the current status of the system’s primary battery
pack. BL0–BL2 can indicate var ious conditions of t he battery as cond itions change. T hese
inputs can be used to force the system into one of the power saving modes when activated
(Low-going Edge).
LBL2 OLatche d Battery Low Detect 2 can be d riven Low and la tched on the low- going edg e of the
BL2 inpu t to indi cate to the sys tem that th e c hip has b een force d into the Suspen d mode by
a battery d ead ind icati on from the BL 2 signa l. It is cleare d by one of the “al l clear” in dicato rs
that allow the system to resume after a battery dead indication.
SUS_RES I Suspend/Resume O peration: When the chip is in Hyper-Speed, High-Sp eed, Low-Speed,
or Standby mode, a software-configurable edge on this pin can cause the internal logic to
enter Sus pend mode. When in Suspend, a software-con figurable ed ge on this pin can cau se
the chip to enter the High-Speed or Low-Speed mode. The choice of edge is configured using
the SUS_RES Pin Configuration Register at CSC index 50h.
Table 19. Signal Description Table (Continued)
Signal Type Description
Bus Cycle Initiated VL_M/IO VL_D/C VL_W/R
Interrupt A c knowledge 0 0 0
Halt/Special Cycle 0 0 1
I/O Read 0 1 0
I/O Write 0 1 1
Code Read 1 0 0
Reserved 1 0 1
Memory Read 1 1 0
Memory Write 1 1 1
66 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Clocks
32KXTAL1
32KXTAL2 32.768-kHz Crystal Interface Sign als are used for the 32 .768-kHz cry stal. This is the main
clock source for the chip and drives the internal Phase-Locked Loops (PLLs) that generate
all other clock frequencies needed in the system.
CLK_IO I/O Clock Input /Output is an inp ut to drive the integra ted 8254 timer with a 1.19318-MHz clock
signal from an external source, or an output to bring out certain internal clock sources to drive
external devices.
LF_INT, LF_LS,
LF_VID, LF_HS ALoop Filters connect external RC loop filters required by the internal PLLs. LF_VID is not
supported on the ÉlanSC410 microcontroller.
Parallel Port
(Note: The names in parentheses in this section are those used in EPP mode.)
ACK (INTR) I Printer Acknowledge: In standard mode, this signal is driven by the paral lel port d evice with
the state of the printer acknowledge signal. I n EPP mode, this signal indicates to th e chip that
the parallel port device has generated an interrupt request.
AFDT (DSTRB)OAuto Line Feed Detect: In standard mode, this signal is driven by the chip indicating to the
parallel port device to insert a line feed at the end of every line. In EPP mode, this signal is
driven active by the chip during reads or writes to the EPP data registers.
BUSY (WAIT)IPrinter Busy: In standard mode, this signal is driven by the parallel port device with the state
of the printer busy signal. In EPP mode, this signal adds wait states to the current cycle.
ERROR IError: The print er asserts this sig nal to inform the pa rallel port of a dese lect conditio n, paper
end (PE) or other error condition.
INIT OInitialize Printer: This signals the printer to begin an initialization routine.
PE I Paper End: The printer asserts this signal when it is out of paper.
PPDWE OParallel Port Write Enable controls an external 374 type latch in a unidirectional parallel port
design. This de vice la tches the SD7–SD0 bus ont o the par allel po rt data bus. To imp lemen t
a bidirec tional parall el port, this p in can be re confi gured to act as an addres s decode for t he
parallel port data port. PPDWE can then be externally gated with IOR and IOW to provide
the Parallel Port Data Read and Write Strobes, respectively.
PPOEN OParallel Port Output Buffer Enable supports a bidirectional parallel port design. PPOEN
controls the output enable of the external Parallel Port Output Buffer (373 octal D-type
transparent latch) .
SLCT I Printer Select is returned by a printer upon receipt of SLCTIN.
SLCTIN (ASTRB)OPrinter Selected: In Standard mode, this signal is driven by the chip to select the parallel
port devi ce. In EPP mode, this signal is driv en active by the chip during reads or writes to the
EPP address register.
STRB (WRITE)OStrobe: In Standard mode, this signal indicates to the parallel port device to latch the data
on the parallel port data bus. In EPP mode, this signal is driven active during writes to the
EPP data or the EPP address register.
Serial Port
CTS IClear To Send is driven back to the serial port to indicate that the external data carrier
equipment (DCE) is ready to accept data.
DCD IData Carrier Detect is driven back to the serial port from a piece of data carrier equipment
when it h as detected a carrier signal f rom a communications target.
DSR IData Set Ready indicates that the external DCE is ready to establish a communication link
with the internal serial port controller.
DTR OData Terminal Ready indi ca tes to th e e xte rnal DC E t hat the i ntern al se ria l p ort controlle r is
ready to communicate.
RIN IRing Indicate is used by an external mo dem to inform the serial port that a ring signal was
detected . A change in state on thi s signal b y the ext ernal modem c an be config ured to caus e
a modem status interrupt. This signal can be used to cause the chip to resume from a
Suspend sta t e.
Table 19. Signal Description Table (Continued)
Signal Type Description
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 67
RTS ORequest To Send indicates to the external DCE that the internal serial port controller is ready
to send data.
SIN I Serial Data In receives the serial data fro m the external serial device or DCE into the interna l
serial po rt co ntro ller.
SOUT O Serial Data Out transmits the serial data from the internal serial port controller to the external
serial device or DCE.
Keyboard Interfaces
KBD_COL7–
KBD_COL0 OMatrix-Scanned Keyboard Column Outputs drive the matrix keyboard column lines.
(Open Collector Output with programmable termination)
KBD_ROW14–
KBD_ROW0 STI Matrix-Scanned Keyboard Row Inputs samples the row lines on the matrix keyboard.
XT_CLK I/O XT Keyboard Clock is the clock signal for an external XT keyboa rd interface.
(Open Collector Output)
XT_DATA I/O XT Keyboard Data is the data signal for an external XT keyboard interface.
(Open Collector Output)
General-Purp ose Inpu t/Output
GPIO31–GPIO15
GPIO_CS14–
GPIO_CS0
BGeneral Purpose I/Os and Programmable Chip Selects
Each of the GPIOs can be programmed to be an input or an output.
As outputs , all of the GP IOs can be p rogrammed to b e High or Low. Some of the GPIOs c an
be programmed to be High or Low for each of the power management modes. Also as
outputs, some of these pins can be individually programmed as chip selects for other
external peripheral d evices. The se can be con figured as d irect memory add ress deco des or
I/O decodes qualified or non-qualified by the ISA bus command signals. Any one of the
GPIO_CSx signals can be configured as ROMCS2.
As inputs, all the GPIOs can be read back with a register bit. Some of these pins can be
individually programmed to act as activity triggers, wake-up sources, or SMIs.
Serial Infrared Port
SIRIN I Infrared Serial Input is the digital input for the serial infrared interface.
SIROUT O Infrared Serial Output is the digital output for the serial infrared interface.
PC Card Controller (ÉlanSC400 Microcontroller Only)
(Note: The names in parentheses in this section are those used in PC Card Memory and I/O mode.)
BVD1_A
(STSCHG_A)–
BVD1_B
(STSCHG_B)
IBattery V oltage Detect is driven Low by a PC Card when its on-board battery is dead. When
the PC Card interface is configured for I/O, this signal can be driven by the card to indicate
a card status change. It is typically used to generate a system IRQ in this mode. These
signals are not supported on the ÉlanSC410 microcontroller.
BVD2_A (SPKR_A)
(DRQ_A)–
BVD2_B (SPKR_B)
(DRQ_B)
IBattery V oltage Detect is driven Low by a PC Card when its on-board battery is weak. When
the PC Card interface is configured for I/O, this signal can be driven by the card’s speaker
output. When enabled, this signal can drive the chip SPKR output. When PC Card DMA is
enabled, the DMA request from the PC Card can be programmed to appear on this signal.
See also the description for WP_A (IOIS16_A) (DRQ_A) and WP_B (IOIS16_ B) (DRQ_B);
the DMA request can also be programmed to appear on these pins. These signals are not
supported on the ÉlanSC410 microcontroller.
CD_A–CD_B
CD_A2 ICard Detect indicates that the card is properly inserted. Socket A is capable of being
configu r ed to u se tw o car d detect i npu ts and Sock et B is only pro vi ded w ith on e. I f only on e
card detect is t o b e used for a soc ke t, t he input si gnals s hou ld be drive n f r om a lo gic al AN D
(digit al OR) of the CD1 and C D2 signa ls from th eir respec tive card interfaces . These s ignals
are not supported on the ÉlanSC410 microcontroller.
Table 19. Signal Description Table (Continued)
Signal Type Description
68 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
ICDIR O Card Data Direction controls the direction of the card data buffers or voltage translators. It
works with the MCEL and MCEH card enable signals to control data buffers on the card
interface. When this signal is High, the data flow is from the chip to the card socket, indicating
a data write cycle. When thi s signal is Lo w, the data flow is from the card socket into the chip,
indicating a read cycle. This signal is not supported on the ÉlanSC410 microcontroller.
MCEH_A, MCEH_B OCard Enables, High Byte enables a PC Card’s high da ta bus byte trans ceive rs for the
respective card interfaces . These signals are not supported o n the ÉlanSC410 microcontroller.
MCEL_A, MCEL_B OCard Enables, Low Byte enables a PC Card’ s low data bus by te transceiv ers for the
respective card interfaces . These signals are not supported o n the ÉlanSC410 microcontroller.
OE OPC Card Output Enable: This is the PC Card memory read signal. This signal is not
supported on the ÉlanSC410 microcontroller.
PCMA_VCC OPC Card Socket A VCC Enable can be used to control the VCC to Socket A. This signal is
not supported on the ÉlanSC410 microcontroller.
PCMA_VPP2–
PCMA_VPP1 OPC Card Socke t A VPP Selects can be used to control the VPP to Socket A. Thes e sig nals
are not supported on the ÉlanSC410 microcontroller.
PCMB_VCC OPC Card Socket B VCC Enable can be used to control the VCC to Socket B. This signal is
not supported on the ÉlanSC410 microcontroller.
PCMB_VPP2–
PCMB_VPP1 OPC Card Socke t B VPP Selects can be used to control the VPP to Socket B. Thes e sig nals
are not supported on the ÉlanSC410 microcontroller.
RDY_A (IREQ_A),
RDY_B (IREQ_B)ICard Ready indicates that the respective card is ready to accept a new data transfer
command. When the card interface is configured as an I/O interface, this signal is used as
the card Interrupt Request input into the chip. These signals are not supported on the
ÉlanSC410 microcontroller.
REG_A (DACK_A),
REG_B (DACK_B) OAttribute Memory Select signals are driven inactive (High) for accesses to a PC Card’s
common memory, and asserted (Low) for accesses to a PC Card’s attribute memory and
I/O space for their respective card interfaces. When PC Card DMA is enabled, the DMA
acknow ledge to th e PC Card app ears on thi s signal. The se signal s are not su pported on the
ÉlanSC410 microcontroller.
RST_A, RST_B O Card Reset signals are the reset for their respective cards. When active, this signal clears
the Interru pt and Gene ral Control Re gister (PC Card in dex 03h and 43h), thus pl acing a ca rd
in an unconfigured (Memory-Only mode) state. It also indicates the beginning of any additional
card initialization. Th ese sig nals are not su pported on the ÉlanSC 410 mic rocontroller.
WAIT_AB IExtend Bus Cycle delays the completion of the memory access or I/O access that is
currently in progress. When this signal is asserted (Low), wait states are inserted into the
cycle i n progr ess. Only o ne W A IT i nput is pro vided on the chip. Externa l logic i s requi red for
a two-socket im plementation to logically AND (digitally OR) each card’s WAIT signal
together. This signal is not supported on the ÉlanSC410 microcontroller.
WE (TC) O PC Card Write Enable is the PC Card m emory write signal. Dat a is trans ferred from the chip
to the PC Card. When PC Card DMA is enabled, the DMA Terminal Count to the PC Card
appears on this signal. This signal is not supported on the ÉlanSC410 microcontroller.
WP_A (IOIS16_A)
(DRQ_A), WP_B
(IOIS16_B)
(DRQ_B)
IWrite Protect indicates the status of the respective card’s Write Protect switch. When the
respective card is configured for an I/O interface, this signal is used by the card to indicate
back to the chip that the currently accessed port is 16 bits wide. When PC Card DMA is
enabled, the DMA request from the PC Card can be programmed to appear on this signal.
See also the description for BVD2_A (SPKR_A) (DRQ_A) and BVD2_B (SPKR_B)
(DRQ_B); the DMA request can also be programmed to appear on these pins. These signals
are not supported on the ÉlanSC410 microcontroller.
LCD Graphics Controller (ÉlanSC400 Microcontroller Only)
FRM O LCD Panel Line Frame Start is asserted by the chip at the start of every frame to indicate
to the LCD panel that the next data clocked out is intended for the start of the first scan line
on the pan el. Som e pane ls refe r to this signa l as FL M or S (s can st art-u p). This sign al is n ot
supported on the ÉlanSC410 microcontroller.
Table 19. Signal Description Table (Continued)
Signal Type Description
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 69
LC O LCD Panel Line Clock is activ ated at the start of every pi xel lin e. It is c ommonl y referre d to
by LCD data sheets as CL1 or CP1. This signal is not supported on the ÉlanSC410
microcontroller.
LCDD7–LCDD0 O LCD Panel Data bits: LCDD7–LCDD0 are data bits for the LCD panel interface. When
driving 4-bit single-scan panels, bits 3–0 form a nibble-wide LCD data interface. In dual-scan
panel mode, LCDD3–LCDD0 are the data bits for the top half of the LCD, and LCDD7–
LCDD4 are the data bits for the bottom half of the LCD. When driving 8-bit single-scan panels
(monochrome or color STN), these bits are the 8-bit data interface. These signals are not
supported on the ÉlanSC410 microcontroller.
LVDD OLCD Panel VDD Voltage Control is used to control the assertion of the LCD’s VDD volt age.
This is p rovided to be part of the solution in sequencing the panel’s VDD, DATA, and VEE in
the proper order during panel power-up and power-down to prevent damage to the panel
from CMOS driver l atc h u p. VDD is us ed to pow er th e LCD l ogi c a nd is usu all y + 5 V or +3 V
DC. This signal is not supported on the ÉlanSC410 microcontroller.
LVEE OLCD Panel VEE Voltage Control is us ed to c ont rol the assertion of th e L C D’ s VEE voltage.
This is p rovided to be part of the solution in sequencing the panel’s VDD, DATA, and VEE in
the proper order during panel power-up and power-down to prevent damage to the panel
from CMOS driver latch up. VEE is the LCD contra st voltage and is either positive or ne gative
with an amplitude of 15–30 V DC.This signal is not supported on the ÉlanSC410
microcontroller.
MOLCD Panel AC M odulation is t he AC modu lation s ignal for the LCD. AC modula tion causes
the LC D p ane l d r iv ers to reve rse p ola rity t o p r ev en t a n i nte rna l DC bi as fro m form in g on the
panel. This signal is not supported on the ÉlanSC410 microcontroller.
SCK O LCD Panel Shift Cloc k is the nib bl e/by te strobe u se d by th e LC D panel to l atc h a nibble or
byte of incoming data. Commonly referred to by LCD panels as CL2 or CP2. This signal is
not supported on the ÉlanSC410 microcontroller.
Boundary Scan Test Interface
BNDSCN_TCK I Test Clock is th e boundary -s ca n i nput cloc k that is us ed to sh ift serial da ta patterns in from
BNDSCN_TDI.
BNDSCN_TDI I Test Data In put is the serial inp ut strea m for boundary -scan inpu t data. Th is pin has a w eak
internal p ull up re si stor. It is sampled on the risin g ed ge o f BNDSCN_TCK. If not drive n, thi s
input is sampled High internally.
BNDSCN_TDO O
TS Test Data Output is the serial output stream for boundary-scan result data. It is in the high-
impedance state except when scanning is in progress.
BNDSCN_TMS I T est Mode Selec t is an input for controlling the test access port. Thi s pin has a weak internal
pullup resistor. If it is not driven, it is sampled High internally.
Reset and Power
BBATSEN A Backup Battery Sense: RTC (Real Time Clock) backup battery voltage is sampled on this
pin each time the AVCC pin has power applied to it followed by a chip master reset. If this
samples below 2.4 V , the VRT bit (R TC index 0Dh) is cleared un til read one time. At this time,
the VRT bit is set until BBATSEN is sampled again. BBATSEN also provides a power-on-
reset signal for the RTC when an RTC backup battery is applied for the first time.
GND Ground Pins
RESET IReset Input is an asynchronous ha rdware reset input equiv alent to POWERGOOD in the A T
system architecture.
VCC 3.3-V DC Supply Pins provide power to the discrete logic and I/O pins.
VCC_A Analog 3.3-V Supply Pins provide power to the analog section of the chip, including the internal
PLLs and in tegr ated osci lla tor circuit . Extr eme ca re shoul d be tak en that th is sup ply vo ltage
is isolated properly to provide a clean, noise free voltage to the PLLs.
VCC_CPU CPU 3.3-V DC Supply Pins provide power to the internal CPU.
VCC_RTC RTC 3.3-V Supply Pin provides power to the inter nal real-time clock and on-board static/
configuration RAM. This pin can be driven independently of all other power pins.
Table 19. Signal Description Table (Continued)
Signal Type Description
70 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Multiplexed Pin Function Options
Table 20 shows how to configure each multiplexed
signal on the ÉlanSC400 and ÉlanSC410
microcontrollers.
Note that those signals marked with a superscript 1 (1)
are not supported on the ÉlanSC410 microcontroller.
Pins with multiplexed functions have their functions
selected in one of three ways:
■By configuration pins that are latched during reset
■By assertion at BNDSCN_EN
■By firmware via programmed configuration registers
Table 20. Multiplexed Pin Configuration Options
Signal You Want Signals You Give Up How to Configure the Signal You Want on the Pin Pin #
System Interfa ce
BALE KBD_ROW10 Set CSC index 39h[2]. D2
DBUFOE GPIO_CS4 Hardwire strap the CFG3 pin High. C4
DBUFRDH GPIO_CS3 Hardwire strap the CFG3 pin High. D17
DBUFRDL GPIO_CS2 Hardwire strap the CFG3 pin High. C18
MCS16 KBD_ROW12 Set CSC index 39h[2]. F3
PDACK1 KBD_ROW7 Set CSC index 39h[2]. D3
PDRQ1 KBD_ROW8 Set CSC index 39h[2]. C2
PIRQ0 GPIO_CS8 Set CSC index 38h[1]. W18
PIRQ1 GPIO_CS7 Set CSC index 38h[2]. Y19
PIRQ2 KBD_ROW9 Set CSC index 39h[2]. E3
PIRQ3 KBD_COL2 Set CSC index 3Ah[1]. A2
PIRQ4 KBD_COL3 Set CSC index 3Ah[1]. B3
PIRQ5 KBD_COL4 Set CSC index 3Ah[2]. C3
PIRQ6 KBD_COL5 Set CSC index 3Ah[2]. A1
PIRQ7 KBD_COL6 Set CSC index 3Ah[2]. B2
R32BFOE KBD_ROW13 Hardwire-strap both the CFG1 and CFG0 pins High to enable the
32-bit ROM interface on ROMSC0. This automatically enables
R32BFOE.
A3
SBHE KBD_ROW11 Set CSC index 39h[2]. C1
Configuration Pins (Pinstraps) (See “Using the Configur ation Pi ns to Select Pin Functions” on page 74.)
Memory Interface
CASH2 KBD_ROW2 Set bit 3 of the DRAM Bank x Configuration Register.
Set CSC index 00h[7] and 00h[3], or
Set CSC index 01h[7] and 01h[3], or
Set CSC index 02h[7], or
Set CSC index 03h[7].
C17
CASH3 KBD_ROW3 B18
CASL2 KBD_ROW0 B19
CASL3 KBD_ROW1 D16
MA12 KBD_ROW6 B17
RAS2 KBD_ROW4 D15
RAS3 KBD_ROW5 C16
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 71
VL-Bus Interface
VL_ADS LCDD11 Enable the VL-bus interface by setting CSC index 14h[3]. C19
VL_BE0 SCK1F19
VL_BE1 LC1E20
VL_BE2 M1F18
VL_BE3 LCDD71D20
VL_BLAST LVDD1A19
VL_BRDY LVEE1A20
VL_D/C LCDD51E18
VL_LCLK FRM1E19
VL_LDEV LCDD61 F17
VL_LRDY LCDD41D19
VL_M/IO LCDD31 C20
VL_RST LCDD01B20
VL_W/R LCDD21 D18
ISA Bus
AEN GPIO_CS10 Set CSC index 38h[0]. V17
IOCHRDY G PIO_CS6 Set CSC index 38h[3]. V18
IOCS16 GPIO_CS5 Set CSC index 38h[4]. W19
PDACK0 GPIO_CS11 Set CSC index 38h[0] W17
PDRQ0 GPIO_CS12 Set CSC index 38h[0]. Y17
TC GPIO_CS9 Set CSC index 38h[0]. Y18
GPIOs
GPIO15 PCMA_VPP21 Clear CS C index 39h[5]. Y15
GPIO16 PCMB_VCC1 Clear CS C index 39h[6]. V15
GPIO17 PCMB_VPP11Clear CS C index 39h[6]. W15
GPIO18 PCMB_VPP21Clear CS C index 39h[6]. Y14
GPIO19 LBL2 Clear CSC ind ex 39h[4] . V14
GPIO20 CD_A21Clear CSC index 3Ah[0]. G18
GPIO21 PPDWE Clear CSC index 39h[1– 0]. V3
GPIO22 PPOEN Clear CSC ind ex 39h[1– 0]. T3
GPIO23 SLCT, WP_B1Clear CSC index 39h[1– 0]. U 4
GPIO24 BUSY, BVD2_B1Clear CS C index 39h[1– 0]. U 3
GPIO25 ACK, BVD1_B1Cl ear C SC index 39h[1– 0]. U2
GPIO26 PE, RDY_B1Cl ear C SC index 39h[1– 0]. W2
GPIO27 ERROR, CD_B1Clear CSC index 39h[1– 0]. V4
GPIO28 INIT, REG_B1Clear CSC index 39h[1– 0]. Y2
GPIO29 SLCTIN, RST_B1Clear CSC index 39h[1–0]. W3
GPIO30 AFDT, MCEH_B1Clear CSC index 39h[1– 0]. W1
GPIO31 STRB, MCEL_B1 Clear CS C index 39h[1– 0]. V2
GPIO_CS2 DBUFRDL Hardwire-st rap the CF G3 pin Low. C18
GPIO_CS3 DBUFRDH H a rdw ire -st rap the CF G3 pin Low. D17
GPIO_CS4 DBUFOE Hardwire-str ap the CFG3 pin Low. C4
GPIO_CS5 IOCS16 Clear CS C index 38h[4]. W19
GPIO_CS6 IOCHRDY Clear CSC index 38h[3]. V18
GPIO_CS7 PIRQ1 Clear CSC index 38h[2] . Y19
GPIO_CS8 PIRQ0 Clear CSC index 38h[1] . W18
GPIO_CS9 TC Clear CSC index 38h[0]. Y18
GPIO_CS10 AEN Clear CSC ind ex 38h[0]. V17
Table 20. Multiplexed Pin Configuration Options (Continued)
Signal You Want Signals You Give Up How to Configure the Signal You Want on the Pin Pin #
72 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
GPIO_CS11 PDACK0 Clear CSC index 38h[0] . W 17
GPIO_CS12 PDRQ0 Cl ear CS C index 38h[0] . Y17
GPIO_CS13 PCMA_VCC1Clear CSC index 39h[5]. V16
GPIO_CS14 PCMA_VPP11 Cl ear CS C index 39h[5]. W16
Parallel Port
ACK GP IO25, BVD1_ B1Write CSC index 39h[1–0] to 10. U2
AFDT GPIO30, MCEH_B1 W1
BUSY GPIO24, BVD2_B1U3
ERROR GPIO27, CD_B1 V4
INIT GPIO28, REG_B1Y2
PE GPIO26, RDY_B1W2
PPDWE GPIO21 V3
PPOEN GPIO22 T3
SLCT GPIO23, WP_B1U4
SLCTIN GPIO29, RST_B1W3
STRB GPIO31, MCEL_B1 V2
Keyboard Interface
KBD_COL0 XT_DATA Clear CSC index 39h[3] . E2
KBD_COL1 XT_CLK Clear C SC index 39h[3] . D 1
KBD_COL2 PIRQ3 Clear CSC index 3Ah[1]. A2
KBD_COL3 PIRQ4 Clear CSC index 3Ah[1]. B3
KBD_COL4 PIRQ5 Clear CSC index 3Ah[1]. C 3
KBD_COL5 PIRQ6 Clear CSC index 3Ah[1]. A1
KBD_COL6 PIRQ7 Clear CSC index 3Ah[1]. B2
KBD_ROW0 CASL2 Clear CSC index 00h[7] and 00h[3], or
clear CSC index 01 h[7] and 0 1h[3], o r
clear CSC index 02 h[7], or
clear CSC index 03 h[7].
B19
KBD_ROW1 CASL3 D16
KBD_ROW2 CASH2 C17
KBD_ROW3 CASH3 B18
KBD_ROW4 RAS2 D15
KBD_ROW5 RAS3 C16
KBD_ROW6 MA12 B17
KBD_ROW7 PDACK1 Clear CSC index 39h[2]. D3
KBD_ROW8 PDRQ1 Clear CSC ind ex 39h[2]. C2
KBD_ROW9 PIRQ2 Clear CSC index 39h[2] . E3
KBD_ROW1 0 BALE Clear CSC index 39h[2] . D2
KBD_ROW11 SBHE Clear CSC index 39h[2] . C 1
KBD_ROW12 MCS16 Clear CSC index 39h[2] . F3
KBD_ROW13 R32BFOE Do not enable the 32-bit ROM interface on ROMCS0 (e.g., do not
hardwire-strap both the CFG1 and CFG0 pins High). A3
XT_CLK KBD_COL1 Clear CSC index 39h[3] . D1
XT_DATA KBD_CO L0 Clear CSC index 39h[3] . E2
PC Card (ÉlanSC400 Microcontroller Only)
BVD1_B1 GPIO25, ACK Write CSC index 39h[1–0] to 01. U2
BVD2_B1 GPIO24, BUSY Write CSC index 39h[1–0] to 01. U3
CD_A2 1 GPIO20 Set CSC index 3Ah[0]. G18
CD_B1 G PIO27, ERROR Write CSC index 39h[1–0] to 01. V4
LBL21 GPIO19 Set CSC index 39h[4]. V14
MCEH_A1 BNDSCN_TMS Pull the BNDSCN_EN pin Low. N3
MCEH_B1 GPIO30, AFDT Write CSC index 39h[1–0] to 01. W1
MCEL_A1 BDNSCN_TCK Pull the BNDSCN_EN pin Low. P2
Table 20. Multiplexed Pin Configuration Options (Continued)
Signal You Want Signals You Give Up How to Configure the Signal You Want on the Pin Pin #
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 73
MCEL_B1 GPIO31, STRB Write CSC index 39h[1–0] to 01. V2
PCMA_VCC1 GPIO_CS13 Set CSC index 39h[5]. V16
PCMA_VPP11 GPIO_CS14 Set CSC index 39h[5]. W16
PCMA_VPP21 GPIO15 Set CSC index 39h[5]. Y15
PCMB_VCC1 GPIO16 Set CSC index 39h[6]. V15
PCMB_VPP11 GPIO17 Set CSC index 39h[6]. W15
PCMB_VPP21GPIO18 Set CSC index 39h[6]. Y14
RDY_B1 GPIO26, PE Write CSC index 39h[1–0] to 01. W2
REG_A1 BNDSCN_TDO Pull the BNDSCN_EN pin Low. M2
REG_B1 GPIO 28, INIT Write CSC index 39h[1–0] to 01. Y2
RST_A1 BNDSCN_TDI Pull the BNDSCN_EN pin Low. R1
RST_B1 GPIO29, SLCTIN Write CSC index 39h[1–0] to 01. W3
WP_B1 GPIO23, SLCT Write CSC index 39h[1–0] to 01. U4
LCD Graphics Controller (ÉlanSC400 Microcontroller Only)
FRM1 VL_LCLK Enable the graphics controller by setting CSC index DDh[2]. E19
LC1 VL_BE1 E20
LCDD01 VL_RST B20
LCDD11 VL_ADS C19
LCDD21 VL_W/R D18
LCDD31 VL_M/IO C20
LCDD41 VL_LRDY D19
LCDD51 VL_D/C E18
LCDD61 VL_LDEV F17
LCDD71 VL_BE3 D20
LVDD1 VL_BLAST A19
LVEE1 VL_BRDY A20
M1 VL_BE2 F18
SCK1 VL_BE0 F19
Boundary Scan Interface
BDNSCN_TCK MCEL_A 1Pull the BNDSCN_EN signal High. P2
BNDSCN_TDI RST_A1R1
BNDSCN_TDO REG_A1 M2
BNDSCN_TMS MCEH_A 1N3
Miscellaneous
BL0 CLK_IO Write CSC index 38h[7–6] to 01. W14
CLK_IO BL0 Wr ite CS C inde x 38h[7 –6] to 1 0 to en abl e CLK_IO as an output or to
11 to enable CLK_IO as a timer clock input. W14
Notes:
1. This signal is not supported on the ÉlanSC410 microcontroller.
Table 20. Multiplexed Pin Configuration Options (Continued)
Signal You Want Signals You Give Up How to Configure the Signal You Want on the Pin Pin #
74 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Using the Configuration Pins to Select
Pin Functions
The configuration pins are used only for those func-
tions that must be selected at reset, prior to firmware
execution. All other I/O functions are selected using
configuration registers.
Table 21 provi des an overvi ew of the c onfigu ratio n pin
functions. Al l of the CFG pins have wea k internal pul l-
down resistors that select the default function. External
pullup resistors are required to select an alternative
function.
Notes:
1. CFG3 is defined as the enable/disable for the DBUFOE,
DBUFRDL, and DBUFRDH signals. They can be enable d
independently of whether a x32 D bus is selected via the
firmware to support the VL local bus or x32 DRAM interface.
2. The x32 ROM option must be selected for ROMCS0 for
the R32BFOE si gnal t o be enabl ed. T he sele ction of the
DBUFOE, DBUFRDL, and DBUFRDH signals are still
dependent only on the CFG3 signal.
CFG0 and CFG1 Pins
These pins (shown in Table 22) configure the data bus
width (x8, x16, or x32) of the ROM interface that is se-
lected by the ROMCS 0 pin. If a x32 ROM is sel ected,
these pins also enable the ROM x32 Data Bus Buffer
Output En able signal (R3 2BFOE). If a 32- bit data bus
width is selected for the ROM interface, the R32BFOE
signal will be asserted for all ROMCSx accesses to
32-bit ROM. Exercise caution because the data bus
width for th e ROMCS0 i nterface ca n also be cha nged
through programming. This feature was implemented
mainly for testing.
.
CFG2 Pin—ÉlanSC400 Microcontroller Only
This configuration pin (see Table 23) is used on the
ÉlanSC400 microcontroller to select the ROMCS0
steering at system boot time. The boot ROM chip se-
lect (ROMCS0) can either be enabled to drive the
ROMCS0 pin or ca n be rerouted to d rive the PC C ard
(Socket A only) interface chip selects. The CFG0 and
CFG1 pins are still used to select the data bus width for
the ROMCS0 d ecode, rega rdless of the CFG2 c onfig-
uration. Th e PC Card RO MCS0 red irec tion s hould no t
be selected when the CFG0 and CFG1 configuration
pins are set to select a x32 ROM interface.
When the ROM chip select decode has been redi-
rected to PC Card Socket A, all of the normal PC Card
controller features can still be used to drive the PC
Card Socket A interface. The ROM chip select decode
remappi ng to the P C Ca rd soc ke t c an be en abl ed an d
disabled using firmware at any time.
Table 21. Pinstrap Bus Buffer Options
CFG3
(1)CFG1 CFG0 ROMCS0
Data
Width
DBUFOE
DBUFRDL
DBUFRDH R32BFOE
0 0 0 x8 Disabled Disabled
0 0 1 Reserved Reserved Reserved
0 1 0 x16 Disabled Disabled
011x32
2Disabled Enabled
1 0 0 x8 Enabled Disabled
1 0 1 Reserved Reserved Reserved
1 1 0 x16 Enabled Disabled
111x32
2Enabled Enabled
Table 22. CFG0 and CFG1 Configuration
CFG1 CFG0 Configuration
00x8 ROMCS0
ROM interface
01Reserved
1 0 x16 ROMCS0 ROM interface
1 1 x32 ROMCS0 ROM interface
Table 23. CFG2 Configuration (ÉlanSC400
microcontroller only)
CFG2 Configuration
0 Enables the ROMCS0 decode
on the ROMCS0 pin
1 Enables the ROMCS0 decode
to access PC Card Socket A
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 75
CFG3 Pin
This configuration pin is used for selecting between the
GPIO_CS4–GPIO_CS2 I/O pins and the SD bus buffer
control signals: DBUFOE, DBUFRDL, and DBUFRDH.
When the buffer control signal configuration is selected
using the CFG3 pin, the DBUFOE, DBUFRDL, and
DBUFRDH signals are dr iven f rom boot ti me on fo r all
accesses to the peripheral data bus. These signals are
used for the external system bus transceiver control.
See Table 24 for the CFG3 configuration definitions.
BNDSCN_EN Pin
The BNDSCN_EN configuration pin (see Table 25) is
used to enable the boundary scan function I/O pins.
The following pins are configured for their boundary
scan function when BNDSCN_EN is asserted:
■BNDSCN_TCK
■BNDSCN_TMS
■BNDSCN_TDI
■BNDSCN_TDO
Table 24. CFG3 Configuration
CFG3 Configuration
0Enables the GPIO_CS4–GPIO_CS2 signals
on the I/O pins
1 Enables the SD bus buf f er cont rol si gnals
DBUFOE, DBUFRDL, and DBUFRDH
on the I/O pins
Table 25. BNDSCN_EN Configuration
BNDSCN_EN Configuration
0 Enables the PC Card function
1 Enables the boundary scan functions:
BNDSCN_TCK, BNDSCN_TMS,
BNDSCN_TDI, and BNDSCN_TDO
76 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
CLOCKING
Clock Generation
The ÉlanSC400 and ÉlanSC410 microcontrollers re-
quire only one 32.768-kHz crystal to generate all the
other clock frequencies required by the system. The
output of the on-chi p cr ysta l os ci ll ato r ci rcu it is use d to
generate the various frequencies by utilizing four
Phase- Locked Loop (P LL) circu its. The PLL cl ock dis-
tribution scheme is shown in Figure 4. Table 26 shows
all the PLL output frequencies and their usage. (Note
that these four PL L circui ts are in a dditio n to th e inter-
nal CPU PLL and do not replace it.)
The crystal oscillator needs two pins, but it does not re-
quire any ex ternal compone nts except the cr ystal; the
load capacitors and the feedback resistor are inte-
grated on-chip.
The four PLLs are called Intermediate PLL, Low-Speed
PLL, High-Speed PLL, and Graphics Dot Clock PLL.
Each of th e i nteg ra ted phas e-l oc ke d lo ops ha s a dedi-
cated pin to support the required external loop filter.
These pins are: LF_INT (Intermediate PLL), LF_LS
(Low-Speed PLL), LF_HS (High-Speed PLL), and
LF_VID (Gr aph ic s D ot Cl oc k PLL ). (Th e LF_ VID pin is
not supp orted on th e É la n SC 4 10 mi croc on tr o ll e r .) Two
capaci tors and one res istor are requ ired to imple ment
each loop filter.
Figure 4. Clock Generation Block Diagram
Notes:
On the ÉlanSC400 microcontroller, the graphics controller’s DRAM interface is clocked by the 66-MHz DRAM clock.
Both the ROM/Flash memory interface and the PC Card controller are clocked from the CPU clock. They also have the option
to be run from the slow system clock.
Neither the graphics controller nor the PC Card controller are supported on the ÉlanSC410 microcontroller.
32.768-kHz
Crystal
Oscillator
Intermediate
Low-Speed
Graphics
High-Speed
20.736–
36.864 MHz
32.768 kHz
66.3552 MHz
1.47456 MHz
36.864 MHz
PLL
PLL
Dot Clock
PLL
PLL
Real-Time
Clock
PMU
UART
Timer
Graphics
ISA Bus
DRAM
DMA
CPU and
Controller
Controller
Controller
Divisors
Divisors
DRAM
Controller
VL-Bus
Controller
ROM/Flash
Interface
PC Card
Controller
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 77
Integrated Peripheral Clock Sources
Table 26 and Figure 5 show the primary peripheral
clock s internal t o the micr ocontroller and the P LL and
divider sources that are used in the generation of these
clocks. Note that several of the peripheral clocks are
programmable. This programmability is either directly
controlled by system firmware or is forced due to a
power-m anagement mode ch ange. The graphics c on-
troller and the PC Card controller are not supported on
the ÉlanSC410 microcontr oller.
Table 26. Integrated Peripheral Clock Sources
Source PLL Divider Resulting Frequency Where Used
Intermediate PLL
1.4746 MHz 1 1.4746 MHz Low-speed PLL input
Low- speed PLL
36.864 MHz 1 36.864 MHz High-speed PLL input
Graphics dot clock PLL input
20 1.8432 MHz UART
2 18.4328 MHz UART
31 1.1892 MHz PIT
Grap hics dot clock PL L
36.864 MHz Programmable 20.736–36 .864 MHz Graphics controller dot clock
1 36.864 MHz Graphics controller
High-speed PLL
66.3552 MHz 1 66.3552 MHz DRAM controller
Graphics controller
2 33.1776 MHz CPU
VL-bus control ler
4 16.5888 MHz CPU
VL-bus control ler
DMA controller
8 8.2944 MHz CPU
VL-bus control ler
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
16 4.1472 MHz CPU
VL-bus control ler
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
32 2.0736 MHz CPU
VL-bus control ler
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
64 1.0368 MHz CPU
VL-bus control ler
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
78 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 5. Clock Source Block Diagram
/4
/8
/16
33.1776 MHz
16.5888 MHz
8.2944 MHz
4.1472 MHz
2.0736 MHz
1.0368 MHz
66.3552 MHz
/32
/64
/2
DRAM Clock Select
CPU Clock Select
ISA Bus Clock Select
DMA Clock Select
36.864 MHz
DRAM and
CPU and
ISA Bus, ROM,
DMA
Controllers
32.768 kHz
PLL Block
1.4746 MHz
36.864 MHz
20.736 MHz–
66.3552 MHz
Intermediate PLL
Low-Speed PLL
Graphics Dot
High-Speed PLL
Oscillator
/2
CLK_IO
Graphics
/20
/31 1.1892 MHz
1.193 18 MHz
UART
18.432 MHz
1.8432 MHz
32.768 kHz RTC
CLK_IO
32.768 kHz
Dot Clock
Timer
Clock PLL 36.864 MHz
Graphics Dot
Clock Select
Enable
Enable
Enable
Enable
PMU
CLK_IO Select
Controllers
Controller
Controller
DRAM
Controller
and PMU
VL-Bus
Controller
Graphics
and PC Card
Notes:
The graphics controller and the PC Card controller are not supported on the ÉlanSC410 microcontroller.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 79
32-kHz Crystal Oscillator
The 32-kHz oscillator circuit is shown in Figure 6; the
only external component required for operation is a
32.768-kHz crystal. The inverting amplifier (AMP) is in-
tegrated on-chip together with the feedback resistor
and the load capac i tor s. A s sh own i n Figur e 7, the on-
chip oscillator circuit can be bypassed by removing the
external crystal, grounding the 32KXTAL1 pin, and
driving the 32KXTAL2 pin with an external 32-kHz
clock. (The 32KXTAL2 pin should not exceed 2.0 V.)
When 32KX TAL1 is grounded, the amplifier no longer
affects the circuit.
Figure 6. 32-kHz Crystal Circuit
Figure 7. 32-kHz Oscillator Circuit
Loop Filters
Each of the PLLs in the ÉlanSC400 and ÉlanSC410 mi-
crocontrollers requires an external loop filter. For a
cleaner circuit, the designer should consider the following:
■Place the loop filter components as close as
possible to the loop filter signals (LF_INT, LF_LS,
LF_HS, and LF_VID (ÉlanSC400 microcontroller
only)), which are located in one corner of the
microcontroller.
■Route the loop filter signals first and by hand.
■Keep all clocks and noisy signals away from the
loop filter area (even on the inner layers).
For an even clea ner cir cuit, the des igner could option-
ally place an analog VCC power plane directly under the
loop filter circuit.
The value of the loop filt er parameters can also affect
the performance of the filter . For example, the values of
C1 and R affect lock time and jitter (in creasing RC in-
creases lock time and decreases jitter). The value of
C2 can help clean up high-frequency noise. Note tha t
using too large of values for the components can cause
the PLL to become unstable. The loop filter component
value specifications are shown in Table 28 on page 84.
Intermediate and Low-Speed PLLs
Figure 8 on page 80 shows the bl oc k dia gram for bot h
the Interm ediate and L ow-Speed PLL s. Each cons ists
of a phase detector, a charge pump, a voltage con-
trolled oscillator (VCO), an external loop filter, and a
feedback divider. This is a generic implementation of
the charge-pump PLL architecture; all four PLLs use
the same architecture. The Intermediate and Low-
Speed PLLs differ only in component values and fre-
quency of operation.
The phase detector compares the phase and fre-
quency of the two clock signals, reference frequency
(Fr) and feedback frequency (Ff). The Up signal is a
logic 1 if Fr leads Ff, while the Down signal is a logic 1
if Ff leads Fr. The Up and Down signals control the
charge pum p. The ch arge p ump either cha rg es or di s-
charges the loop filter capacitors to change the VCO
input voltage level. Because the VCO output frequency
tracks the VCO input voltage, the VCO output fre-
quency is adj usted whe never Fr and Ff d iffer in phas e
or frequency.
The feedback divide ratio determines the frequency
multiplication factor.
Frequency multiplication is 1/(Feedback Divider).
For the Intermediate PLL, the feedback divider is 1/45;
therefore, the frequency multiplication is 45. With an
input frequency of 32.768 kHz, the output frequency is
1.47456 MHz.
The input clock for the Low-Speed PLL, Fr, originates
at the Intermediate PLL output. Fr is multiplied by 25 to
generate the 36.864-MHz clock output.
AMP
32KXTAL2
32.768-kHz Crystal
32KXTAL1
Internal
External
32 kHz 32KXTAL1
Oscillator 32KXTAL2
2 V
max
Pin #Y4
80 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 8. Intermediate and Low-Speed PLLs Block Diagram
Graphics Dot Clock PLL (ÉlanSC400 Microcontroller Only)
The input clock to the Graphics Dot Clock PLL is the
output clock (36.864 MHz) of the Low-Speed PLL di-
vided by 16. The Graphics Dot Clock PLL is not sup-
ported on the ÉlanSC410 microcontroller. The output
frequenc y is program mable usi ng three exte nded reg-
ister bits (PLLRATIO[2–0]) in the range of 20.736 MHz
to 36.864 MHz (spaced 2.304 MHz apart). These three
bits (in graphics i ndex regis ter 4Ch) contr ol the outpu t
frequency by selecting the divide value in the feedback
divider as shown in Table 27.
The Graphics Dot Clock PLL requires a stabilization
period after changing frequency. Figure 9 shows the
block diagram for the Graphics Dot Clock PLL.
Phase
Detector Down
Up Charge
Pump
Loop Filter
VCO Vc
Divider
Reference
(Fr)
(Ff)
VCCA
Frequency
Feedback
Frequency
Frequency Output (Fo) Internal External
C1
RC2
Table 27. Frequency Selection Control for
Graphics Dot Clock PLL
PLLRATIO[2–0] Divider Output Frequency
(MHz)
000 9 20.736
001 10 23.04
010 11 25.344
011 12 27.648
100 13 29.952
101 14 32.256
110 15 34.56
111 16 36.864
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 81
Figure 9. Graphics Dot Clock PLL Block Diagram
High-Speed PLL
The High-S peed PLL generates a 66.3552 -MHz clo ck
for the DRAM controller. Figure 10 on pag e 82 shows
the block diagram for the High-Speed PLL. The input to
the High-Speed PLL is the output of the Low-Speed
PLL divided by five. The feedback divider is nine, which
results in an output frequency (Fo) of 66.3552 MHz.
This frequency is divided by 2 in the PMU to provide the
33-MHz input for the PLL in the CPU core.
Band Gap Block
The band gap reference circuit generates the bias cur-
rents for th e fou r P LLs an d pr ov id es a 2.4-V refe re nc e
source for the RTC voltage monitor. The current
sources, constant over VCC, temperature, and process
variation s, ar e us ed by th e four P LL c harge p ump s for
adjusting the PLL operating frequency . The 2.4-V refer-
ence voltage is used by the RTC voltage monitor to de-
tect a low backup battery voltage level.
RTC Voltage Monitor
The voltage monitor for the RTC block is shown in
Figure 11 on page 82. Its functions are to provide a
reset signal to the RTC block when it detects a low
backup battery voltage , and to provide an early warn-
ing signal when the system is powering down.
The internal RTC reset signal is asserted on power-up
if the back-up battery voltage drops below 2.4 V. The
one shot prevents multiple resets during power-on.
An internal power-down signal is used by the RTC to
isolate the RTC core from the rest of the
microcontroller. The RTC voltage monitor uses the
RESET assertion to dete ct a power-down. For proper
operation, RESET and VCC must follow the timing in
Figure 12 on page 83.
Dow n
Up Charge
Pump
Loop Filter
VCCA
36.864 MHz Phase
Detector
Vc
20.736–
Fo
Ff
Fr
Divider
/16
(9–16) 36.864 MHz
VCO
PLLRATIO[2–0]
Programmable
Internal External
C1
RC2
82 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 10. High-Speed PLL Block Diagram
Figure 11. RTC Voltage Monitor Circuit
Down
Up Charge
Pump
Loop Filter
VCCA
36.864 MHz Phase
Detector
Vc
Ff
Fr
Divider
/5
(9) VCO
66.3552 MHz
Fo
Internal External
C1
RC2
BBATSEN
Band Gap
One
Shot RTC Reset
+
–
Internal RTC
RESET
32 kHz
D
CK
Q
Flip
Flop
Power-Down
Voltage
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 83
Figure 12. Timing Diagram for RTC-On Power-Down Sequence
Clock Specifications
The specifications for the external components re-
quired to implement the four PLL loop filters are shown
in Table 28 on page 84.
Table 29 on page 84 lists the electrical specifications
for the analog VCC (VCCA) pin.
The on-chip crystal oscillator circuit supports most
generic 32.768-kHz crystals as long as the
specification for the crystals meet the electrical
paramete rs listed in Table 30 on page 84.
The worst-case start-up time required for the PLLs is
shown in Table 31 on page 84.
The PLL jitter specification is listed in Table 32 on
page 85.
Programmable Interval Timer (PIT)
The ÉlanSC400 and ÉlanSC410 microcontrollers are
equipped with a Programmable Interval Timer (PIT)
that is software-compatible with PC/AT 8254 system
timers. Historically, the clock source for this timer has
been 1.19318 MHz. However, the internal PIT clock
source is 1.1892 MHz. The user has two options:
■Use the internal PIT clock source (1.1892 MHz),
which can adversely affect the Legacy software that
depends on the 1.19318-MHz frequency.
■Drive an external 1.19318-MHz clock onto the
CLK_IO pin and program this signal to be the
source of the PIT clock.
For mo re det ails on this fe atur e, ref er to th e subse ction
on configuring Timer Channel 0 in the programmable
interval timer section of the
ÉlanSC400 and
ÉlanSC410 Microcontrollers User’s Manual
, order
#21030.
Notes:
1. These timings apply only when powering down the chip while leaving only the RTC powered.
2. Applies to all V
CC
except for the V
CC
_RTC, which is left on for this mode.
3. Guarantees at least one rising edge after reset before 2.7 volts is reached.
RESET
VCC
32 kHz
3.3 V 2.7 V
33 µs
(min)
84 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 28. Loop-Filter Component Specification for PLLs
Parameter Intermediate PLL Low-Speed
PLL Graphics Dot
Clock PLL High-Speed
PLL Tolerance
C1 0.01 µF 470 pF 470 pF 330 pF ±10%
C2 0.001 µF 22 pF 33 pF 15 pF ±10%
R4.7 KΩ4.7 KΩ4.7 KΩ4.7 KΩ±10%
Table 29. Analog VCC (VCCA) Specification
Parameter Min Typ Max Unit
Peak-to-peak noise on VCCA 75 mV
Cur rent consumptio n in High-Speed mode 2 mA
Current consumption in Low-Spe ed mode 2 mA
Current consumption in Standby mode 2 mA
Current consumption in Suspend mode ( PLLs off) 11
Notes:
1. 2 mA if PLLs are enabled.
µA
Table 30. 32.768-kHz Crystal Characteristics
Parameter Min Typ Max Unit
Nominal frequency 32.768 kHz
Load capac ita nce 13.5 15 16.5 pF
Q value 50 103
Series resistance 60 KΩ
Insulati on resistanc e 100 MΩ
Shunt capacitance 2.5 pF
Table 31. Start-Up Time Specifications PLLs
Symbol Parameter Min Typ Max Unit
t1 Inte rme di ate PLL loc k 10 ms
t2 Low-Speed PLL lock 100 µs
t3 High-Speed PLL lock 100 µs
t4 Graphics Dot Clock P LL lock 100 µs
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 85
Figure 13. PLL Enabling Ti ming Sequence
Ta ble 32. PLL Jitter Specification
PLL Min Typ Max Unit
Intermediate PLL frequency 1.4524 1.47456 1.4967 MHz
Intermediate PLL cycle-to-cycle jitter 20.4 ns
Low-Speed PLL frequency 36.311 36.864 37.417 MHz
Low-Speed PLL cycle-to-cycle jitter 0.82 ns
Graphics Dot Clock PLL frequency –1.5% Target +1.5% MHz
Graphics Dot Cl ock PLL cycle-to-cycle jitter 1 ns
High-Speed PLL frequency 65.360 66.3552 67.351 MHz
High-Speed P LL c y cle-to-cycle ji tter 0.5 ns
t4
RESET
Intermediate PLL
Low-Speed PLL
High-Speed PLL
PLLRATIO[2:0]
Graphics Dot Clock
(Wakeup)
Lock
t1
Lock
t2
Lock
t3
PLL Lock
86 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . .–65°C to +125°C
Ambient Temperature Under Bias . . –65°C to +110°C
Supply Voltage VCC with Respect
to GND. . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Voltage on 5-V-Tolerant Pins . .–0.5 V to (VCC+2.6 V)
Voltage on Other Pins . . . . . . .–0.5 V to (VCC+0.5 V)
Stresses above those listed may cause permanent device
failure. Functionality at or above these limits is not implied.
Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temper a tur e (TA)
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage (VCC) . . . . . . . . . . . . +3.0 V to +3.6 V
CPU Voltage (VCC_CP U) (33 & 66 MHz) +2 .7 V to +3. 6 V
CPU Voltage (VCC_CPU) (100 MHz) +3.3 V to +3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AN D INDUSTRIAL OPERATING RANGES
(BALL GRID ARRAY (BGA), 33 MHZ, 3.3 V)1
Notes:
1. V
CCIO
= 3.0 V–3.6 V. For 33 and 66 MHz, T
CASE
= 0
°
C to +95
°
C (commercial). T
CASE
= –40
°
C to +95
°
C (industrial).
For 100 MHz, T
CASE
= 0
°
C to +85
°
C (commercial). Current out of a pin is given as a negative value.
Symbol Parameter Description Min Typ Max Unit
fOSC Frequency of Operation (internal CPU clock) 0 100 MHz
PCC Supply Power—CPU clock = 33 MHz (VCC_CPU=3.3 V) 703 879 mW
PCCSS2
2. In Suspend and Critica l Suspend, the power state is the same . The PLLs are off, the LCD is dis abled, and the CPU and all log ic
are in the lowest power state. The power management unit is active.
Suspend Power at 3.3 V and 25°C—CPU idle, all internal
clocks stopped except 32.768 kHz 264
(80 µA) 643.5
(195 µA) µW
Suspend Power at 3.3 V and 70°C—CPU idle, all internal
clocks stopped except 32.768 kHz 726
(220 µA) 1950.5
(585 µA) µW
POFF R T C Power Only at 3.3 V 16 33 µW
VOH(CMOS) Output High Voltage IOH(CMOS) = –0.5 mA VCC–0.45 V
VOL(CMOS) Output Low Voltage IOL(CMOS) = +0.5 mA 0.45 V
VIH(CMOS) Input High Voltage 2.03
3. V
CC
at 3.3 V.
VCC+0.3 V
VIH(5-VTOL) Input High Voltage (5-V tolerant inputs) 2.03VCC+2.5 V
VIL(CMOS) Input Low Voltage –0.3 +0.8 V
ILI Input Leakage Current (0.1 V ≤ VOUT ≤ VCC)
(All pins except those with internal pullup/pulldown resistors) ±10 µA
IIH Input Leakage Current (VIH = VCC – 0.1 V)
(All pins with internal pulldown resistors) 60 µA
IIL Input Leakage Current (VIL = 0.1 V)
(Pins with interna l pull up res istors ) –60 µA
ILO Output Leakage Current (0.1 V ≤ VOUT ≤ VCC)
(All pins except those with internal pullup/pulldown resistors) ±15 µA
AVCCRP–P Analog VCC ripple peak to peak 100 mV
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 87
CAPACITANCE
Notes:
These para meters are not 10 0% tested, but are evaluated at in itial charac terizatio n and at any time the design is mo dified whe re
capacitance may be affected.
Table 33. Operating Voltage (Commercial and Industrial)
Power Pin Type 33 MHz 66 MHz 100 MH z
Min Max Min Max Min Max
Analog 2.7 3.6 2.7 3.6 2.7 3.6
CPU 2.7 3.6 2.7 3.6 3.3 3.6
RTC 2.7 3.6 2.7 3.6 2.7 3.6
VCC 2.7 3.6 2.7 3.6 2.7 3.6
Symbol Parameter Descriptions Test Conditions Min Max Unit
CIN Input Capacitance FC = 1 MHz 15 pF
Clock Capacit ance 15 pF
COUT Output Capacitance 20 pF
CI/O I/O Pin Capacitance 20 pF
88 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
TYPICAL POWER NUMBERS
Power Requirements Under Different Power Management Modes
Table 34 shows the maximum and typical power dissipation for the ÉlanSC400 and ÉlanSC410 microcontrollers.
Table 34. Power Estimates
Power Management Mode (CPU Clock Speed)
Hyper-Speed1
(100 MHz)
Notes:
1. Hyper -Speed mode is defined with a CPU clock frequency of 66 or 100 MHz. There is a time penalty to enga ge and disengage
Hyper-Speed mode, because a CPU Stop Clock/Stop Grant sequence is required to “arbitrate” the internal CPU PLL start-
up, cac he flus h, and th e clea ring of al l intern al pip elines and w rite buf fers. The DX2 m ode (66 M Hz) is a clock- doubl ed mod e
with th e CPU o peratin g at 66 MHz and th e rest o f the s ystem logi c opera ting a t 33 MH z. Th e DX4 mode (100 MHz ) is a cl ock
tripled mode with the CPU running at 100 MHz and the rest of the system running at 33 MHz.
Hyper-Speed1
(66 MHz) High-Speed2
(33 MHz)
2. High-Speed mode is defined with a maximum CPU clock speed of 33 MHz with a 1x dynamic clock-speed change control
capabi lity. Dynamic clock contro l all ows fast, unarbit rated CP U clo ck-sp eed c hange s. Table 34 assum es a CPU fre quenc y of
33 MHz and tha t th e internal LCD c on troller is enabled. Other H igh -Spee d m od e p ow er es tim ate s w i th C PU V
CC
= 3.3 V are
shown below:
CPU Clock = 33 MHz/2 = 16.5 MHz, Max = 601 mW, Typical = 480 mW
CPU Clock = 33 MHz/4 = 8.25 MHz, Max = 370 mW, Ty pical = 296 mW
Low-Speed3
(~4 MHz)
3. Low-Sp eed mode limi ts the maximum CPU cloc k frequency to 8 MH z. T a ble 34 assumes 8 M Hz/2 = ~4.1 25 (CPU speed) an d
that the Internal LCD controller is enabled. Other Low-Speed power estimates with CPU at 3.3 V are shown below:
8 MHz/1 = 8.25 MHz, Max = 370 mW, Typical = 296 mW
8 MHz/4 = 2.06 MHz, Max = 164 mW, Typical = 132 mW
Standby4
(0 MHz)
4. Standby mode is defin ed as having the CPU idle and stoppe d (0 MHz), but vide o screen refresh con tinues. IRQ0 (DOS T imer
IRQ source) is assumed to be programmed as an activity and is generated at a rate of 60 Hz. This causes the PMU to tran-
sition to the Temporary Low-Speed mode where the CPU is clocked at 8 MHz. The assumed duration of the IRQ0 handler
routine is 25
µ
s and, upon the interrupt return instruction, the PMU immediately re-enters the Standby mode, the LCD con-
troller is enabled, and DRAM refresh type is slow CAS-before-RAS.
Off5
5. Off is de fine d as th e V
CC
_RTC supply pin having power applied and all other V
CC
pins are no t powe red. In this mode, the
core CP U, p ow er ma na gem en t un it, PLL s, etc . h av e n o pow e r ap pli ed . The RTC wi ll have an in terna ll y iso la ted power plane
and source its power fr om the V
CC
_RTC supply pin.
Maximum at 3.3 V 2194 mW
(~665 mA) 1527 mW
(~463 mA) 879 mW
(~266 mA) 240 mW
(~73 mA) 63 mW
(~19 mA) 33 µW
(10 µA)
Typical at 3.3 V 1818 mW
(551 mA) 1222 mW
(~370 mA) 703 mW
(~213 mA) 192 mW
(~58 mA) 50 mW
(~15 mA) 16 µW
(4.8 µA)
Maximum at 2.7 V N/A 941 mW 586 mW 144 mW 60 mW 33 µW
Typical at 2.7 V N/A 753 mW 469 mW 115 mW 48 mW 16 µW
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 89
DERATING CURVES
This secti on des cribes how to use t he derati ng cu rves
on the following pages to determine potential specified
timing variations based on system capacitive loading.
The Pin State Tables beginning on page 42 in this doc-
ument have a column named “Max Load.” This column
describe s the specification load presented to the spe-
cific pin when testing was performed to generate the
timing specification documented in the AC Characteris-
tics section of this data sheet.
For example, to find out the effect of capacitive loading
on a DRAM specification such as MWE hold from CAS
Low, first find the specification load for MWE from
Table 7 on page 44. The va lue here i s 70 pF. Note th e
output drive type is programmable to C, D, or E. For
this exam ple, assum e a drive strength o f D, a system
DRAM interface of 3.3 V, and a system load on the mi-
crocontroller’s MWE pin of 90 pF.
Referring to Figure 20, 3.3-V I/O Drive Type D Rise
T ime, on page 90, a time value of approximately 8.1 ns
corresponds to a capacitive load of 70 pF.
Also referring to Figure 20, a time value of approxi-
mately 10 ns corresponds to a capacitive load of 90 pF.
Subtrac ting 8.1 ns fro m the 10 ns, it can be seen tha t
the rise time on the MWE signal will increase by 1.9 ns.
Therefore, th e M WE hol d f rom CA S Low (min) param-
eter will increase from 30 ns to 31.9 ns (30 ns +1.9 ns).
If the capacitive load on MWE had been less than 70
pF, the time given in the derating curve for the load
would be s ubtracte d from the time given for the sp eci-
fication load. This difference can then be subtracted
from the M WE hold from CAS Low (min) paramete r to
determine the derated AC timing parameter.
Figure 15. 3.3-V I/O Drive Type A Fall TimeFigure 14. 3.3-V I/O Drive Type A Rise Time
10
20
30
40
50
60
70
80
90
100
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
10
20
30
40
50
60
70
80
90
100
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
Figure 17. 3.3-V I/O Drive Type B Fall TimeFigure 16. 3.3-V I/O Drive Type B Rise Time
5
10
15
20
25
30
35
40
45
50
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
5
10
15
20
25
30
35
40
45
50
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
90 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 19. 3.3-V I/O Drive Type C Fall TimeFigure 18. 3.3-V I/O Drive Type C Rise Time
5
30
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
5
10
15
20
25
30
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
10
15
20
25
Figure 21. 3.3-V I/O Drive Type D Fall TimeFigure 20. 3.3-V I/O Drive Type D Rise Time
2
4
6
8
10
12
14
16
18
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
2
18
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
4
6
8
10
12
14
16
Figure 23. 3.3-V I/O Drive Type E Fall TimeFigure 22. 3.3-V I/O Drive Type E Rise Time
2
3
4
5
6
7
8
9
10
11
12
13
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
2
3
4
5
6
7
8
9
10
11
12
13
20 40 60 80 100 120 140 160
Time (ns)
Load (pF)
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 91
AC SWITCHING CHARACTERISTICS AND WAVEFORMS
The AC sp ecifications provided in the AC charac teris-
tics tables that follow consist of output delays, input
setup requirements, and input hold requirements.
AC specifications measurement is defined by the
figures that follow each timing table. All timings are
referenced to 1.5 V unless otherwise specified.
Output delays are specified with minimum and maxi-
mum limits, measured as shown. The minimum delay
times are hold times provided to external circuitry.
Input setup and hold times are specified as minimums,
defining the smallest acceptable sampling window.
Within th e sampling wi ndow, a sy nchronous inpu t sig-
nal must be stable for correct microcontroller operation.
Key to Switching Waveforms
AC SWITCHING TEST WAVEFORMS
Notes:
For AC testing, inputs are driven at 3 V for a logic 1 and 0 V for a logic 0.
WAVEFORMS INPUTS OUTPUTS
Must be Steady Will be Steady
May Change from H to L Will be Changing from H to L
May Change from L to H Will be Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High-Impedance "Off” State
VCC ÷ 2
VCC ÷ 2
VIH = VCC
Input
VIL = 0
Test Points
Output
92 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AC Switching Characteristics over Commercial and Industrial Operating Ranges
Figure 24. Power-Up Timing Sequence
Table 35. Power-On Reset Cycle
Symbol Parameter Description Notes 33-MHz External Bus Unit
Min Typ Max
t1 VCC_RTC valid hold before all other VCCs are valid 0 s
t2 RESET valid hold from all VCC valid (except VCC_RTC) 1
Notes:
1. This parameter is dependent on the 32-kHz oscillator start-up time, which is dependent on the characteristics of the crystal,
leakage and capacitive coupling on the board, and ambient temperature.
0.5 s
t3 VCC_RTC valid to BBATSEN active 100 µs
t4 CFGx setup to RESET inactive 5 µs
t5 CFGx hold from RESET inactive 0 ns
t6 RSTDRV pulse width 300 ms
VCC_RTC
t1
All VCCs
RESET
t2
BBATSEN
t3
RSTDRV
t6
CFGx
t4 t5
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 93
Table 36. ROM/Flash Memory Cycles
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
t1 SA3–SA0 delay from SA31–SA4 6 ns
t2a SA stable to ROMCSx assertion 16ns
t2b SA stable to ROMCSx assertion
when qualified with command (ROMRD or ROMWR)
120 ns
t2c SA stable to ROMCSx assertion
when qualified with command (ROMRD or ROMWR)
1100 ns
t3 ROMCSx deassertion to SA change 153 ns
t4 SD setup to ROMRD or ROMCSx deassertion or burst address
switching, whichever is first, for 8-/16-/32-bit device
215 ns
t5 ROMWR setup to ROMCSx 0ns
t6 Data hold from SA, ROMRD, or ROMCSx change, whichever is fir st 20ns
t7 ROMCSx pulse width 325 ns
t8 DBUFOE, R32BFOE setup to ROMRD, ROMWR Low -8 ns
t9 ROMRD pulse width 325 ns
t10 SA3–SA0 burst address valid duration 325 ns
t11 ROMWR pul se widt h 325 ns
t12 SD setup to ROMWR asse rtio n for 32-bit device 217 ns
t13 SD hold from ROMWR deassertion 220 ns
t14 SA hold from ROMWR deassertion 220 ns
t15 ROMRD delay from SA stable 115 ns
t16a ROMRD, ROMWR pulse width for 8-bit device 530 ns
t16b ROMRD, ROMWR pulse width for 16-bit device 240 ns
t17a Data setup from ROMRD for 8-bit device 2, 4 489 ns
t17b Data setup from ROMRD for 16-b it device 2, 4 209 ns
t18 ROMRD deassertion to SA unstable 20 ns
t19 Data hold from ROMRD deassertion 20ns
t20 SA hold from ROMWR deassertion 53 ns
t21a SD setup to ROMWR assertion for 16-bit device 2-29 ns
t21b SD setup to ROMWR asse rtion for 8-b it device 233 ns
t22 SD hold from ROMWR deassertion 226 ns
t23 IOCHRDY assertion to ROMRD, ROMWR deassertion 125 ns
t24a IOCHRDY deassertion from ROMRD, ROMWR for 8-bit 378 ns
t24b IOCHRDY deassertion from ROMRD, ROMWR for 16-bit 66 ns
t25 R32BFOE/DBUFOE hold from ROMRD High 0 ns
t26 R32BFOE/DBUFOE hold from ROMWR High 26 ns
t27 DBUFRDL, DBUFRDH setup to ROMRD, ROMWR Low -8 ns
t28 DBUFRDL, DBUFRDH hold from ROMRD High 0 ns
t29 DBUFRDL, DBUFRDH hold from ROMWR high 26 ns
94 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Notes:
1. T he RO MCSx address decode is programmable for an early decode (via bit 5 in CSC index 23h, 25h, and 27h). The early
address-decode is available to provide the ROMCSx by qualifying the address signals only; it is not qualified with the com-
mands (ROMRD, ROMWR). The timing pa ramete r t2a p ertains to the ea rly ad dress -decod e featu re bein g enable d (ROM CSx
is add res s-d eco de on ly ). Pa ram eter s t 2b and t2 c are ob serv ed w he n the ea rly addres s-decode fe atu re i s dis ab led (R OM CS x
is address-decode qualified with command). The early decode can be enabled for both Fast-mode and Normal-mode ROM
accesses.
2. When a x32 DRA M or VL b us is enab led , addit ional d elay m ust be added to acco mmod ate for the delay through the ext ernal
data buffers required for the SD bus in this mode.
3. There are two types of programmable wait states. The first programmable wait state is always used in the first access for
either burst or non-burst supported device. It starts at the assertion of the chip select or at the transition of SA3–SA0, which-
ever oc cu rs l ate r. The sec ond pro gram mabl e w a it s tat e is u se d on ly for any s ub seq uen t b urs t rea d a cc esse s t o a burs t m od e
ROM device. It starts at the transition of SA3–SA0. The burst address valid duration depends on which wait state is used. If
the wait state is set to zero, then the minimum address duration is 30 ns (one bus clock cycle).
4. If wait states are added via the deassertion of IOCHRDY, the data setup time to IOCHRDY assertion is 0 ns (minimum).
Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle
t4 t6
t7t7
t9
t27 t8 t9 t25
t28
t2b
t6
t1 t1
SA25–SA4
SA3–SA0
ROMCSx
ROMWR
ROMRD
SD15–SD0
DBUFOE
DBUFRDL
D15–D0
(x32 ROM)
DBUFRDH
R32BFOE
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 95
Figure 26. Fast Mode CPU Read of Three Consecutive Bytes from 8-Bit ROM/Flash Memory
Figure 27. Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles
t4 t10
t6 t10
t2b
3 * t93 * t9
t1 t1
t2a
012
SA25–SA4
SA3–SA0
ROMCSx
ROMWR
ROMRD
SD7–SD0
N
otes:
T
he ROM controller fetches the number of bytes requested by the CPU as dictated by the CPU BE (Byte Enable) signals and
r
eturns the data as a single transfer. In this example, BE was set to “0001”. Therefore, the ROM controller generates additional
a
ddresses to read all three bytes before returning them to the CPU.
t5
t11
t8
t27 t11 t13
t26
t29
t2b t14
t12
t2a
SA25–SA0
ROMCSx
ROMWR
ROMRD
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
D15–D0
(x32 ROM)
R32BFOE
96 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 28. Fast Mode 16-Bit Burst ROM Read Cycles
Figure 29. Fast Mode CPU Burst Read from 32-Bit Burst Mode ROM/Flash Memory
t10t10 t4 t6
8 * t78 * t7
8 x t98 x t9
t2b
t1 t1
t2a
SA25–SA4
SA3–SA1
ROMCSx
ROMWR
ROMRD
SD15–SD0
t4 t6
4 * t74 * t7
4 * t94 * t9
t2b
t10t10
t8
t27
t25
t28
t1 t1
t2a
SA25–SA4
SA3–SA2
ROMCSx
ROMWR
ROMRD
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
R32BFOE
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 97
Figure 30. Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles
Figure 31. Normal Mode 8-/16-Bit Flash Memory Write Cycles
t15 t18
t23
t16a,b
t17a,b
t24a,bt27
t8 t16a,b t28
t25
t2c t3
t19
t1 t1
t2a
SA25–SA4
SA3–SA0
ROMCSx
ROMRD
ROMWR
SD15–SD0
DBUFOE
IOCHRDY
DBUFRDL
DBUFRDH
R32BFOE
t16a,b
t21a,b t16a,b t22
t23
t20
t8
t27
t24a,b t26
t29
t1 t1
t2a
SA25–SA4
SA3–SA0
ROMCSx
ROMWR
ROMRD
SD15–SD0
DBUFOE
DBUFRDL
IOCHRDY
DBUFRDH
R32BFOE
98 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 37. DRAM Cycles
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
t1 Row address setu p time 15ns
t2 RAS to CAS delay 142.75 ns
t3 Row address hold time 114.25 ns
t4 Column address s etup time 10ns
t5 Column address hold time 114.25 ns
t6a CAS pulse width (CPU, Fast Page mode) 142.75 ns
t6a CAS pulse width (graphics controller, Fast Page mode) 128.5 ns
t6b CAS pulse width (EDO mode) 128.5 ns
t7a CAS precharge (non-interleaved) 114.25 ns
t7b CAS precharge (interleaved) 171.25 ns
t8a CAS hold 185.5 ns
t8b CAS hold (EDO) 166.5 ns
t9a Fast page mode cycle time (non-interleaved) 157 ns
t9b Fast page mode cycle time (interleaved) 1114 ns
t9c EDO mode cycle time 157 ns
t10 Access time from RAS 166.5 ns
t11 Acces s time f rom colum n add res s 135 ns
t12a Access time from CAS 120 ns
t12b Access time from CAS (EDO) 122 ns
t13 Access time from CAS precharge 140 ns
t14a Read data hold from CAS 10ns
t14b Read data hold from CAS (EDO) 15ns
t15 MA12–MA0 switching time 115 ns
t16 Delay betwe en ban k CAS si gna ls 115 ns
t17 MWE setup to CAS 110 ns
t18 MWE hold from CAS 130 ns
t19 Write data setup to CAS 110 ns
t20 Write data hold from CAS 130 ns
t21 RAS precharge 160 ns
t22 RAS pulse width 175 ns
t23 RAS hold 128.5 ns
t24 MWE low from CAS (EDO data disable) 114.25 ns
t25 MWE pulse width (EDO) 114.25 ns
t26 Data high impedance from MWE 115 ns
t27 RAS to CAS precharge time 115 ns
t28 CAS setup time (CAS-before-RAS refresh) 110 ns
t29 CAS hold time (CAS-before-RAS refresh) 125 ns
t30 RAS pulse width during self-refresh cycle 1100 us
t31 RAS precharge time during self-refresh cycle 1130 ns
t32 WE setup time (CAS-before-RAS refresh) 125 ns
t33 WE hold time (CAS-before-RAS refresh) 125 ns
Notes:
1. All timings assume 70-ns DRAMs, fastest progra mmable timing , and a 66-MHz clock for th e memory controller.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 99
Figure 32. DRAM Page Hit Read, Interleaved
Figure 33. DRAM Page Hit Write, Interleaved
t1
t4
t2 t6a
t8a t7b t16 t6a
t9b
t16
t4 t6a
t3 t15 t5 t15
t10 t11
t12a
t14a t12a t11
RAS
CASL3–CASL0
MA12–MA0
MWE
D31–D0
CASH3–CASH0
t4
t17
t19
t1
t2
t6a
t8a
t7b t6a
t9b
t16 t6a t7b t9b t6a
t3 t15 t5 t15
t18
t20 t20
RAS
CASL3–
CASH3–
MA12–MA0
MWE
D31–D0
CASL0
CASH0
100 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 34. DRAM Page Miss Read, Interleaved
Figure 35. DRAM Page Hit Read, Non-Interleaved
t1
t4
t21 t22 t23
t2 t6a
t8a
t16 t6a
t3 t5
t10 t11
t12a
t14a t12a
RAS
CASL3–CASL0
CASH3–CASH0
MA12–MA0
MWE
D31–D0
t15
t1
t4
t2 t6a
t8a
t7a
t4
t6a
t9a
t3 t15 t5 t15
t10 t11
t12a t12a
t13 t14a
RAS
CASH3–CASH0
MA12–MA0
MWE
D31–D0
CASL3–CASL0
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 101
Figure 36. DRAM Page Hit Write, Non-Interleaved
Figure 37. DRAM Page Miss Read, Non-Interleaved
t1
t4
t17
t19
t2
t6a
t8a
t7a t6a
t9a
t3t15 t15 t5
t18
t20
RAS
MA12–MA0
MWE
D31–D0
CASH3–CASH0
CASL3–CASL0
t1
t4
t21 t22 t23
t2 t6a
t8a
t7a t6a
t9a
t3 t5 t15
t10 t11
t12a t14a t12a
t13
RAS
MA12–MA0
MWE
D31–D0
CASH3–CASH0
CASL3–CASL0
t15
102 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 38. EDO DRAM Page Hit Read, Non-Interleaved
Figure 39. EDO DRAM Page Miss Read, Non-Interleaved
t1
t4
t2 t6b
t8b t7at6b
t9c
t3 t15 t5 t15
t24 t25
t10 t11
t12b t12b
t13 t14b t11 t26
RAS
MA12–MA0
MWE
D31–D0
CASH3–CASH0
CASL3–CASL0
Notes:
The EDO D RAM page hit wr ite timing is similar to DRAM page hit wr ite timing. See Figure 36 on page 101 for more inf ormation.
t1
t4
t21 t22
t2 t6b
t8b
t3 t5
t24 t25
t10 t11
t12b
t26
RAS
MA12–MA0
MWE
D31–D0
CASH3–CASH0
CASL3–CASL0
Notes:
The EDO DRAM page miss write timing is similar to DRAM page miss write timing. See Figure 36 on page 101 for more
information.
t15
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 103
Figure 40. DRAM CAS-Before-RAS Refresh
Figure 41. DRAM Self-Refresh
t7a
t28
t28
t27
t27
t27
t27
t29t29
t29
t29
t7a
t27
t27
t27
t27
t32
t22t32 t33
t32 t33
t22
t22t32 t33
clk_mem
RAS0
RAS1
RAS2
RAS3
MWE
CASH3–CASH0
CASL3–CASL0
t28
t28
t22 t33
t7a
t28
t27 7a t27
t30t21 t31
RAS
MWE
SS
SS
CASH3–CASH0
CASL3–CASL0
Notes:
Beca us e t he sequenc e s how n ab ov e i s performed w hen th e m ic roc ontroller is in Sus pen d mode, the D RAMs m us t s el f-refr esh.
The RAS and CAS signals are held active (Low) for the entire time that the microcontroller is in Suspend mode. The timing
diagram also shows a following cycle that brings RAS and CAS High again. The Low pe riod of RAS and CAS can be of a long
duration.
104 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 42. DRAM Slow Refresh
t28
t27
t7a t29
t22t32 t33
t22 t33
t22 t33
t22 t33
RAS0
RAS1
RAS2
RAS3
MWE
CASH3–CASH0
CASL3–CASL0
Notes:
The diagram above shows RAS and CAS behavior for an ÉlanSC400 or ÉlanSC410 microcontroller running at a frequency of
16 MHz or les s. In this ca se, the RAS si gnals are not staggered and all are drive n (Low) at the s ame time to co nsume less DRAM
bandwidth for refresh activity (consumed due to a slower clock frequency).
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 105
Table 38. ISA Cycles
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
t1a Setup, SA, SBHE stable to command assertion, 16-bit I/O,
8-bit I/O, Mem 120 ns
t1b Setup, SA, SBHE stable to command assertion, 16-bit Mem 120 ns
t2a Delay, MCS16 stable from SA 102 ns
t2b Delay, IOCS16 stable from SA 122 ns
t3a Pulse width, IOW, 8-bit cycle 530 ns
t3b Pulse width, MEMW, 8-bit cycle 530 ns
t3c Pulse width, IOR, 8-bit cycle 530 ns
t3d Pulse width, MEMR, 8-bit cycle 530 ns
t3e Pulse width, IOW, 16-bit cycle 165 ns
t3f Pulse width, MEMW, 16-bit cycle 240 ns
t3g Pulse width, IOR, 16-bit cycl e 165 ns
t3h Pulse width, MEMR, 16-bit cycle 240 ns
t4 SA, SBHE hold from command deassertion 53 ns
t5a IOCHRDY delay from IOR, MEMR, IOW, MEMW (8-bit) 378 ns
t5b IOCHRDY delay from IOR, MEMR, IOW, MEMW (16-bit) 66 ns
t6 IOR, MEMR, IOW, MEMW delay from IOCHRDY 125 ns
t7a IOR, MEMR, IOW, MEMW high time (8-bit) 187 ns
t7b IOR, MEMR, IOW, MEMW high time (16-bit) 125 ns
t8 Delay, BALE rising from IOR, MEMR, IOW, MEMW deassertion 46 ns
t9 IOCHRDY pulse width 120 ns 1 5 .6 µs
t11a Setup, SD to write command assertion, 8-bit memory, I/O write and
16-bit I/O wr ite 33 ns
t11b Setup, SD to write command assertion, 16-bit memory write -29 ns
t12 Hold, SD from write command deassertion 30 ns
t13a Data access time, 8-bit read 489 ns
t13b Data access time, 16-bit I/O read 132 ns
t13c Data access time, 16-bit memory read 209 ns
t14 Hold, SD from read command deassertion 0 ns
t15 Setup, SA, SBHE stable to BALE falling edge 61 ns
t16 Pulse width, BALE 60 ns
t17 Setup, AEN high to IOR/IOW asse rtion 145 ns
t19 Setup, SA, SBHE stable to command assertion 102 ns
t20 Hold, DRQ from DACK assertion 0 ns
t21 Setup , DACK as sertion to I/O command asse rtion 145 ns
t22a Setu p, IOR assertion to MEMW command 235 ns
t22b Setu p, M EM R command assertion to IOW command 0 ns
t23 Delay, IOCHRDY assertion to command high 200 ns
t24 Delay, memory command to IOCHRDY deassertion 125 ns
t25 Hold, command off to DACK off 60 ns
t26 Hold, read command off from write command off 50 ns
t27 Hold, AEN from command off 60 ns
106 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
t29 Hold, SA, SBHE from read command 53 ns
t30 Setup, TC to read command deassertion 470 ns
t31 Hold, TC from read command deassertion 60 ns
t32a Pulse width, I/O write command 400 ns
t32b Pulse width, I/O read command 700 ns
t33a Pulse width, memory read command 800 ns
t33b Pulse width, memory write command 470 ns
t34 Delay, MEMR to valid data 272 ns
t35 Hold, SD from MEMR deassertion 11 ns
t36 Delay, IOR to valid data 241 ns
t37 Hold, SD from IOR deasserti on 11 ns
t38 Setup, SD to MEMW assertion -21 ns
t39 Setup, SD to IOW ass ertion -214 ns
t41 Setup, DBUFRDL/DBUFRDH to write command Low 145 ns
t42 Hold, DBUFRDL/DBUFRDH from write command High 130 ns
t43 Setup, DBUFRDL/DBUFRDH to read command Low 10ns
t44 Hold, DBUFRDL/DBUFRDH from read command High 110 ns
t45 Setup, DBUFOE Low to write command Low 145 ns
t46 Hold, DBUFOE from write co mmand High 130 ns
t47 Setup, DBUFOE Low to read command Low 10ns
t48 Hold, DBUFOE from read command High 110 ns
t49 Setup, DBUFRDL/DBUFRDH to mem read command Low, DMA 10ns
t50 Hold, DBUFRDL/DBUFRDH from mem read command High, DMA 110 ns
t51 Setup, DBUFOE Low to mem read command Low, DMA 10ns
t52 Hold, DBUFOE from mem read command High, DMA 110 ns
t53 Setup, DBUFRDL/DBUFRDH to I/O read command Low, DMA 10ns
t54 Setup, DBUFOE Low to I/O read command Low, DMA 10ns
t55 Hold, DBUFOE from I/O read command High, DMA 110 ns
t56 Hold, DBUFRDL/DBUFRDH from I/O read command High, DMA 110 ns
Notes:
1. These parameters are applicable only when an external data transceiver is used to isolate the SD bus.
Table 38. ISA Cycles (Continued)
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 107
Figure 43. 8-Bit ISA Bus Cycles
t1a t1a t4
t3a,b
t5a
t11a
t41
t45 t4
t6
t5a
t13a
t43
t47
t6 t3c,d
t12
t42
t46
t14
t44
t48
t7a
t9
SA25–SA0, SBHE
IOW/MEMW
IOR/MEMR
IOCHRDY
SD7–SD0
SD7–SD0
DBUFRDL
DBUFOE
(Write)
(Read)
108 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 44. 16-Bit ISA Bus Cycles
t2a,bt1a,b
t15
t2a,b t2a,b
t1a,b
t15
t16t16 t16t16
t3e,f
t5b
t41
t45
t11a,b
t3e,f
t4
t6
t47
t5b
t3g,h
t44
t6
t46
t14
SA25–SA0, SBHE
BALE
IOW/MEMW
IOR/MEMR
IOCS16/MCS16
IOCHRDY
DBUFRDL
DBUFOE
SD15–SD0
SD15–SD0
t9
DBUFRDH
(Write)
(Read)
t4
t42
t43 t48
t7bt13b,c
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 109
Figure 45. ISA DMA Read Cycle
t20
t21 t25
t19 t29
t17 t27
t22b t24
t32a
t39 t26
t49
t51 t30
t23 t31
t35
t50
t52
PDRQx
PDACKx
SA25–SA0, SBHE
AEN
IOW
MEMR
SD15–SD0
IOCHRDY
TC
DBUFRDL
DBUFOE
DBUFRDH
t32a
t34
t33a
110 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 46. ISA DMA Write Cycle
t20
t21 t25
t19 t29
t17 t27
t22a
t24
t38 t26
t36
t30
t23
t31
t37
t56
t55
PDRQx
PDACKx
SA23–SA0, SBHE
AEN
MEMW
IOR
SD15–SD0
IOCHRDY
TC
DBUFRDL
DBUFOE
DBUFRDH
t33b
t53
t54
t32b
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 111
Table 39. VESA Local Bus Cycles
Symbol Parameter Description 33-MHz
External Bus Unit
Min Max
t1 VL_LCLK period 27 ns
t2 VL_L C LK pulse Hi gh 14 ns
t3 VL_L C LK pulse Low 14 ns
t4 VL_ADS delay from VL_LCLK 3 18 ns
t5 SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W /R, VL_D/C delay from
VL_LCLK 318ns
t6 VL_BLAST valid from VL_LCLK 3 18 ns
t7 VL_LDEV valid from SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W/R,
VL_D/C 20 ns
t81
Notes:
1. LDEV is checked on the following rising edge of the CPU clock (not shown, up to 100 MHz) from the assertion of ADS. ADS
can assert a minimum of 20 ns after address change.
VL_LDEV setup to VL_LCLK 15 ns
t9 VL_LRDY, VL_BRDY setup to VL_LCLK 12 ns
t10 VL_LRDY, VL_BRDY (VL-Bus target is driver) hold from VL_LCLK 0 ns
t11 VL_LRDY (VL-Bus target is driver) three stated from VL_LCLK 0 ns
t12 Read data setup to VL_LCLK 5 ns
t13 Read data hold from VL_CLK 0 ns
t14 Write data delay from VL_CLK 3 18 ns
112 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 47. VESA Local Bus Cycles
t2
t3 t9
t12
t8 t9 t12
t4 t4
t5 t5
t7 t7
t13 t13
t14
t10 t10 t11
t10
t6 t6 t6
VL_LCLK
CPUADS1
VL_ADS
S
A25–SA2, VL_BE
VL_LDEV
Read Data
Write Data
VL_LRDY
VL_BRDY
VL_BLAST
Notes:
1. This signal is shown as a timing reference only. It is not available as a pin on the ÉlanSC400 microcontroller.
t11
t1
t14
t14
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 113
Table 40. Parallel Port Cycles1
Notes:
1. The signal names used in Figure 48 and Figure 49 are the PC/AT Compatible and Bidirectional mode signal names.
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
t1 PPDWE delay from IOW 2
2. During EPP mode and Bidirectional mode, PPDWE acts as the parallel port chip select and is asserted for both reads and
writes. For PC/AT Compatible mode, PPDWE will be asserted only for parallel port write cycles.
220ns
t2 PPOEN delay from IOW 220ns
t3 STRB delay from IOW 220ns
t4 SLCTIN, AFDT valid from IOW 3
3. These timings are only valid for EPP mode.
220ns
t5 SD setup to IOW 50 ns
t6 SD hold from IOW 50 ns
t7 BUSY asserted from IOW asserted 4
4. BUSY is asserted to add wait states to the parallel port access.
300 ns
t8 IOW deasserted from BUSY deasserted 4100 ns
t9 IOW pulse widt h 450 ns
t10 SLCTIN, AFDT recovery 1000 ns
t11 DBUFOE setup to IOW 5
5. DBUFOE and DBUFRDL may be required when using the VESA local bus interface or a x32 DRAM interface.
20 ns
t12 DBUFOE hold from IOW 520 ns
t13 PPDWE delay from IOR 2220ns
t14 SLCTIN, AFDT valid from IOR 3220ns
t15 SD setup to IOR deasserted 20 ns
t16 SD hold from IOR 0ns
t17 BUSY asserted from IOR asserted 4300 ns
t18 IOR deasserted from BUSY deasserted 4100 ns
t19 IOR pulse width 450 ns
t20 DBUFOE, DBUFRDL setup to IOR 50ns
t21 DBUFOE, DBUFRDL hold from IOR 510 ns
114 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
.
Figure 48. EPP Parallel Port Write Cycle
t11 t8
t5 t9
t1 t1
t2 t2
t3 t3
t4 t4 t10
t4 t4 t10
t6
t7
t12
Address Register Access
Data Register Access
IOW
PPDWE
PPOEN
STRB
SLCTIN
AFDT
SD7–SD0
BUSY
DBUFOE
DBUFRDL
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 115
Figure 49. EPP Parallel Port Read Cycle
Table 41. General-Purpose Input/Output Cycles
Symbol Parameter Description 33-MHz External Bus Unit
Min Max
t1 SA stable to GPIO_CSx rising edge 10 ns
t2 SA stable to GPIO_CSx falling edge 10 ns
t3 IOW rising edge to GPIO_CSx rising edge 5 ns
t4 IOW falling edge to GPIO_CSx falling edge 5 ns
t5 IOR rising edge to GPIO_CSx rising edge 5 ns
t6 IOR falling edge to GPIO_CSx falling edge 5 ns
t7 SA stable to GPIO_CSx (8042CS) falling edge 10 ns
t8 SA stable to GPIO_CSx (8042CS) rising edge 10 ns
t9 SA stable to GPIO_CSx (MEMCS) falling edge 10 ns
t10 SA stable to GPIO_CSx (MEMCS) rising edge 10 ns
t11 MEMW rising edge to GPIO_CSx rising edge 5 ns
t12 MEMW falling edge to GPIO_CSx falling edge 5 ns
t13 MEMR rising edge to GPIO_CSx rising edge 5 ns
t14 MEMR falling edge to GPIO_CSx falling edge 5 ns
t18
t15
t19
t13 t13
t14 t14 t10
t14 t14 t10
t16
t17
t20 t21
Address Register Access
Data Register Access
IOR
PPDWE
PPOEN
STRB
SLCTIN
AFDT
SD7–SD0
BUSY
DBUFOE
DBUFRDL
116 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 50. I/O Decode (R/W), Address Decode Only
Figure 51. I/O Decode (R/W), Command Qualified
t2 t1 t2 t1
SA25–SA0
GPIO_CSx
IOW
IOR
IOCHRDY
SD7–SD0/SD15–SD0
Notes:
See the ISA bus section on page 105 for detailed timings between these signals.
(Write)
(Read)
D7–D0/D15–D0
t4 t3 t6 t5
SA25–SA0
GPIO_CSx
IOW
IOR
IOCHRDY
Notes:
See the ISA bus section on page 105 for detailed timings between these signals.
SD7–SD0/SD15–SD0
(Write)
(Read)
SD7–SD0/SD15–SD0
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 117
Figure 52. I/O Decode (R/W), GPIO_CSx as 8042CS Timing
Figure 53. Memory CS Decode (R/W), Address Decode Only
t7 t8 t7 t8
SA25–SA0
GPIO_CSx
IOW
IOR
IOCHRDY
60h or 64h 60h or 64h
Notes:
See the ISA bus section on page 105 for detailed timings between these signals.
SD7–SD0
(Read)
SD7–SD0
(Write)
t9 t10 t9 t10
SA25–SA0
GPIO_CSx
MEMW
MEMR
IOCHRDY
Notes:
See the ISA bus section on page 105 for detailed timings between these signals.
SD7–SD0
(Read)
SD7–SD0
(Write)
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 119
Table 42. PC Card Cycles—ÉlanSC400 Microcontroller Only
Symbol Parameter Description Notes 33-MHz External Bus Unit
Min Max
t1 REG_x, SA setup to command active 1,2
Notes:
1. T is the nominal period of the selected clock: in Standard mode, this is the 125-ns ISA bus clock; in Enhanced mode, it is the
30-ns local bus clock.
2. S determines the setup time as programmed into the Setup Timing Register selected from one of four timing sets. Its value
can be programmed to a range of 1 to 4096 • 63.
ST-10 ns
t2 Command pul se width 1, 3
3. C determines the command active time as programmed into the Command Timing Register selected from one of four timing
sets. Its value can be programmed to a range of 1 to 4096 • 63.
CT-10 ns
t3 SA hold and write data valid from command inactive 1, 4
4. R determines the recovery time as programmed into the Recovery Timing Register selected from one of four timing sets. Its
value can be programmed to a range of 1 to 4096 • 63.
RT-10 ns
t4 WAIT_AB Active from command active 1, 3 (C-2)•T-10 ns
t5 Command hold from WAIT_AB inactive 12T ns
t6 SD setup before read command inactive 12T+10 ns
t7 SD valid from read command inactive 0 ns
t8 SD valid from WAIT_AB inactive 1T+10 ns
t9 IOIS16 setup before command inactive 13T+10 ns
t10 MCEH_x delay from IOIS16 active 1T-10 ns
t11 IOIS16 delay from valid SA 35 ns
t12 Setup, DACK assertion to DMA I/O command active 145 ns
t13a Pu lse width, DMA I/O write command 220 ns
t13b Pulse width, DMA I/O read command 700 ns
t14 Hold, DMA I/O command inactive to DACK inactive 60 ns
t15 DMA I/O command setup to TC active 15 ns
t16 TC pulse width 62 ns
t17a SD setup to DMA IOW active -241 ns
t17b SD valid delay from DMA IOR active 100 ns
t18a SD hold from DMA IOW inactive 0 ns
t18b SD hold from DMA IOR inacti ve 0 n s
120 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 55. PC Card Attribute Memory Read Cycle (ÉlanSC400 Microcontroller Only)
Table 43. PC Card Attribute Memory Read Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 OE WE SD15–SD8 SD7–SD0
Byte Access L
LH
HL
LL
HL
LH
HThree-state
Three-state Even byte
Not valid
Word Access L L L Indeterminate L H Not valid Even byte
Odd-Byte-Only Access L L H Indeterminate L H Not valid Three-state
t4 t6 t7
t8
t5
t3
t1 t2
Read Cycle Data
SA25–SA0
REG_A
MCEL_A
MCEH_A
OE
WAIT_AB
SD15–SD8
SD7–SD0
DBUFOE
DBUFRDL
DBUFRDH
REG_B
MCEL_B
MCEH_B
Three-state or Not Valid for Attribute Memory Read Cycles
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 121
Figure 56. PC Card Attribute Memory Write Cycle (ÉlanSC400 Microcontroller Only)
Table 44. PC Card Attribute Memory Write Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 OE WE SD15–SD8 SD7–SD0
Byte Access L
LH
HL
LL
HH
HL
LIndeterminate
Indeterminate Even byte
Indeterminate
Word Access L L L Indeterminate H L Indeterminate Even byte
Odd -B yt e-On ly Acc es s L L H Indeterminate H L Indeterminate Indeterminate
t4 t5
t3
t1 t2
Write Cycle Data
Not Valid for Attribute Memory Write Cycles
SA25–SA0
WE
WAIT_AB
SD15–SD8
SD7–SD0
DBUFOE
DBUFRDL
DBUFRDH
REG_A
MCEL_A
MCEH_A
REG_B
MCEL_B
MCEH_B
122 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 57. PC Card Common Memory Read Cycle (ÉlanSC400 Microcontroller Only)
Table 45. PC Card Common Memory Read Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 OE WE SD15–SD8 SD7–SD0
Byte Access H
HH
HL
LL
HL
LH
HThree-state
Three-state Even byte
Odd byte
Word Access H L L Indeterminate L H Odd byt e Even byt e
Odd-Byte- Onl y Access H L H Indeterminate L H Odd byte T hree -state
t4 t6 t7
t8
t5
t3
t1 t2
Read Cycle Data
SA25–SA0
OE
WAIT_AB
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
REG_A
MCEL_A
MCEH_A
REG_B
MCEL_B
MCEH_B
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 123
Figure 58. PC Card Common Memory Write Cycle (ÉlanSC400 Microcontroller Only)
Table 46. PC Card Common Memory Write Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 OE WE SD15–SD8 SD7–SD0
Byte Access H
HH
HL
LL
HH
HL
LIndeterminate
Indeterminate Even byte
Odd byte
Word Access H L L Indeterminate H L Odd byte Even byte
Odd-Byt e-Only Access H L H Indeterminate H L Odd byte Indeterminate
t4 t5
t3
t1 t2
Write Cycle Data
SA25–SA0
WE
WAIT_AB
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
REG_A
MCEL_A
MCEH_A
REG_B
MCEL_B
MCEH_B
124 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 59. PC Card I/O Read Cycle
Table 47. PC Card I/O Read Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 IOR IOW SD15–SD8 SD7–SD0
Byte Access L
LH
HL
LL
HL
LH
HThree-state
Three-state Even byte
Odd byte
Word Access L L L Indeterminate L H Odd byte Even byte
Hig h B yte O nl y L L H Indeterminate L H Odd byte Three-state
t11
t4 t6 t7
t9
t8
t5
t3
t1
t2
t10
Read Cyc le Data
SA25–SA0
IOR
WAIT_AB
WP_x
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
(IOCS16_x)
MCEH_A
MCEH_B
MCEL_A
MCEL_B
REG_A
REG_B
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 125
Figure 60. PC Card I/O Write Cycle
Table 48. PC Card I/O Write Function (ÉlanSC400 Microcontroller Only)
Mode REG_x MCEH_x MCEL_x SA0 IOR IOW SD15–SD8 SD7–SD0
Byte Access L
LH
HL
LL
HH
HL
LIndeterminate
Indeterminate Even byte
Odd byte
Word Access L L L Indeterminate H L Odd byt e Ev en byte
Odd-Byt e-Only Access L L H Indeterminate H L Odd byte Indeterminate
t11
t4
t9
t5
t3
t1 t2
t10
Write Cycle Data
SA25–SA0
IOW
WAIT_AB
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
WP_x
(IOCS16_x)
REG_A
REG_B
MCEL_A
MCEL_B
MCEH_A
MCEH_B
126 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 61. PC Card DMA Read Cycle (Memory Read to I/O Write)
Table 49. PC Card DMA Read Function (ÉlanSC400 Microcontroller Only)
Mode DACK DREQ MCEH_x MCEL_x OE WE IOR IOW SD15–SD8 SD7–SD0
Byte Access H L H L H TC H L Indeterminate Even byte
Word Access H L L L H TC H L Odd byte Even byte
t14
t12 t13a
t15 t16
t17a t18a
DMA Data to Card
REG_A, REG_B,
MCEL_A, MCEL_B,
OE, IOR
IOW
WE (TC)
SD15–SD0
DBUFOE
DUBFRDH
DBUFRDL
(DACK)
MCEH_A, MCEH_B
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 127
Figure 62. PC Card DMA Write Cycle (I/O Read to Memory Write)
Table 50. PC Card DMA Write Function (ÉlanSC400 Microcontroller Only)
Mode DACK DREQ MCEH_x MCEL_x OE WE IOR IOW SD15–SD8 SD7–SD0
Byte Access H L H L TC H L H Indeterminate Even byte
Word Access H L L L TC H L H Odd byte Even byte
t14
t12 t13b
t15 t16
t17b t18b
DMA Data from Card
WE, IOW
IOR
OE (TC)
SD15–SD0
DBUFOE
DBUFRDL
DBUFRDH
REG_A, REG_B,
(DACK)
MCEL_A, MCEL_B,
MCEH_A, MCEH_B
128 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Figure 63. Graphics Panel Interface Timing (ÉlanSC400 Microcontroller Only)
Table 51. LCD Graphics Controller Cycles—ÉlanSC400 Microcontroller Only
Symbol Parameter Description Notes 33-MHz
External Bus Unit
Min Max
t1a SCK period, monochrome panel 1
Notes:
1. T = period of internal video dot clock—programmable via the Pixel Clock Control Register.
4T ns
t1b SCK period, color STN panel 2T ns
t2 SCK High time 1Tns
t3 SCK Low time 1Tns
t4 Setup, data to SCK falling edge 1T-15 ns
t5 Hold, LCD_data from SCK falling edge 1T-15 ns
t6 Widt h, LC 18T ns
t7 Setup, FRM to LC falling 1,2
2. Programmable to within resolution of 8T intervals (single-screen mode) or 16T intervals (dual-screen mode).
ns
t8 Hold, FRM from LC falling 1,2 ns
t9 Delay, LC falling to M phase change 0 15 ns
t11a Delay, power-on sequencing, LVDD to signals 3
3. Programmable through PMU Control Register 1, bits 2–0.
7.8 62.5 ms
t11b Delay, power-on sequencing, signals to LVEE 4
4. Programmable through PMU Control Register 1, bits 5–3.
7.8 62.5 ms
t12a Delay, power-off sequencing, LVEE to signals, normal power-down 5
5. Programmable through PMU Control Register 2, bits 2–0.
62.5 500 ms
t12b Delay, power-off sequencing, signals to LVDD, normal power-down 6
6. Programmable through PMU Control Register 2, bits 5–3.
62.5 500 ms
t13 Delay, LVEE to LCD_SIGNALS off, emergency power-down 0 ns
t14 Delay, LCD_SIGNALS off to LVDD off, emergency power-down 0 ns
t15 Delay, emergency power-off sequencing from BL2 edge 0 10 µs
t2
t4 t5
t1a,b
t6
t7 t8 t9
t3
SCK
LCDD7–
LC
FRM
M
LCDD0
130 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
THERMAL CHARACTERISTICS
The thermal specifications for the ÉlanSC400 and
ÉlanSC410 microcontrollers are given as a TCASE (the
case temperature) specification. The 33-MHz and
66-MHz devices are specified for operation when
TCASE is with the range of 0°C–+95°C. The 100-MHz
device is specified for operation when TCASE is within
the range of 0°C–+85°C. TCASE can be measured in
any environment to determine whether the microcon-
troller is within specified operating range. The case
temperature should be measured at the center of the
top surface opposite the solder balls.
The ambient temperature (T A) is guaranteed as long as
TCASE is not violated. The ambient temperature can be
calculated from ΨJ-T and θJA from the following
equations:
TJ = TCASE + P • ΨJ-T
TA = TJ – P • θJA
TCASE = TA + P • (θJA – ΨJ-T)
where:
TJ is the junction temperature (°C).
TA is the ambient temperature (°C).
TCASE is the case temper atu re (°C).
ΨJ-T is the junction-to-case thermal resistance (°C/W).
θJA is the junction-to-ambient thermal resistance
(°C/W).
P is the maximum power consumption (W).
The values for θJA and ΨJ-T are given in Table 52 for
the BGA 292 package. These numbers are valid only
for packages with all 292 balls soldered to a board with
two power planes and two signal planes.
Table 53 shows the TA allowable (without exceeding
TCASE) at various airflows and operating frequencies.
P is calculated using the ICC at 3.3 V as tabulated in the
DC Characteristics section beginning on page 86.
Table 52. Thermal Resistance ΨJ-T and θJA (°C/W) for the 292-BGA Package)
Table 53. Maximum T A at Various Airflows in °C
Airflow in Feet/Minute (m/s)
Thermal
Resistance 0
(0) 200
(1.01) 400
(2.03) 600
(3.04) 800
(4.06)
θJA 25.0 20.5 19.0 18.1 17.4
ΨJ-T 6.2 6.2 6.2 6.2 6.2
Airflow in Feet/Minute (m/s)
0 200 400 600 800
Maximum TA(0) (1.01) (2.03) (3.04) (4.06)
at 33 MHz 83.7 86.4 87.3 87.8 88.3
at 66 MHz 72.0 77.5 79.3 80.4 81.3
at 100 MHz 50.8 59.0 61.7 63.4 64.6
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 131
PHYSICAL DIMENSIONS—BGA 292—PLASTIC BALL GRID ARRAY
A1 CORNER
A1 CORNER I.D.
0.50
0.70
0.51
0.61
ENCAPSULATION
4X.20
16-038-BGA292-2_AB
ES114
9.14.98 lv
SIDE VIEW
DETAIL A
SCALE:NONE
0.15 C
SEATING PLANE
TOP SIDE
(DIE SIDE)
A
0.15 C
0.15 C
27.00
BSC
3X
0.50 R.
B
A
27.00 BSC
21.20
22.80
17.00 MIN
0.60
0.90
.30
.10
S
CAB
S
C
(DATUM B)
BOTTOM VIEW
ALL ROWS AND COLUMNS
0.635
BSC
0.635
BSC
1.27 BSC
24.13
BSC
A1 CORNER
A1 CORNER I.D.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 19 18 17 16 15 14 13 12 11 10
987654321
24.13 BSC (DATUM A)
4.445
3X
ALIGNMENT MARK
0.75 SQ 3X
THERMAL BALLS
2.11
2.61
C
132 Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Trademarks
1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo and combinations thereof, Am186, Am188, E86, K86, Élan, Comm86, and Systems in Silicon are trademarks, and Am386
and Am486 are registered trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Microsoft
and Windows are registered trademarks of Microsoft Corp. Other product names used in this publication are for identification purposes and may
be trademarks of their respective companies.
