1 of 17
SPECIAL FEATURES
4096 bits of Read/Write Nonvolat ile
Memory (DS1993)
1024 bits of Read/Write Nonvolat ile
Memory (DS1992)
256-bit S cr atchpad Ensures Integrit y of Dat a
Transfer
M emory Partitioned in to 256 -b it P ages for
Packetizing Dat a
Dat a I ntegr ity Assured with Strict
Read/ Wr ite Protocols
Operating Temperatu r e Range from -40°C to
+70°C
Over 10 years of data ret ent ion
ORDERING INFORMATION
DS1992L-F5+ F5 Micro Can
DS1993L-F5+ F5 Micro Can
+Denotes a lead(Pb)-free/RoHS-compliant product.
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Ad hesive Pad
DS9101 Multipurpose Clip
DS9093RA Mo unting Lock R ing
DS9093F Snap-I n Fob
DS9092 iBu tton Pr obe
F5 MicroCan
COMMON iButton FEATURES
Unique, Factory-Lasered and Tested 64-bit
Registration Number (8-bit Family Code +
48-bit Serial Number + 8-bit CRC Tester)
Assures Absolute Traceability Because No
Two Pa r ts are Alike
Mult idrop Controller for MicroLAN
Digital Identification and Information by
Mome nt ar y Co nt act
Chip-Based Data Carrier Compactly Stores
Information
Data Can be Accessed While Affixed to
Object
Econo mically Commu nic ates to Bus Mast er
with a S ing le Digit a l S ig na l at 16. 3kbps
Standard 16 mm Diamet er and 1-Wire®
Pr otocol Ensure Compati bility with iButton®
Family
Button Sha pe is Self-Aligning with Cup-
Shaped Probes
Durab le Stainless St eel Case Engraved w ith
Reg istr at ion Number Wit h stands Hars h
Environments
E asily Affixe d wit h Self-S tick Adhesive
Back ing, Latched by it s F lange, or Locked
with a Ring Pressed onto its Rim
Presence Detector Acknow ledges Whe n
Reader F irst App lies Vo ltage
Meets U L 913, 5t h Ed., Rev. 1997-02-24;
Intrinsically Safe Appar at us, Approved under
E ntity Conc e pt for us e in Cla s s I, Division 1 ,
Group A, B, C, a nd D Locatio ns
DS1992/DS1993
1Kb/4K b Memory iButton
1-Wire and iB utton are registered trademarks of Maxim Integrate d Product s, Inc.
19-4865; Rev 4/11
DS1992/DS1993
2 of 17
iButton DESCRIPTION
The DS1992/DS1993 memory iButtons (hereafter referred to as DS199x) are rugged read/write data
carriers that act as a localized database, easily accessible with minimal hardware. The nonvolatile
memory and optional timekeeping capability offer a simple solution to storing and retrieving vital
informat ion pertaining to the object to which the iButton is attached. Data is transferred serially t hrough
the 1-Wire protoco l t hat r eq uires onl y a single dat a lead and a ground ret ur n.
The scrat chpad is an add itio nal page t hat act s as a buffer w h e n w riti ng to memory. D a ta is firs t w ritt e n to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad co mmand
transfers the data to memory. This process ensures data integr ity when modifying the memory. A 48-bit
serial number is factory lasered int o each DS199x to provide a guarant eed unique ident it y t hat a llo w s for
abso lut e traceab ility. T he dur able Micro Can packa ge is h ig hly resist ant t o en viro nme nt al hazards suc h as
dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning with mating receptacles,
allowing the DS199x to be easily used by human operators. Accessories permit the DS199x to be
mounted on almost any surface including plastic key fobs, photo-I D badges, and PC boards.
App licat io ns inc lude acces s cont rol, wor k-in-pro gress t rack ing , e lect ro nic trave lers, stor age of ca libr at io n
co nstant s, and debit tokens.
OPERATION
The DS199x have three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, and 3)
1024-bit ( DS1992) or 4096-bit ( DS1993) SRAM. All dat a is read and writ ten least s ignifica nt bit firs t.
The memory functions are not available until the ROM function protocol has been established. This
protocol is described in the ROM functions flow chart (Figure 9). The master must first provide one of
fo ur ROM fu nct ion co mmands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a
ROM function sequence has been successfully executed, the memory functions are accessible and the
mast er can t hen pro vide any o ne o f the four memo r y function commands (Figure 6).
PARASITE POWER
The b lo ck d iagram (F igur e 1) s ho ws the paras it e-po wered circu it r y. This c ir cu it r y st eals po wer wheneve r
t he dat a input is high. T he dat a line pro vide s suffic ie nt power as long as the spec ified timing and volt age
requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
batter y power is no t consumed for 1-Wire ROM function commands, and 2) if the batter y is exhausted for
any reason, the ROM may st ill be read nor mally. The remaining circuit ry of the DS1992 and DS1993 is
sole ly oper ated by bat tery energy.
64-BIT LASERED ROM
Each DS199 x contain a unique ROM code that is 64 bits lo ng. The first 8 bit s are a 1-Wire family code.
The next 48 bit s are a u nique serial number. T he last 8 bits are a CRC o f t he fir st 56 bit s (see Figur e 2).
The 1-Wir e CRC is ge nerated us ing a po lyno mial generato r consist ing o f a shift reg ister and XOR gat es
as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Maxim
1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift
regist er bits are initia lized to zero . T hen st arting w it h t he least sig ni f icant b it of the fa m i ly co de, 1 bit at a
t ime is s hift ed in . Aft er t he 8 t h b it of t he f a m il y c od e ha s be e n ente r ed , t he n t he s eri a l numb e r is e nt e r ed .
After the 48th bit of the serial number has been entered, the shift register contains the CRC value.
Shifting in t he 8 bits o f CRC should return the shift regist er to all zeros.
DS1992/DS1993
3 of 17
Figure 1. DS1992/DS1993 BLOCK DIAGRAM
SRAM
16 PAGES of 25 6-
BITs (1993)
256-BIT
SCRATCHPAD
1-W
ROM
CONTROL
FUNCTION
64-BIT
ROM
LASERED
PARASITE-
CIRCUITRY
POWERED
MEMORY
FUNCTION
CONTROL
1-WIRE
PORT
3V LITHIUM
4 PAGES of 256-
BITs (1992)
Fig ur e 2. 64-BIT LASERED ROM
MSB
LSB
8-Bit CRC Code
48-Bi t Seri al Num ber 8-Bit F amil y Code
(06h)1993
(08h)1992
MSB
LSB
MSB
LSB
MSB
LSB
Fig ur e 3. 1 -Wire CRC CODE
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
Polynomial = X
8
+ X
5
+ X
4
+ 1
1st
STAGE
2nd
STAGE
3rd
STAGE
4th
STAGE
6th
STAGE
5th
STAGE
7th
STAGE
8th
STAGE
INPUT DATA
DS1992/DS1993
4 of 17
Figure 4a. DS1993 MEMORY MAP
PAGE 0
PAGE
PAGE 1
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
SCRATCHPAD
MEMORY
0000h
0020h
0040h
0060h
0080h
00A0h
00C0h
00E0h
0100h
0120h
0140h
0160h
0180h
01A0h
01C0h
01E0h
NO TE: Each page is 32 bytes (256 bit s). The hex values
represent the starting address for each page or register.
Figure 4b. DS1992 MEMORY MAP
PAGE 0
PAGE
PAGE 1
PAGE 2
PAGE 3
SCRATCHPAD
MEMORY
0000h
0020h
0040h
0060h
NO TE: Each page is 32 bytes (256 bit s). The hex values
represent the starting address for each page or register.
DS1992/DS1993
5 of 17
MEMORY
The memo ry map in Figure 4 shows a 32-Byte page ca lled the scrat chpad, and additio nal 32-B yte p ages
called memory. The DS1992 contains pages 0 though 3 that make up the 1024-bit SRAM. The DS1993
contain pages 0 through 15 that make up the 4096-bit SRA M.
The scrat chpad is an add itio nal page t hat act s as a buffer w hen wr iting to memo r y. Dat a is fir st writ t en t o
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad co mmand
t r ansfers the data to memory. T h is pro cess ensur es data int egrity w hen modifying the memory.
MEMORY FUNCTION COMMANDS
The Memo ry Fu nction Flo w Chart ( F igur e 6) describes the pro tocols necess ary for access ing the memory.
An example follows the flow chart. Three address registers are provided as s hown in Figure 5. The first
two registers represent a 16-bit target address (TA1, TA2). The third register is the ending offset/data
status byte (E/S).
The target address points to a unique Byte location in memory. The first 5 bits of the target address
(T4:T0) represent the Byte offset within a page. This Byte offset points to one of 32 possible Byte
locations within a given page. For instance, 00000b points to the first Byte of a page where as 11111b
wo uld point to the last Byt e of a page.
The third register (E/S) is a read only register. The first 5 bits (E4: E0) of this register are called the
ending offset. The ending offset is a Byte offset within a page (1 of 32 Bytes). Bit 5 (PF) is the partial
Byte flag. B it 6 (OF) is the o verflow flag. Bit 7 (AA) is the authoriz ation accepted flag.
Figure 5. ADDRES S REGISTERS
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0
TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8
ENDING ADDRESS WITH
DATA S TATUS (E/S )
(READ ONLY) AA OF PF E4 E3 E2 E1 E0
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user must first provide the 2-Byte target address,
fo llo wed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the
byte offset (T 4:T 0). T he ending o ffset ( E4: E 0) is the B yte offset at which the host sto ps writing data. T he
maximum ending offset is 11111 b (31d). If the host attempt s to writ e data past t his maximum offset, the
overflow flag (OF) is set and the rema in ing dat a is ig no red. If the user writes an inco mp let e Byt e and a n
o verflow has no t o ccur r ed , the partial Byte flag (PF) is set.
Read Scratchpad Command [AAh]
This co mmand can be used to verify scrat chpad da ta and tar get address. A ft er issuing t he read scrat chp ad
command, the user can begin reading. The first two Bytes are the target address. The next Byte is the
ending o ffset/ dat a statu s Byte (E /S) followed by t h e scratchpad dat a beg inning at t he Byt e offset (T4 : T0).
The user can read data unt il the end of the scrat chp ad , after which the dat a r ead is al l logic 1’ s.
DS1992/DS1993
6 of 17
Copy Scratchpad [55h]
This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, t he user must provide a 3-byte authorization pattern. This pattern must exactly match the data
contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA
(Authoriz ation Accept ed) flag is set and the cop y begins. A logic 0 is transmitt ed aft er the dat a has bee n
copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy is in
progress. Cop y t ypicall y t akes 30µs.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset t hro ugh t he ending offset is cop ied to me mor y, start ing at t he target address. Anywhere
from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only
partially written. T he AA flag is cleared only b y executing a write scr atchpad command.
Read Memory [F0h]
The read memor y co mmand can be used to read the ent ire me mor y. After issuing t he co mmand, the user
must pr ovide the 2-Byt e target ad dr ess. After the t wo Bytes, the user read s data beg inning from the t ar get
address and may continue until the end of memory, at which point logic 1’s are read. It is important to
realize that the target address registers contains the address provided. The ending offset/data status Byte
is unaffec ted.
The hardware of the DS199x provides a means to accomplish error-free writ ing t o the memo ry section.
To safeguard read ing dat a in the 1-Wire environment and t o simu lt aneously speed up dat a transfers, it is
recommended to packetize data into data packets of the size of one memory page each. Such a packet
would t ypic ally store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that
eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Application No te 114 for the recommended file str u ctu r e t o be used w ith the 1-Wire envir onment. )
DS1992/DS1993
7 of 17
Fig ur e 6. ME MO R Y FU NCTION S FLOW CH ART
Ma ster TX Memory
Function Command
Y
DS199x sets Scratchpad
Offs et = (T4:T 0) and
Clears (PF, OF, AA)
DS199x sets (E4:E0)
= Scratchpad Offset
DS199x Increments
Scratchpad Offset
Bus Master TX
TA1 (T7:T0)
Bus Master TX
TA2 (T15:T8)
Ma ster TX Data Byte
To Scratchpad Offset
Bus Master
TX Reset
?
N
0FH
Write
?
Scratchpad
N
Bus Master
TX Data
?
Y
N
PF = 1
N
Y
Bus Master
TX Reset
?
To Figure 6
S ec ond Part
Bus Master RX
TA1 (T7:T0)
Bus Master RX
TA2 (T15:T8)
Ma ster RX Ending
Offset with Data
Status (E/S)
DS199x Sets
Scratchpad
Offset=(T4:T0)
Bus Master
TX Reset
?
DS199x Increments
Scratchpad Offset
Y
Ma ster RX Data
Byte From
Scratchpad Offset
N
N
Scratch-
pad Offset =
11 11 1b ?
Y
Y
Scratchpad
AAH
Read
?
Bus Master
RX "1"s
From Figure 6
S ec ond Part
OF = 1
Scratch-
pad Offset =
11 11 1b ?
N
Partial
Byte Wri t ten
?
N
Y
Y
Y
DS199x TX
Pre sence Pulse
(See Figure 9)
DS1992/DS1993
8 of 17
Fig ur e 6. ME MO R Y FU NCTION S FLOW CH ART (continued)
Y
N
Bus Master TX
TA1 (T7:T0)
Bus Master TX
TA2 (T15:T8)
Scratchpad
55H
Copy
?
N
Y
From Figure 6
First Part
Bus Master TX
E/S Byte
DS199x Copies
Scra tchpad Data
T o Mem or y
Authorization
C ode M atch
?
DS199x TX "1"s
DS199x TX "0"s
AA = 1
F0H
R ead M em ory
?
N
To Figure 6
First Part
Y
N
Bus Master
TX Reset
?
Bus Master
TX Reset
?
Y
N
Y
Y
Bus Master TX
TA1 (T7:T0)
Bus Master TX
TA2 (T15:T8)
DS199x s ets M em or y
Address = (T15:T0)
N
Y
N
Ma ster RX Data
B yte From
Memory Address
Bus Master
TX Reset
?
Memory
DS199x
Address Counter
Increments
Bus Master
RX "1"s
Address
= 21Dh ?
DS1992/DS1993
9 of 17
MEMORY FUNCTION EXAMPLES
Example: Write two data Bytes to memory locat io ns 0026h and 0027 h (t he se vent h and eig hth Bytes of
page 1) . Read ent ire memory.
MAS TER MODE
DATA (LSB FIRST)
COMMENTS
TX
Reset
Reset pulse (480µs to 960µs)
RX
Presence
Presence p ulse
TX
CCh
Issu e skip ROM comma nd
TX
0Fh
Issu e w rite scr atchpad command
TX
26h
TA1, beginning o ffset = 6
TX
00h
TA2, address = 0026h
TX
<2 data Bytes>
Writ e 2 B ytes o f data to scratchpad
TX
Reset
Reset pulse
RX
Presence
Presence p ulse
TX
CCh
Issu e skip ROM comma nd
TX
Aah
Issue read scr atchpad command
RX
26h
Read TA1, beg inn ing offset = 6
RX
00h
Read TA2, add r ess = 0026h
RX
07h
Read E/S , ending offset = 7 , flags = 0
RX
<2 data Bytes>
Read scratchpad data and verify
TX
Reset
Reset pulse
RX
Presence
Presence p ulse
TX
CCh
Issu e skip ROM comma nd
TX
55h
Issue co p y scr atchpad command
TX
26h
TA1
TA2 AUT HORI ZATION CODE
E/S
TX
00h
TX
07h
TX
Reset
Reset pulse
RX
Presence
Presence p ulse
TX
CCh
Issu e skip ROM comma nd
TX
F0h
Issue read memory command
TX
00h
TA1, beginning o ffset = 6
TX
00h
TA2, address = 0000h
RX
<128 Bytes (DS1992)>
<512 Bytes (DS1993)>
Read entire memory
TX
Reset
Reset pulse
RX
Presence
Presence p ulse, done
DS1992/DS1993
10 of 17
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS199x is a slave device. The bus master is t ypic ally a microcontroller or PC. Fo r small configurations
the 1-Wire communication signals can be generated under software control using a single port pin. For
multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip
(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor
from responding in r ea l-time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
seque nce, and 1-Wire s ignaling (signal t ypes a nd timing). T he 1-Wire pr o tocol defines bus t r ansactions in
terms o f t he bus st ate during specific t ime slo ts t hat are init iated o n the falling edge o f sync pu ls es from
t he bus mast er. For a more d etailed protoco l descript ion, refer to Chapt er 4 of the Book of DS19xx iButton
Standards.
HARDWARE CONFIGURATION
T he 1 -Wire bus has only a single line by definit ion; it is import ant t hat each d evice on the bus be able t o
drive it at the appro priat e t ime. To facil it at e t his, e ach dev ic e att ached t o the 1-Wire bu s mus t ha ve o p en-
drain or three-state outputs. The 1-Wire port of the DS199x is open drain with an internal circuit
equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3kbps and requires a pullup resistor of
approximat ely 5kΩ. The idle st ate for t he 1-Wir e bus is hig h. If fo r a ny r ea so n a t r ansa ct io n nee ds t o be
suspended, t he bus must be left in th e id le stat e if t he tr ansact io n is t o resu me. I f t his does not o ccur and
t he bu s is le ft lo w fo r mor e t ha n 120 µs, one or more of the devices o n t he bus may be reset.
Figure 8. HARDWARE CONFIGURATION
Open Drain
Port Pin
RX = RECEIVE
TX = TRAN SMIT
100 Ω
MOSFET
V
PUP
RX
TX
TX
RX
DATA
R
PU
5 µA
Typ.
BUS MAST ER
DS199x 1-Wire PORT
TRANSACTION SEQUENCE
The prot ocol fo r access ing the DS199x through the 1-Wire port is as follows:
Initialization
ROM Func tio n Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
DS1992/DS1993
11 of 17
slave(s). The presence pulse lets the bus master know that the DS199x is on the bus and is ready to
o per at e. Fo r mor e d etails, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM funct ion co mmands. Al l
ROM fu nct io n co mmand s are 8 bits long. A list of these commands follo w s (see the flo w c hart in Figur e
9).
Read ROM [33h]
This command allows the bus master to read the DS199x’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single DS199x on the bus. If
more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the
same t ime ( op en dra in pro duces a w ir ed-AND result ). The resulta nt fa mil y code and 48-b it s erial numbe r
us uall y result in a mismatc h of t he C R C .
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS199x on a multidrop bus. Only the DS199x that exactly matches the 64-bit ROM sequence
will respo nd to the fo llow ing memory fu nct io n command. All sla ves t hat do not match t he 64-bit RO M
seque nce wait for a reset p ulse. T h is command can be used w ith sing le o r multip le de v ices on t he bus.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more tha n one s lave is prese nt on t he bus
and, fo r examp le, a read co mmand is issued follow ing t he Skip ROM comma nd , d at a collision w il l o cc ur
on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND
result).
Search ROM [F0h]
When a system is initially brought up, the bus master may not k now the numbe r of d ev i c es on th e 1-Wire
bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of
eliminat ion t o ident ify the 64-bit ROM cod es o f a ll sla ve dev ices on t he bus. T he searc h ROM pro cess i s
t he repet it ion of a s imple 3-step ro utine: read a b it, read t he complement of the b it , t hen write t he des ire d
va lue of that bit. The bus mast er per fo r ms t his si mple, 3-st ep r out ine o n ea ch b it o f t he ROM. Aft er o ne
co mp lete pas s, t he bus mast er knows t he 64-bit R OM co de of one de vice. Add it io nal passes will identify
the ROM codes o f the remaining de vices. See C hapter 5 of the Boo k of DS19 xx iButto n Standards for a
co mprehen s ive discuss ion of a search ROM, including an act u al example.
1-Wire SIGNALING
The DS199x require strict protocols t o ensure data int egr it y. The protocol consists of four types of
signa ling o n o ne line: reset sequ ence wit h reset pu lse and pr ese nce p ulse, wr ite 0, wr ite 1, and read dat a.
The bus mast er initiates all these sig nals e xcept prese nce pu lse. T he initialization seque nce required to
begin an y communication with the DS199 x is s how n in Figure 1 0. A reset pulse fo llow ed by a presence
pu lse indicat es the DS199 x is ready to send or receive data g iven the co r r ect ROM command and
memory f unc tio n command . The bus mas te r t rans mits (Tx) a r eset pu lse (tRSTL, min imum 48 0µs ). T he bus
mast er t hen relea se s the line a nd go es into r eceive mod e ( Rx). The 1-Wir e bu s is pu lled to a high state
t hrough t he pullup resistor. After detecting the rising edge on the data line, the DS199x waits (tPDH, 15µs
to 60µs) and t hen t ransmits the prese nce pu lse (tPDL, 60µs to 240µs).
DS1992/DS1993
12 of 17
Figure 9. ROM FUNCTIONS FLOW CHART
F0H
Search ROM
Command
?
CCH
Skip ROM
Command
?
DS199x TX Bit 0
DS199x TX Bit 0
Master TX Bit 0
Bit 0
M atc h ?
DS199x TX Bit 1
DS199x TX Bit 1
Master TX Bit 1
Bit 1
M atc h ?
DS199x TX Bit 63
DS199x TX Bit 63
Ma ster TX Bit 63
Bit 63
M atc h ?
Ma ster TX Memory
Function Command
33H
Read ROM
Command
?
DS199x TX
Serial Number
6 Bytes
DS199x TX
CRC Byte
DS199x TX
Family Code
1 Byte
Match ROM
55H
Command
?
Bit 0
M atc h ?
Bit 1
M atc h ?
Bit 63
M atc h ?
Master TX Bit 1
Master TX Bit 0
N
Y
N
Y
N
N
Y
N
N
N
N
Y
Y
Y
Y
Y
Y
N
Y
N
Master TX ROM
Function Command
Master TX
Reset P ul se
DS199x TX
Pre sence Pulse
Ma ster TX Bit 63
DS1992/DS1993
13 of 17
Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE
RESISTOR
MASTER
DS199x
MASTER RX "PRESENCE PULSE"
480 µs
≤
t
RSTL
<
∞
*
480 µs
≤
t
RSTH
<
∞
**
15 µs
≤
t
PDH
< 60 µs
60
≤
t
PDL
< 240 µs
MASTER TX
"RESET PULSE"
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
t
RSTH
t
RSTL
t
PDH
t
PDL
t
R
* In order not to mask interrup signaling
by ot h er d evices on the 10Wir e bus t
RSTL
+ t
R
shoul d alw ays b e less than 960 us
** Includes recovery time
READ/WRITE TIME SLOTS
The definit io ns o f write and read time slots are illustrated in Figure 11. The master driving the data line
low initiates all time slots. The falling edge of the data line synchronizes the DS199x to the master by
triggering a delay circuit in the DS199x. During write time slots, the delay circuit determines when the
DS199x samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit
determines how long the DS199x ho lds the data line lo w overr iding the 1 generated by t he master. If the
dat a b it is a 1, the iButton lea ves the read dat a t ime slot uncha nged.
Figure 11. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
15µs
60µs
DS199x
Sampling Window
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
t
SLOT
t
REC
t
LOW1
60 µs
≤
t
SLOT
< 120 µs
1 µs
≤
t
LOW1
< 15 µs
1 µs
≤
t
REC
<
∞
RESISTOR
MASTER
DS1992/DS1993
14 of 17
Figure 11. READ/WRITE TIMING DIAGRAM (continued)
Write-Zero Time Slot
15µs
RESISTOR
MASTER
DS199x
60µs
t
LOW0
Sampling Window
60 µs
≤
t
LOW0
< t
SLOT
< 120 µs
1 µs
≤
t
REC
<
∞
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
t
SLOT
t
REC
Read-Data Time Slot
RESISTOR
MASTER
DS199x
Master
Sampling Window
60 µs
≤
t
SLOT
< 120 µs
1 µs
≤
t
LOWR
< 15 µs
0
≤
t
RELEASE
< 45 µs
1 µs
≤
t
REC
<
∞
t
RDV
= 15 µs
t
SU
< 1 µs
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
t
SLOT
t
REC
t
LOWR
t
SU
t
RDV
t
RELEASE
DS1992/DS1993
15 of 17
PHYSICAL SPECIFICATIONS
Size See mechanical drawing
Weight 3.3 grams (F5 package)
Expect ed Ser v ice Life 10 years at +25 °C
Safety Meets UL 913, 5th Ed., Rev. 1997-02-24; Intrinsically Safe
Apparatus, Approved under Entity Concept for use in
C lass I , Division 1, Group A, B, C, a nd D Locatio ns
ABSOLUTE MAXIMUM RAT INGS
Voltage Range on any Pin R ela tive to G r ound -0.5V to +7.0V
Operating Temperature Range -40°C to +70°C
Stor ag e T emperat ur e Range -40°C to +70°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
1-Wire Pullup Voltage
( Note s 1, 3)
VPUP 2.8 6.0 V
Logic 1 (Notes 1, 2)
V
IH
2.2
V
Logic 0 (Note 1)
VIL
-0.3
+0.3
V
Output Logic Lo w at 4mA
(Not e 1)
VOL 0.4 V
I nput L oa d C urr ent (Note 4)
IL
5
µA
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
I/O (1-Wir e) (Notes 5, 6)
CIN/OUT
100
800
pF
AC ELECTRICAL CHARACTERISTICS
(VPUP = 2.8V to 6.0V, TA = -40°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
T ime Slo t
t
SLOT
60
120
µs
Write 1 L ow T ime
t
LOW1
1
15
µs
Write 0 Low Time
t
LOW0
60
120
µ
s
Read Dat a V alid
t
RDV
exac tly 15
µ
s
Relea s e Time
tRELEASE
0
15
45
µs
Read Dat a S et up (Not e 7)
tSU
1
µs
Reco ver y Time
t
REC
1
µs
Re s e t Time High ( N ote 8 )
t
RSTH
480
µ
s
Reset Time Lo w ( Not e 9 )
tRSTL 480 960 µ
s
Presence Detect Hig h
t
PDH
15 60 µ
s
Presence Detect Lo w
tPDL
60
240
µ
s
DS1992/DS1993
16 of 17
Note 1: All voltages are refere nced t o g ro u nd.
Note 2: VIH is a function of the externa l pullup r es i stor and t he VCC power supply.
Note 3: VPUP = exter nal pullup voltage.
Note 4: Input load is to gro und.
Note 5: Capacit ance on the dat a line could be 800pF whe n power is first ap plied. I f a 5kΩ r e sistor is used
to pull up the data line to VPUP, 5µs aft er po wer has been applied, the parasite capacit anc e does not affect
normal com munications.
Note 6: Guar ant eed by desig n; not production t ested.
Note 7: Read data setu p t ime r efers to t he t ime the host must pull the 1-Wire bus low to r ead a bit. Data is
guarant eed to be va lid within 1µs o f t his falling edge, and re mains valid fo r 14µs minimum (15 µs total
from falling edge o n 1-Wire bu s) .
Note 8: An ad dit ional reset or communicatio n sequenc e canno t begin until the reset h ig h t ime has
expired.
Note 9: The reset low time (t RSTL) should be rest r icted to a maximum of 960µs, to allow interrupt
signaling ; otherwise, it co uld mask or conceal inter r upt pulses.
PACKAGE INFORMATION
For th e latest pa ckage out l ine information and land patterns (footprin t s), go to www.maxim-ic.com/packages. N ot e that a “+ ”,
“#” , or “-” in the package code in dicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACK AG E CODE OU TLINE NO . LAND PATTERN NO.
F5 iButton IB+5BW 21-0266 —
DS1992/DS1993
17 of 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
7/08 Updated the F5 MicroCan fac e bra nd w ith the lat est per PCN H020201. 1
10/08
Cha nge t he last sentence of the Para si te Power sectio n to “The
advantag es of parasit e p ower ar e t wo-fold: 1) by p aras iting off t his
input, battery po wer is not consumed for 1-Wire R O M function
co mmands, and 2) if the battery is exhausted for any reaso n, the ROM
may s till be read normall y. T he remaining circu it ry of the DS1992 and
DS1993 is so lely o perated by batter y energy.”
2
I n the DC Electrical Characteristic s section, r eloc ated V
PUP
from the
header t o t he EC table, cha nged VILMAX from 0.8V to 0.3V, and
r emove d the V OH parameter fo r the 1-Wire pin.
15
8/09
Updated t he part nu mbers in the Ordering Inf ormation t able to indicate
a lead( Pb)-free/RoHS compliant product.
1
4/11
Updated t he UL certificate reference in the Common iButton Features
and Physical Specifications sections; added the Package Inf ormation
section.
1, 15, 16
