General Description
The MAX17024 pulse-width modulation (PWM) con-
troller provides high efficiency, excellent transient
response, and high DC-output accuracy needed for
stepping down high-voltage batteries to generate low-
voltage core or chipset/RAM bias supplies in notebook
computers. The output voltage can be controlled using
the dynamic REFIN, which supports input voltages
between 0 to 2V. The REFIN adjustability combined
with a resistive voltage-divider on the feedback input
allows the MAX17024 to be configured for any output
voltage between 0 to 0.9 x VIN.
Maxim’s proprietary Quick-PWM™ quick-response, con-
stant-on-time PWM control scheme handles wide
input/output voltage ratios (low-duty-cycle applications)
with ease and provides 100ns “instant-on” response to
load transients while maintaining a relatively constant
switching frequency. Strong drivers allow the MAX17024
to efficiently drive large synchronous-rectifier MOSFETs.
The controller senses the current across the sense
resistor series with the synchronous rectifier to achieve
highly accurate valley current-limit protection.
The MAX17024 includes a voltage-controlled soft-start
and soft-shutdown to limit the input surge current, pro-
vide a monotonic power-up (even into a precharged
output), and provide a predictable power-up time. The
controller also includes output undervoltage and ther-
mal-fault protection.
The MAX17024 is available in a tiny 14-pin, 3mm x
3mm TDFN package. For space-constrained applica-
tions, refer to the MAX17016 single step-down with 26V
internal MOSFETs capable of supporting 10A continu-
ous load. The MAX17016 is available in a small 40-pin,
6mm x 6mm TQFN package.
Applications
Notebook Computers
I/O and Chipset Supplies
GPU Core Supply
DDR Memory—VDDQ or VTT
Point-of-Load Applications
Step-Down Power Supply
Features
Quick-PWM with Fast Transient Response
Supports Any Output Capacitor
No Compensation Required with
Polymers/Tantalum
Stable with Ceramic Output Capacitors Using
External Compensation
Precision 2V ±10mV Reference
Dynamically Adjustable Output Voltage
(0 to 0.9 x VIN Range)
Feedback Input Regulates to 0 to 2V REFIN
Voltage
0.5% VOUT Accuracy Over Line and Load
26V Maximum Input Voltage Rating
Resistively Programmable Switching Frequency
Undervoltage/Thermal Protection
Voltage Soft-Start and Soft-Shutdown
Monotonic Power-Up with Precharged Output
Power-Good Window Comparator
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
________________________________________________________________
Maxim Integrated Products
1
MAX17024
GND
TDFN
(3mm x 3mm)
TOP VIEW
245
13 11 10
VCC
REF
REFIN
DL
VDD
LX
DH
1
14
PGOOD
3
12
N.C.
6
9
CSBST
7
8
FBTON
EN
Pin Configuration
19-1040; Rev 0; 10/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Ordering Information
Note: This device is specified over the -40°C to +85°C operating
temperature range.
+
Denotes a lead-free package.
*
EP = Exposed paddle.
PART PIN-PACKAGE PKG
CODE
TOP
MARK
MAX17024ETD 14 TDFN-EP* 3mm x 3mm T1433-1 ADO
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA= 0°C to +85°C, unless otherwise specified. Typical values
are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
TON to GND ...........................................................-0.3V to +28V
VDD to GND..............................................................-0.3V to +6V
VCC to GND................................................-0.3V to (VDD + 0.3V)
EN, PGOOD to GND.................................................-0.3V to +6V
REF, REFIN to GND....................................-0.3V to (VCC + 0.3V)
CS, FB to GND ...........................................-0.3V to (VCC + 0.3V)
DL to GND..................................................-0.3V to (VDD + 0.3V)
BST to GND.................................................(VDD - 0.3V) to +34V
BST to LX..................................................................-0.3V to +6V
BST to VDD .............................................................-0.3V to +28V
DH to LX....................................................-0.3V to (VBST + 0.3V)
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
14-Pin 3mm x 3mm TDFN
(derated 24.4mW/°C above +70°C)....................1951mW
Operating Temperature Range (extended).........-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
Input Voltage Range VIN 2 26 V
Quiescent Supply Current (VDD) IDD + ICC FB forced above REFIN 0.7 1.2 mA
Shutdown Supply Current (VDD) ISHDN EN = GND, TA = +25°C 0.1 2 µA
VDD-to-VCC Resistance RCC 20
RTON = 97.5k (600kHz) 118 139 160
RTON = 200k (300kHz) 250 278 306
On-Time tON
VIN = 12V,
VFB = 1.0V
(Note 3) RTON = 302.5k354 417 480
ns
Minimum Off-Time tOFF(MIN) (Note 3) 200 300 ns
TON Shutdown Supply Current EN = GND, VTON = 26V,
VCC = 0V or 5V, TA = +25°C 0.01 1 µA
REFIN Voltage Range VREFIN (Note 2) 0 VREF V
REFIN Input Current IREFIN REFIN = 0.5V to 2V, TA = +25°C -50 +50 nA
FB Voltage Range VFB (Note 2) 0 VREF V
TA = +25°C 0.495 0.5 0.505
VREFIN = 0.5V,
measured at FB,
VIN = 2V to 26V TA = 0°C to +85°C 0.493 0.507
TA = +25°C 0.995 1.0 1.005
VREFIN = 1.0V TA = 0°C to +85°C 0.993 1.007
FB Voltage Accuracy VFB
VREFIN = 2.0V TA = 0°C to +85°C 1.990 2.0 2.010
V
FB Input Bias Current IFB 0.5V to 2.0V, TA = +25°C -0.1 +0.1 µA
FB Output Low Voltage ISINK = 3mA 0.4 V
Load-Regulation Error VCS = 2mV to 20mV 0.1 %
Line-Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.25 %
Soft-Start/Stop Slew Rate SSSR Rising/falling edge on EN 0.4 1.2 2.2 mV/µs
Dynamic REFIN Slew Rate DYNSR Rising edge on REFIN 3 9.45 18 mV/µs
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE
No load 1.990 2.00 2.010
Reference Voltage VREF VCC = 4.5V
to 5.5V IREF = -10µA to +50µA 1.98 2.00 2.02 V
FAULT DETECTION
With respect to the internal target voltage
(error comparator threshold); rising edge;
hysteresis = 50mV
250 300 350 mV
Dynamic transition VREF +
0.30
Upper PGOOD Trip Threshold VPGOOD_H
Minimum VPGOOD_H threshold 0.7
V
Lower PGOOD Trip Threshold VPGOOD_L
With respect to the internal target voltage
(error comparator threshold) falling edge;
hysteresis = 50mV
-240 -200 -160 mV
Output Undervoltage
Fault-Propagation Delay tUVP FB forced 25mV below VPGOOD_L
trip threshold 100 200 350 µs
VPGOOD_L falling edge, 25mV overdrive 5
VPGOOD_H rising edge, 25mV overdrive 5
PGOOD Propagation Delay tPGOOD
Startup delay 100 200 350
µs
PGOOD Output Low Voltage ISINK = 3mA 0.4 V
PGOOD Leakage Current IPGOOD FB = REFIN (PGOOD high impedance),
PGOOD forced to 5V, TA = +25°C 1 µA
Dynamic REFIN Transition Fault
Blanking Threshold
Fault blanking initiated; REFIN deviation
from the internal target voltage (error
comparator threshold); hysteresis = 10mV
±50 mV
Thermal-Shutdown Threshold TSHDN Hysteresis = 15°C 160 °C
VCC Undervoltage Lockout
Threshold VUVLO(VCC) Rising edge, PWM disabled below this
level; hysteresis = 100mV 3.95 4.2 4.45 V
CURRENT LIMIT
Current-Limit Threshold VCS 18 20 22 mV
Current-Limit Threshold
(Negative) VINEG -24 mV
Current-Limit Threshold
(Zero Crossing) VZX VGND - VCS 1 mV
CS Input Current ICS V
CS = ±200mV, TA = +25°C -1 +1 µA
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA= 0°C to +85°C, unless otherwise specified. Typical values
are at TA= +25°C.) (Note 1)
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA= 0°C to +85°C, unless otherwise specified. Typical values
are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVERS
Low state 1.2 3.5
DH Gate Driver On-Resistance RON(DH) BST - LX forced to 5V High state (pullup) 1.2 3.5
High state (pullup) 1.7 4
DL Gate Driver On-Resistance RON(DL) Low state (pulldown) 0.9 2
DH Gate Driver Source/
Sink Current IDH DH forced to 2.5V, BST - LX forced to 5V 1.5 A
DL Gate Driver Source Current IDL(SOURCE) DL forced to 2.5V 1 A
DL Gate Driver Sink Current IDL(SINK) DL forced to 2.5V 2.4 A
DH low to DL high 10 25
Driver Propagation Delay DL low to DH high 15 35 ns
DL falling, CDL = 3nF 20
DL Transition Time DL rising, CDL = 3nF 20 ns
DH falling, CDH = 3nF 20
DH Transition Time DH rising, CDH = 3nF 20 ns
Internal BST Switch On-Resistance RBST IBST = 10mA, VDD = 5V 4 7
INPUTS AND OUTPUTS
EN Logic-Input Threshold VEN EN rising edge, hysteresis = 450mV (typ) 1.20 1.7 2.20 V
EN Logic-Input Current IEN EN forced to GND or VDD, TA = +25°C -0.5 +0.5 µA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA= -40°C to +85°C, unless otherwise specified.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
PWM CONTROLLER
Input Voltage Range VIN 2 26 V
Quiescent Supply Current (VDD) IDD + ICC FB forced above REFIN 1.2 mA
RTON = 97.5k (600kHz) 115 163
RTON = 200k (300kHz) 250 306
On-Time tON
VIN = 12V,
VFB = 1.0V
(Note 3) RTON = 302.5k (200kHz) 348 486
ns
Minimum Off-Time tOFF(MIN) (Note 3) 350 ns
REFIN Voltage Range VREFIN (Note 2) 0 VREF V
FB Voltage Range VFB (Note 2) 0 VREF V
VREFIN = 0.5V 0.49 0.51
VREFIN = 1.0V 0.99 1.01
FB Voltage Accuracy VFB Measured at FB,
VIN = 2V to 26V
VREFIN = 2.0V 1.985 2.015
V
FB Output Low Voltage ISOURCE = 3mA 0.4 V
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = VEN = 5V, REFIN = REF. TA= -40°C to +85°C, unless otherwise specified.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
REFERENCE
Reference Voltage VREF VDD = 4.5V to 5.5V 1.985 2.015 V
FAULT DETECTION
Upper PGOOD Trip Threshold VPGOOD_H
With respect to the internal target voltage
(error comparator threshold) rising edge;
hysteresis = 50mV
250 350 mV
Lower PGOOD Trip Threshold VPGOOD_L
With respect to the internal target voltage
(error comparator threshold)
falling edge; hysteresis = 50mV
-240 -160 mV
Output Undervoltage
Fault-Propagation Delay tUVP FB forced 25mV below VPGOOD_L
trip threshold 80 400 µs
PGOOD Output Low Voltage ISINK = 3mA 0.4 V
VCC Undervoltage Lockout
Threshold VUVLO(VCC) Rising edge, PWM disabled below this level,
hysteresis = 100mV 3.95 4.45 V
CURRENT LIMIT
Current-Limit Threshold VCS 17 23 mV
GATE DRIVERS
Low state (pulldown) 3.5
DH Gate Driver On-Resistance RON(DH) BST - LX forced
to 5V High state (pullup) 3.5
High state (pullup) 4
DL Gate Driver On-Resistance RON(DL) Low state (pulldown) 2
Internal BST Switch On-Resistance RBST IBST = 10mA, VDD = 5V 7
INPUTS AND OUTPUTS
EN Logic-Input Threshold VEN EN rising edge hysteresis = 450mV (typ) 1.20 2.20 V
Note 1: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by
design and characterization.
Note 2: The 0 to 0.5V range is guaranteed by design, not production tested.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V,
and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds.
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
6 _______________________________________________________________________________________
Typical Operating Characteristics
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200kΩ, TA = +25°C, unless otherwise noted.)
1.05V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17024 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
0.1 1
1.054
1.052
1.056
1.058
1.060
1.050
0.01 10
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX17024 toc05
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
10.1
50
100
150
200
250
300
350
0
0.01 10
VIN = 12V
VOUT = 1.5V
SWITCHING FREQUENCY
vs. TEMPERATURE
MAX17024 toc06
TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
20 40 60 80-20 0
330
350
340
360
320
-40 100
ILOAD = 10A
ILOAD = 5A
VIN = 12V
VOUT = 1.5V
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
MAX17024 toc07
INPUT VOLTAGE (V)
MAXIMUM OUTPUT CURRENT (A)
18 2112 159
9.8
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
9.6
624
VOUT = 1.5V
MAXIMUM OUTPUT CURRENT
vs. TEMPERATURE
MAX17024 toc08
TEMPERATURE (°C)
MAXIMUM OUTPUT CURRENT (A)
20 40 60 80 100-20 0
10.5
11.5
11.0
12.0
10.0
-40
VOUT = 1.5V
NO-LOAD SUPPLY CURRENT IBIAS
vs. INPUT VOLTAGE
MAX17024 toc09
INPUT VOLTAGE (V)
IBIAS (mA)
1816 222010 12 148
0.30
0.40
0.50
0.60
0.70
0.80
0.20
624
VOUT = 1.5V
1.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX17024 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
1.00.1
65
70
75
80
85
90
95
100
60
0.01 10
12V 20V
7V
1.5V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17024 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
0.1 1
1.51
1.52
1.53
1.50
0.01 10
1.05V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX17024 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
1.00.1
65
70
75
80
85
90
95
100
60
0.01 10
12V 20V
7V
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
_______________________________________________________________________________________
7
NO-LOAD SUPPLY CURRENT IIN
vs. INPUT VOLTAGE
MAX17024 toc10
INPUT VOLTAGE (V)
IIN (mA)
1816 222010 12 148
0.04
0.02
0.06
0.10
0.08
0.14
0.12
0.16
0.18
0.20
0
624
VOUT = 1.5V
REF OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17024 toc11
LOAD CURRENT (µA)
REF OUTPUT VOLTAGE (V)
3020 40100
1.992
1.991
1.993
1.995
1.994
1.997
1.996
1.998
1.999
2.000
1.990
-10 50
REFIN-TO-FB OFFSET
VOLTAGE DISTRIBUTION
MAX17024 toc12
OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
10
30
20
40
50
+85°C
+25°C
SAMPLE SIZE = 100
0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
Typical Operating Characteristics (continued)
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200kΩ, TA = +25°C, unless otherwise noted.)
CURRENT-LIMIT THRESHOLD
VOLTAGE DISTRIBUTION
MAX17024 toc13
CS THRESHOLD VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
20
10
40
30
50
0
18.0
18.4
18.8
19.2
19.6
20.0
20.4
20.8
21.2
21.6
22.0
+85°C
+25°C
SAMPLE SIZE = 100
SOFT-START WAVEFORM
(HEAVY LOAD)
MAX17024 toc14
200µs/div
C. VOUT, 1V/div
D. INDUCTOR CURRENT,
10A/div
1.5V
6A
0
5V
0
0
0
5V A
B
C
D
A. EN, 5V/div
B. PWRGD, 5V/div
IOUT = 6A
SOFT-START WAVEFORM
(LIGHT LOAD)
MAX17024 toc15
200µs/div
C. VOUT, 1V/div
D. INDUCTOR CURRENT,
10A/div
1.5V
0
5V
0
0
0
5V A
B
C
D
A. EN, 5V/div
B. PWRGD, 5V/div
IOUT = 1A
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
8 _______________________________________________________________________________________
SHUTDOWN WAVEFORM
MAX17024 toc16
200µs/div
D. VOUT, 1V/div
E. INDUCTOR CURRENT,
5A/div
1.5V
0
5V
5V
0
0
0
0
5V
A
B
C
D
E
A. EN, 5V/div
B. PWRGD, 5V/div
C. DL, 5V/div
IOUT = 6A
LOAD-TRANSIENT RESPONSE
MAX17024 toc17
20µs/div
C. INDUCTOR CURRENT, 5A/div
1.49V
8A
1A
1.53V
10A
0A
A
B
C
A. IOUT 10A/div
B. VOUT, 20mV/div
IOUT = 1A TO 8A TO 1A
OUTPUT OVERLOAD WAVEFORM
MAX17024 toc18
200µs/div
C. DL, 5V/div
D. PGOOD, 5V/div
5V
5V
14A
0
0
1.5V
0
0
A
B
C
D
A. INDUCTOR CURRENT,
10A/div
B. VOUT, 1V/div
IOUT = 2A TO 14A
DYNAMIC OUTPUT-VOLTAGE TRANSITION
MAX17024 toc19
40µs/div
C. INDUCTOR CURRENT,
10A/div
D. LX, 10V/div
10A
0
1.5V
1.5V
1.05V
1.05V
12V
0
A
B
C
D
A. REFIN, 500mV/div
B. VOUT, 200mV/div
IOUT = 2A
Typical Operating Characteristics (continued)
(MAX17024 Circuit of Figure 1, VIN = 12V, VDD = 5V, RTON = 200kΩ, TA = +25°C, unless otherwise noted.)
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 VDD Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to
+5.5V). Bypass VDD to power ground with a 1µF or greater ceramic capacitor.
2 DL
Low-Side Gate Driver. DL swings from GND to VDD. The MAX17024 forces DL low during VCC UVLO
and REFOK lockout conditions.
3 N.C. Not Connected
4 LX Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1.
5 DH
High-Side Gate Driver. DH swings from LX to BST. The MAX17024 pulls DH low whenever the
controller is disabled.
6 BST
Boost Flying-Capacitor Connection. Connect to an external 0.1µF 6V capacitor as shown in Figure 1.
The MAX17024 contains an internal boost switch/diode (see Figure 2).
7 TON
Switching Frequency-Setting Input. An external resistor between the input power source and TON
sets the switching period (TSW = 1 / fSW) according to the following equation:
where CTON = 16.26pF and VFB = VREFIN under normal operating conditions. If the TON current
drops below 10µA, the MAX17024 shuts down and enters a high-impedance state. TON is high
impedance in shutdown.
8 FB
Feedback Voltage-Sense Connection. Connect directly to the positive terminal of the output
capacitors for output voltages less than 2V as shown in Figure 1. For fixed-output voltages greater
than 2V, connect REFIN to REF and use a resistive divider to set the output voltage (Figure 4). FB
senses the output voltage to determine the on-time for the high-side switching MOSFET.
9 CS
Current-Sense Input Pin. Connect to low-side MOSFET current-sense resistor. The current-limit
threshold is 20mV (typ).
10 REFIN
External Reference Input. REFIN sets the feedback regulation voltage (VFB = VREFIN) of the
MAX17024 using the resistor-divider connected between REF and GND. The MAX17024 includes
an internal window comparator to detect REFIN voltage transitions, allowing the controller to blank
PGOOD and the fault protection.
11 REF
2V Reference Voltage. Bypass to analog ground using a 470pF to 1nF ceramic capacitor. The
reference can source up to 50µA for external loads.
12 EN
Shutdown Control Input. Connect to VDD for normal operation. Pull EN low to place the controller
into its 2µA shutdown state. When disabled, the MAX17024 slowly ramps down the target/output
voltage to ground and after the target voltage reaches 0.1V, the controller forces both DH and DL
low and enters the low-power shutdown state. Toggle EN to clear the fault-protection latch.
13 VCC 5V Analog Supply Voltage. Internally connected to VDD through an internal 20 resistor. Bypass
VCC to analog ground using a 1µF ceramic capacitor.
14 PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 200mV (typ)
below or 300mV (typ) above the target voltage (VREFIN) during soft-start and soft-shutdown. After the
soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation.
PGOOD is blanked—forced high-impedance state—when a dynamic REFIN transition is detected.
EP
(15) GND Ground/Exposed Pad. Internally connected to the controller’s ground plane and substrate.
Connect directly to ground.
TCR k
V
V
SW TON TON FB
OUT
=+
()
⎛
⎝
⎜⎞
⎠
⎟
65.Ω
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
10 ______________________________________________________________________________________
Standard Application Circuit
The MAX17024 standard application circuit (Figure 1)
generates a 1.5V or 1.05V output rail for general-purpose
use in a notebook computer. Table 1 lists the compo-
nent manufacturers.
Detailed Description
The MAX17024 step-down controller is ideal for the
low-duty-cycle (high-input voltage to low-output volt-
age) applications required by notebook computers.
Maxim’s proprietary Quick-PWM pulse-width modulator
in the MAX17024 is specifically designed for handling
fast load steps while maintaining a relatively constant
operating frequency and inductor operating point over
a wide range of input voltages. The Quick-PWM archi-
tecture circumvents the poor load-transient timing
problems of fixed-frequency, current-mode PWMs while
also avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time
(regardless of input voltage) PFM control schemes.
C1
4.7µF
EN
OFFON
VDD
VCC
C2
1µF
PGOOD
R4
100kΩ
REFIN
R2
54.9kΩ
BST
LX
CBST
0.1µF
RCS
2mΩ
L1
D1 COUT
TON
R3
97.6kΩ
DH
DL
FB
HILO
REF
RTON
200kΩ
AGND
AGND
PWR
PWR
PWR
AGND PWR
AGND
AGND
12
10
1
13
7
6
5
4
2
GND (EP)
14
11
8
OUTPUT
1.05V/1.50V
10A (MAX)
INPUT
7V TO 24V
5V BIAS
SUPPLY
CS 9
MAX17024
CIN
PWR
C3
1nF
R1
49.9kΩ
Figure 1. MAX17024 Standard Application Circuit
Table 1. Component Suppliers
MANUFACTURER WEBSITE
AVX www.avxcorp.com
BI Technologies www.bitechnologies.com
Central
Semiconductor www.centralsemi.com
Coiltronics www.cooperet.com
Fairchild
Semiconductor www.fairchildsemi.com
International Rectifier www.irf.com
KEMET www.kemet.com
NEC Tokin www.nec-tokin.com
MANUFACTURER WEBSITE
Panasonic www.panasonic.com
Pulse www.pulseeng.com
Renesas www.renesas.com
SANYO www.edc.sanyo.com
Siliconix (Vishay) www.vishay.com
Sumida www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK www.component.tdk.com
TOKO www.tokoam.com
Toshiba www.toshiba.com
Wurth www.we-online.com
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 11
DYNAMIC OUTPUT
TRANSITION DETECTION
BST
LX
ONE-SHOT
TRIG
Q
tOFF(MIN)
ON-TIME
COMPUTE OUT
TON
ERROR
AMPLIFIER
EA + 0.3V
ONE-SHOT
TRIG Q
tON
ZERO CROSSING
FB
EA
PGOOD
EN
PGOOD
AND FAULT
PROTECTION
EA - 0.2V
BLANK
REFIN
VALLEY CURRENT LIMIT
GND
CS
S
R
Q
S
R
QDH
IN
SOFT-
START/STOP
DL
VCC
VDD
2V
REF
INTEGRATOR
(CCV)
REF
MAX17024
Figure 2. MAX17024 Functional Block Diagram
+5V Bias Supply (VCC/VDD)
The MAX17024 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s main 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator, such as the MAX1615.
The 5V bias supply powers both the PWM controller
and internal gate drive, so the maximum current drawn
is determined by:
IBIAS = IQ+ fSWQG= 2mA to 20mA (typ)
The MAX17024 includes a 20Ωresistor between VDD
and VCC, simplifying the PCB layout request.
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figure 2). This architecture
relies on the output filter capacitor’s ESR to act as a cur-
rent-sense resistor, so the output ripple voltage provides
the PWM ramp signal. The control algorithm is simple:
the high-side switch on-time is determined solely by a
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
12 ______________________________________________________________________________________
one-shot whose pulse width that is inversely proportion-
al to input voltage and directly proportional to output
voltage. Another one-shot sets a minimum off-time
(200ns typ). The on-time one-shot is triggered if the
error comparator is low, the low-side switch current is
below the valley current-limit threshold, and the mini-
mum off-time one-shot has timed out.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltage. The high-side
switch on-time is inversely proportional to the input volt-
age as sensed by the TON input, and proportional to
the feedback voltage as sensed by the FB input:
On-Time (tON) = TSW (VFB / VIN)
where TSW (switching period) is set by the resistance
(RTON) between TON and VIN. This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. Connect a resis-
tor (RTON) between TON and VIN to set the switching
period TSW = 1 / fSW:
where CTON = 16.26pF. When used with unity-gain feed-
back (VOUT = VFB), a 96.75kΩto 303.25kΩcorresponds
to switching periods of 167ns (600kHz) to 500ns
(200kHz), respectively. High-frequency (600kHz) opera-
tion optimizes the application for the smallest compo-
nent size, trading off efficiency due to higher switching
losses. This may be acceptable in ultra-portable devices
where the load currents are lower and the controller is
powered from a lower voltage supply. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
For continuous conduction operation, the actual switching
frequency can be estimated by:
where VDIS is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous recti-
fier, inductor, and PCB resistances; VCHG is the sum of
the resistances in the charging path, including the high-
side switch, inductor, and PCB resistances; and tON is
the on-time calculated by the MAX17024.
Power-Up Sequence (POR, UVLO)
The MAX17024 is enabled when EN is driven high, and
the 5V bias supply (VDD) is present. The reference
powers up first. Once the reference exceeds its UVLO
threshold, the internal analog blocks are turned on and
masked by a 50µs one-shot delay to allow the bias cir-
cuitry and analog blocks enough time to settle to their
proper states. With the control circuitry reliably pow-
ered up, the PWM controller may begin switching.
Power-on reset (POR) occurs when VCC rises above
approximately 3V, resetting the fault latch and prepar-
ing the controller for operation. The VCC UVLO circuitry
inhibits switching until VCC rises above 4.25V. The con-
troller powers up the reference once the system
enables the controller, VCC exceeds 4.25V, and EN is
driven high. With the reference in regulation, the con-
troller ramps the output voltage to the target REFIN volt-
age with a 1.2mV/µs slew rate:
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PGOOD becomes high impedance approximately
200µs after the target REFIN voltage has been reached.
The MAX17024 automatically uses pulse-skipping mode
during soft-start and uses forced-PWM mode during
soft-shutdown.
For automatic startup, the battery voltage should be
present before VCC. If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling EN or
cycling the VCC power supply below 0.5V.
If the VCC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately
and forces a high-impedance output (DL and DH
pulled low).
Shutdown
When the system pulls EN low, the MAX17024 enters
low-power shutdown mode. PGOOD is pulled low
immediately, and the output voltage ramps down with a
1.2mV/µs slew rate:
tV
mV s
V
Vms
START FB FB
==
12 12./ ./µ
fVV
tVV
SW FB DIS
ON IN CHG
=+
−(+V
DIS)
TCR k
V
V
SW TON TON FB
OUT
=+
()
⎛
⎝
⎜⎞
⎠
⎟
65.Ω
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 13
Slowly discharging the output capacitors by slewing
the output over a long period of time (typically 0.5ms to
2ms) keeps the average negative inductor current low
(damped response), thereby preventing the negative
output-voltage excursion that occurs when the con-
troller discharges the output quickly by permanently
turning on the low-side MOSFET (underdamped
response). This eliminates the need for the Schottky
diode normally connected between the output and
ground to clamp the negative output-voltage excursion.
After the controller reaches the zero target, the
MAX17024 shuts down completely—the drivers are dis-
abled (DL and DH pulled low)—the reference turns off,
activates 10Ωpulldown on FB, and the supply currents
drop to about 0.1µA (typ).
When a fault condition—output UVP or thermal shut-
down—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the
controller, toggle EN or cycle VCC power below 0.5V.
The MAX17024 automatically uses pulse-skipping
mode during soft-start and uses forced-PWM mode
during soft-shutdown.
Automatic Pulse-Skipping
The MAX17024 permanently operates in automatic skip
mode. An inherent automatic switchover to PFM takes
place at light loads. This switchover is affected by a
comparator that truncates the low-side switch on-time
at the inductor current’s zero crossing. The zero-cross-
ing comparator threshold is set by the differential
across the low-side MOSFET sense resistor.
The controller automatically transitions to fixed-frequency
PWM operation when the load reaches the same critical
condition point (ILOAD(SKIP)) that occurs at the skip and
the PWM boundary.
DC output-accuracy specifications refer to the thresh-
old of the error comparator. When the inductor is in
continuous conduction, the MAX17024 regulates the
valley of the output ripple, so the actual DC output volt-
age is higher than the trip level by 50% of the output
ripple voltage. In discontinuous conduction (IOUT <
ILOAD(SKIP)), the output voltage has a DC regulation
level higher than the error-comparator threshold by
approximately 1.5% due to slope compensation.
Since the output is not able to sink current, the timing for
negative dynamic output-voltage transitions depends on
the load current and output capacitance. Letting the
output voltage drift down is typically recommended to
reduce the potential for audible noise since this elimi-
nates the input current surge during negative output-
voltage transitions.
Valley Current-Limit Protection
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that senses the inductor current
through the low-side MOSFET sense resistor. If the cur-
rent through the low-side MOSFET exceeds the valley
current-limit threshold, the PWM controller is not
allowed to initiate a new cycle. The actual peak current
is greater than the valley current-limit threshold by an
amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the inductor value and input
voltage. When combined with the undervoltage protec-
tion circuit, this current-limit method is effective in
almost every circumstance.
Integrated Output Voltage
The MAX17024 regulates the valley of the output ripple,
so the actual DC output voltage is higher than the slope-
compensated target by 50% of the output ripple voltage.
Under steady-state conditions, the MAX17024’s internal
integrator corrects for this 50% output ripple-voltage
error, resulting in an output voltage accuracy that is
dependent only on the offset voltage of the integrator
amplifier provided in the
Electrical Characteristics
table.
Dynamic Output Voltages
The MAX17024 regulates FB to the voltage set at REFIN.
By changing the voltage at REFIN (Figure 1), the
MAX17024 can be used in applications that require
dynamic output-voltage changes between two set
points. For a step-voltage change at REFIN, the rate of
change of the output voltage is limited either by the
internal 9.45mV/µs slew-rate circuit or by the component
selection—inductor current ramp, the total output
capacitance, the current limit, and the load during the
transition—whichever is slower. The total output capaci-
tance determines how much current is needed to
change the output voltage, while the inductor limits the
current ramp rate. Additional load current may slow
down the output voltage change during a positive REFIN
voltage change, and may speed up the output voltage
change during a negative REFIN voltage change.
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
14 ______________________________________________________________________________________
Output Voltages Greater than 2V
Although REFIN is limited to a 0 to 2V range, the out-
put-voltage range is unlimited since the MAX17024 uti-
lizes a high-impedance feedback input (FB). By adding
a resistive voltage-divider from the output to FB to ana-
log ground (Figure 3), the MAX17024 supports output
voltages above 2V. However, the controller also uses
FB to determine the on-time, so the voltage-divider
influences the actual switching frequency, as detailed
in the
On-Time One-Shot
section.
Internal Integration
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This internal amplifi-
er integrates the feedback voltage and provides a fine
adjustment to the regulation voltage (Figure 2), allowing
accurate DC output-voltage regulation regardless of the
compensated feedback ripple voltage and internal
slope-compensation variation. The integrator amplifier
has the ability to shift the output voltage by ±55mV (typ).
The MAX17024 disables the integrator by connecting the
amplifier inputs together at the beginning of all downward
REFIN transitions done in pulse-skipping mode. The inte-
grator remains disabled until 20µs after the transition is
completed (the internal target settles) and the output is in
regulation (edge detected on the error comparator).
C1
4.7µF
EN
OFFON
VDD
VCC
C2
1µF
PGOOD
R4
100kΩ
REFIN
BST
LX
CBST
0.1µF
L1
COUT
TON
DH
DL
FB
REF
RTON
332kΩ
AGND
AGND
PWR
PWR
PWR
AGND PWR
12
10
1
13
7
6
5
4
2
CS 9
GND (EP)
14
11
8
OUTPUT
3.3V
INPUT
7V TO 24V
5V BIAS
SUPPLY
MAX17024
CIN
PWR
R7
20.0kΩ
RCS
R6
13.0kΩ
AGND
C3
1nF
Figure 3. High Output-Voltage Application Using a Feedback Divider
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 15
Power-Good Outputs (PGOOD)
and Fault Protection
PGOOD is the open-drain output that continuously
monitors the output voltage for undervoltage and over-
voltage conditions. PGOOD is actively held low in shut-
down (EN = GND) during soft-start and soft-shutdown.
Approximately 200µs (typ) after the soft-start termi-
nates, PGOOD becomes high impedance as long as
the feedback voltage is above the PGOOD_L threshold
(REFIN - 200mV) and below the PGOOD_H threshold
(REFIN + 300mV). PGOOD goes low if the feedback
voltage drops 200mV below the target voltage (REFIN)
or rises 300mV above the target voltage (REFIN), or the
SMPS controller is shut down. For a logic-level PGOOD
output voltage, connect an external pullup resistor
between PGOOD and VDD. A 100kΩpullup resistor
works well in most applications. Figure 4 shows the
power-good and fault-protection circuitry.
PGOOD
When the feedback voltage drops 200mV below the
target voltage (REFIN), the controller immediately pulls
PGOOD low and triggers a 200µs one-shot timer. If the
feedback voltage remains below the VPGOOD_L thresh-
old for the entire 200µs, the undervoltage fault latch is
set and the SMPS begins the shutdown sequence.
When the internal target voltage drops below 0.1V, the
MAX17024 forces DL low. Toggle EN or cycle VCC
power below VCC POR to clear the fault latch and
restart the controller.
Thermal-Fault Protection (TSHDN)
The MAX17024 features a thermal fault-protection cir-
cuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
PGOOD low, and shuts down the controller. Both DL
and DH are pulled low. Toggle EN or cycle VCC power
below VCC POR to reactivate the controller after the
junction temperature cools by 15°C.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving mode-
rate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large VIN -
VOUT differential exists. The high-side gate driver (DH)
sources and sinks 1.5A, and the low-side gate driver
(DL) sources 1.0A and sinks 2.4A. This ensures robust
gate drive for high-current applications. The DH floating
high-side MOSFET driver is powered by internal boost
switch charge pumps at BST, while the DL synchro-
nous-rectifier driver is powered directly by the 5V bias
supply (VDD).
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
POWER-GOOD
UV FAULT
TARGET
- 200mV
TARGET
+ 300mV
UV FAULT
LATCH
FB
VPGOOD_H
SOFT-START
COMPLETE
EN
V
PGOOD_L
ONE-
SHOT
200µs
IN
CLK
OUT
POWER-GOOD AND FAULT PROTECTION
Figure 4. Power-Good and Fault Protection
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
16 ______________________________________________________________________________________
There must be a low-resistance, low-inductance path
from the DL and DH drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17024 interprets the
MOSFET gates as “off” while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL low is
robust, with a 0.9Ω(typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
ground to VIN. Applications with high-input voltages and
long inductive driver traces must ensure rising LX edges
do not pull up the low-side MOSFETs’ gate, causing
shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-to-
drain capacitance (CRSS), gate-to-source capacitance
(CISS - CRSS), and additional board parasitics should
not exceed the following minimum threshold:
Typically, adding a 4700pF between DL and power
ground (CNL in Figure 5), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ωin series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (RBST in Figure 5). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple-current ratio). The prima-
ry design trade-off lies in choosing a good switching fre-
quency and inductor operating point, and the following
four factors dictate the rest of the design:
•Input voltage range: The maximum value
(VIN(MAX)) must accommodate the worst-case input
supply voltage allowed by the notebook’s AC
adapter voltage. The minimum value (VIN(MIN))
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
•Maximum load current: There are two values to
consider. The peak load current (ILOAD(MAX))
determines the instantaneous component stresses
and filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
ous load current (ILOAD) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Most notebook loads gener-
ally exhibit ILOAD = ILOAD(MAX) x 80%.
•Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and VIN2. The opti-
mum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
VV
C
C
GS TH IN RSS
ISS
()
>⎛
⎝
⎜⎞
⎠
⎟
BST
DH
LX
(RBST)*
INPUT (VIN)
CBST
CBYP
L
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
DL
PGND
NL
NH
(CNL)*
VDD
Figure 5. Gate Drive Circuit
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 17
•Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor,
which can be calculated from the on-time and minimum
off-time. The worst-case output sag voltage can be
determined by:
where tOFF(MIN) is the minimum off-time (see the
Electrical
Characteristics
table).
The amount of overshoot due to stored inductor energy
when the load is removed can be calculated as:
Setting the Valley Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at ILOAD(MAX) minus
half the inductor ripple current (∆IL), therefore:
where ILIMIT(LOW) equals the minimum current-sense
threshold voltage (see the
Electrical Characteristics
table) divided by the low-side MOSFET sense resis-
tance RCS.
Output Capacitor Selection
The output filter capacitor must have low-enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements. Additionally, the ESR
impacts stability requirements. Capacitors with a high
ESR value (polymers/tantalums) do not need additional
external compensation components.
In core and chipset converters and other applications
where the output is subject to large-load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
In low-voltage applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. The maximum ESR to meet ripple require-
ments is:
where fSW is the switching frequency.
RVf L
VV V V
ESR IN SW
IN OUT OUT RIPPLE
≤−
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
RR V
I
ESR PCB STEP
LOAD MAX
+
()
≤∆()
II I
LIMIT LOW LOAD MAX L
() ()
>−∆
2
VIL
CV
SOAR LOAD MAX
OUT OUT
≈
()
∆()
2
2
V
VT
Vt
CV VV T
Vt
SAG
OUT SW
IN OFF MIN
OUT OUT IN OUT SW
IN OFF MIN
=
()
⎛
⎝
⎜⎞
⎠
⎟+
⎡
⎣
⎢⎤
⎦
⎥
−
()
⎛
⎝
⎜⎞
⎠
⎟−
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
LI
LOAD(MAX) 2
∆()
()
2
II I
PEAK LOAD MAX L
=+
()
∆
2
LVV
f I LIR
V
V
IN OUT
SW LOAD MAX
OUT
IN
=−
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
()
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
18 ______________________________________________________________________________________
With most chemistries (polymer, tantalum, aluminum
electrolytic), the actual capacitance value required
relates to the physical size needed to achieve low ESR
and the chemistry limits of the selected capacitor tech-
nology. Ceramic capacitors provide low ESR, but the
capacitance and voltage rating (after derating) are
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load tran-
sients. Generally, once enough capacitance is added to
meet the overshoot requirement, undershoot at the ris-
ing load edge is no longer a problem (see the VSAG and
VSOAR equations in the
Transient Response
section).
Thus, the output capacitor selection requires carefully
balancing capacitor chemistry limitations (capacitance
vs. ESR vs. voltage rating) and cost. See Figure 6.
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the in-phase feedback ripple relative to the switching
frequency, which is typically dominated by the output
ESR. The boundary of instability is given by the fol-
owing equation:
where COUT is the total output capacitance, RESR is the
total equivalent-series resistance of the output capaci-
tors, RPCB is the parasitic board resistance between
the output capacitors and feedback sense point, and
RCOMP is the effective resistance of the DC- or AC-cou-
pled current-sense compensation (see Figure 8).
For a standard 300kHz application, the effective zero
frequency must be well below 95kHz, preferably below
50kHz. With these frequency requirements, standard
tantalum and polymer capacitors already commonly
used have typical ESR zero frequencies below 50kHz,
allowing the stability requirements to be achieved with-
out any additional current-sense compensation. In the
standard application circuit (Figure 1), the ESR needed
to support a 15mVP-P ripple is 15mV / (10A x 0.3) =
5mΩ. Two 330µF, 9mΩpolymer capacitors in parallel
provide 4.5mΩ(max) ESR and 1 / (2πx 330µF x 9mΩ)
= 53kHz ESR zero frequency. See Figure 7.
f
RC
RRR R
SW
EFF OUT
EFF ESR PCB COMP
ππ
≥
=++
1
2
CIN
L1
COUT
PWR
PWR
RCS
PWR
PWR
BST
LX
TON
DH
DL
FB
GND
AGND 2fSW
RESRCOUT 1
≥
STABILITY REQUIREMENT
MAX17024
CS
OUTPUT
INPUT
Figure 6. Standard Application with Output Polymer or Tantalum
PCB PARASITIC RESISTANCE
SENSE RESISTANCE FOR EVALUATION
OUTPUT VOLTAGE REMOTELY
SENSED NEAR POINT OF LOAD
FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
CIN
L1
COUT
PWR
PWR
RCOMP
100Ω
PWR
BST
LX
TON
CCOMP
0.1µF
DH
DL
FB
GND
AGND
2fSW
RESRCOUT 1
≥
fSW
AND RCOMPCCOMP 1
≥
STABILITY REQUIREMENT
MAX17024
CLOAD
PWR
OUTPUT
INPUT
PWR
CS
Figure 7. Remote-Sense Compensation for Stability and Noise Immunity
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 19
Ceramic capacitors have a high-ESR zero frequency,
but applications with sufficient current-sense compen-
sation can still take advantage of the small size, low
ESR, and high reliability of the ceramic chemistry. Using
the inductor DCR, applications using ceramic output
capacitors can be compensated using either a DC-
compensation or AC-compensation method (Figure 8).
The DC-coupling requires fewer external compensation
capacitors, but this also creates an output load line that
depends on the inductor’s DCR (parasitic resistance).
Alternatively, the current-sense information may be AC-
coupled, allowing stability to be dependent only on the
inductance value and compensation components and
eliminating the DC load line.
OPTION B: AC-COUPLED CURRENT-SENSE COMPENSATION
OPTION A: DC-COUPLED CURRENT-SENSE COMPENSATION
DC COMPENSATION
<> FEWER COMPENSATION COMPONENTS
<> CREATES OUTPUT LOAD LINE
<> LESS OUTPUT CAPACITANCE REQUIRED
FOR TRANSIENT RESPONSE
AC COMPENSATION
<> NOT DEPENDENT ON ACTUAL DCR VALUE
<> NO OUTPUT LOAD LINE
CIN
L
COUT
RSENA
RSENB
CSEN
PWR
PWR
BST
LX
TON
DH
DL
STABILITY REQUIREMENT
L
MAX17024
OUTPUT
INPUT
FEEDBACK RIPPLE IN-PHASE WITH INDUCTOR CURRENT
1
2fSW
RSENBRDCR
RSENA + RSENB
CIN
L
COUT
RSEN
RCOMP
CCOMP
CSEN
PWR
PWR
PWR
BST
LX
TON
DH
GND
AGND
STABILITY REQUIREMENT
OUTPUT
INPUT
FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
((RSENA || RSENB) CSEN)COUT ≥AND LOAD LINE =
1
2fSW
1
fSW
L
(RSENCSEN)COUT ≥AND RCOMPCCOMP ≥
PWR
FB
GND
AGND
PWR
CS
DL
MAX17024
FB
PWR
CS
Figure 8. Feedback Compensation for Ceramic Output Capacitors
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
20 ______________________________________________________________________________________
When only using ceramic output capacitors, output
overshoot (VSOAR) typically determines the minimum
output capacitance requirement. Their relatively low
capacitance value may allow significant output over-
shoot when stepping from full-load to no-load condi-
tions, unless designed with a small inductance value
and high switching frequency to minimize the energy
transferred from the inductor to the capacitor during
load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback-
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The IRMS requirements can be determined by the fol-
lowing equation:
The worst-case RMS current requirement occurs when
operating with VIN = 2VOUT. At this point, the above
equation simplifies to IRMS = 0.5 x ILOAD.
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input.
If the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tanta-
lum input capacitors are acceptable. In either configu-
ration, choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both these sums.
Ideally, the losses at VIN(MIN) should be roughly equal to
losses at VIN(MAX), with lower losses in between. If the
losses at VIN(MIN) are significantly higher than the losses
at VIN(MAX), consider increasing the size of NH(reducing
RDS(ON) but with higher CGATE). Conversely, if the losses
at VIN(MAX) are significantly higher than the losses at
VIN(MIN), consider reducing the size of NH(increasing
RDS(ON) to lower CGATE). If VIN does not vary over a
wide range, the maximum efficiency occurs where the
resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (RDS(ON)), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur (see the
MOSFET Gate Drivers
section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high-input voltages.
However, the RDS(ON) required to stay within package-
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. High-
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in the high-side MOS-
FET (NH) due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
PD N sistive V
VIR
HOUT
IN LOAD DS ON
( Re ) ( ) ()
=⎛
⎝
⎜⎞
⎠
⎟2
II
VVVV
RMS LOAD
IN OUT IN OUT
=⎛
⎝
⎜⎞
⎠
⎟−
()
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 21
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on NH:
where COSS is the NHMOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the NHMOS-
FET, and IGATE is the peak gate-drive source/sink cur-
rent (2.4A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x VIN2x fSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
VIN(MAX), consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX), but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
where IVALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (DL) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side, MOSFETs require
boost capacitors larger than 0.1µF. For these applica-
tions, select the boost capacitors to avoid discharging
the capacitor more than 200mV while charging the
high-side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and QGATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
Minimum Input-Voltage Requirements
and Dropout Performance
The output voltage-adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time settings. When
working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the on-times. This
error is greater at higher frequencies. Also, keep in
mind that transient response performance of buck reg-
ulators operated too close to dropout is poor, and bulk
output capacitance must often be added (see the VSAG
equation in the
Transient Response
section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP / ∆IDOWN is an indicator of the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and VSAG greatly increases
unless additional output capacitance is used.
CnC
mV F
BST =×=
224
200 024.µ
CNQ
mV
BST GATE
=×
200
II I
II LIR
LOAD VALLEY MAX L
VALLEY MAX LOAD MAX
=+
=+
⎛
⎝
⎜⎞
⎠
⎟
()
() ()
∆
2
2
PD N sistive V
VIR
LOUT
IN MAX LOAD DS ON
( Re )
() ()
=−⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
12
PD N Switching V I f Q
I
H IN MAX LOAD SW
GSW
GA
()
()
()
=
TTE
OSS IN MAX SW
CV f
⎛
⎝
⎜⎞
⎠
⎟+
()
2
2
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
22 ______________________________________________________________________________________
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where VFB is the voltage-positioning droop, VCHG, is the
parasitic voltage drop in the charge path, and tOFF(MIN)
is from the
Electrical Characteristics
table. The absolute
minimum input voltage is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able VSAG. If operation near dropout is anticipated,
calculate VSAG to be sure of adequate transient
response.
Dropout design example:
VFB = 1.5V
fSW = 300kHz
tOFF(MIN) = 350ns
No droop/load line (VDROOP = 0)
VDROPCHG = 150mV (10A load)
h = 1.5:
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, VIN must be greater than 1.84V, even with
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 2.0V.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
• Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the VCC
bypass capacitor, REF bypass capacitors, REFIN
components, and feedback compensation/dividers.
• Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load effi-
ciency by 1% or more. Correctly routing PCB traces
is a difficult task that must be approached in terms of
fractions of centimeters, where a single mΩof excess
trace resistance causes a measurable efficiency
penalty.
• Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes away from sen-
sitive analog areas (REF, REFIN, FB).
VVV mV
ns kHz V
IN MIN() .
(. ) .=−+
−××
⎡
⎣
⎢⎤
⎦
⎥=
1 5 0 150
1 1 0 350 300 184
VVV mV
ns kHz V
IN MIN() .
(. ) .=−+
−××
⎡
⎣
⎢⎤
⎦
⎥=
1 5 0 150
1 1 5 350 300 196
VVV V
ht f
IN MIN FB DROOP CHG
OFF MIN SW
()
()
=−+
−×
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
1
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
______________________________________________________________________________________ 23
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, CIN,
COUT, and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST capacitors,
VDD bypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
having 4 separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the GND pin and
VDD bypass capacitor go; the controller’s analog
ground plane where sensitive analog components,
the controller’s GND pin, and VCC bypass capacitor
go. The controller’s ground plane must meet the
power ground plane only at a single point directly
beneath the IC (this si done automatically inside the
MAX17024 through the back pad). These ground
planes should connect to the high-power output
ground with a short metal trace from GND (back
pad) to the source of the low-side MOSFET (the mid-
dle of the star ground). This point must also be very
close to the output capacitor ground terminal.
5) Connect the output power planes (VCORE and sys-
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit
as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 7169
PROCESS: BiCMOS
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
24 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX17024
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
25
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A 0.70 0.80
D 2.90 3.10
E 2.90 3.10
A1 0.00 0.05
L 0.20 0.40
PKG. CODE N D2 E2 eJEDEC SPEC b[(N/2)-1] x e
PACKAGE VARIATIONS
0.25 MIN.k
A2 0.20 REF.
2.00 REF0.25±0.050.50 BSC2.30±0.1010T1033-1
2.40 REF0.20±0.05- - - - 0.40 BSC1.70±0.10 2.30±0.1014T1433-1
1.50±0.10 MO229 / WEED-3
0.40 BSC - - - - 0.20±0.05 2.40 REFT1433-2 14 2.30±0.101.70±0.10
T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF
T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF
T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF
2.30±0.10 MO229 / WEED-3 2.00 REF0.25±0.050.50 BSC1.50±0.1010T1033-2
Note: MAX17024ETD+ Package Code = T1433-1