PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
14 December 2012 Product data sheet
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1. General description
NPN/PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a leadless
medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package.
NPN/NPN complement: PBSS4230PAN. PNP/PNP complement: PBSS5230PAP.
2. Features and benefits
•Very low collector-emitter saturation voltage VCEsat
•High collector current capability IC and ICM
•High collector current gain hFE at high IC
•Reduced Printed-Circuit Board (PCB) requirements
•High efficiency due to less heat generation
•AEC-Q101 qualified
3. Applications
•Load switch
•Battery-driven devices
•Power management
•Charging circuits
•Power switches (e.g. motors, fans)
4. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per transistor; for the PNP transistor with negative polarity
VCEO collector-emitter
voltage
open base - - 30 V
ICcollector current - - 2 A
ICM peak collector current single pulse; tp ≤ 1 ms - - 3 A
TR1 (NPN)
RCEsat collector-emitter
saturation resistance
IC = 1 A; IB = 100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 145 mΩ
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 2 / 21
Symbol Parameter Conditions Min Typ Max Unit
TR2 (PNP)
RCEsat collector-emitter
saturation resistance
IC = -1 A; IB = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 195 mΩ
5. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 E1 emitter TR1
2 B1 base TR1
3 C2 collector TR2
4 E2 emitter TR2
5 B2 base TR2
6 C1 collector TR1
7 C1 collector TR1
8 C2 collector TR2
Transparent top view
6
7 8
5 4
1 2 3
DFN2020-6 (SOT1118)
sym139
B1
E1 C2
B2C1
TR1
TR2
E2
6. Ordering information
Table 3. Ordering information
PackageType number
Name Description Version
PBSS4230PANP DFN2020-6 plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body 2 x 2 x 0.65 mm
SOT1118
7. Marking
Table 4. Marking codes
Type number Marking code
PBSS4230PANP 2J
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor with negative polarity
VCBO collector-base voltage open emitter - 30 V
VCEO collector-emitter voltage open base - 30 V
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 3 / 21
Symbol Parameter Conditions Min Max Unit
VEBO emitter-base voltage open collector - 7 V
ICcollector current - 2 A
ICM peak collector current single pulse; tp ≤ 1 ms - 3 A
IBbase current - 0.3 A
IBM peak base current single pulse; tp ≤ 1 ms - 1 A
[1] - 370 mW
[2] - 570 mW
[3] - 530 mW
[4] - 700 mW
[5] - 450 mW
[6] - 760 mW
[7] - 700 mW
Ptot total power dissipation Tamb ≤ 25 °C
[8] - 1450 mW
Per device
[1] - 510 mW
[2] - 780 mW
[3] - 730 mW
[4] - 960 mW
[5] - 620 mW
[6] - 1040 mW
[7] - 960 mW
Ptot total power dissipation Tamb ≤ 25 °C
[8] - 2000 mW
Tjjunction temperature - 150 °C
Tamb ambient temperature -55 150 °C
Tstg storage temperature -65 150 °C
[1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm2.
[3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
[4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm2.
[7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
[8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 4 / 21
Tamb (°C)
-75 17512525 75-25
006aad165
0.5
1.0
1.5
Ptot
(W)
0
(1)
(2)
(3) (4)
(5)
(6)
(7)
(8)
(1) 4-layer PCB 70 µm, mounting pad for collector 1 cm2
(2) FR4 PCB 70 µm, mounting pad for collector 1 cm2
(3) 4-layer PCB 70 µm, standard footprint
(4) 4-layer PCB 35 µm, mounting pad for collector 1 cm2
(5) FR4 PCB 35 µm, mounting pad for collector 1 cm2
(6) 4-layer PCB 35 µm, standard footprint
(7) FR4 PCB 70 µm, standard footprint
(8) FR4 PCB 35 µm, standard footprint
Fig. 1. Per transistor: power derating curves
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
[1] - - 338 K/W
[2] - - 219 K/W
[3] - - 236 K/W
[4] - - 179 K/W
[5] - - 278 K/W
[6] - - 164 K/W
[7] - - 179 K/W
Rth(j-a) thermal resistance
from junction to
ambient
in free air
[8] - - 86 K/W
Rth(j-sp) thermal resistance
from junction to solder
point
- - 30 K/W
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 5 / 21
Symbol Parameter Conditions Min Typ Max Unit
Per device
[1] - - 245 K/W
[2] - - 160 K/W
[3] - - 171 K/W
[4] - - 130 K/W
[5] - - 202 K/W
[6] - - 120 K/W
[7] - - 130 K/W
Rth(j-a) thermal resistance
from junction to
ambient
in free air
[8] - - 63 K/W
[1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm2.
[3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
[4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm2.
[7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
[8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
006aad166
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02 0.01
0
FR4 PCB 35 µm, standard footprint
Fig. 2. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 6 / 21
006aad167
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02 0.01
0
FR4 PCB 35 µm, mounting pad for collector 1 cm2
Fig. 3. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad168
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02 0.01
0
4-layer PCB 35 µm, standard footprint
Fig. 4. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 7 / 21
006aad169
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
4-layer PCB 35 µm, mounting pad for collector 1 cm2
Fig. 5. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aac610
10- 5 1010- 2
10- 4 102
10- 1
tp (s)
10- 3 103
1
102
10
103
Zth(j-a)
(K/W)
1
0
duty cycle = 1
0.01
0.02
0.05
0.1
0.2
0.33
0.5
0.75
FR4 PCB 70 µm, standard footprint
Fig. 6. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 8 / 21
006aac611
10- 5 1010- 2
10- 4 102
10- 1
tp (s)
10- 3 103
1
102
10
103
Zth(j-a)
(K/W)
1
0
duty cycle = 1
0.01
0.02
0.05
0.1
0.2
0.33
0.5
0.75
FR4 PCB 70 µm, mounting pad for collector 1 cm2
Fig. 7. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad170
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
4-layer PCB 70 µm, standard footprint
Fig. 8. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 9 / 21
006aad171
10-5 1010-2
10-4 102
10-1
tp (s)
10-3 103
1
10
102
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02 0.01
0
4-layer PCB 70 µm, mounting pad for collector 1 cm2
Fig. 9. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
10. Characteristics
Table 7. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
TR1 (NPN)
VCB = 24 V; IE = 0 A; Tamb = 25 °C - - 100 nAICBO collector-base cut-off
current VCB = 24 V; IE = 0 A; Tj = 150 °C - - 50 µA
IEBO emitter-base cut-off
current
VEB = 5 V; IC = 0 A; Tamb = 25 °C - - 100 nA
VCE = 2 V; IC = 100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
250 380 -
VCE = 2 V; IC = 500 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
230 350 -
VCE = 2 V; IC = 1 A; pulsed; tp ≤ 300 µs;
δ ≤ 0.02 ; Tamb = 25 °C
200 310 -
hFE DC current gain
VCE = 2 V; IC = 2 A; pulsed; tp ≤ 300 µs;
δ ≤ 0.02 ; Tamb = 25 °C
150 230 -
IC = 500 mA; IB = 50 mA; Tamb = 25 °C - 60 80 mV
IC = 1 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- 120 160 mV
IC = 2 A; IB = 100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- 230 300 mV
VCEsat collector-emitter
saturation voltage
IC = 2 A; IB = 200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- 220 290 mV
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 10 / 21
Symbol Parameter Conditions Min Typ Max Unit
RCEsat collector-emitter
saturation resistance
IC = 1 A; IB = 100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 145 mΩ
IC = 500 mA; IB = 50 mA; Tamb = 25 °C - - 1 V
IC = 1 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 1 V
IC = 2 A; IB = 100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 1.1 V
VBEsat base-emitter saturation
voltage
IC = 2 A; IB = 200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 1.2 V
VBEon base-emitter turn-on
voltage
VCE = 2 V; IC = 0.5 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 0.9 V
tddelay time - 10 - ns
trrise time - 50 - ns
ton turn-on time - 60 - ns
tsstorage time - 310 - ns
tffall time - 60 - ns
toff turn-off time
VCC = 12.5 V; IC = 1 A; IBon = 50 mA;
IBoff = -50 mA; Tamb = 25 °C
- 370 - ns
fTtransition frequency VCE = 10 V; IC = 50 mA; f = 100 MHz;
Tamb = 25 °C
60 120 - MHz
Cccollector capacitance VCB = 10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
- 13.5 18 pF
TR2 (PNP)
VCB = -24 V; IE = 0 A - - -100 nAICBO collector-base cut-off
current VCB = -24 V; IE = 0 A; Tj = 150 °C - - -50 µA
IEBO emitter-base cut-off
current
VEB = -5 V; IC = 0 A - - -100 nA
VCE = -2 V; IC = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
260 370 -
VCE = -2 V; IC = -500 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
210 290 -
VCE = -2 V; IC = -1 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
160 230 -
hFE DC current gain
VCE = -2 V; IC = -2 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
100 145 -
IC = -500 mA; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- -75 -110 mVVCEsat collector-emitter
saturation voltage
IC = -1 A; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- -155 -220 mV
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 11 / 21
Symbol Parameter Conditions Min Typ Max Unit
IC = -2 A; IB = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- -295 -420 mV
IC = -2 A; IB = -200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- -275 -390 mV
RCEsat collector-emitter
saturation resistance
IC = -1 A; IB = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - 195 mΩ
IC = -500 mA; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - -1 V
IC = -1 A; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - -1 V
IC = -2 A; IB = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - -1.1 V
VBEsat base-emitter saturation
voltage
IC = -2 A; IB = -200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - -1.2 V
VBEon base-emitter turn-on
voltage
VCE = -2 V; IC = -0.5 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
- - -0.9 V
tddelay time - 10 - ns
trrise time - 50 - ns
ton turn-on time - 60 - ns
tsstorage time - 200 - ns
tffall time - 45 - ns
toff turn-off time
VCC = -12.5 V; IC = -1 A; IBon = -0.05 A;
IBoff = 0.05 A; Tamb = 25 °C
- 245 - ns
fTtransition frequency VCE = -10 V; IC = -50 mA; f = 100 MHz;
Tamb = 25 °C
50 95 - MHz
Cccollector capacitance VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
- 22 29 pF
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 12 / 21
006aad188
200
400
600
hFE
0
IC (mA)
10-1 104
103
1 102
10
(1)
(2)
(3)
VCE = 2 V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 10. TR1 (NPN): DC current gain as a function of
collector current; typical values
VCE (V)
0 542 31
006aad189
1
2
3
IC
(A)
0
IB= 15 mA 13.5 12 10.5
9
7.5
6
4.5
3
1.5
Tamb = 25 °C
Fig. 11. TR1 (NPN): Collector current as a function of
collector-emitter voltage; typical values
006aad190
0.4
0.8
1.2
VBE
(V)
0
IC (mA)
10-1 104
103
1 102
10
(1)
(2)
(3)
VCE = 2 V
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 12. TR1 (NPN): Base-emitter voltage as a function
of collector current; typical values
006aad191
0.6
0.8
0.4
1.0
1.2
VBEsat
(V)
0.2
IC (mA)
10-1 104
103
1 102
10
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb= 100 °C
Fig. 13. TR1 (NPN): Base-emitter saturation voltage as a
function of collector current; typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 13 / 21
006aad192
10-1
10-2
1
VCEsat
(V)
10-3
IC (mA)
10-1 104
103
1 102
10
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 14. TR1 (NPN): Collector-emitter saturation voltage
as a function of collector current; typical values
006aad193
10-1
10-2
1
VCEsat
(V)
10-3
IC (mA)
10-1 104
103
1 102
10
(1)
(2)
(3)
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
Fig. 15. TR1 (NPN): Collector-emitter saturation voltage
as a function of collector current; typical values
IC (mA)
10-1 104
103
1 102
10
006aad194
1
10-1
102
10
103
RCEsat
(Ω)
10-2
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 16. TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
IC (mA)
10-1 104
103
1 102
10
006aad195
1
10-1
102
10
103
RCEsat
(Ω)
10-2
(1)
(2)
(3)
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
Fig. 17. TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 14 / 21
006aad196
200
400
600
hFE
0
IC (mA)
-10-1 -104
-103
-1 -102
-10
(1)
(2)
(3)
VCE = −2 V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 18. TR2 (PNP): DC current gain as a function of
collector current; typical values
VCE (V)
0 -5-4-2 -3-1
006aad197
-1
-2
-3
IC
(A)
0
IB= -30 mA -27 -24 -21
-18
-15
-12
-9
-6
-3
Tamb = 25 °C
Fig. 19. TR2 (PNP): Collector current as a function of
collector-emitter voltage; typical values
006aad198
-0.4
-0.8
-1.2
VBE
(V)
0
IC (mA)
-10-1 -104
-103
-1 -102
-10
(1)
(2)
(3)
VCE = −2 V
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 20. TR2 (PNP): Base-emitter voltage as a function
of collector current; typical values
006aad199
-0.6
-0.8
-0.4
-1.0
-1.2
VBEsat
(V)
-0.2
IC (mA)
-10-1 -104
-103
-1 -102
-10
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 21. TR2 (PNP): Base-emitter saturation voltage as a
function of collector current; typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 15 / 21
006aad200
-10-1
-10-2
-1
VCEsat
(V)
-10-3
IC (mA)
-10-1 -104
-103
-1 -102
-10
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 22. TR2 (PNP): Collector-emitter saturation voltage
as a function of collector current; typical values
006aad201
IC (mA)
-10-1 -104
-103
-1 -102
-10
-10-2
-10-1
-1
-10
VCEsat
(V)
-10-3
(1)
(2)
(3)
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
Fig. 23. TR2 (PNP): Collector-emitter saturation voltage
as a function of collector current; typical values
006aad202
IC (mA)
-10-1 -104
-103
-1 -102
-10
1
10
102
103
RCEsat
(Ω)
10-1
(1)
(2)
(3)
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 24. TR2 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
IC (mA)
-10-1 -104
-103
-1 -102
-10
006aad203
1
10-1
102
10
103
RCEsat
(Ω)
10-2
(1)
(2)
(3)
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB= 10
Fig. 25. TR2 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 16 / 21
11. Test information
Fig. 26. TR1 (NPN): BISS transistor switching time definition
Fig. 27. TR1 (NPN): Test circuit for switching times
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 17 / 21
Fig. 28. TR2 (PNP): BISS transistor switching time definition
Fig. 29. TR2 (PNP): Test circuit for switching times
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 18 / 21
12. Package outline
10-05-31Dimensions in mm
0.04
max
0.65
max
0.77
0.57
(2×)
0.54
0.44
(2×)
2.1
1.9
2.1
1.9
1.1
0.9
0.3
0.2
0.65
(4×)
0.35
0.25
(6×)
43
1 6
Fig. 30. Package outline DFN2020-6 (SOT1118)
13. Soldering
sot1118_fr
Dimensions in mm
solder paste
solder resist
occupied area
solder lands
0.49 0.49
0.650.65
0.875
0.875
2.25
0.35
(6×)
0.3
(6×)
0.4
(6×)
0.45
(6×)
0.72
(2×)
0.82
(2×)
1.05
(2×)
1.15
(2×)
2.1
Fig. 31. Reflow soldering footprint for DFN2020-6 (SOT1118)
14. Revision history
Table 8. Revision history
Data sheet ID Release date Data sheet status Change notice Supersedes
PBSS4230PANP v.1 20121214 Product data sheet - -
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 19 / 21
15. Legal information
15.1 Data sheet status
Document
status [1][2]
Product
status [3]
Definition
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
15.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 20 / 21
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
NXP Semiconductors PBSS4230PANP
30 V, 2 A NPN/PNP low VCEsat (BISS) transistor
PBSS4230PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 14 December 2012 21 / 21
16. Contents
1 General description ............................................... 1
2 Features and benefits ............................................1
3 Applications ........................................................... 1
4 Quick reference data ............................................. 1
5 Pinning information ............................................... 2
6 Ordering information ............................................. 2
7 Marking ................................................................... 2
8 Limiting values .......................................................2
9 Thermal characteristics .........................................4
10 Characteristics ....................................................... 9
11 Test information ................................................... 16
11.1 Quality information .........................................
12 Package outline ................................................... 18
13 Soldering .............................................................. 18
14 Revision history ...................................................18
15 Legal information .................................................19
15.1 Data sheet status ............................................... 19
15.2 Definitions ...........................................................19
15.3 Disclaimers .........................................................19
15.4 Trademarks ........................................................ 20
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 December 2012
