DS-CPC7593 - R02 www.clare.com 1
Features
•TTL logic level inputs for 3.3V logic interfaces
•Smart logic for power up / hot plug state control
•Improved switch dv/dt immunity of 500 V/µs
•Small 20 pin or 28 pin SOIC or 28 pin
micro-leadframe (MLP) package
•MLP version provides 65% PCB area reduction over
4th generation EMRs
•Monolithic IC reliability
•Low, matched, RON
•Eliminates the need for zero-cross switching
•Flexible switch timing for transition from ringing
mode to talk mode.
•Clean, bounce-free switching
•SLIC tertiary protection via integrated current
limiting, voltage clamping and thermal shutdown
•5 V operation with power consumption < 10.5 mW
•Intelligent battery monitor
•Logic-level inputs, no external drive circuitry required
Applications
•Standard voice linecards
•Integrated Voice and Data (IVD) linecards
•Central office (CO)
•Digital Loop Carrier (DLC)
•PBX Systems
•Digitally Added Main Line (DAML)
•Hybrid Fiber Coax (HFC)
•Fiber in the Loop (FITL)
•Pair Gain System
•Channel Banks
Description
The CPC7593 is a member of Clare’s next generation
Line Card Access Switch (LCAS) family. This
monolithic 10-pole line card access switch is available
in a 20 or 28 pin SOIC or a 28 pin MLP package. It
provides the necessary functions to replace three
2-Form-C electromechanical relays on analog line
cards or combined voice and data line cards found in
central office, access, and PBX equipment. The
device contains solid state switches for tip and ring line
break, ringing injection and test access. The CPC7593
requires only a +5 V supply and provides stable start
up conditioning during system power up and for hot
plug insertion applications. Once active, the inputs
respond to traditional TTL logic levels enabling the
CPC7593 to be used with 3.3V only logic.
Ordering Information
For delivery in tubes, specify CPC7593Zx for the 20
pin SOIC (38/tube), CPC7593Bx for the 28 pin SOIC
(27/tube), or CPC7593Mx for the MLP (54/tube). For
tape and reel delivery, add “TR”, sans quotes to the
part number. SOIC: 20 or 28 pin (500/reel), MLP
(1000/reel).
Part Number Description
CPC7593xA With protection SCR
CPC7593xB Without protection SCR
CPC7593xC Extra logic state and protection SCR
CPC7593xD Extra logic state but without protection SCR
CPC7593
T
LINE
R
LINE
T
BAT
V
DD
R
BAT
D
GND
V
BAT
F
GND
V
REF
IN
TESTin
IN
RINGING
IN
TESTout
T
SD
LATCH
7
10 8 5
22
6
12
13
14
28
124
2019
23
17
16
15
18
L
A
T
C
H
Switch
Control
Logic
SCR
Tr i p
Circuit
+5 Vdc
SLIC
Secondary
Protection
X
X
X
X
X
X
XX
XSW5
SW7
SW6
SW2
SW4 SW10
SW8
T
TESTin
(T )
CHANTEST
T
TESTout
(T )
DROPTEST
R
TESTout
(R )
DROPTEST
R
TESTin
(R )
CHANTEST
T
RINGING
SW3 SW9
SW1
300 (min.)Ω
RINGING
V
BAT
X
Tip
Ring
NOTE 1: Pin assignments are for the 28 pin package.
NOTE 2: Block diagram shown with the optional protection SCR.
R
RINGING
CPC7593
Line Card Access Switch
CPC7593
2 www.clare.com R02
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6.4 TESTout Switches, SW5 and SW6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.5 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6.6 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6.7 TESTin Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.10 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.10.1 Truth Table for CPC7593xA and CPC7593xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.10.2 Truth Table for CPC7593xC and CPC7593xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Under Voltage Switch Lock Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.3 Make-Before-Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.4 Make-Before-Break Operation Logic Table (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.5 Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.6 Break-Before-Make Operation Logic Table (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.7 Alternate Break-Before-Make Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.8 Alternate Break-Before-Make Operation Logic Table (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.10 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1 CPC7593Z - 20 Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.2 CPC7593B - 28 Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3 CPC7593M - 28 Pin MLP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 CPC7593Z - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 CPC7593B - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 CPC7593M - Tape and Reel Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CPC7593
R02 www.clare.com 3
1. Specifications
1.1 Package Pinout 1.2 Pinout
CPC7593B &
CPC7593M
TBAT
FGND
DGND
TTESTin
IN TESTin
R
TTESTout
INTESTout
RTESTout
TLINE
TRINGING
VDD
T
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD
VBAT
RBAT
TESTin
RLINE
RRINGING
LATCH
INRINGING
27
26
25
24
23
22
21
20
19
18
17
16
15
28
1
3
4
5
6
7
8
2
9
10
11
12
13
14
INTESTout
INRINGING
INTESTin
LATCH
RTESTout
RRINGING
RLINE
RBAT
RTESTin
VBAT
DGND
TSD
VDD
NC
TTESTout
TRINGING
TLINE
TBAT
TTESTin
FGND
CPC7593Z
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
Pin
28
Pin Name Description
11 FGND Fault ground.
2 NC No connection.
3 NC No connection.
4 NC No connection.
25 TTESTin Tip lead of the TESTin bus.
36 TBAT Tip lead of the SLIC.
47 TLINE Tip lead of the line side.
58
TRINGING Ringing generator return.
9 NC Not connected.
610TTESTout Tip lead of the TESTout bus.
7 11 NC No connection.
812 VDD +5 V supply.
913 TSD Temperature shutdown pin.
10 14 DGND Digital ground.
11 15 INTESTout Logic control input.
12 16 INRINGING Logic control input.
13 17 INTESTin Logic control input.
14 18 LATCH Data latch enable control input.
15 19 RTESTout Ring lead of the TESTout bus.
16 20 RRINGING Ringing generator source.
21 NC No connection.
17 22 RLINE Ring lead of the line side.
18 23 RBAT Ring lead of the SLIC.
19 24 RTESTin Ring lead of the TESTin bus.
25 NC No connection.
26 NC No connection.
27 NC No connection.
20 28 VBAT Battery supply.
CPC7593
4 www.clare.com R02
1.3 Absolute Maximum Ratings
Absolute maximum electrical ratings are at 25°C
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
1.4 ESD Rating
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements.
Typical values are characteristic of the device at 25°C
and are the result of engineering evaluations. They are
provided for informational purposes only and are not
part of the manufacturing testing requirements.
Specifications cover the operating temperature range
TA = -40°C to +85°C. Also, unless otherwise specified
all testing is performed with VDD = +5Vdc, logic low
input voltage is 0Vdc and logic high input voltage is
+5Vdc.
Parameter Minimum Maximum Unit
+5 V power supply (VDD)-0.3 7 V
Battery Supply - -85 V
DGND to FGND
separation -5 +5 V
Logic input voltage -0.3 VDD +0.3 V
Logic input to switch output
isolation -330V
Switch open-contact
isolation (SW1, SW2, SW3,
SW5, SW6, SW7, SW9,
SW10)
-330V
Switch open-contact
isolation (SW4) -465V
Switch open-contact
isolation (SW8) -250V
Operating relative humidity 5 95 %
Operating temperature -40 +110 °C
Storage temperature -40 +150 °C
ESD Rating (Human Body Model)
1000 V
CPC7593
R02 www.clare.com 5
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
+25° C
RON -
14.5 -
Ω+85° C 20.5 28
-40° C 10.5 -
On Resistance
Matching
Per SW1 & SW2 On Resistance test
conditions. ∆RON - 0.15 0.8 Ω
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 225
-
mA
VSW (on) = ±10 V, +85° C 80 150
VSW (on) = ±10 V, -40° C - 400 425
Dynamic current limit
(t ≤ 0.5 µs)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±320 V
ISW
-0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±330 V -0.3
-40° C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±310 V -0.1
dv/dt sensitivity - - - 500 - V/µs
CPC7593
6 www.clare.com R02
1.6.2 Ringing Return Switch, SW3
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW3 (differential) = TLINE to TRINGING
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW(on) = ±0 mA, ±10 mA, +25° C
RON -
60 -
Ω
ISW(on) = ±0 mA, ±10 mA, +85° C 85 110
ISW(on) = ±0 mA, ±10 mA, -40° C 45 -
DC current limit
VSW (on) = ± 10 V, +25° C
ISW
- 120
-mA
VSW (on) = ± 10 V, +85° C 70 85
VSW (on) = ± 10 V, -40° C - 210
Dynamic current limit
(t ≤ 0.5 µs)
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW (TRINGING, TLINE) = ±310 V 0.1
dv/dt sensitivity - -- 500 - V/µs
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1.6.3 Ringing Switch, SW4
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW4 (differential) = RLINE to RRINGING
All-Off state.
+25° C
VSW (differential) = -255 V to +210 V
VSW (differential) = +255 V to -210 V
ISW -
0.05
1µA
+85° C
VSW (differential) = -270 V to +210 V
VSW (differential) = +270 V to -210 V
0.1
-40° C
VSW (differential) = -245 V to +210 V
VSW (differential) = +245 V to -210 V
0.05
On Resistance ISW (on) = ±70 mA, ±80 mA RON -1015Ω
On Voltage ISW (on) = ± 1 mA VON -1.53 V
On-State
Leakage Current
Inputs set for ringing -Measure ringing
generator current to ground. IRINGING -0.10.25mA
Steady-State Current* Inputs set for ringing mode. ISW - - 150 mA
Surge Current*
Ringing switches on, all other switches
off. Apply ±1 kV 10x1000 µs pulse with
appropriate protection in place.
ISW --2A
Release Current SW4 transition from on to off. IRINGING - 450 - µA
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW (RRINGING, RLINE) = ±310 V 0.1
dv/dt sensitivity - - - 500 - V/µs
*Secondary protection and current limiting must prevent exceeding this parameter.
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1.6.4 TESTout Switches, SW5 and SW6
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW5 (differential) = TLINE to TTESTOUT
VSW6 (differential) = RLINE to RTESTOUT
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = +260 V to -60 V
0.3
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW (on) = ±10 mA, ±40 mA, +25° C
RON -
35 -
Ω
ISW (on) = ±10 mA, ±40 mA, +85° C 50 70
ISW (on) = ±10 mA, ±40 mA, -40° C 26 -
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 140 -
mA
VSW (on) = ±10 V, +85° C 80 100 -
VSW (on) = ±10 V, -40° C - 210 250
Dynamic current limit
(t ≤ 0.5 µs)
Test out switches on, all other switches
off. Apply ±1 kV, 10x1000 µs pulse with
appropriate protection in place.
ISW -2.5- A
Logic input to switch
output isolation
VSW5 (TTESTout, TLINE)
VSW6 (RTESTout, RLINE)
+25° C, Logic inputs = gnd,
VSW = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW = ±310 V 0.1
dv/dt sensitivity - - 500 - V/µs
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1.6.5 Ringing Test Return Switch, SW7
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage Current
VSW7 (differential) = TTESTin to
TRINGING
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW (on) = ±10 mA, ±40 mA, +25° C
RON -
60 -
Ω
ISW (on) = ±10 mA, ±40 mA, +85° C 85 100
ISW (on) = ±10 mA, ±40 mA, -40° C 45 -
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 120
-mA
VSW (on) = ±10 V, +85° C 60 80
VSW (on) = ±10 V, -40° C - 210
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TRINGING, TTESTin) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TRINGING, TTESTin) = ±330 V 0.3
-40° C, Logic inputs = gnd,
VSW (TRINGING, TTESTin) = ±310 V 0.1
dv/dt sensitivity - - 500 - V/µs
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1.6.6 Ringing Test Switch, SW8
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State
Leakage current
VSW8 (differential) = RTESTin to
RRINGING
All-Off state.
+25° C,
VSW (differential) = -60 V to +175 V
ISW -
0.05
1µA
+85° C,
VSW (differential) = -60 V to +175 V 0.1
-40° C,
VSW (differential) = -60 V to +175 V 0.05
On Resistance ISW(ON) = ±70 mA, ±80 mA RON -35-Ω
On Voltage ISW(ON) = ±1 mA VON - 0.75 1.5 V
Steady-State Current* Inputs set for ringing test mode. ISW - - 100 mA
Surge Current* Inputs set for ringing test mode. ISW --1A
Release Current SW4 transition from on to off. ISW - 450 - µA
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (RRINGING, RTESTin) = ±320 V,
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (RRINGING, RTESTin) = ±330 V, 0.3
-40° C, Logic inputs = gnd,
VSW (RRINGING, RTESTin) = ±310 V, 0.1
dv/dt sensitivity - - 500 - V/µs
*Protection and current limiting must prevent exceeding this parameter.
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1.6.7 TESTin Switches, SW9 and SW10
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-state leakage
current
VSW9 (differential) = TTESTin to TBAT
VSW10 (differential) = RTESTin to RBAT
All-Off state.
+25° C,
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
ISW -
0.1
1µA
+85° C,
VSW (differential) = -330 V to gnd
VSW (differential) =+270 V to -60 V
0.3
-40° C,
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
On Resistance
ISW (on) = ±10 mA, ±40 mA, +25° C
RON -
35 -
Ω
ISW (on) = ±10 mA, ±40 mA, +85° C 50 70
ISW (on) = ±10 mA, ±40 mA, -40° C 26 -
DC current limit
VSW (on) = ±10 V, +25° C
ISW
- 160 -
mA
VSW (on) = ±10 V, +85° C 80 110 -
VSW (on) = ±10 V, -40° C - 210 250
Logic input to switch
output isolation
+25° C, Logic inputs = gnd,
VSW (TTESTin, RTESTin) = ±320 V
ISW -
0.1
1µA
+85° C, Logic inputs = gnd,
VSW (TTESTin, RTESTin) = ±330 V 0.3
-40° C, logic inputs = gnd,
VSW (TTESTin, RTESTin) = ±310 V 0.1
dv/dt sensitivity - - 500 - V/µs
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1.7 Digital I/O Electrical Specifications
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Input Characteristics
Input voltage, Logic low Input voltage falling VIL 0.8 1.1 -
V
Input voltage, Logic high Input voltage rising VIH -1.72.0
Input leakage current,
INRINGING, INTESTin,
and INTESTout Logic high
VDD = 5.5 V, VBAT = -75 V, VIH = 2.4V IIH -0.11µA
Input leakage current,
INRINGING, INTESTin,
and INTESTout Logic low
VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL -0.11µA
Input leakage current,
LATCH Logic high VDD = 4.5 V, VBAT = -75 V, VIH = 2.4V IIH 719-µA
LATCH Pull-up
Minimum Load
VDD = 4.5 V, VBAT = -75 V, IIN = -10 µA
Latch input transitions to logic high. Logic = High True
Input leakage current,
LATCH Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL - 47 125 µA
Input leakage current,
TSD Logic high VDD = 5.5 V, VBAT = -75 V, VIH = VDD IIH 10 16 30 µA
Input leakage current,
TSD Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL 10 16 30 µA
Output Characteristics
Output voltage,
TSD Logic high VDD = 5.5 V, VBAT = -75 V, ITSD = 10µAV
TSD_off 2.4 VDD -V
Output voltage,
TSD Logic low VDD = 5.5 V, VBAT = -75 V, ITSD = 1mA VTSD_on -00.4V
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1.8 Voltage and Power Specifications
1.9 Protection Circuitry Electrical Specifications
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Voltage Requirements
VDD -VDD 4.5 5.0 5.5 V
VBAT
1 -VBAT -19 -48 -72 V
1VBAT is used only for internal protection circuitry. If VBAT rises above-10 V, the device will enter the all-off state and will remain in the all-off state until the battery
drops below -15 V
Power Specifications
Power consumption
VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V, Measure IDD and IBAT
,
Talk and All-Off States P - 4.7 10.5 mW
All other states P - 5.2 10.5 mW
VDD current in talk and
all-off states VDD = 5 V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V
IDD -0.92.0
mA
VDD current in all other
states
IDD -1.02.0
VBAT current in any state VDD = 5V, VBAT = -48 V, VIH = 2.4V,
VIL = 0.4V IBAT -410µA
Parameter Conditions Symbol Minimum Typical Maximum Unit
Protection Diode Bridge
Forward Voltage drop,
continuous current
(50/60 Hz)
Apply ± dc current limit of break
switches VF -2.83.5
V
Forward Voltage drop,
surge current
Apply ± dynamic current limit of break
switches VF -5-
Optional Protection SCR
Surge current - - - - * A
Trigger current:
Current into VBAT pin.
SCR activates, +25° C ITRIG -150 -mA
SCR activates, +85° C 80
Hold current: Current
through protection SCR
SCR remains active, +25° C IHOLD
- 220 -mA
SCR remains active, +85° C 110 145
Gate trigger voltage IGATE = ITRIGGER
§
VTBAT or
VRBAT
VBAT -4 -VBAT -2 V
Reverse leakage current VBAT = -48 V IVBAT --1.0µA
On-state voltage 0.5 A, t = 0.5 µsV
TBAT or
VRBAT
--3 -V
2.0 A, t = 0.5 µs-5
Temperature Shutdown Specifications
Shutdown activation
temperature Not production tested - limits are
guaranteed by design and Quality
Control sampling audits.
TTSD_on 110 125 150 °C
Shutdown circuit
hysteresis TTSD_off 10 - 25 °C
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
§VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
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1.10 Truth Tables
1.10.1 Truth Table for CPC7593xA and CPC7593xB
1.10.2 Truth Table for CPC7593xC and CPC7593xD
State INRINGING INTESTin INTESTout Latch TSD
TESTin
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTout
Switches
Talk000
0
Z 1
Off On Off Off Off
TESTout 0 0 1 Off Off Off Off On
TESTin010 On Off Off Off Off
Simultaneous
TESTin and
TESTout
011 On Off Off Off On
Ringing 1 0 0 Off Off Off On Off
Ringing
Generator
Te s t
110 OffOff
On Off Off
Latched X X X 1 Unchanged Unchanged Unchanged Unchanged Unchanged
All-Off
1 0 1 0 Off Off Off Off Off
1 1 1 0 Off Off Off Off Off
X X X X 0 Off Off Off Off Off
1 Z = High Impedance. If TSD is tied high, thermal shutdown is disabled, therefore TSD must be allowed to float for the thermal shutdown mechanism function normally.
State INRINGING INTESTin INTESTout Latch TSD
TESTin
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTout
Switches
Talk000
0
Z 1
Off On Off Off Off
TESTout 0 0 1 Off Off Off Off On
TESTin010 On Off Off Off Off
Simultaneous
TESTin and
TESTout
011 On Off Off Off On
Ringing 1 0 0 Off Off Off On Off
Ringing
Generator
Te s t
110 OffOff
On Off Off
Simultaneous
TESTout and
Ringing
Generator
Te s t
111 OffOff
On Off On
Latched X X X 1 Unchanged Unchanged Unchanged Unchanged Unchanged
All-Off 1 0 1 0 Off Off Off Off Off
X X X X 0 Off Off Off Off Off
1 Z = High Impedance. If TSD is tied high, thermal shutdown is disabled, therefore TSD must be allowed to float for the thermal shutdown mechanism function normally.
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2. Functional Description
2.1 Introduction
The CPC7593 has the following states:
•Talk. Loop break switches SW1 and SW2 closed, all
other switches open.
•Ringing. Ringing switches SW3 and SW4 closed, all
other switches open.
•TESTout. Testout switches SW5 and SW6 closed,
all other switches open.
•Ringing generator test. SW7 and SW8 closed, all
other switches open.
•TESTin. Testin switches SW9 and SW10 closed, all
other switches open.
•Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
•Simultaneous TESTout and Ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
•All-Off. All switches open.
See “Truth Tables” on page 14 for more information.
The CPC7593 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via TTL
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low RON and excellent
matching characteristics. The ringing switch, SW4,
has a minimum open contact breakdown voltage of
465 V at +25°C, sufficiently high with proper protection
to prevent breakdown in the presence of a transient
fault condition (i.e., passing the transient on to the
ringing generator).
Integrated into the CPC7593 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7593 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the TLINE and RLINE terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7593
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7593 operates from a single +5 V supply
only. This gives the device extremely low idle and
active power consumption with virtually any range of
battery voltage. The battery voltage used by the
CPC7593 has a two fold function. For protection
purposes it is used as a fault condition current source
for the internal integrated protection circuitry.
Secondly, it is used as a reference so that in the event
of battery voltage loss, the CPC7593 will enter the
all-off state.
2.2 Under Voltage Switch Lock Out Circuitry
2.2.1 Introduction
Smart logic in the CPC7593 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising VDD and
when to assert the under voltage switch lock out
circuitry with a falling VDD. Any time unsatisfactory low
VDD conditions exist, the lock out circuit overrides user
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the all-off state. Upon restoration of
VDD, the switches will remain in the all-off state until
the LATCH input is pulled low.
The rising VDD switch lock-out release threshold is
internally set to ensure all internal logic is properly
biased and functional before accepting external switch
commands from the inputs to control the switch states.
For a falling VDD event, the lock-out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
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To facilitate hot plug insertion and system power up
state control, the LATCH pin has an integrated weak
pull up resistor to the VDD power rail that will hold a
non-driven LATCH pin at a logic high state. This
enables board designers to use the CPC7593 with
FPGAs and other devices that provide high
impedance outputs during power up and logic
configuration. The weak pull up allows a fan out of up
to 32 when the system’s LATCH control driver has a
logic low minimum sink capability of 4mA.
2.2.2 Hot Plug and Power Up Circuit Design
Considerations
There are six possible start up scenarios that can
occur during power up. They are:
1. All inputs defined at power up & LATCH = 0
2. All inputs defined at power up & LATCH = 1
3. All inputs defined at power up & LATCH = Z
4. All inputs not defined at power up & LATCH = 0
5. All inputs not defined at power up & LATCH = 1
6. All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7593 will hold all of it’s switches in the all-off state
during power up. When VDD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7593 will transition
from the all-off state to the state defined by the inputs
when VDD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7593 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all-off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid VDD the
LCAS will revert to any one of the legitimate states
listed in the truth tables and there after may randomly
change states based on input pin leakage currents
and loading. Because the LCAS state after power up
can not be predicted with this start up condition it
should never be utilized.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.3 Switch Logic
2.3.1 Start-up
The CPC7593 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state. An internal pullup on the LATCH pin
locks the CPC7593 in the all-off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3.2 Switch Timing
The CPC7593 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the break switches SW1 and
SW2 using simple TTL logic-level inputs. The two
available techniques are referred to as
make-before-break and break-before-make operation.
When the switch contacts of SW1 and SW2 are closed
(made) before the ringing switch contacts of SW3 and
SW4 are opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made). With
the CPC7593, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
The logic sequences for either mode of operation are
given in “Make-Before-Break Operation Logic Table
(Ringing to Talk Transition)” on page 17,
“Break-Before-Make Operation Logic Table (Ringing to Talk
Transition)” on page 17 and “Alternate Break-Before-Make
Operation Logic Table (Ringing to Talk Transition)” on
page 18. Logic states and explanations are shown in
“Truth Tables” on page 14.
2.3.3 Make-Before-Break Operation
To use make-before-break operation, change the logic
inputs from the ringing state directly to the talk state.
Application of the talk state opens the ringing return
switch, SW3, as the break switches SW1 and SW2
close. The ringing switch, SW4, remains closed until
the next zero-crossing of the ringing current. While in
the make-before-break state, ringing potentials in
excess of the CPC7593 protection circuitry thresholds
will be diverted away from the SLIC.
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2.3.4 Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
2.3.5 Break-Before-Make Operation
Break-before-make operation of the CPC7593 can be
achieved using two different techniques.
The first method uses manipulation of the (INRINGING,
INTESTin, INTESTout) logic inputs as shown in
“Break-Before-Make Operation Logic Table (Ringing to Talk
Transition)” on page 17.
1. At the end of the ringing state apply the all-off
state (1,0,1). This releases the ringing return
switch (SW3) while the ringing switch remains on
waiting for the next zero current event.
2. Hold the all-off state for at least one-half of a
ringing cycle to assure that a zero crossing event
occurs and that the ringing switch (SW4) has
opened.
3. Apply inputs for the next desired state. For the
talk state, the inputs would be (0,0,0).
Break-before-make operation occurs when the ringing
switch opens before the break switches SW1 and
SW2 close.
2.3.6 Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
2.3.7 Alternate Break-Before-Make Operation
The second break-before-make method is also
available for use with all versions of the CPC7593. As
shown in “Truth Table for CPC7593xA and CPC7593xB” on
page 14 and “Truth Table for CPC7593xC and CPC7593xD”
on page 14, the bi-directional TSD interface disables all
of the CPC7593 switches when pulled to a logic low.
State INRINGING INTESTin INTESTout Latch TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0 0
0Z
-Off
On On Off
Make-
Before-
Break
000
SW4 waiting for next
zero-current crossing to turn
off. Maximum time is one-half
of the ringing cycle. In this
transition state, current that is
limited to the break switch dc
current limit value will be
sourced from the ring node of
the SLIC.
On Off On Off
Ta l k 0 0 0 Zero-cross current has
occurred On Off Off Off
State INRINGING INTESTin INTESTout Latch TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0 0
0Z
-Off
On On Off
All-off * 101
Hold this state for at least
one-half of ringing cycle.
SW4 waiting for zero current
to turn off.
Off Off On Off
Break-
Before-
Make *
101 Zero current has occurred.
SW4 has opened Off Off Off Off
Talk 0 0 0 Break switches close. On Off Off Off
* For the CPC7593xA/B versions the input pattern (1,1,1) may also be used for the all-off state.
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Although logically disabled, an active (closed) ringing
switch (SW4) will remain closed until the next current
zero crossing event.
As shown in the table “Break-Before-Make Operation
Logic Table (Ringing to Talk Transition)” on page 17, this
operation is similar to the one shown in “Alternate
Break-Before-Make Operation Logic Table (Ringing to Talk
Transition)” on page 18, except in the method used to
select the all-off state and when the INRINGING,
INTESTin and INTESTout inputs are reconfigured for the
talk state.
1. Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3. During the TSD low period, set the INRINGING,
INTESTin and INTESTout inputs to the talk state
(0,0,0).
4. Release TSD allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0” which over rides logic input pins and
forces an all-off state and “Z” which allows switch
control via the logic input pins and operation of the
thermal shutdown mechanism. This requires the use
of an open-collector type buffer.
Forcing TSD to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
2.3.8 Alternate Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
2.4 Data Latch
The CPC7593 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch are via the input pins, while the output of the data
latch are internal nodes used for state control. When
the LATCH enable control pin is at logic 0 the data
latch is transparent and the input data control signals
flow directly through the latch to the state control
circuitry. A change in input will be reflected by a
change in switch state. Whenever the LATCH enable
control pin is at logic 1, the latch is active and data is
locked. Subsequent input changes will not result in a
change to the control logic or affect the existing switch
state.
Switches will remain in the state they were in when the
LATCH pin changes from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. However, neither the TSD input nor the TSD
output control functions are affected by the latch
function. Since internal thermal shutdown control and
external “All-off” control is not affected by the state of
the LATCH enable input, TSD will override state
control.
State INRINGING INTESTin INTESTout Latch TSD Timing Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0 0 0 Z - Off On On Off
All-off 1 0 1
X0
Hold this state for at least
one-half of ringing cycle.
SW4 waiting for zero current
to turn off.
Off Off On Off
Break-
Before-
Make
000 Zero current has occurred.
SW4 has opened Off Off Off Off
Talk 0 0 0 0 Z Break switches close. On Off Off Off
CPC7593
R02 www.clare.com 19
2.5 TSD Pin Description
The TSD pin is a bi-directional I/O structure with an
internal pull up sourced from VDD. As an output, this
pin indicates the status of the thermal shutdown
circuitry. Typically, during normal operation, this pin will
be pulled up to VDD but under fault conditions that
create excess thermal loading the CPC7593 will enter
thermal shutdown and a logic low will be output.
As an input, the TSD pin can be utilized to place the
CPC7593 into the “All-Off” state by simply pulling the
input low via an open collector type buffer. Using a
standard output with an active drive logic high
capability may disable the thermal shutdown
mechanism. Without the ability to enter thermal
shutdown during a fault condition, permanent damage
to the CPC7593 will occur.
Under no circumstances should the TSD pin be pulled
high via an external device. The CPC7593’s internal
pull up has a nominal value of 16µA.
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See Clare application note AN-144,
Impulse Noise Benefits of Line Card Access Switches for
more information. The attributes of ringing switch SW4
may make it possible to eliminate the need for a
zero-cross switching scheme. A minimum impedance
of 300 Ω in series with the ringing generator is
recommended.
2.7 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7593. Switch state control is powered
exclusively by the +5 V supply. As a result, the
CPC7593 exhibits extremely low power consumption
during active and idle states.
Although battery power is not used for switch control, it
is required to supply trigger current for the integrated
internal protection circuitry SCR during fault
conditions. This integrated SCR is designed to
activate whenever the voltage at TBAT or RBAT drops 2
to 4 V below the applied voltage on the VBAT pin.
Because the battery supply at this pin is required to
source trigger current during negative overvoltage
fault conditions at tip and ring, it is important that the
net supplying this current be a low impedance path for
high speed transients such as lightning. This will
permit trigger currents to flow enabling the SCR to
activate and thereby prevent a fault induced negative
overvoltage event at the TBAT or RBAT nodes.
2.8 Battery Voltage Monitor
The CPC7593 also uses the VBAT pin to monitor
battery voltage. If the system battery voltage is lost,
the CPC7593 immediately enters the all-off state. It
remains in this state until the system battery voltage is
restored. The device also enters the all-off state if the
battery voltage rises more positive than about –10 V
and remains in the all-off state until the battery voltage
drops below –15 V. This battery monitor feature draws
a small current from the battery (less than 1 µA
typical) and will add slightly to the device’s overall
power dissipation.
This monitor function performs properly if the
CPC7593 and SLIC share a common battery supply
origin. Otherwise, if battery is lost to the CPC7593 but
not to the SLIC, then the VBAT pin will be internally
biased by the potential applied at the TBAT or RBAT
pins via the internal protection circuitry SCR trigger
current path.
2.9 Protection
2.9.1 Diode Bridge/SCR
The CPC7593 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
FGND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage source at VBAT
, the SCR
conducts and faults are shunted to FGND via the SCR
or the diode bridge.
In order for the SCR to crowbar or foldback, the SCR’s
on-voltage (see “Protection Circuitry Electrical
Specifications” on page 13) must be less than the
applied voltage at the VBAT pin. If the VBAT voltage is
less negative than the SCR on-voltage, or if the VBAT
supply is unable to source the trigger current, the SCR
will not crowbar.
CPC7593
20 www.clare.com R02
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current is directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
VBAT reference voltage by two to four volts, steering
the fault current to ground.
Note: Neither the CPC7593xB or the CPC7593xD
contains the protection SCR but instead uses a diode
bridge to clamp both polarities of a fault transient.
These diodes direct the negative potential’s fault
current to the VBAT pin.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state when a 1000V 10x1000 µS pulse
(GR-1089-CORE lightning) is applied to the line
though a properly clamped external protector, the
current seen at TLINE or RLINE will be a pulse with a
typical magnitude of 2.5 A and a duration of less than
0.5 µs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though the break switches
SW1 and SW2 on to the integrated protection circuit
but is limited by the dynamic DC current limit response
of the two break switches. The DC current limit
specified over temperature is between 80 mA and 425
mA, and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power cross fault condition,
the measured current into TLINE or RLINE will decrease
as the device temperature increases. If the device
temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
2.10 Thermal Shutdown
The thermal shutdown mechanism will activate when
the device die temperature reaches a minimum of
110° C, placing the device in the all-off state
regardless of INRINGING, INTESTin and INTESTout logic
inputs. During thermal shutdown events the TSD pin
will output a logic low with a nominal 0 V level. A logic
high is output from the TSD pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the all-off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the die drops below the
deactivation level of the thermal shutdown circuit. This
permits the device to return to normal operation. If the
transient has not passed, current will again flow up to
the value allowed by the dynamic DC current limiting
of the switches and heating will resume, reactivating
the thermal shutdown mechanism. This cycle of
entering and exiting the thermal shutdown mode will
continue as long as the fault condition persists. If the
magnitude of the fault condition is great enough, the
external secondary protector will activate shunting the
fault current to ground.
The thermal shutdown mechanism of the CPC7593
will be disabled by forcing a logic 1 to TSD. Therefore,
only an open-collector or open-drain type interface
should be used to control the TSD pin’s input function.
2.11 External Protection Elements
The CPC7593 requires only over voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7593. A foldback or crowbar type protector is
recommended to minimize stresses on the CPC7593.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
CPC7593
R02 www.clare.com 21
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 CPC7593Z - 20 Pin SOIC Package
DIMENSIONS
MM
(INCHES)
0.40 MIN - 1.27 MAX
(0.016 MIN - 0.050 MAX)
0.25 MIN - 0.75 MAX X 45°
(0.010 MIN - 0.029 MAX X 45°)
0.23 MIN - 0.32 MAX
(0.009 MIN - 0.013 MAX)
0°-8°
PIN 1
PIN 20
10.00 MIN - 10.65 MAX
MAX)(0.394 MIN - 0.419
7.40 MIN - 7.60 MAX
MAX)(0.291 MIN - 0.299
0.10 MIN - 0.30 MAX
(0.004 MIN - 0.012 MAX)
0.33 MIN - 0.51 MAX
(0.013 MIN - 0.020 MAX)
1.27 TYP
(0.050 TYP)
0.508 MAX - 0.762 MAX
MAX)(0.020 MIN - 0.030
12.60 MIN - 13.00 MAX
MAX)(0.496 MIN - 0.512
2.35 MIN - 2.65 MAX
(0.093 MIN - 0.104 MAX)
CPC7593
22 www.clare.com R02
3.1.2 CPC7593B - 28 Pin SOIC Package
3.1.3 CPC7593M - 28 Pin MLP Package
NOTE: For optimum solder joint size, MLP package
printed circuit board lands should extend no more than
0.05 mm past the chip post on the short sides, and no
more than 0.025 mm past the chip posts on the long
sides.
As the metallic pad on the bottom of the MLP package
is connected to the substrate of the die, Clare
recommends that no printed circuit board traces cross
this area to avoid potential shorting issues.
DIMENSIONS
MM
(INCHES)
7.391 MIN/7.595 MAX
(0.291 MIN/0.299 MAX)
10.109 MIN/10.516 MAX
(0.398 MIN/0.414 MAX)
17.983 MIN/18.085 MAX
(0.708 MIN/0.712 MAX)
1.270 TYP
(0.050 TYP)
PIN 28
PIN 1
0.508 MIN/1.016 MAX)
(0.020 MIN/0.040 MAX)
0.2311 MIN/0.3175 MAX
(0.0091 MIN/0.0125MAX)
0.254 MIN/0.737 MAX X 45°
(0.010 MIN/0.029 MAX X 45°)
2.235 MIN/2.438 MAX
(0.088 MIN/0.096 MAX)
0.366 MIN/0.467 MAX TYP
(0.014 MIN/0.018 MAX TYP)
2.438 MIN/2.642 MAX
(0.096 MIN/0.104 MAX)
0.660±0.102
(0.026±0.004)
0.37
(0.0146)
Pin 1
TOP VIEW
SIDE VIEW
Seating Plane
Dimensions in mm (inches)
Dimensions and tolerances conform to ANSI Y14.5M-1994
11.0
(0.4334)
7.0
(0.2758)
0.90 ± 0.10
(0.0355 ±0.0039)
0.02 +0.03/-0.02
(0.0008 +0.0012/-0.0008)
0.20
(0.0079)
Bottom side
metallic pad
0.75
(0.0295)
0.33 +0.07/
(0.0130 +0.0028/ )
-0.05
-0.0020
0.55 ± 0.10
(0.0217 0.0040)±
0.60
(0.0236)
0.70
(0.0276)
0.18
(0.0071)
0.18
(0.0071)
0.61
(0.0240)
BOTTOM VIEW
5.0±0.05
(0.1970±0.0020)
7.5 ± 0.05
(0.2955 ± 0.0020)
CPC7593
R02 www.clare.com 23
3.2 Tape and Reel Specifications
3.2.1 CPC7593Z - Tape and Reel Dimensions
3.2.2 CPC7593B - Tape and Reel Dimensions
3.2.3 CPC7593M - Tape and Reel Dimensions
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=3.20 0.15
(0.13 0.01)
+
+
K1=2.60 0.15
(0.10 0.01)
+
+
P=12.00
(0.47)
A0=10.75 0.15
(0.42 0.01)
+
+
B0=13.40 0.15
(0.53 0.01)
+
+
W=24.00 0.3
(0.94 0.01)
+
+
A0=10.75
(0.42)
B0=18.50
(0.73)
W=24.00±0.3
(0.94±0.01)
K1=2.60
(0.10)
K0=3.20
(0.13)
P=12.00
(0.47)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=1.35
(0.05)
P=12.00
(0.47)
A0=7.35
(0.29)
B0=11.35
(0.45)
W=24.00 0.3
(0.94 0.01)
+
+
CPC7593
24 www.clare.com R02
3.3 Soldering
3.3.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
of LCAS products using IPC/JEDEC standard
J-STD-020. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-020 per
the labelled moisture sensitivity level (MSL), Level 1
for the SOIC packages, and Level 3 for the MLP
package.
3.3.2 Reflow Profile
Recommended soldering processes are limited to
245°C component body temperature for 10 seconds.
3.4 Washing
Clare does not recommend ultrasonic cleaning of
LCAS parts
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC7593-R02
© Copyright 2004, Clare, Inc.
All rights reserved. Printed in USA.
11/17/2004
