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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−40°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
D10-Bit Resolution A/D Converter
D11 Analog Input Channels
DThree Built-In Self-Test Modes
DInherent Sample-and-Hold Function
DTotal Unadjusted Error . . . ±1 LSB Max
DOn-Chip System Clock
DEnd-of-Conversion (EOC) Output
DTerminal Compatible With TLC542
DCMOS Technology
description
The TLC1542-EP and TLC1543-EP are CMOS 10-bit switched-capacitor successive-approximation
analog-to-digital converters. These devices have three inputs, a 3-state output chip select (CS), input/output
clock (I/O CLOCK), address input (ADDRESS), and data output (DATA OUT)] that provide a direct 4-wire
interface to the serial port of a host processor. The TLC1542-EP and TLC1543-EP allow high-speed data
transfers from the host.
In addition to a high-speed A/D converter and versatile control capability, the TLC1542-EP and TLC1543-EP
have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal
self-test voltages. The sample-and-hold function is automatic. At the end of the A/D conversion, the
end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated
in the TLC1542-EP and TLC1543-EP features differential high-impedance reference inputs that facilitate
ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A
switched-capacitor design allows low-error conversion over the full operating free-air temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range
.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST
,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of thi
s
component beyond specified performance and environmental limits.
!"#$%& !%&'% %()#'&% % *)"!& % #)$ &'% %$ *'$
( $+$,*#$%&- $ &'&" ( $'! $+!$ %!'&$ % &$ *'.$/0
*$!(1%. & $,$!&)!', !')'!&$)&!-
Copyright 2006, Texas Instruments Incorporated
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20
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15
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11
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
EOC
I/O CLOCK
ADDRESS
DATA OUT
CS
REF+
REF−
A10
A9
DW PACKAGE
(TOP VIEW)
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AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
(DW)
−40°C to 125°C
TLC1542QDWREP{
−40°C to 125°CTLC1543QDWREP
†This part number is in the product preview stage
of development.
functional block diagram
14-Channel
Analog
Multiplexer
4
10
10
4
REF+ REF−
DATA
OUT
ADDRESS
I
/O CLOCK
CS
3
EOC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
2
3
4
5
6
7
8
9
11
12
18
15
17
19
16
14 13
10-Bit
Analog-to-Digital
Converter
(Switched Capacitors)
Sample and
Hold
Input Address
Register
Self-Test
Reference
Output
Data
Register
System
Clock,
Control Logic,
and I/O
Counters
10-to-1 Data
Selector and
Driver
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
Ci = 60 pF TYP
(equivalent input
capacitance)
5 MΩ TYP
A0−A10 A0−A10
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
ADDRESS 17 I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be
converted next. The address data is presented with the MSB first and shifts in on the first four rising edges
of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for
the remainder of the current conversion period.
A0−A10 1−9,
11, 12 I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The
driving source impedance should be less than or equal to 1 kΩ.
CS 15 I Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA
OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal
system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling
edges of the internal system clock.
DATA OUT 16 O The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DAT A OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant
bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK.
On the tenth falling edge of I/O CLOCK, DAT A OUT is driven to a low logic level so that serial interface data
transfers of more than ten clocks produce zeroes as the unused LSBs.
EOC 19 O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data is ready for transfer.
GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to this terminal.
I/O CLOCK 18 I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK
with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF+ 14 I The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage
range is determined by the difference between the voltage applied to this terminal and the voltage applied
to the REF− terminal.
REF− 13 I The lower reference voltage value (nominally ground) is applied to this terminal.
VCC 20 I Positive supply voltage
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal o f D ATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.
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detailed description (continued)
There are six basic serial-interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are:
DA fast mode with a 10-clock transfer and CS inactive (high) between conversion cycles,
DA fast mode with a 10-clock transfer and CS active (low) continuously,
DA fast mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles,
DA fast mode with a 16-clock transfer and CS active (low) continuously,
DA slow mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and
DA slow mode with a 16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in
mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data
are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also
depends on the mode of operation, but a minimum of 10 clock pulses is required for the conversion to begin.
On the tenth clock falling edge, the EOC output goes low and returns to the high logic level when the conversion
is complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes
DATA OUT low, to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than
10 clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
MODES CS NO. OF
I/O CLOCKS MSB AT DATA OUT†TIMING
DIAGRAM
Mode 1 High between conversion cycles 10 CS falling edge Figure 9
Fast Modes
Mode 2 Low continuously 10 EOC rising edge Figure 10
Fast Modes Mode 3 High between conversion cycles 11 to 16‡CS falling edge Figure 11
Mode 4 Low continuously 16‡EOC rising edge Figure 12
Slow Modes
Mode 5 High between conversion cycles 11 to 16‡CS falling edge Figure 13
Slow Modes
Mode 6 Low continuously 16‡16th clock falling edge Figure 14
†These edges also initiate serial-interface communication.
‡No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the tenth I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is 10 clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning D ATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
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mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is 10 clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK and the rising edge of the eleventh clock must occur
before the conversion period is complete; otherwise, the device loses synchronization with the host-serial
interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or three internal test inputs).
analog inputs and test modes
The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according
to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
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analog inputs and test modes (continued)
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
ANALOG INPUT
SELECTED
BINARY HEX
A0 0000 0
A1 0001 1
A2 0010 2
A3 0011 3
A4 0100 4
A5 0101 5
A6 0110 6
A7 0111 7
A8 1000 8
A9 1001 9
A10 1010 A
Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
VALUE SHIFTED INTO
ADDRESS INPUT
OUTPUT RESULT (HEX)
‡
SELF-TEST
VOLTAGE
SELECTED†BINARY HEX
OUTPUT RESULT (HEX)‡
Vref+ − Vref−
21011 B 200
Vref− 1100 C 000
Vref+ 1101 D 3FF
†Vref+ is the voltage applied to the REF+ input, and Vref− is the voltage applied to the REF−
input.
‡The output results shown are the ideal values and vary with the reference stability and
with internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF−)
voltage. In the switching sequence, 10 capacitors are examined separately until all 10 bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF−. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half VCC), a 0 bit is placed in
the output register and the 512-weight capacitor is switched to REF−. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to R E F+ through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
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converter and analog input (continued)
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
SC
Threshold
Detector
Node 512
REF−
REF+
ST
512
VI
To Output
Latches
REF+REF+ REF+ REF+
124816128256 1
REF+ REF+
REF− REF− REF− REF− REF− REF− REF− REF−
STSTSTSTSTSTSTST
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation and can abort a conversion sequence in any mode. A
high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to the completion of the conversion, because the output
data can be corrupted.
reference voltage inputs
There are two reference inputs used with the device: REF+ and REF−. These voltage values establish the upper
and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+,
REF−, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF+ and at zero when the input signal is equal to or lower than REF−.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive reference voltage, Vref+ V
CC + 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative reference voltage, Vref− −0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF− and GND wired together (unless otherwise noted).
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5 5.5 V
Positive reference voltage, Vref+ (see Note 2) VCC V
Negative reference voltage, Vref− (see Note 2) 0 V
Differential reference voltage, Vref+ − V ref− (see Note 2) 2.5 VCC VCC+0.2 V
Analog input voltage (see Note 2) 0 VCC V
High-level control input voltage, VIH VCC = 4.5 V to 5.5 V 2 V
Low-level control input voltage, VIL VCC = 4.5 V to 5.5 V 0.8 V
Setup time, address bits at data input before I/O CLOCK↑, tsu(A) (see Figure 4) 100 ns
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) 0 ns
Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5) 0 ns
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5) 1.425 µs
Clock frequency at I/O CLOCK (see Note 4) 0 2.1 MHz
Pulse duration, I/O CLOCK high, twH(I/O) 190 ns
Pulse duration, I/O CLOCK low, twL(I/O) 190 ns
Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 6) 1µs
Transition time, ADDRESS and CS, tt(CS) 10 µs
Operating free-air temperature, TATLC1542-EP, TLC1543-EP −40 125 °C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF− convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ − V ref−); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH
High-level output voltage
VCC = 4.5 V, IOH = −1.6 mA 2.4
V
VOH High-level output voltage VCC = 4.5 V to 5.5 V, IOH = −20 µA VCC−0.1 V
VOL
Low-level output voltage
VCC = 4.5 V, IOL = 1.6 mA 0.4
V
VOL Low-level output voltage VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1 V
IOZ
Off-state (high-impedance state)
VO = VCC, CS at VCC 10
A
IOZ
Off-state (high-impedance state)
output current VO = 0, CS at VCC −10 µA
IIH High-level input current VI = VCC 0.005 2.5 µA
IIL Low-level input current VI = 0 −0.005 −2.5 µA
ICC Operating supply current CS at 0 V 0.8 2.5 mA
Selected channel leakage
current TLC1542-EP/
Selected channel at VCC,Unselected channel at 0 V 1
A
current TLC1542-EP/
TLC1543-EP Selected channel at 0 V, Unselected channel at VCC −1 µA
Maximum static analog
reference current into REF+ Vref+ = VCC, Vref− = GND 10 µA
Ci
Input
Analog inputs 7
pF
C
i
Input
capacitance Control inputs 5
pF
†All typical values are at VCC = 5 V, TA = 25°C.
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operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
EL
Linearity error (see Note 6)
TLC1542-EP ±0.5 LSB
ELLinearity error (see Note 6) TLC1543-EP ±1 LSB
EZS
Zero-scale error (see Note 7)
TLC1542-EP See Note 2 ±1 LSB
EZS Zero-scale error (see Note 7) TLC1543-EP See Note 2 ±1 LSB
EFS
Full-scale error (see Note 7)
TLC1542-EP See Note 2 ±1 LSB
EFS Full-scale error (see Note 7) TLC1543-EP See Note 2 ±1 LSB
Total unadjusted error (see Note 8)
TLC1542-EP ±1 LSB
Total unadjusted error (see Note 8) TLC1543-EP ±1 LSB
ADDRESS = 1011 512
Self-test output code (see Table 3 and Note 9) ADDRESS = 1100 0
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1101 1023
tconv Conversion time See timing diagrams 21 µs
tcTotal cycle time (access, sample, and conversion) See timing diagrams
and Note 10
21
+10 I/O
CLOCK
periods
µs
tacq Channel acquisition time (sample) See timing diagrams
and Note 10 6I/O
CLOCK
periods
tvValid time, DATA OUT remains valid after I/O CLOCK↓See Figure 6 10 ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 240 ns
td(I/O-EOC) Delay time, tenth I/O CLOCK↓ to EOC↓See Figure 7 70 240 ns
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB) See Figure 8 100 ns
tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 150 ns
tr(EOC) Rise time, EOC See Figure 8 300 ns
tf(EOC) Fall time, EOC See Figure 7 300 ns
tr(DATA) Rise time, data bus See Figure 6 300 ns
tf(DATA) Fall time, data bus See Figure 6 300 ns
td(I/O-CS) Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11) 9µs
†All typical values are at TA = 25°C.
NOTES: 6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
EOC
CL = 50 pF 12 kΩ
DATA OUT
Test Point VCC
RL = 2.18 kΩ
CL = 100 pF 12 kΩ
Test Point VCC
RL = 2.18 kΩ
Figure 2. Load Circuits
CS
DATA
OUT
2.4 V
0.4 V
90%
10%
tPZH, tPZL tPHZ, tPLZ
0.8 V
2 V
Figure 3. DATA OUT Enable and Disable
Voltage Waveforms
ADDRESS
th(A)
0.8 V
2 V
I/O CLOCK
Address
Valid
tsu(A)
0.8 V
Figure 4. ADDRESS Setup and Hold Time
Voltage Waveforms
Last
Clock
CS 0.8 V
2 V
0.8 V
tsu(CS)
0.8 V
I/O CLOCK
th(CS)
First
Clock
Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms
0.4 V
2.4 V
0.4 V
2.4 V
2 V 0.8 V
I/O CLOCK
DATA OUT
tt(I/O)
0.8 V
2 V
tr(DATA), tf(DATA)
td(I/O-DATA)
tv
tt(I/O)
0.8 V
I/O CLOCK Period
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10th
Clock 0.8 V
2.4 V 0.4 V
tf(EOC)
td(I/O-EOC)
I/O CLOCK
EOC
Figure 7. I/O CLOCK and EOC Voltage Waveforms
0.4 V
2.4 V
EOC
Valid MSB
DATA OUT
0.4 V 2.4 V
tr(EOC)
td(EOC-DATA)
Figure 8. EOC and DATA OUT Voltage Waveforms
timing diagrams
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval InitializeInitialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z State
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
(see Note A)
EOC
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed. Figure 9. Timing for 10-Clock Transfer Using CS
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
(see Note A)
Must be High on Power Up
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
ÎÎÎ
Low
Level Hi-Z
See Note B
11 16
(see Note A)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Must Be High on Power Up
14 15 16
See Note B
(see Note A)
ÎÎÎ
ÎÎÎ
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The first I/O CLOCK must occur after the rising edge of EOC.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
11
ÏÏÏ
ÏÏÏ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Hi-Z State
16
See Note B
ÏÏÏ
ÏÏÏ
Low
Level
(see Note A)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Î
Î
ÎÎÎ
ÎÎÎ
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Must be High on Power Up
14 15 16
See Note C
See Note B
Low Level
Access Cycle B
(see Note A)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
C. The I/O CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1000000000
0111111111
0000000010
0000000001
0000000000
1111111110
0 0.0096 2.4528 2.4576 2.4624
Digital Output Code
1000000001
1111111101
1111111111
4.9056 4.9104 4.9152
512
511
2
1
0
1022
Step
513
1021
1023
0.0024
VI − Analog Input Voltage − V
VZT =VZS + 1/2 LSB
VZS
See Notes A and B
4.9080
0.0048
VFT = VFS − 1/2 LSB
VFS
NOTES: A. This curve is based on the assumption that Vref+ and Vref− have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
Processor Control
Circuit
Analog
Inputs
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O CLOCK
CS
ADDRESS
DATA OUT
EOC
REF+
REF−
GND
TLC1542/43
To Source
Ground
5-V DC Regulator
1
2
3
4
5
6
7
8
9
11
12
15
18
17
16
19
14
13
10
Figure 16. Serial Interface
SGLS152A − JANUAR Y 2004 − REVISED FEBRUARY 2006
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by:
VC = VS 1−e
−t
c
/R
t
C
i
( )
(
1)
where R
t
= R
s
+ r
i
The final voltage to 1/2 LSB is given by:
(2)VC (1/2 LSB) = VS − (VS/2048)
Equating equation 1 to equation 2 and solving for time tc gives:
VS −(VS/2048) = VS 1−e
( )
(
3)
−t
c
/R
t
C
i
and t
c
(1/2 LSB) = R
t
× C
i
× ln(2048) (
4)
Therefore, with the values given the time for the analog input signal to settle is:
(5)
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams.
Rsri
VSVC
1 kΩ MAX
Driving Source†TLC1542/3
Ci
50 pF MAX
VI
VI= Input Voltage at A0−A10
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Equivalent Input Capacitance
†Driving source requirements:
•Noise and distortion for the source must be equivalent to the resolution of the converter.
•Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC1543QDWREP ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04647-01XE ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC1543-EP :
•Catalog: TLC1543
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC1543QDWREP SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC1543QDWREP SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 2
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