XC3000-FPGAS-(XC3000A/L,-XC3100A/L) - Xilinx, Inc.

November 9, 1998 (Version 3.1) 7-3

Features

• Complete line of four related Field Programmable Gate

Array prod u ct fam ilie s

- XC3000A, XC3000L, XC3100A, XC3100L

• Ideal for a wide ra nge of cus tom VLSI design tasks

- Replaces TTL, MSI, and othe r PLD logic

- Integrates complete sub-systems into a single

package

- Avoi ds the NR E, time de lay, and ri sk of c onvent iona l

masked gate arrays

• Hig h-performance CMOS static memory technology

- Guaranteed toggle rates of 70 to 370 MHz, logic

delays from 7 to 1.5 ns

- System clock speeds over 85 MHz

- Low quiescent and active power consumption

• Flexib le FPGA ar ch ite ctu re

- Compatible arr ays rang ing fr om 1,000 to 7,500 gate

complexity

- Extensive register, combinatorial, and I/O

capabilities

- High fan-out signal distribution, low-skew clock nets

- Internal 3-state bus capabilities

- TTL or CMOS input thresholds

- On-chip crystal oscillator amplifier

• Unlimited reprogrammability

- Easy design iteration

- In-system logic changes

• Extensive packaging options

- Over 20 different packages

- Plastic and cer amic surface- mount and pin-grid-

array pa ckages

- Thin and Very Thin Quad Flat Pack ( T QFP and

VQFP) options

• Ready for volume production

- Standard, off-the-shelf product availability

- 100% factory pre-tested devices

- Excellent reliability record

• Compl ete Development System

- Schema tic capture, automatic place and route

- Logic and timing simulation

- Interactive design editor for design optimization

- Timing calculato r

- Interfaces to po pular design environments li ke

Viewlogic, Cadence, Mentor Graphics, and others

Additional XC3100A F eatur es

• Ultra-h igh -s peed FPGA family with six memb e rs

- 50-85 MHz system clock rates

- 190 to 370 MHz guaranteed flip-flop toggle rates

- 1.55 to 4.1 ns logic delays

• High -end addi tional family member i n the 22 X 22 CLB

array-size XC3195A device

• 8 mA outp u t sink curren t an d 8 mA so ur ce cur re nt

• Maximum power-down and quiescent current is 5 mA

• 100% architecture and pin-out compatible with other

XC3000 families

• Soft ware and bitstream compatible with the XC3000,

XC3000A, and XC3000L families

XC3100A combines the features of the XC3000A and

XC3100 families:

• Additional interco nnect resources for TBUFs and CE

inputs

• Error checking of the configura tion bitstream

• Soft startup holds all outputs slew-rate limited during

initial powe r-up

• More advanced CMOS process

Low-Voltage Versions Availab le

• Low-voltage devices function at 3.0 - 3.6 V

• XC3000L - Low-voltage versions of XC3000A devices

• XC3100L - Low-voltage versions of XC3100A devices

0XC3000 Series

Field Programmable Gate Arrays

(XC3000A/L, XC3100A/L)

November 9, 1998 (Version 3.1) 07*

Produ ct Des cr ipt ion

Device Max Logic

Gates Typical Gate

Range CLBs Array User I/Os

Max Flip-Flops H oriz ontal

Longlines Configuration

Data Bits

XC3020A, 3020L, 3120A 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779

XC3030A, 3030L, 3130A 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176

XC3042A, 3042L, 3142A, 3142L 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784

XC3064A, 3064L, 3164A 4,500 3,500 - 4,500 224 16 x 14 120 688 32 46,064

XC3090A, 3090L, 3190A, 3190L 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160

XC3195A 7,500 6,500 - 7,500 484 22 x 22 176 1,320 44 94,984

XC3000 Series Field Programmable Gate Arrays

7-4 November 9, 1998 (Version 3.1)

Introduction

XC3000-Series Field Programmable Gate Arrays (FPGAs)

provide a group of high-performance, high-density, digital

integrated circuits. Their regular, extendable, flexible,

user-programmable array architecture is composed of a

configuration program store plus three types of config-

urable elements: a perimeter of I/O Blocks (IOBs), a core

array of Configurable Logic Bocks (CLBs) and resources

for interconnection. The general structure of an FPGA is

shown in Figure 2. The development system provides

schematic capture and auto place-and-route for design

entry. Logic and timing simulation, and in-circuit emulation

are ava ilabl e as desig n verifi cation altern atives. Th e desi gn

editor is used for interactive design optimization, and to

compile the data pattern that represents the configuration

program.

The FPGA user logic functions and interconnections are

determined by the configuration program data stored in

internal static memory cells . The program can be loaded in

any of several modes to accommodate various system

requirements. The program data resides externally in an

EEPROM, EPROM or ROM on the application circuit

boar d, or on a f lop py di sk o r har d dis k. On- chi p ini tial izat ion

logic provides for optional automatic loading of program

data at po wer-up. The companion XC17XX Serial C onfigu-

ration PROMs provide a very simple serial configuration

program storage in a one-time programmable package.

The XC30 00 Field Prog ramm able Ga te Array families p ro-

vide a variety of logic capacities, package styles, tempera-

ture ranges and speed grades.

XC3000 Series Overview

There are now four distinct family groupings within the

XC3000 Series of FPGA devices:

• XC3000A Family

• XC3000L Family

• XC3100A Family

• XC3100L Family

All four families share a common architecture, develop-

ment software, design and programming methodology, and

also common package pin-outs. An extensive Product

Description covers these common aspects.

Detailed parametric information for the XC3000A,

XC3000L, XC3100A, and XC3100L product families is then

provided. (The XC3000 and XC3100 families are not rec-

ommended for new designs.)

Here is a simple overview of those XC3000 products cur-

rently emphasized:

•XC3000A Family — The XC3000A is an enhanced

version of the basic XC3000 family, featuring additional

interconnect res ources and other user-friendly

enhancement s.

•XC3000L Family — The XC3000L is identical in

architecture and features to the XC3000A family, but

operates at a nominal supply volta ge of 3.3 V. The

XC30 00L is the right solution for battery-operated and

low- power ap plications.

•XC3100A Family — The XC3100A is a

performance-optimized relati ve of the XC3000A family.

While both families are bitstream and footprint

compat ible , the XC 3100A fa mily ex tends t oggle rates to

370 MHz and in-s ystem performance to ov er 80 MHz.

The XC 3100A family al so offers one additional array

siz e, the XC3195A.

•XC3100L Family — The XC3100L is identical in

architectures and features to the XC3100A family, but

operates at a nominal supply voltage of 3.3V.

Figure 1 illustrates the relationships between the families.

Compared to the original XC3000 family, XC3000A offers

addit ional fu nctiona lity and increa sed speed. The XC3000 L

family offers the same additional functionality, but reduced

speed due to its lower supply voltage of 3.3 V. The

XC3100A family offers substantially higher speed and

higher density with the XC3195A.

New XC3000 Series Compared to Original

XC3000 Family

For readers already familiar with the original XC3000 family

of FPGAs, the major new features in the XC3000A,

XC3000L, XC3100A, and XC3100L families are listed in

this section .

All of these new families are upward-compatible extensions

of the original XC3000 FPGA architecture. Any bitstream

used to config u re an XC 300 0 d evic e will co nfig ur e th e co r -

responding XC3000A, XC3000L, XC3100A, or XC3100L

device exactly the same way.

The XC3100A and XC3100L FPGA architectures are

upward-compatible extensions of the XC3000A and

XC3000L a rchit ectures . Any bits tream us ed to conf igure a n

XC3000A or XC3000L device will configure the corre-

sponding XC3100A or XC3100L device exactly the same

way.

November 9, 1998 (Version 3.1) 7-5

XC3000 Series Field Programmable Gate Arrays

Improvements in the XC3000A and XC3000L

Families

The XC3000A and XC3000L families offer the following

enhancement s over the popular XC3000 family:

The XC3000A and XC3000L families have additional inter-

connect resources to drive the I-inputs of TBUFs driving

horizontal Longlines. The CLB Clock Enable input can be

driv en fro m a secon d vert ical Longlin e. These two ad dition s

result in more efficient and faster designs when horizontal

Longlines are used for data bussin g.

During configuration, the XC3000A and XC3000L devices

check the bit-stream format for stop bits in the appropriate

positions. Any error terminates the configuration and pulls

INIT Low.

When the configuration process is finished and the device

starts up in user mode , the first ac tivation o f the outputs is

automatically slew-rate limited. This feature, called Soft

Startup, avoids the potential ground bounce when all

out-puts are turned on simultaneously. After start-up, the

slew rat e of the in dividu al output s is, as in the XC 3000 fam-

ily, determined by the individual configuration option.

Improvements in the XC3100A and XC3100L

Families

Based on a more advanced CMOS process, the XC3100A

and XC3100L families are architecturally-identical, perfor-

mance-optimized relatives of the XC3000A and XC3000L

families. While all families are footprint compatible, the

XC3100A family extends achievable system performance

beyond 85 MHz.

XC3100 XC3100A

(XC3195A)

Gate Capacity

X7068

Functionality

XC3000L XC3000A

XC3100L

Speed

Figure 1: XC3000 FPGA Families

XC3000 Series Field Programmable Gate Arrays

7-6 November 9, 1998 (Version 3.1)

Detailed Functional Description

The perimeter of configurable Input/Output Blocks (IOBs)

provides a programmable interface between the internal

logic array and the dev ice package pins. The array of Con-

figu rable Log ic Bl ocks (CLB s) perfo rms user- specif ied log ic

functions. The interconnect resources are programmed to

for m networks, carryi ng logic si gnals a m ong blocks, analo-

gous to printed circuit board traces connecting MSI/SSI

packages.

The block logic functions are im plemented by programmed

look -u p tabl e s. Fu nc t iona l op tio ns ar e imp l eme nted b y pro -

gram-controlled multiplexers. Interconnecting networks

between blocks are implemented with metal segments

joined by program-controlled pass transistors.

These FPGA functions are established by a configuration

program which is loaded into an internal, distributed array

of configuration memory cells. The configuration program

is loaded i nto the device at power-up and may be relo aded

on command. The FPGA includes logic and control signals

to implement automatic or passive configuration. Program

data may be either bit serial or byte parallel. The develop-

ment system generates the configuration program bit-

stream used to configure the device. The memory loading

process is independent of the user logic functions.

Configuration Memory

The static memo ry cell used for t he config uration me mory

in the Field Programmable Gate Array has been designed

specific ally for high r eliability and n oise immunit y. Int egrity

of the de vi c e con fi g ur ati on me mor y b ased o n th i s des i gn is

assured even under adverse conditions. As shown in

Figure 3, the basic memory cell consists of two CMOS

inver ters plus a pas s tr ansis tor used fo r wr itin g and r eadi ng

cell data. The cell is only written during configuration and

only read during readback. During normal operation, the

cell provides continuous control and the pass transistor is

off and does not affect cell stability. This is quite different

from the operation of conventional memory devices, in

whic h the cells are frequently re ad and rewritten.

P9 P8 P7 P6 P5 P4 P3 P2 GNDPWR

P11

P12

P13

U61

TCL

KIN

ADACABAA

3-State Buffers With Access

to Horizontal Long Lines Configurable Logic

Blocks

Interconnect Area

BBBA

Frame Pointer

Configuration Memory

I/O Blocks

X3241

Figure 2: Field Programmable Gate Array Structure.

It consists of a peri m eter of programma ble I/ O blocks, a core of configurable l o gic blocks and their interconnec t resources.

These are all controlled by the distributed array of configuration program memory cells.

November 9, 1998 (Version 3.1) 7-7

XC3000 Series Field Programmable Gate Arrays

The memor y ce ll out put s Q and Q u se gr ound a nd VCC lev-

els and provide continuous, direct control. The additional

capacitive load together with the absence of address

decod ing and s ense am plifiers pro vide high st ability to th e

cell. Due to the structure of the configuration memory cells,

they are not affected by extreme power-supply excursions

or very high levels of alpha particle radiation. In reliability

testing, no soft errors have been observed even in the

presence of very high doses of alpha radiation.

The method of loading the configuration data is selectable.

Two methods use serial data, while three use byte-wide

data. The inte rnal config uration logic utiliz es fram ing infor -

mation , embedd ed in the p rogram d ata by the developme nt

system, to direct memory-cell loading. The serial-data

framing and length-count preamble provide programming

compatibility for mixes of various FPGA device devices in a

synchronous, serial, daisy-chain fa shion.

I/O Block

Each user -conf igurab le IOB sh own in Figure 4, pr ovides a n

interface between the external package pin of the device

and the internal user logic. Each IOB includes both regis-

tered a nd di rec t inpu t pat hs. E ach IO B prov ides a progr am-

mable 3-state output buffer, which may be driven by a

registered or direct output signal. Configuration options

allow each IOB an inversion, a controlled slew rate and a

high impedance pull-up. Each input circuit also provides

input clamping diodes to provide electrostatic protection,

and circuits to inhibit latch-up produced by input currents.

Data

Read or

Write

Configuration

Control

X5382

Figure 3: Static Configuration Memory Cell.

It is loaded with one bit of configuration program and con-

trols one program selection in the Field Programmable

Gate Array.

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

Figu re 4: Input/O utput Block.

Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice

of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.

A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch tra n sparent) signal and vice

versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS

thresholds.

XC3000 Series Field Programmable Gate Arrays

7-8 November 9, 1998 (Version 3.1)

The input-buffer portion of each IOB provides threshold

detection to translate external signals applied to the pack-

age pin to internal logic levels. The global input-buffer

thres hold of the IOBs can be programme d to be compa tible

with eith er TTL or CMOS levels . The buffered input sign al

drives the data input of a storage element, which may be

configured as either a flip-flop or a latch. The clocking

polarity (rising/falling edge-triggered flip-flop, High/Low

transparent latch) is programmable for each of the two

clock lines on each of the four die edges. Note that a clock

line driving a

rising

edge-t ri g ge red f l ip- fl o p mak es a ny l a tch

driven by the same line on the s ame edge Low-level tra ns-

parent and vice versa (

falling

edge,

High

transparent). All

Xilinx primitives in the supported schematic-entry pack-

ages, however, are positive edge-triggered flip-flops or

High transparent latches. When one clock line must drive

flip-flop s as well as la tches, it is n ecessary t o compen sate

for the difference in clocking polarities with an additional

inverter either in the flip-flop clock input or the latch-enable

input. I/O storage elements are reset during configuration

or by the active-Low chip RESET input. Both direct input

(from IOB p in I) a nd reg istered input (fro m IOB p in Q) sig-

nals are available for interconnect.

For reliable operation, inputs should have transition times

of less than 100 ns and should not be left floating. Floating

CMOS input-pin circuits might be at threshold and produce

oscillatio ns. This ca n produce a dditional p ower dis sipation

and system noise. A typical hysteresis of about 300 mV

reduces sensitivity to input noise. Each user IOB includes a

programmabl e high- impedan ce pull-up resistor, which may

be select ed by the pro gram to prov ide a consta nt High for

otherwise undriven package pins. Although the Field Pro-

grammable Gate Array provides circuitry to provide input

protection for electrostatic discharge, normal CMOS han-

dling precautions should be observed.

Flip-flop loop delays for the IOB and logic-block flip-flops

are short, providing good performance under asynchro-

nous cl ock and da ta condit ions. Sh ort loop del ays mini mize

the probability of a metastable condition that can result

from assertion of the clock during data transitions. Because

of the s hort -loop -de lay ch arac terist ic in th e Fie ld Pr ogram -

mable Gate Array, the IOB flip-flops can be used to syn-

chronize external signals applied to the device. Once

synchronized in the IOB, the signals c an be used internally

without further consideration of their clock relative timing,

except as it applies to the internal logic and routing-path

delays.

IOB output buffers provide CMOS-compatible 4-mA

source-or-sink drive for high fan-out CMOS or TTL- com-

pati ble signal l evels (8 mA in the XC31 00A family). The net-

work driving IOB pin O becomes the registered or direct

data source for the output buffer. The 3-state control signal

(IOB) pin T can control output activity. An open-drain output

may be obtained by using the same signal for driving the

output and 3-state signal nets so that the buffer output is

enabled only for a Low.

Configuration program bits for each IOB control features

such as optional output register, logic signal inversion, and

3-state and s lew-rate control of the output.

The program-controlled memory cells of Figure 4 control

the following options.

• Logic inversion of the output is controlled by one

configuration program bit per IOB.

• Logic 3-state control of each IOB output buffer is

determined by the state s of conf iguration program bits

that turn the buffer o n , or off, or select the output buffer

3-state control interconnection (IOB pin T). When this

IOB o ut put c on tr ol s i gn al i s Hi g h, a l og i c one, t he buffer

is disabled and the package pin is high impedance.

When th is IOB out put contr ol signa l is Low, a logic ze ro,

the buffer is enabled an d the pac kage pin is active.

Inversion of the buffer 3-sta te control-logic sense

(output enable) is controlled by an additional

configuration program bit.

• Direct or registered output is selectable for each IOB.

The re gist er us es a pos iti ve-e dge, cl ock ed fl ip-fl op. The

cloc k source may be supplied (IOB pin OK) by either of

two metal lines available along each die edge. Each of

these lines is driven by an invertible buffer.

• Increased output transition speed can be selected to

improve critic al timing. Slower transitions reduce

capacitive-load peak currents of non-cri tical outpu ts

and minimize system noise.

• An internal high-impedance pull-up resistor (active by

default) prevents unconnected inputs from floating.

Unlike the original XC3000 series, the XC3000A,

XC3000L, XC3100A, and XC3100L families include the

Soft Startup feature. When the configuration process is fin-

ished and the device starts up in user mode, the first activa-

tion of the outputs is automatically slew-rate limited. This

feature avoids potential ground bounce when all outputs

are turned on simultaneously. After start-up, the slew rate

of the individual outputs is determined by the individual

configuration optio n .

Summary of I/O Options

• Inputs

-Direct

- Flip-flop/latch

- CMOS/TTL t hreshold (chip i nputs)

- Pull-up resistor /open ci rcuit

• Outputs

- Direct/registered

- Inverted/not

- 3-state/on/off

- Fu ll speed /sle w limited

- 3-state/output enable (inverse)

November 9, 1998 (Version 3.1) 7-9

XC3000 Series Field Programmable Gate Arrays

Configura ble Logic Block

The array of CLBs provides the functional elements from

which the user ’s logic is constructed. The logic blocks are

arranged in a matrix within the perimeter of IOBs. For

example, the XC3020A has 64 such blocks arranged in 8

rows and 8 columns. The development system is used to

compile the configuration data which is to be loaded into

the internal configuration memory to define the operation

and interconnection of each block. User definition of CLBs

and their interconnecting networks may be done by auto-

matic transla tion from a sche matic-cap ture logic di agram or

optionally by installing library or user macros.

Each CLB h as a combin atorial logic se ction, tw o flip-flops,

and an internal control section. See Figure 5. There are:

five logic inputs (A, B, C, D and E); a common clock input

(K); an asynchronous direct RESET input (RD); and an

enable clock (EC). All may be driven from the interconnect

resources adjacent to the blocks. Each CLB also has two

outp uts (X a nd Y) which may dr ive interconnect networ ks.

Data inp ut for either flip-f lop within a CLB is su pplied from

the func tion F or G ou tputs of the combin atori al logic, or the

block input, DI. Both flip-flops in each CLB share the asyn-

chronous RD which, when enabled and High, is dominant

over clocked inputs. All flip-flops are reset by the

active-Low chip input, RESET, or during the configuration

process. The flip-flops share the enable clock (EC) which,

when Low, recirculates the flip-flops’ present states and

inhibits response to the data-in or combinatorial function

inputs on a CL B. The user may enable thes e control inputs

and select their sources. The user may also select the

clock net input (K), as well as its active sense within each

CLB. This programmable inversion eliminates the need to

route both phases of a clock signal throughout the device.

COMBINATORIAL

FUNCTION

LOGIC

VARIABLES

DIN

ENABLE CLOCK

CLOCK

DIRECT

RESET

1 (ENABLE)

X3032

0 (INHIBIT)

(GLOBAL RESET)

CLB OUTPUTS

DATA IN 0

MUX

Figure 5: Configurable Logic Block.

Each C LB inc lud es a co m bi nato ria l logic sect ion , two flip- flo ps an d a pro gram me mo ry co nt rolled m u ltip lex er se le ctio n of

function. It has the following:

- five logic variabl e inputs A, B, C, D, and E

- a direct data in DI

- an enable clock EC

- a clock (invertible) K

- an asyn chro nous direct RESET RD

- two outputs X and Y

XC3000 Series Field Programmable Gate Arrays

7-10 November 9, 1998 (Version 3.1)

Flexible routing allows use of common or individual CLB

clocking.

The combinatorial-logic portion of the CLB uses a 32 by 1

look-up table to implement Boolean functions. Variables

selected from the five logic inputs and two internal block

fli p-flo ps are used as table address inputs . The combinato-

rial propagation delay through the network is independent

of the logic function generated and is spik e free for single

input variable changes. This technique can generate two

independent logic functions of up to four variables each as

shown in F igure 6a, or a single function of five variables as

shown in Figure 6b, or some functions of seven variables

as show n in Figure 6c . Figure 7 shows a modulo-8 binary

counte r wit h pa r alle l en abl e. It us es one CL B of ea ch typ e.

The partial functions of six or seven variables are imple-

mented using the input variable (E) to dynamically select

between two functions of four different variables. For the

two functions of four variables each, the independent

results (F and G) may be used as data inputs to either

flip-flop or either logic block output. For the single function

of five variables and merged functions of six or seven vari-

ables , th e F and G outpu ts ar e ide ntica l. Sy mmetr y of the F

and G functions and the flip-flops allows the interchange o f

CLB ou tputs to optimiz e routi ng ef ficie ncies of the networ ks

interconnecting the CLBs and IOBs.

Programmab le Inter con n ect

Programmable-interconnection resources in the Field Pro-

grammable Gate Array provide routing paths to connect

inputs and outputs of the IOBs and CLBs into logic net-

works . Inter connec tions between b locks are com posed o f a

two-layer grid of metal segments. Specially designed pass

transistors, each controlled by a configuration bit, form pro-

grammable interconnect points (PIPs) and switching matri-

ces us ed to impl ement t he necess ary connec tions be tween

selected metal segments and block pins. Figure 8 is an

exampl e of a routed net. The developm ent system prov ides

automatic routing of these interconnections. Interactive

routing is also available for design optimization. The inputs

of the CLBs or IOBs are multiplexers which can be pro-

grammed to select an input network from the adjacent

interconnect segments.

Since the switch connections to

block inputs are unidirectional, as are block outputs,

they a re usabl e only for block i nput connect ion and n ot

for routing.

Figure 9 illustrates routing access to logic

block input variables, control inputs and block outputs.

Three t yp es of metal reso urce s ar e pr ovide d to accom mo-

date various netw ork inte rconnect requirem ents.

• General Purpose Interconnect

• Direct Co nn ec tio n

• Longlines (multiplexed busses and wide AND gates)

QY Any Function

of Up to 4

Variables

QY Any Function

of Up to 4

Variables

QY Any Function

of 5 Variables

QY Any Function

of Up to 4

Variables

QY Any Function

of Up to 4

Variables

X5442

FGM

Mode

Figure 6: C o mbinational Logic Options

6a. Combinatorial Logic Option FG generates two func-

tions of four variables each. One variable, A, must be

common to b ot h fu nct i ons. Th e se cond a nd t hi rd var i ab le

can be any choice of B, C, QX and QY. The fourth vari-

able can be any choice of D or E.

6b. Combinator ial Logic Option F generates any function

of fi ve var iabl es: A , D, E and two ch oic es out of B , C, Q X,

QY.

6c. Combinatorial Logic Option FGM allows variable E to

selec t be tween t wo f unct ions o f fo ur va ria bles: Bot h hav e

common inputs A and D and any choice out of B, C, QX

and QY for the remaining two variables. Option 3 can

then i mpl e men t so me func t i ons o f s i x or se ve n v ar i able s.

November 9, 1998 (Version 3.1) 7-11

XC3000 Series Field Programmable Gate Arrays

General Purpose Interconnect

Genera l pur po se int er c onn ect, a s s ho wn i n Figure 10, con-

sists of a grid of five horizontal and five vertical metal seg-

ments located between the rows and columns of logic and

IOBs. Each segment is the height or width of a logic block.

Switching matrices join the ends of these segments and

all ow progra mmed inte rconnec tions b etween t he meta l grid

segme nts of ad joining rows and columns. The switches of

an unprogrammed device are all non-conducting. The con-

nections through the switch matrix may be established by

the automatic routing or by selecting the desired pairs of

matrix pins to be connected or disconnected. The legiti-

mate switching matrix combinations for each pin are indi-

cated in Figure 11.

Special buffers within the general interconnect areas pro-

vide periodic signal isolation and restoration for improved

performance of lengthy nets. The interconnect buffers are

avai labl e to pro pagat e s i gnal s in ei t her di re c tio n on a giv en

general interconnect segment. These bidirectional (bidi)

buf fer s are f ound a djac ent to t he sw itch ing matr ic es, ab ove

and to the right. The other PIPs adjacent to the matrices

are accessed to or from Longlines. The development sys-

tem automatically defines the buffer direction based on the

location of the interconnection network source. The delay

calculator of the development system automatically calcu-

lates and displ ays the bl oc k, in terc onnec t a nd buf fe r del ays

for any paths selected. Generation of the simulation netlist

with a worst-case delay model is provided.

Direct Interconnect

Dire ct inter conn ect, sh own in Figure 12, provides the most

efficient implementation of networks between adjacent

CLBs or I/O Blocks. Signals routed from block to block

using the d irec t inte rc onne ct ex hibit minim um inter conn ect

propagation and use no general interconnect resources.

For each CLB, the X output may be connected directly to

the B input of the CLB immediately to its right and to the C

input of th e CLB to its l eft. The Y out put ca n use d irect i nter-

connec t to d rive t he D in put of the b lock immed iatel y abov e

and the A input of the block below. Direct interconnect

shoul d be used to maximi ze the speed of high-pe rformanc e

portions of logic. Where logic blocks are adjacent to IOBs,

direct connect is provided alternately to the IOB inputs (I)

and outputs (O) on all four edges of the die. The ri ght edge

provides additional direct connects from CLB outputs to

adjacent IOBs. Direct interconnections of IOBs with CLBs

are sh own in Figure 13.

D Q

Count Enable

Parallel Enable

Clock

Dual Function of 4 Variables

Function of 6 Variables

Function of 5 Variables

Mode

FGM

Mode

Terminal

Count

X5383

Figure 7: Counter.

The modulo-8 binary counter with parallel enable and

clock enable uses one combinatorial logic block of each

option.

Figure 8: A D esign Edito r view of routing resource s

used to form a typical interconnection network from

CLB GA.

XC3000 Series Field Programmable Gate Arrays

7-12 November 9, 1998 (Version 3.1)

Figure 9: Design Edi tor Lo cati ons of in terc onnect acc ess, C LB co ntrol inpu ts, logi c inpu ts a nd out put s. The d ot pa tter n

represents the available programmable i nterconnection poi nts (PIP s).

Some of the interconnect PIPs are directional.

November 9, 1998 (Version 3.1) 7-13

XC3000 Series Field Programmable Gate Arrays

Figure 10: FPGA General -Purpose Interconnect.

Composed of a grid of metal segments that may be inter-

connected through switch matrices to form networks for

CLB an d IOB inputs and outputs.

Figure 11: Switch Ma trix Int erconne ctio n Opti ons for

Each Pin.

Switch matrices on the edges are different.

Figure 12: CLB X and Y Outputs.

The X and Y outputs of each CLB have single contact,

direct access to inputs of adjacent CLBs

XC3000 Series Field Programmable Gate Arrays

7-14 November 9, 1998 (Version 3.1)

Figure 13: XC3020A Die-E dge IOBs. The XC3020A die-edge IOBs are provided with dir ect access to adjacent CLB s.

Global Buffer Direct Input Global Buffer Inerconnect

Alternate Buffer Direct Input

* Unbonded IOBs (6 Places)

November 9, 1998 (Version 3.1) 7-15

XC3000 Series Field Programmable Gate Arrays

Longlines

The Lo nglines bypas s the s witch mat rice s and are inte nded

primarily for signals that must travel a long distance, or

must have minimum skew among multiple destinations.

Longlines, shown in Figure 14, run vertically and horizon-

tall y the height or width of th e interco nnect area. E ach inter-

connection column has three vertical Longlines, and each

interconnection row has two horizontal Longlines. Two

additional Longlines are located adjacent to the outer sets

of switching matrices. In devices larger than the XC3020A

and XC3120A FPGAs, two vertical Longlines in each col-

umn are connectable half-length lines. On the XC3020A

and XC3120A FPGAs, only the outer Longlines are con-

nectable half-length l ines.

Longli n es c an be dr ive n b y a l og ic blo ck or I OB o utpu t on a

column-by-column basis. This capability provides a com-

mon low skew control or clock line within each column of

logic blocks. Interconnections of these Longlines are

shown in Figure 15. Isolation buffers are provided at each

input to a Longline and are enabled automatically by the

deve lopment system when a connection is made.

Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in

each ro w and column. The global buf fer in the upper l eft die corner drives a common l ine thr oughout the FPGA.

XC3000 Series Field Programmable Gate Arrays

7-16 November 9, 1998 (Version 3.1)

Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routi ng area.

Three -sta t e b uffer s al low th e us e of ho riz on ta l Lo ng l ines t o fo rm on- ch i p wir ed AND a nd mul t ipl e xe d b uses . The lef t t wo

non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as

connectable half-length lines.

VCC

DADBDCDN

VCC Z = DA • DB • DC • ... • DN

X3036

(LOW)

Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high

impedance), the pull-up re sistor(s) provide the High output. The buffer inputs are driven by the control sign als or a Low.

DAA•+=D

BB•+D

CC•+ D

NN•Z…+

X1741A

WEAK

KEEPER CIRCUIT

Figure 17: 3-State B u ffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.

November 9, 1998 (Version 3.1) 7-17

XC3000 Series Field Programmable Gate Arrays

A buffer in the upper left corner of the FPGA chip drives a

global n et which is av ailable to all K inputs of logic bloc ks.

Using the global buffer for a clock signal provides a

skew-free, high fan-out, synchronized clock for use at any

or all of the IOBs and CLBs. Configuration bits for the K

input to each logic block can select this global line or

another routing resource as the clock source for its

fli p-flops . This net may also be programme d to drive the die

edge clock lines for IOB use. An enhanced speed, CMOS

thres hold, dir ect acces s to this b uffer is availabl e at the sec -

ond pad from the top of the left die edg e.

A buffer in the lower right corner of the array drives a hori-

zontal Longline that can drive programmed connections to

a vertical Longline in each interconnection column. This

alternate buffer also has low skew and high fan-out. The

network formed by this alternate buffer’s Longlines can be

selected to drive the K inputs of the CLBs. CMOS thresh-

old, high speed access to this buffer is available from the

third pad fr om the bottom of the right die edge.

Internal Busses

A pai r of 3- state b uff ers, lo cated a djace nt to ea ch CLB, per-

mits logi c to drive the horizo ntal Longlines. Logic operation

of the 3-sta te buf fer c ontrols allow s them t o implem ent wid e

multiplexing functions. Any 3-state buffer input can be

selected as drive for the horizontal long-line bus by apply-

ing a Low logic level on its 3-state control line. See

Figure 16. The user is required to avoid contention which

can r esult from m ultiple driver s with oppo sing logic le vels.

Control of the 3-state input by the same signal that drives

the buf f er i nput, c reat es a n open-d rain wired -AND functi on.

A logic High on both buffer inputs creates a high imped-

ance , whi ch r ep r esen t s n o co nt enti o n. A l ogic Lo w e nab les

the buffer to dr iv e t he Lon gli n e Lo w. See Figure 17. Pull-up

resistors are available at each end of the Longline to pro-

vide a High output when all connected buffers are non-con-

ducting. This forms fast, wide gating functions. When data

drives the inputs, and separate signals drive the 3-state

control lines, these buffers form multiplexers (3-state bus-

ses). In this case, care must be used to prevent contention

through multiple active buffers of conflicting levels on a

common line. Each horizontal Longline is also driven by a

weak keeper circuit that prevents undefined floating levels

by main taining the p revious logic le vel wh en th e line is not

driven by an active buffer or a pull-up resistor. Figure 18

shows 3-state buffers, Longlines and pull - up resistors.

3-STATE CONTROL

P40 P41 P42 P43 RST

P46

X1245

P47

BCL

KIN

P48

.lk

.ck

I/O CLOCKS

BIDIRECTIONAL

INTERCONNECT

BUFFERS

GLOBAL NET 3 VERTICAL LONG

LINES PER COLUMN

HORIZONTAL LONG LINE

PULL-UP RESISTOR

HORIZONTAL LONG LINE

OSCILLATOR

AMPLIFIER OUTPUT

DIRECTINPUT OF P47

TO AUXILIARY BUFFER

CRYSTAL OSCILLATOR

BUFFER

3-STATE INPUT

3-STATE BUFFER

ALTERNATE BUFFER

Figure 18: Design Editor.

An extra large view of possible interconnections in the lower right corner of the XC3020A.

XC3000 Series Field Programmable Gate Arrays

7-18 November 9, 1998 (Version 3.1)

Crystal Oscillator

Figure 18 also s how s th e l oca ti o n o f an int er nal high s pe ed

inverting amplifier that may be used to implement an

on-chip crystal osc illator. I t is associate d with the auxiliary

buffer in the lower right corner of the die. When the oscilla-

tor is configured and connected as a signal source, two

special user IOBs are also configured to connect the oscil-

lator amplifier with external crystal oscillator components

as show n in Figure 19. A divide by two option is available to

assure symmetry. The oscillator circuit becomes active

early in the conf iguration process to allow the oscillator to

stabilize. Actual internal connection is delayed until com-

pletion of configuration. In Figure 19 the feedback resistor

R1, between the output and input, biases the amplifier at

threshold. The inversion of the amplifier, together with the

R-C networks and an AT-cut series resonant crystal, pro-

duce the 360-deg ree phase shift of the Pierce oscillator. A

series resistor R2 may be included to add to the amplifier

output impedance when needed for phase-shift control,

crystal resistance matching, or to limit the amplifier input

swing to control clipping at large amplitudes. Excess feed-

back voltage may be corrected by the ratio of C2/C1. The

amplifier is designed to be used from 1 MHz to about

one-half the specified CLB toggle frequency. Use at fre-

quencies below 1 MHz may require individual characteriza-

tion w ith respect to a series resistance. Crystal oscillat ors

above 20 MH z general ly requi re a crysta l which oper ates in

a third overtone mode, where the fundamental frequency

must be suppressed by an inductor across C2, turning this

parallel resonant circuit to double the fundamental crystal

frequency, i.e., 2/3 of the desired third harmonic frequency

network. When the oscillator inverter is not used, these

IOBs and their package pins are available for general user

I/O.

Alternate

Clock Buffer XTAL1

XTAL2

(IN)

C1 C2

Internal External

C1, C2

Suggested Component Values

0.5 – 1 MΩ

0 – 1 kΩ

(may be required for low frequency, phase

shift and/or compensation level for crystal Q)

10 – 40 pF

1 – 20 MHz AT-cut parallel resonant

X7064

68 PIN

PLCC

84 PIN

PLCC

PGA

J11

L11

132 PIN

PGA

P13

M13

160 PIN

PQFP

XTAL 1 (OUT)

XTAL 2 (IN)

100 PIN

CQFP

PQFP

164 PIN

CQFP

105

44 PIN

PLCC

175 PIN

PGA

T14

P15

208 PIN

PQFP

110

100

176 PIN

TQFP

D Q

Figure 19: Crystal Oscillator Inverter. When activated, and by selecting an ou tput network for its buffer, the crystal

oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional

divide-by-two mode i s available to assure symmetry.

November 9, 1998 (Version 3.1) 7-19

XC3000 Series Field Programmable Gate Arrays

Configuration

Initialization Phase

An internal power-on-reset circuit is triggered when power

is ap plied. When VCC reaches the voltage at which portions

of the FPGA device begin to operate (nominally 2.5 to 3 V),

the programmable I/O output buffers are 3-stated and a

high-impedance pull-up resistor is provided for the user

I/O pins. A time-out delay is initiated to allow the power

suppl y voltage to stab ilize. Durin g this time th e power-down

mode i s inhi bi t ed. The I n i tia li zati o n st at e t ime -o ut (abo ut 11

to 33 ms) is determined by a 14-bit counter driven by a

self-generated internal timer. This nominal 1-MHz timer is

subject to variations with process, temperature and power

supply. As shown in Table 1, five configuration mode

choices are available as determined by the input levels of

three m od e pin s ; M0, M1 an d M 2.

In Master configuration modes, the device becomes the

source of the Configuration Clock (CCLK). The beginning

of configuration of devices using Peripheral or Slave

modes must be delayed long enough for their initialization

to be completed. An FPGA with mode lines selecting a

Master configuration mode extends its initialization state

using four times the delay (43 to 130 ms) to assure that all

daisy-chained slave devices, which it may be driving, will

be ready even if the master is very fast, and the slave(s)

very sl ow . Figure 20 shows the st ate sequenc es. At the en d

of Initialization, the device enters the Clear state where it

clears the configuration memory. The active Low,

open-drain initialization signal INIT indicates when the Ini-

tialization and Clear states are complete. The FPGA tests

for the absence of an external active Low RESET before it

makes a final sample of the mode lines and enters the Con-

figur ati on st ate. An e xter nal wire d-AND of o ne o r mor e IN IT

pins c an be used to cont rol config uration by t he assertio n of

the active -Low RESET of a master mode device or to sig-

nal a proc es so r tha t the FPG A s ar e no t yet initia lized .

If a conf iguration has begun, a r e-assertion of RESET for a

minimum of three internal timer cycles will be recognized

and the FPGA will initiate an abort, returning to the Clear

state to clear the partially loaded configuration memory

words. The FPGA will then resample RESET and the mod e

lines bef or e re -e nt er in g the C on fig ur at ion stat e.

During configuration, the XC3000A, XC3000L, XC3100A,

and XC3100L devices check the bit-stream format for stop

bits in the appropriate positions. Any error terminates the

configuration and pulls INIT Low.

Table 1: Configuration Mode Choices

M0 M1 M2 CCLK Mode Data

0 0 0 output Master Bit Serial

0 0 1 output Master Byte Wide A ddr. = 0000 up

010— reserved —

0 1 1 output M as te r Byte Wide Addr. = FFFF down

1 0 0 — reserved —

1 0 1 output Peripheral Byte Wide

1 1 0 — reserved —

1 1 1 input Slave Bit Serial

All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low

Initialization

Power-On

Time Delay

Clear

Configuration

Memory

Test

Mode Pins Configuration

Program Mode Start-Up Operational

Mode

Power Down

No HDC, LDC

or Pull-Up

X3399

INIT Output = Low

Clear Is

~ 200 Cycles for the XC3020A—130 to 400 µs

~ 250 Cycles for the XC3030A—165 to 500 µs

~ 290 Cycles for the XC3042A—195 to 580 µs

~ 330 Cycles for the XC3064A—220 to 660 µs

~ 375 Cycles for the XC3090A—250 to 750 µs

RESET

Active

PWRDWN

Inactive PWRDWN

Active

Active RESET

Operates on

User Logic

Low on DONE/PROGRAM and RESET

Active RESET

Power-On Delay is

214 Cycles for Non-Master Mode—11 to 33 ms

216 Cycles for Master Mode—43 to 130 ms

Figure 20: A State Diagram of the Configur ation Process for Power-up and Reprogram.

XC3000 Series Field Programmable Gate Arrays

7-20 November 9, 1998 (Version 3.1)

A re-program is initiated.when a configured XC3000 serie s

devi ce se nses a Hig h- to -L ow tr ansi t ion a nd s ub seque nt >6

µs Low level on the DONE/PROG package pin, or, if this

pin i s ext e rna ll y hel d p er man entl y Low, a High-to- Low t ran -

sit ion and s ubsequ ent >6 µs Low time on the RESET pack-

age pin.

The device returns to the Clear state where the configura-

tion memory is cleared and mode lines re-sampled, as for

an aborted configuration. The complete configuration pro-

gram is cleared and loaded during each configuration pro-

gram cyc le.

Lengt h co un t co nt ro l allo ws a syst em of mu ltiple F ie l d Pr o-

grammable Gate Arrays, of assorted sizes, to begin opera-

tion in a synchronized fashion. The configuration program

generated by the development system begins with a pre-

amble of 111111110010 fo llowed by a 24-bit length count

representing the total number of configuration clocks

needed to complete loading of the configuration pro-

gram(s). The data framing is shown in Figure 21. All

FPGAs connected in series read and shift preamble and

length count in on positive and out on negative c onfigura-

tion clock edges. A device which has received the pream-

ble and length count then presents a High Data Out until it

has intercepted the appropriate number of data frames.

When the configuration program memory of an FPGA is full

and the length count does not yet compare, the device

shifts any additional data through, as it did for preamble

and length count. When the FPGA configuration memory is

full and the len gt h co unt co m pa re s, the de vice will ex ecute

11111111

0010

< 24-Bit Length Count >

1111

0 <Data Frame # 001 > 111

0 <Data Frame # 002 > 111

0 <Data Frame # 003 > 111

. . .

0 <Data Frame # 196 > 111

0 <Data Frame # 197 > 111

1111

—Dummy Bits*

—Preamble Code

—Configuration Program Length

—Dummy Bits (4 Bits Minimum)

For XC3120

197 Configuration Data Frames

(Each Frame Consists of:

A Start Bit (0)

A 71-Bit Data Field

Three Stop Bits

Postamble Code (4 Bits Minimum)

Header

Program Data

Repeated for Each Logic

Cell Array in a Daisy Chain

*The LCA Device Require Four Dummy Bits Min; Software Generates Eight Dummy Bits X5300_01

Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data

frames generated by the Development Sy stem.

The Length Count produced by the program = [(40-bit preamble + sum of program data + 1 per daisy chain device)

rounded up to multiple of 8] – (2 ≤ K ≤ 4) where K is a function of DON E and RESET timing selec ted. An additional 8 is

added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is

reached.

Device

XC3020A

XC3020L

XC3120A

XC3030A

XC3030L

XC3130A

XC3042A

XC3042L

XC3142A

XC3142L

XC3064A

XC3064L

XC3164A

XC3090A

XC3090L

XC3190A

XC3190L XC3195A

Gates 1,000 to 1,500 1,500 to 2,000 2,000 to 3,000 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500

CLBs 64 100 144 224 320 484

Row x Col (8 x 8) (10 x 10) (12 x 12) (16 x 14) (20 x 16) (22 x 22)

IOBs 64 80 96 120 144 176

Flip-flops 256 360 480 688 928 1,320

Horizontal Longlines 16 20 24 32 40 44

TBUFs/Horizontal LL 9 11 13 15 17 23

Bits per Frame

(including1 start and 3 stop bits) 75 92 108 140 172 188

Frames 197 241 285 329 373 505

Program Data =

Bits x Frames + 4 bits

(excl udes header)

14,779 22,176 30,784 46,064 64,160 94,944

PROM si ze (bits) =

Program Data

+ 40-bit Header

14,819 22,216 30,824 46,104 64,200 94,984

November 9, 1998 (Version 3.1) 7-21

XC3000 Series Field Programmable Gate Arrays

a sync hron ous s tart- up seq uenc e and b ecome opera tiona l.

See Figure 22. Two CCLK cycles after the completion of

loading configuration data, the user I/O pins are enabled as

configured. As selected, the internal user-logic RESET is

released either one clock cycle before or after the I/O pins

becom e act ive. A sim ilar t iming selec tion is prog ramm able

for the DONE/PROG outpu t sign al. DO NE/P ROG may also

be programmed to be an open drain or include a pull-up

resistor to accommodate wired ANDing. The High During

Configuration (HDC) and Low During Configuration (LDC)

are two user I/O pins which are driven active while an

FPGA is in its Initialization, Clear or Configure states. They

and DONE/PROG provide signals for control of external

logic signals such as RESET, bu s enable or PROM en able

during configuration. For parallel Master configuration

modes, these signals provide PROM enable control and

allow the data pins to be shared with user logic signals.

User I/O inputs can be programmed to be either TTL or

CMOS compatible thresholds. At power-up, all inputs have

TTL th resh olds an d can c hange to C MOS thre shol ds at t he

completion of configuration if the user has selected CMOS

thres holds. The thr eshold of PWRDW N and the di rect cloc k

inputs are fixed at a CMOS level.

If the crystal oscillator is used, it will begin operation before

configuration is complete to allow time for stabilization

before it is connected to the internal circuitry.

Configuration Data

Configuration data to define the function and interconnec-

tion w ithin a Fiel d Programm able Gate A rray is load ed from

an exte rnal st orage at power-up and aft er a re- program s ig-

nal. Sev eral metho ds of auto matic and cont rolled lo ading of

the required data are available. Logic levels applied to

mode selection pins at the start of configuration time deter-

mine t he met hod to be us ed. See Table 1. Th e dat a may b e

either bit-serial or byte-parallel, depending on the configu-

ration mode. The different FPGAs have different sizes and

numbers of data frames. To maintain compatibility between

various device types, the Xilinx product families use com-

patible configuration formats. For the XC3020A, configura-

tion requires 14779 bits for each device, arranged in 197

data frames. An additional 40 bits are used in the header.

See Figure 22. The specific data format for each device is

produced by the development system and one or more of

these file s c an th en be comb ined a nd ap pende d to a leng th

count preamble and be transformed into a PROM format

file by the development system. A compatibility exception

precludes the use of an XC2000-series device as the mas-

ter for XC3000-series devices if their DONE or RESET are

programmed to occur after their outputs become active.

The Tie Optio n define s outp ut leve ls of un use d block s of a

design and connects these to unused routing resources.

This prevents indeterminate levels that might produce par-

asitic supply currents. If unused bloc ks are not su fficient to

complete the ti e, the user can indicate nets which must not

Preamble Length Count Data

12 24 4 Data Frame

Start

Bit Start

Bit

Last Frame Postamble

I/O Active

DONE

Internal Reset

Length Count*

The configuration data consists of a composite

40-bit preamble/length count, followed by one or

more concatenated FPGA programs, separated by

4-bit postambles. An additional final postamble bit

is added for each slave device and the result rounded

up to a byte boundary. The length count is two less

than the number of resulting bits.

Timing of the assertion of DONE and

termination of the INTERNAL RESET

may each be programmed to occur

one cycle before or after the I/O outputs

become active.

Heavy lines indicate the default condition X5988

PROGRAM

Weak Pull-Up

Stop

STOP

DIN

Figure 22: Configur ation and Start-up of One or More FPGAs.

XC3000 Series Field Programmable Gate Arrays

7-22 November 9, 1998 (Version 3.1)

be used to drive the remaining unused routing, as that

might affect timing of user nets. Tie can be omitted for quick

breadboard iterations where a few additional milliamps of

Icc are acce ptable.

The configuration bitstream begins with eight High pream-

ble bits, a 4-bit preamble code and a 24-bit length count.

When configuration is initiated, a counter in the FPGA is set

to zero and begins to count the total number of configura-

tion cloc k cycles ap plied to the de vice. As each configu ra-

tion data frame is supplied to the device, it is internally

assembled into a data word, which is then loaded in parallel

into one word of the internal configuration memory array.

The configuration loading process is complete when the

curre nt le ngth c ount equ als t he load ed len gth c ount and the

required configuration program data frames have been

writ ten . Inte rnal us er f lip- flops are hel d Rese t du ring confi g-

urati on.

Two user-programmable pins are defined in the unconfig-

ured F ield Prog ramm able Gat e Array. Hig h During Config-

uration (HD C) and Low During Configuration (LDC) as well

as DONE/PROG may be used as external control signals

during configuration. In Master mode configurations it is

convenient to use LDC as an active-Low EPROM Chip

Enable. After the last configuration data bit is loaded and

the length count compares, the user I/O pins become

active. Op tions allow tim ing choice s of one clock e arlier or

later for the timing of the end of the internal logic RESET

and the assertion of the DONE signal. The open-drain

DONE/PROG output can be AND-tied with multiple devices

and us ed as an active -High REA DY, an ac tive-L ow P ROM

enable or a RESET to other portions of the system. The

state diagram of Figure 20 illustrates the configuration pro-

cess.

Configuration Modes

Master Mode

In Master mode, the FPGA automatically loads configura-

tion data from an external memory device. There are three

Master modes that use the internal timing source to supply

the configuration clock (CCLK) to time the incoming data.

Master Se rial mode uses serial configura tion data supplied

to Data- in (DIN) from a synch ron ous seria l so urce such as

the Xilinx Serial Configuration PROM shown in Figure 23.

Master Parallel Low and High modes automatically use

para llel data supplied to the D0–D7 pins in respon se to the

16-bit address generated by the FPGA. Figure 25 shows

an example of the parallel Master mode connections

requi red. T he HEX s tarting addres s is 0 000 and increme nts

for Master Low mode and it is FFFF and decrements for

Master High mode. These two modes provide address

compatibility with microprocessors which begin execution

from opposite ends of memory.

Peripheral Mode

Peripheral mode provides a simplified interface through

which the device may be loaded byte-wide, as a processor

peripheral. Figure 27 shows the peripheral mode connec-

tions. Processor write cycles are decoded from the com-

mon assertion of the active low Write Strobe (WS), and two

active low and one active high Chip Selects (CS0, CS1,

CS2). The FPGA generates a configuration clock from the

internal timing generator and serializes the parallel input

data for internal framing or for succeeding slaves on Data

Out (DOUT). A output Hi gh on R EADY/BUSY pin indicates

the completion of loading for each byte when the input reg-

iste r is read y for a new byt e. As wi th Master modes, Periph-

eral mode may also be used as a lead device for a

daisy-chain of slave devices.

Slave Serial Mode

Slave Serial mode provides a simple interface for loading

the Field Programmable Gate Array configuration as

shown in Figure 29. Serial data is supplied in conjunction

with a sync h ron izi n g inpu t c loc k. M ost S lav e m ode a ppli c a-

tions are in daisy-chain configurations in which the data

input is dri ven from the p revio us FPGA’s data out, whil e the

clock is supplied by a lead device in Master or Peripheral

mode. Data may also be supplied by a processor or other

special circuits.

Daisy Chain

The development system is used to create a composite

configuration for selected FPGAs including: a preamble, a

length count for the total bitstream, multiple concatenated

data programs and a postamble plus an additional fill bit

per de vice in t he serial chain. After loading a nd pass ing-on

the preamble and length count to a possible daisy-chain, a

lead device will load its configuration data frames while pro-

viding a High DOUT to possible down-stream devices as

shown in Figure 25. Loading continues while the lead

device has received its configuration program and the cur-

rent length count has not reached the full value. The addi-

tional data is passed through the lead device and appears

on the D at a Ou t ( DOU T) p in i n s er ial f or m. T he l ead d ev i ce

also ge nerat es the C onfig ura tion Clo ck (CC LK) to sy nch ro-

nize the serial output data and data in of down-stream

FPGAs. Data is read in on DIN of slave devic es by th e pos-

itive edge of CCLK and shifted out the DOUT on the nega-

tive edge o f CCLK. A p ar allel M as te r m o de d ev ice use s it s

internal timing generator to produce an internal CCLK of 8

times its EPROM address rate, while a Peripheral mode

device produces a burst of 8 CCLKs for each chip select

and write-strobe cycle. The internal timing generator con-

tinues to operate for general timing and synchronization of

inputs in all modes.

November 9, 1998 (Version 3.1) 7-23

XC3000 Series Field Programmable Gate Arrays

Special Configuration Functions

The configuration data includes control over several spe-

cial functions in addition to the normal user logic functions

and interconnect.

• Input thresholds

• Readb a ck disable

• DONE pull-up resistor

•DONE timing

• RESET timing

• Oscillato r freq u en cy div ide d by two

Each of these functions is controlled by configuration data

bits which are selected as part of the normal development

system bitstream generation process.

Input Thresholds

Prior to the completion of configuration all FPGA input

thresholds are TTL compatible. Upon completion of config-

uration, the input thresholds become either TTL or CMOS

compatible as programmed. The use of the TTL threshold

option requires some additional supply current for thresh-

old shifting. The exception is the threshold of the

PWRDWN input and direct clocks which always have a

CMOS input. Prior to the completion of configuration the

user I/O pins each have a high impedance pull-up. The

configuration program can be used to enable the IOB

pull -up resis tors i n the Oper ati onal mo de t o act e it her a s an

input load or to avoid a floating input on an otherwise

unused pin.

Readback

The co nten ts of a Fie ld Progr amm able G at e Arr ay ma y be

read back if it has been programmed with a bitstream in

which the Readback option has been enabled. Readback

may be used for verification of configuration and as a

method of det ermi ning the stat e of i nte rnal lo gic nod es dur -

ing debugging. There are three options in generating the

configu ra tio n bit str ea m .

• “Neve r” inhib its th e Re ad ba ck capa bility.

• “One-ti me,” inhibits Readba ck after one Readback has

been execute d to verify the configuration.

• “On- com m a nd ” allo ws unr es tric te d us e of Re ad ba ck .

Readback is accomplished without the use of any of the

user I/O pins; only M0, M1 and CCLK are used. The initia-

tion of Re adb ac k is pr odu c ed by a Lo w to Hi gh tr an sit i o n of

the M0/RTRIG (Read Trigger) pin. The CCLK input must

then be dri v en by ex t er nal l og ic t o re ad ba c k the c onf ig ura -

tion data. The first three Low-to-High CCLK transitions

cloc k out dumm y data . The su bseq uent Lo w-t o-Hig h CCLK

transitions shift the data frame information out on the

M1/RDATA (R ead Data) pin. Note that the logic polarity is

alway s inverted, a z ero in config uration beco mes a one in

Readback, and vice versa. Note also that each Readback

frame has one Start bit (read back as a one) but, unlike in

configuration, each Readback frame has only one Stop bit

(read back as a zero). The third leading dummy bit men-

tioned above can be considered the Start bit of the first

frame . All data fr ames must b e read ba ck to comp lete the

proces s and return t he Mod e Sele ct an d CCLK pins t o their

norm al functions.

Readback data includes the current state of each CLB

flip-flop, each input flip-flop or latch, and each device pad.

These data are imbedded into unused configuration bit

positions during Readback. This state information is used

by the development system In-Circuit Verifier to provide

visibility into the internal operation of the logic while the

system is operating. To readba ck a uniform time-sample of

all sto rage eleme nts, i t may be neces sary t o in hibit the sy s-

tem clock.

Reprogram

To initiate a re-programming cycle, the dual-function pin

DONE/PROG must be given a High-to-Low transition. To

reduce sensitivity to noise, the input signal is filtered for two

cycles of the FPGA internal timing generator. When repro-

gram begi ns, th e user-prog rammabl e I/O out put buf fers ar e

disabled and high-impedance pull-ups are provided for the

package pins. The device returns to the Clear state and

clears the configurat ion memory before it indicates ‘initial-

ized’. Sin ce this Clear ope ration us es chip- individual inter-

nal tim ing, the master might complete the Clear operation

and then s tart conf iguration befor e the slave has com pleted

the Clear operation. To avoid this problem, the slave INIT

pins must be AND-wired and used to force a RESET on the

master (see Figure 25). Reprogram control is often imple-

mented using an external open-collector driver which pulls

DONE/PROG Low. Once a stable request is recognized,

the DONE /PROG pin is held Low until the new configura-

tion ha s b een co mple te d. Even i f t he r e- pro gr am r eques t i s

externally held Low beyond the configuration period, the

FPGA will begin operation upon completion of configura-

tion.

DONE Pull-up

DONE/PROG is an open-drain I/O pin that indicates the

FPGA is in the operational state. An optional internal

pull-up resistor can be enabled by the user of the develop-

ment system. The DONE/PROG pins of mult iple FP GAs in

a daisy -ch ain may be conne cte d toget her t o ind icate all are

DONE or to direct them all to reprogram.

DONE Timing

The timing of the DONE status signal can be controlled by

a selection to occur either a CCLK cycle before, or after , the

outp uts going active. See Figure 22. This facilitates con trol

of external functions such as a PROM enable or holding a

system in a wait state.

XC3000 Series Field Programmable Gate Arrays

7-24 November 9, 1998 (Version 3.1)

RESET Timing

As with DONE timing, the timing of the release of the inter-

nal reset can be controlled to occur either a CCLK cycle

before, or after, the outputs going active. See Figure 22.

This reset keeps all user programmable flip-flops and

latches in a zero stat e du rin g co nf igu ra tio n.

Crystal Oscillator Division

A selection allows the user to incorporate a dedicated

divide-by-two flip-flop between the crystal oscillator and the

alternate clock line. This guarantees a symmetrical clock

signal. Although t he frequ ency s tability of a crystal o scilla-

tor is very good, the symmetry of its waveform can be

affected by b ias or feedback drive.

Bitstream Error Checking

Bitstre am error checki ng protect s agains t erroneous con -

figuration.

Each Xilin x FPG A bitst ream consis ts of a 40- bit pre amble,

followed by a device-specific number of data frames. The

number of bits per f rame is also device-specific; however,

each frame ends with three stop bits (111) followed by a

start bit for the next frame (0).

All devices in all XC3000 families start reading in a new

frame w hen the y find th e first 0 after the end o f the pr evious

frame. An original XC3000 device does not check for the

correct stop bits, but XC3000A, XC3100A, XC3000L, and

XC31 00L devi ces che ck that the last t hree bi ts of any f rame

are actually 111.

Under normal circumstances, all these FPGAs behave the

same way; however, if the bitstream is corrupted, an

XC3000 device will alw ays sta rt a n ew fram e as so on as it

finds the first 0 after the end of the previous frame, even if

the data is completely wrong or out-of-sync. Given suffi-

cient zeros in the data stream, the device will also go Done,

but w ith incorre ct configur ation an d the possib ility of inte r-

nal cont en tio n.

An XC3000A/XC3100A/XC3000L/XC3100L device starts

any new frame only if the three preceding bits are all ones.

If this check fails, it pulls INIT Low and stops the internal

configuration, although the Master CCLK keeps running.

The user must then start a new configuration by applying a

>6 µs Low level on RESET.

This simple check does not protect against random bit

errors, but it offers almost 100 percent protection against

erroneous configuration files, defective configuration data

sources, synchronization errors between configuration

source and FPGA, or PC-board level defects, such as bro-

ken lines or solder-bridges.

Reset Spike Protection

A separate modification slows down the RESET input

before configuration by using a two-stage shift register

driven from the inte rnal cloc k. It tolerates s ubmicroseco nd

High spikes on RESET before co nfiguration. The XC30 00

master can be connected like an XC4000 master, but with

its RESET input used instead of INIT. (On XC30 00, INIT is

output only).

Soft Start-up

After configuration, the outputs of all FPGAs in a

daisy-chain become active simultaneously, as a result of

the same CCLK edge. In the original XC3000/3100

devices, each output becomes active in either fast or

slew-rate limited mode, depending on the way it is config-

ured. This can lead to large ground-bounce signals. In

XC3000A, XC3000L, XC3100A, and XC3100L devices, all

outputs become active first in slew-rate limited mode,

reducing the ground bounce. After this soft start-up, each

individual output slew rate is again controlled by the

respective configuration bit.

November 9, 1998 (Version 3.1) 7-25

XC3000 Series Field Programmable Gate Arrays

Configuration Timing

This s ection describes the configuration modes in deta il.

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA

drives a Xilinx Serial PROM that feeds the DIN input. Each

rising edge of the CCLK output increments the Serial

PROM internal address counter. This puts the next data bit

on the SPROM data output, connected to the DIN pin. The

lead FPGA accepts this data on the subsequent rising

CCLK edge.

The lead FPGA then presents the preamble data (and all

data t hat over flows t he lead d evice) on its DOUT p in. Ther e

is an internal delay of 1.5 CCLK periods, which means that

DOUT changes on the falling CCLK edge, and the next

device in the daisy-chain accepts data on the subsequent

rising CCLK edge.

The SPROM CE input can be driven from either LDC or

DONE. Using LDC avoids potential contention on the DIN

pin, if this pin is configured as user-I/O, but LDC is then

restricted to be a permanently High user output. Using

DONE also avoids contention on DIN, provided the early

DONE option is invoked.

X5989_01

GENERAL-

PURPOSE

USER I/O

PINS

M0 M1 PWRDWN

DOUT

HDC

OTHER

I/O PINS

RESET

DIN

CCLK

DATA

CLK

+5 V

•

OE/RESET

XC3000

FPGA

DEVICE

D/P

SCP

CEO

CASCADED

SERIAL

MEMORY

LDC

INIT

XC17xx

RESET

SLAVE LCAs WITH IDENTICAL

CONFIGURATIONS

DURING CONFIGURATION

THE 5 kΩ M2 PULL-DOWN

RESISTOR OVERCOMES THE

INTERNAL PULL-UP,

BUT IT ALLOWS M2 TO

BE USER I/O.

(LOW RESETS THE XC17xx ADDRESS POINTER)

TO CCLK OF OPTIONAL

VCC VPP

+5 V

DAISY-CHAINED LCAs WITH

DIFFERENT CONFIGURATIONS

TO DIN OF OPTIONAL

IF READBACK IS

ACTIVATED, A

5-kΩ RESISTOR IS

REQUIRED IN

SERIES WITH M1

DATA

CLK

OE/RESET

DAISY-CHAINED LCAs WITH

DIFFERENT CONFIGURATIONS

TO CCLK OF OPTIONAL

SLAVE LCAs WITH IDENTICAL

CONFIGURATIONS

TO DIN OF OPTIONAL

INIT

+5V

Figure 23: Master Serial Mode Circui t Diagram

XC3000 Series Field Programmable Gate Arrays

7-26 November 9, 1998 (Version 3.1)

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by

holding RESET Low until VCC has reac hed 4. 0 V (2.5 V for the XC3000L). A very l ong VCC rise time of >100 ms, or a

non-monot oni cally ris in g VCC may require >6-µs High level on RES ET, followed by a >6-µs Low leve l on RESET and D/P

after VCC has reached 4.0 V (2.5 V for the XC 3000L).

2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain sl ave-mode devices is

High.

3. Master-serial-mode timing is based on slave-mode testing.

Figure 24: Master Serial Mode Programming Switching Ch aracteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

1TDSCK

2TCKDS

n n + 1 n + 2

n – 3 n – 2 n – 1 n

X3223

Description Symbol Min Max Units

CCLK Data In setup 1 TDSCK 60 ns

Data In hold 2 CKDS 0ns

November 9, 1998 (Version 3.1) 7-27

XC3000 Series Field Programmable Gate Arrays

Master Parallel Mode

In Mast e r P ar all el mo de , the le ad FP GA di r ectl y ad dre sse s

an industry-standard byte-wide EPROM and accepts eight

data bits right before incrementing (or decrementing) the

addre ss ou tp ut s.

The eight data bits are serialized in the lead FPGA, which

then presents the preamble data (and all data that over-

flows the lead device) on the DOUT pin. There is an inter-

nal delay of 1.5 CCLK periods, after the rising CCLK edge

that accepts a byte of data, and also changes the EPROM

address, until the falling CCLK edge that makes the LSB

(D0) of this by te appear a t DOUT. This means that DOUT

changes on the falling CCLK edge, and the next device in

the daisy chain accepts data on the subsequent rising

CCLK edge.

X5990

RCLK

General-

Purpose

User I/O

Pins

M0 M1PWRDWN

HDC

Other

I/O Pins

A15

A14

A13

A12

A11

A10

+5 V

.....

FPGA

CCLK

DOUT

System Reset

A11

A12

A13

A14

A15

EPROM

RESET

...

Other

I/O Pins

DOUT

HDC

LDC

FPGA

Slave #1

+5 V

M0 M1PWRDWN

CCLK

DIN

D/P

Reset

DOUT

FPGA

Slave #n

+5 V

M0 M1PWRDWN

CCLK

DIN

D/P

General-

Purpose

User I/O

Pins

RESET

Master

...

+5 V

INIT

...

HDC

LDC

INIT

General-

Purpose

User I/O

Pins

+5 V

D/P

Other

I/O Pins

Note: XC2000 Devices Do Not

Have INIT to Hold Off a Master

Device. Reset of a Master Device

Should be Asserted by an External

Timing Circuit to Allow for LCA CCLK

Variations in Clear State Time.

Open

Collector

INIT N.C.

Reprogram

5 kΩ5 kΩ5 kΩ

5 kΩ Each

If Readback is

Activated, a

5-kΩ Resistor is

Required in

Series With M1

****

Figure 25: Master Parallel Mode Circuit Diagra m

XC3000 Series Field Programmable Gate Arrays

7-28 November 9, 1998 (Version 3.1)

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by

holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a

non-monot oni cally rising VCC ma y require a >6-µs High level on RESET, follow e d by a >6-µs Low level on RESET and D/P

after VCC has reached 4.0 V (2.5 V for the XC3000L).

2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain sl ave-mode devices is

High.

This timing diagram shows that the EPROM requirements are extremely relaxed:

EPROM access time can be longer than 4000 ns. E PROM data output has no hold time requirements.

Figure 26: Master Parallel Mode Programming Switching Characteristics

Address for Byte n

Byte

2TDRC

Address for Byte n + 1

D7D6

A0-A15

(output)

D0-D7

RCLK

(output)

CCLK

(output)

DOUT

(output)

1TRAC

7 CCLKs CCLK

3TRCD

Byte n - 1 X5380

Description Symbol Min Max Units

RCLK

To address valid

To data setup

To data hold

RCLK High

RCLK Low

TRAC

TDRC

TRCD

TRCH

TRCL

600

4.0

200 ns

µs

November 9, 1998 (Version 3.1) 7-29

XC3000 Series Field Programmable Gate Arrays

Peripheral Mode

Peripheral mode uses the trailing edge of the logic AND

conditio n of the CS0, C S1, CS2, and WS inputs to accept

byte-wide data from a microprocessor bus. In the lead

FPGA, t his dat a is loa ded int o a doubl e-bu ff ered UAR T-like

parallel-to-serial converter and is serially shifted into the

internal logic. The lead FPGA presents the preamble data

(and all data that overflows the lead device) on the DOUT

pin.

The Ready/Busy output from the lead device acts as a

handshake signal to the microprocessor. RDY/BUSY goes

Low when a byte has been received, and goes High again

when t h e byte -w i de in pu t b uf f er h as tr an sfer re d i ts i nf or ma-

tion into the shift register, and the buffer is ready to rece ive

new data. The length of the BUSY signal depends on the

activity in the UART. If the shift register had been empty

when th e n ew byt e w as rece i ve d, the BUS Y signal lasts for

only two CCLK periods. If the shift register was still full

when the new byte was received, the BUSY signal can be

as long as nine CCLK periods.

Note that after the last byte has been entered, only seven

of its bits are shifted out. CCLK remains High with DOUT

equal to bit 6 (the next-to- last bit) of the last byte entered.

X5991

ADDRESS

BUS DATA

BUS

D0–7

ADDRESS

DECODE

LOGIC CS0

...

RDY/BUSY

RESET

...

OTHER

I/O PINS

D0–7 CCLK

DOUT

HDC

LDC

FPGA GENERAL-

PURPOSE

USER I/O

PINS

D/P

M0 M1 PWR

DWN

+5 V

CS2

CS1

CONTROL

SIGNALS

INIT

REPROGRAM

+5 V

5 kΩ

* IF READBACK IS

ACTIVATED, A

5-kΩ RESISTOR IS

REQUIRED IN SERIES

WITH M1

OPTIONAL

DAISY-CHAINED

FPGAs WITH DIFFERENT

CONFIGURATIONS

Figure 27: Peripheral Mode Circuit Diagram

XC3000 Series Field Programmable Gate Arrays

7-30 November 9, 1998 (Version 3.1)

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by

holding RESET Low until VCC has reached 4.0 V (2.5 V for the X C3000L). A very l ong VCC rise time of >100 ms, or a

non-monot oni cally rising VCC ma y require a >6-µs High level on RESET, follow e d by a >6-µs Low level on RESET and D/P

after VCC has reached 4.0 V (2.5 V for the XC3000L).

2. Configurati on m ust be delayed unt i l the I NI T of all FPGAs is High.

3. Time from end of WS to CCLK cycle for the new byte of data de pends on comp l eti on of previous byte proces si ng and the

phase of the internal tim in g generator fo r CCLK.

4. CCLK and DOUT timing is t ested in slav e m ode.

5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY

occurs when a byte is loaded i nto an empty parallel-t o-serial converter. The longest TBUSY occurs when a new wo rd i s

loaded into t he i nput registe r before the se cond-level buffer ha s started sh i ft i ng out data.

Note:

This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY

will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted

immediately after th e end of BUSY.

Figure 28: Periphera l Mode Programming Switching C h aracteristics

BUSY

D6DOUT

RDY/BUSY

D7 D0 D1 D2

4WTRB

Valid

2DC

CCLK

D0-D7

CS2

WS, CS0, CS1

WRITE TO FPGA

X5992

Previous Byte New Byte

Description Symbol Min Max Units

WRITE

Eff ective Write time required

(Assertion of CS0, CS1, CS2, WS)1T

CA 100 ns

DIN Setup time required

DIN Hold time req uir ed 2

3TDC

TCD

0ns

RDY/BUSY delay after end of WS 4T

WTRB 60 ns

RDY

Earliest next WS after end of BUSY 5T

RBWT 0ns

BUSY Low time generated 6 TBUSY 2.5 9 CCLK

periods

November 9, 1998 (Version 3.1) 7-31

XC3000 Series Field Programmable Gate Arrays

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK

input(s ) of the FPGA( s). The serial co nfiguration bits tream

must be available at the DIN input of the lead FPGA a short

set-up time before each rising CCLK edge. The lead device

then presents the preamble data (and all data that over-

flow s th e le ad de vi ce) o n i t s D OUT p in. Th ere is an i n tern al

delay of 0.5 CCLK periods, which means that DOUT

changes on the falling CCLK edge, and the next device in

the daisy-chain accepts data on the subsequent rising

CCLK edge.

D/P

RESET

X5993

FPGA

General-

Purpose

User I/O

Pins

+5 V

M0 M1 PWRDWN

CCLK

DIN

STRB

RESET

I/O

Port

Micro

Computer

DOUT

HDC

LDC

...

Other

I/O Pins

INIT

+5 V

5 kΩ

If Readback is

Activated, a

5-kΩ Resistor is

Required in

Series with M1

Optional

Daisy-Chained

LCAs with

Different

Configurations

Figure 29: Slave Serial Mode Circuit Diagram

XC3000 Series Field Programmable Gate Arrays

7-32 November 9, 1998 (Version 3.1)

Notes: 1. The max limit of CCLK Lo w tim e i s caused by dy namic circui try inside the FPGA.

2. Configurati on m ust be delayed unt i l the I NI T of all FPGAs is High.

3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by

holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a

non-monot oni cally rising VCC ma y require a >6-µs High level on RESET, follow e d by a >6-µs Low level on RESET and D/P

after VCC has reached 4.0 V (2.5 V for the XC3000L).

Figure 30: Slave Serial Mode Programming Switching Characte ristics

4TCCH

Bit n Bit n + 1

Bit nBit n - 1

3TCCO

5TCCL

2TCCD

1TDCC

DIN

CCLK

DOUT

(Output)

X5379

Description Symbol Min Max Units

CCLK

To DOUT

DIN setup

DIN hold

High time

Low time (Note 1)

Frequency

TCCO

TDCC

TCCD

TCCH

TCCL

FCC

0.05

100

5.0

µs

MHz

November 9, 1998 (Version 3.1) 7-33

XC3000 Series Field Programmable Gate Arrays

Program Readback Switching Characteristics

Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.

2. RETRIG (M0 posit i ve transition) shal l no t be done until after one clock following a ct i ve I/ O pi ns.

3. Readback shoul d not be initiat ed until con fig uration i s comp l ete.

4. TCCLR is 5 µs min to 15 µs max for XC3000L.

1TRTH

TCCL

TCCRD

TCCL

TRTCC

DONE/PROG

(OUTPUT)

X6116

RTRIG (M0)

CCLK(1)

VALID

READBACK OUTPUT

HI-Z VALID

READBACK OUTPUT

M1 Input/

RDATA Output

Description Symbol Min Max Units

RTRIG RTRIG High 1 TRTH 250 ns

CCLK

RTRIG setup

RDATA delay

High time

Low time

TRTCC

TCCRD

TCCHR

TCCLR

200

0.5

100

µs

XC3000 Series Field Programmable Gate Arrays

7-34 November 9, 1998 (Version 3.1)

General XC3000 Series Switching Characteristics

Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by

holding RESET Low unt i l Vcc has reached 4.0 V (2.5 V for XC3000L). A very l ong Vcc rise ti me of >100 ms, or a

non-monot oni cally rising VCC ma y require a >1-µs High level on RESET, follow ed by a >6 -µs Low level on RESET and D/P

after Vcc has reached 4.0 V (2.5 V for XC3000L).

2. RESET timing relative to val id mode lines (M 0, M1, M2) is relevant when RES ET i s us ed to delay configuration. The

specif i ed hol d time is caus ed by a shift-register f ilt er slowing down the resp onse to RESET dur i ng configuration.

3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).

4 TMRW

2 TMR 3 TRM

5 TPGW

6 TPGI

Clear State Configuration StateUser State

Note 3

VCCPD X5387

RESET

M0/M1/M2

DONE/PROG

INIT

(Output)

PWRDWN

VCC (Valid)

Description Symbol Min Max Units

RESET (2) M0, M1, M2 setup time required

M0, M1, M2 hold time required

RESET Width (Low) req. for Abort

TMR

TRM

TMRW

4.5

µs

DONE/PROG Width (Low) required for Re-config.

INIT response after D/P is pulled Low 5

6TPGW

TPGI

67µs

µs

PWRDWN (3) Power Down VCC VCCPD 2.3 V

November 9, 1998 (Version 3.1) 7-35

XC3000 Series Field Programmable Gate Arrays

Device Performance

The XC3000 families of FPGAs can achieve very high per-

formance. This is the result of

• A sub-micron manufacturing process, developed and

continuously being enhanced for the production of

state-of-the-art CMOS SRAMs.

• Careful optimization of transistor geometries, circuit

design, and lay-out, based on years of experience with

the XC3000 family.

• A look-up table ba sed, coarse-grai ned architecture that

can collapse multiple-layer combinatorial logic into a

single function generator. One CLB can implement up

to four layers of conventional logic in as little as 1.5 ns.

Actual system performance is determined by the timing of

critical paths, including the delay through the combinatorial

and sequential logic elements within CLBs and IOBs, plus

the delay in the interconnect routing. The AC-timing speci-

fications state the worst-case timing parameters for the var-

ious logic resources available in the XC3000-families

architecture. Figure 31 shows a variety of elements

involved in determining system perfo rmance.

Logic block performance is expressed as the propagation

time fr om the in te rc on n ec t p oin t at th e inp u t t o th e block to

the ou tput of the bl ock in th e int erco nnect ar ea. S ince co m-

binatorial logic is implemented with a memory lookup table

within a CLB, the combinatorial delay through the CLB,

called TILO, is always the same, regardless of the function

being implemented. For the combinatorial logic function

driving the data input of the storage element, the critical

timing is data se t-up rela tive to the cl ock edge provide d to

the flip-flop element. The delay from the clock source to the

output of the logic block is critical in the timing signals pro-

duced by sto rage e leme nts. L oadi ng of a logi c-bl ock ou tput

is limited only by the resulting propagation delay of the

larger interconnect network. Speed performance of the

logic block is a function of supply voltage and temperatur e.

See Figure 32.

Interconnect performance depends on the routing

resources used to implement the signal path. Direct inter-

connects to the neighboring CLB provide an extremely fast

path. Local interconnects go through switch matrices

(magic boxes) and suffer an RC delay, equal to the resis-

tance of the pass transi stor mul tipli ed by the ca pacita nce of

the driven metal line. Longlines carry the signal across the

length or breadth of the chip with only one access delay.

Generous on-chip signal buffering makes performance rel-

atively insensitive to signal fan-out; increas ing f an-out from

1 to 8 changes the CLB delay by only 10%. Clocks can be

distributed with two low-skew cl ock distribution networks.

The tools in the Development System used to place and

route a d es ign in an XC 30 00 F PGA aut om at ica ll y cal c ula t e

the actual maximum worst-case delays along each signal

path. This timing information can be back-annotated to the

design’s netlist for use in timing simulation or examined

with , a stat ic timi ng analyzer.

Actual syst em performance is applications dependent. Th e

maximum clock rate that can be used in a system is deter-

mined by the critical path delays within that system. These

delays are combinations of incremental logic and routing

delays, and vary from design to design. In a synchronous

syst em, the maxi mum clock rate depends on the numbe r of

combinatorial logic layers between re-synchronizing

flip-flops. Figure 33 shows the achievable clock rate as a

function of the number of CLB layers.

CLBCLB IOBCLB

PAD

(K)

LogicLogic

CKO

CLOCK

Clock to Output Combinatorial Setup

TCKO TILO TICK

(K)

PAD

IOB

TPID TOKPO

X3178

Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing.

factors. Overall performance can be evaluated with th e timing calculator or by an optional simulation.

XC3000 Series Field Programmable Gate Arrays

7-36 November 9, 1998 (Version 3.1)

Power

Power Distribution

Power for t he FPG A i s d ist rib ut ed t hr oug h a gr i d t o ac hi e ve

high noise immunity and isolation between logic and I/O.

Inside the FPGA, a dedicated VCC and ground ring sur-

rounding the logic array provides power to the I/O drivers.

An i ndep enden t matr ix of VCC and gr oundlin es suppl ies th e

interior logic of the device. Thi s power distribution grid pro-

vide s a stable s upply and g round for all intern al logic, pr o-

viding the external package power pins are all connected

and appropriately decoupled. Typically a 0.1-µF capacitor

connected near the VCC and grou nd pins will pro vide ade-

quate decoupl ing.

Output buffers capable of driving the specified 4- or 8-mA

loads under worst-case conditions may be capable of driv-

ing as much as 25 to 30 times that current in a best case.

Noise can be reduced by minimizing external load capaci-

tance and reducing simultaneous output transitions in the

same direction. It may also be beneficial to locate heavily

loaded output buffers near the ground pads. The I/O Block

output buffers have a slew-limited mode which should be

used wh er e o utput r i se an d fal l t i mes a re n ot s pee d cri t ic al .

Slew-limited outputs maintain their dc drive capability, but

gener ate less external reflections an d inter n al noise.

1.00

0.80

0.60

0.40

0.20

SPECIFIED WORST-CASE VALUES

MAX COMMERCIAL (4.75 V)

MAX MILITARY (4.5 V)

– 55

MIN MILITARY (5.5 V)

MIN COMMERCIAL (4.75 V)

MIN COMMERCIAL (5.25 V)

TYPICAL COMMERCIAL

(+ 5.0 V, 25°C)

TYPICAL MILITARY

TEMPERATURE (°C)

– 40 – 20 0 25 40 70 80 100 125

NORMALIZED DELAY

X6094

MIN MILITARY (4.5 V)

Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variati ons

System Clock (MHz)

250

200

150

100

3 CLBs

(3-12)

4 CLBs

(4-16) 2 CLBs

(2-8) 1 CLB

(1-4)

XC3100A-3

XC3000A--6

CLB Levels:

Gate Levels:

300

Toggle

Rate

X7065

Figure 33: Clock Rate as a Function of Logic

Complexity (Number of Combinational Levels between

Flip-Flops)

November 9, 1998 (Version 3.1) 7-37

XC3000 Series Field Programmable Gate Arrays

Dynamic Power Consumption

Power Consumption

The Fie ld Progr ammable Gate Arra y exhibi ts the l ow power

consumption c haracteristic of CMOS ICs. For any design,

the configuration option of TTL chip input threshold

requires power for the threshold reference. The power

required by the s tatic memory cells that hold the configura-

tion data is very low and may be maintained in a

power-down mode.

Typica lly, most of p ower diss ipat ion is pr oduced by ex ternal

capacitive loads on the output buffers. This load and fre-

quency dependent power is 25 µW/pF/MHz per output.

Anothe r c om p on en t of I/O powe r is th e ex te rn al dc loa din g

on all output pins.

Internal power dissipation is a function of the number and

siz e of t he no des , and t he fr eq uen c y at w h ich th ey chan ge .

In an FPGA, the fraction of nodes changing on a given

clock is typically low (10-20%). For example, in a long

binary counter, the total activity of all counter flip-flops is

equivalent to that of only two CLB outputs toggling at the

clock frequency. Typical global clock-buffer power is

between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz

for the XC3090A. The internal capacitive load is more a

function of interconnect than fan-out. With a typical load of

three general interconnect segments, each CLB output

requires about 0.25 mW per MHz of i ts output frequency.

Because the control storage of the FPGA is CMOS static

memory, its cells require a very low standby current for data

retent ion. In som e systems, t his low data r etention c urrent

characteristic can be used as a method of preserving con-

figurations in the event of a primary power loss. The FPGA

has built in powerdown logic which, when activated, will

disable normal operation of the device and retain only the

configuration data. All internal operation is suspended and

output buff ers are placed i n their hi gh-imped ance st ate wit h

no pull - up s. D i f f ere nt f ro m th e XC 30 00 f ami l y whi ch ca n b e

powered down to a current consumption of a few micro-

amps, the XC3100A draws 5 mA, even in power-down.

This ma kes po wer- down op erati on le ss mean ing ful. In c on-

trast, ICCPD for the XC3000L is only 10 µA.

To f orce the FPGA in to the Po werdown s tate, the user must

pull the PWRDWN pin Low and continue to supply a reten-

tion voltage to the VCC pins. When normal power is

restored, VCC is elevated to its normal operating voltage

and PWRDWN is returned to a High. The FPGA resumes

operation with the same internal sequence that occurs at

the co nc l usi on of c on fig ur at ion. I n te rna l-I / O a nd lo gi c- bl o ck

storage elements will be reset, the outputs will become

enabled and the DONE/PROG pin will be released.

When VCC is shut down or disconnected, some power

might unintentionally be supplied from an incoming signal

driving an I/O pin. The conventional electrostatic input pro-

tection is implemented with diodes to the supply and

ground. A positive voltage applied to an input (or output)

will cause the positive protection diode to conduct and drive

the VCC connection. This condition can produce invalid

power conditions and should be avoided. A large series

resistor might be used to limit the current or a bipolar buffer

may be used to isolate the inpu t sig nal.

XC3042A XC3042L XC3142A

One CLB driving three local interconnects 0.25 0.17 0.25 mW per MHz

One global clock buffer and clock line 2.25 1.40 1.70 mW per MHz

One device output wit h a 50 pF loa d 1.25 1.25 1.25 mW per MHz

XC3000 Series Field Programmable Gate Arrays

7-38 November 9, 1998 (Version 3.1)

Pin Descriptions

Permanently Dedicated Pins

VCC

Two to eight (depending on package type) connections to

the po sitive V supply voltage. All must be con nected.

GND

Two to eight (depending on package type) connections to

ground. All must be connected.

PWRDWN

A Low on this CMOS-compatible input stops all internal

activity, but retains configuration. All flip-flops and latches

are reset, all outputs are 3-stated, and all inputs are inter-

preted as High, independent of their actual level. When

PWDWN returns High, the FPGA becomes operational

with DONE Low for two cycles of the internal 1-MHz clock.

Before and during configuration, PWRDWN must be High.

If not used, PWRDWN must be tied to VCC.

RESET

This is an active Low input which has three functio ns.

Prior to the start of configuration, a Low input will delay the

start of the confi gurat ion proces s. An intern al cir cuit sen ses

the application of power and begins a minimal time-out

cycle. When the time-out and RESET are complete, the

levels of the M lines are sampled and configuration begins.

If RESET is asserted during a configuration, the FPGA is

re-initialized and restarts the configuration at the termina-

tion of RESET.

If RESET is asserted after configuration is complete, it pro-

vides a global asynchronous RESET of all IOB and CLB

storage elements of the FPGA.

CCLK

Duri ng conf ig urati on, Co nfi gurat ion C lock is a n out put of an

FPGA in Master mode or Peripheral mode, but an input in

Slave mode. During Readback, CCLK is a clock input for

shifting c onfigurati on data out of the FPGA.

CCLK drives dynamic circuitry inside the FPGA. The Low

time may, theref ore, n ot excee d a few mi crose conds. W hen

used as an input, CCLK must be “parked High”. An internal

pull-up resistor maintains High when the pin is not being

driven.

DONE/PROG (D/P)

DONE is an open-drain output, configurable with or without

an int ernal pul l-up resis tor of 2 to 8 k Ω. At the completion of

configuration, the FPGA circuitry becomes active in a syn-

chronous order; DONE is programmed to go active High

one cycle either before or after the outputs go active.

Once configuration i s done, a High-to-Low transition of this

pin will cause an initialization of the FPGA and start a

reconfiguration.

M0/RTRIG

As Mode 0, t hi s i np ut i s sa mpl ed on po wer- on t o deter mi n e

the power -on delay (214 cycles if M0 is High, 216 cycles if M0

is Low). Before the start of confi guration, this i nput i s again

sampled together with M1, M2 to determine the configura-

tion mode to be used.

A Low-to-High input transition, after configuration is com-

plete, acts as a Read Trigger and initiates a Readback of

configuration and storage-element data clocked by CCLK.

By sele c tin g t he app ro pri at e Rea dba ck o pt ion w h en ge ner-

ating the bit stream, this o peration may be l imite d to a s ingle

Readback, or be inhibited al together.

M1/RDATA

As Mode 1, this input and M0, M2 are sampled before the

start of configurat ion to establish the conf igurat ion mode to

be used . If Read back i s ne ver u sed, M1 can b e ti ed dire ctl y

to ground or VCC. I f Rea dba ck is ev er us ed, M1 mu st us e a

5-kΩ resistor to ground or VCC, to accommodate the

RDATA output.

As an active-Low Read Data, after configuration is com-

plete, this pin is the output of the Readback data.

User I/O Pins That Can Have Special

Functions

During configuration, this input has a weak pull-up resistor.

Together with M0 and M1, it is sampled before the start of

configuration to establish the configuration mode to be

used. A fter configuration, this pin is a user-programmable

I/O pin.

HDC

During configuration, this output is held at a High level to

indicate that configuration is not yet complete. After config-

uration, this pin i s a user- programmable I/O pin.

LDC

During Configuration, this output is held at a Low level to

indicate that the configuration is not yet complete. After

confi gu ra tio n, t his p i n is a u ser- pr ogr amm abl e I/ O p i n. L DC

is par ticula rly useful in Maste r mode as a Low enable for an

EPROM, but it must then be programmed as a High after

configuration.

INIT

This is an act ive Lo w open-d rai n output with a weak pull -up

and is held L ow d uring th e po wer stabilizat ion a nd int ernal

clear ing of t he co nfigu rati on me mory. It can be used t o i ndi-

cate s tatus to a configuring microprocessor or, as a wired

November 9, 1998 (Version 3.1) 7-39

XC3000 Series Field Programmable Gate Arrays

AND of several slave mode devices, a hold-off signal for a

master mode device. After configuration this pin becomes a

user-programmable I/O pin.

BCLKIN

This is a direct CMOS level input to the alternate clock

buffer (Auxiliary Buffer) in the lower right corner.

XTL1

This u ser I/O pi n can be used to operat e as the outp ut of an

amplifie r dr ivin g an exte rn a l cryst al an d bia s circ uit ry.

XTL2

This user I/O pin can be used as the input of an amplifier

connected to an external crystal and bias circuitry. The I/O

Block is left unconfigured. The oscillator configuration is

activate d by rou ting a net fro m the os cillator buffer sy mbol

output and by the MakeBits program.

CS0, CS 1, CS2, WS

These four inputs represent a set of signals, three active

Low and one active High, that are used to control configu-

ration-data entry in the Peripheral mode. Simultaneous

assertion of all four inputs generates a Write to the internal

data buffer. The removal of any assertion clocks in the

D0-D7 data. I n Mas ter- P ar all e l mode , W S and CS 2 ar e t he

A0 and A1 outputs. After configuration, these pins are

user-programmable I/O pins.

RDY/BUSY

During Peripheral Parallel mode configuration this pin indi-

cates when the chip is ready for another byte of data to be

written to it. After configuration is complete, this pin

becomes a user -programmed I/O pin.

RCLK

During Master Parallel mode configuration, each change

on the A0-15 outputs is preceded by a rising edge on

RCLK, a redundant output signal. After configuration is

complete, this pi n becomes a user-programmed I/O pin.

D0-D7

This set of eight pins represents the parallel configuration

byte for the parallel Master and Peripheral modes. After

configuration is complete, they are user-programmed I/O

pins.

A0-A15

During Master Parallel mode, these 16 pins present an

addre ss output for a confi guration E PROM. After co nfigura-

tion , the y ar e use r -p ro gr a mm a ble I/O pins.

DIN

Durin g Slave or Mast er Seria l confi gurati on, this pin is used

as a serial-data input. In the Master or Peripheral configu-

ration, this is the Data 0 input. After configuration is com-

plete, this pin becomes a user-programmed I/O pin.

DOUT

Durin g conf i gura t io n thi s pin is us ed to out p ut se ri al- c onfi g-

uration data to the DIN pin of a daisy-chained slave. After

configuration is complete, this pin becomes a user-pro-

grammed I/O pin.

TCLKIN

This is a direct CMOS-level input to the global clock buffer.

This pin can also be conf igure d as a user pr ogrammable

I/O pi n. Howe ver , since TCLKIN is the pr eferred input t o the

global clock net, and th e globa l clock net sho uld be use d as

the primary clock source, this pin is usually the clock input

to the chip.

Unrestricted User I/O Pins

I/O

An I/O pin may be programmed by the user to be an Input

or an Out put p in f ollow ing co nfi gura tion. All unrest ric ted I /O

pins, plus the spec ial pins ment ioned on the follo wing page,

have a weak pull-up resistor that becomes activ e as soon

as the device powers up, and stays active until the end of

configuration.

Note:

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak

pull-up resistor.

XC3000 Series Field Programmable Gate Arrays

7-40 November 9, 1998 (Version 3.1)

Pin Functions During Configuration

Configuration Mo de <M2:M1:M0 > *** ** ****

SLAVE

SERIAL

<1:1:1>

MASTER-

SERIAL

<0:0:0> PERIPH

<1:0:1>

MASTER-

HIGH

<1:1:0>

MASTER-

LOW

<1:0:0> 44

PLCC 64

VQFP 68

PLCC 84

PGA 100

PQFP

100

VQFP

TQFP 132

PGA 144

TQFP 160

PQFP 175

PGA 176

TQFP 208

PQFP User

Function

POWR

DWN

(I)

POWER

DWN

(I)

POWER

DWN

(I)

POWER

DWN

(I)

POWER

DWN

(I) 7 17 10 12 B2 29 26 A1 1 159 B2 1 3

POWER

DWN

(1)

M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) 16 31 25 31 J2 52 49 B13 36 40 B14 45 48 RDATA

M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (LOW) (I) 17 32 26 32 L1 54 51 A14 38 42 B15 47 50 RTRIG (I)

M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) 18 33 27 33 K2 56 53 C13 40 44 C15 49 56 I/O

HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HD C (HIGH) 19 34 28 34 K3 57 54 B14 41 45 E14 50 57 I/O

LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) 20 36 30 36 L3 59 56 D14 45 49 D16 54 61 I/O

INIT* INIT* INIT* INIT* INIT* 22403442K66562G145359H156577 I/O

GND GND GND GND GND 23 41 35 43 J6 66 63 H12 55 61 J14 67 79 GND

26 47 43 53 L11 76 73 M13 69 76 P15 85 100 XTL2 OR I/O

RESET (I) RESET (I) RESET (I) RESET (I) RESET (I) 27 48 44 54 K10 78 75 P14 71 78 R15 87 102 RESET (I)

DONE DONE DONE DONE DONE 28 49 45 55 J10 80 77 N13 73 80 R14 89 107 PROGRAM (I)

DATA 7 (I) DATA 7 (I) DATA 7 (I) 50 46 56 K11 81 78 M12 74 81 N13 90 109 I/O

30 51 47 57 J11 82 79 P13 75 82 T14 91 110 XTL1 OR I/O

DATA 6 (I) DATA 6 (I) DATA 6 (I) 52 48 58 H10 83 80 N11 78 86 P12 96 115 I/O

DATA 5 (I) DATA 5 (I) DATA 5 (I) 53 49 60 F10 87 84 M9 84 92 T11 102 122 I/O

CS0 (I) 54 50 61 G10 88 85 N9 85 93 R10 103 123 I/O

DATA 4 (I) DATA 4 (I) DATA 4 (I) 55 51 62 G11 89 86 N8 88 96 R9 108 12 8 I/O

DATA 3 (I) DATA 3 (I) DATA 3 (I) 57 53 65 F11 92 89 N7 92 102 P8 112 132 I/O

CS1 (I) 58 54 66 E11 93 90 P6 93 103 R8 113 133 I/O

DATA 2 (I) DATA 2 (I) DATA 2 (I) 59 55 67 E10 94 91 M6 96 106 R7 118 138 I/O

DATA 1 (I) DATA 1 (I) DATA 1 (I) 60 56 70 D10 98 95 M5 102 114 R5 124 145 I/O

RDY/BUSY RCLK RCLK 61 57 71 C11 99 96 N4 103 115 P5 125 146 I/O

DIN (I) DIN (I) DA T A 0 (I) DATA 0 (I) DATA 0 (I) 38 62 58 72 B11 100 97 N2 106 119 R3 130 151 I/O

DOUT DOUT DOUT DOUT DOUT 39 63 59 73 C10 1 98 M3 107 120 N4 131 152 I/O

CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (O) 40 64 60 74 A11 2 99 P1 108 121 R2 132 153 CCLK (I)

WS (I) A0 A0 1 61 75 B10 5 2 M2 111 124 P2 135 161 I/O

CS2 (I) A1 A1 2 62 76 B9 6 3 N1 112 125 M3 136 162 I/O

A2 A2 3 63 77 A10 8 5 L2 115 128 P1 140 165 I/O

A3 A3 4 64 78 A9 9 6 L1 116 129 N1 141 166 I/O

A15 A15 65 81 B6 12 9 K1 119 132 M1 146 172 5

A4 A4 5 66 82 B7 13 10 J2 120 133 L2 147 173 I/O

A14 A14 6 67 83 A7 14 11 H1 123 136 K2 150 178 I/O

A5 A5 7 68 84 C7 15 12 H2 124 137 K1 151 179 I/O

A13 A13 9 2 2 A6 17 14 G2 128 141 H2 156 184 I/O

A6 A6 10 3 3 A5 18 15 G1 129 142 H1 157 185 I/O

A12 A12 11 4 4 B5 19 16 F2 133 147 F2 164 192 I/O

A7 A7 12 5 5 C5 20 17 E1 134 148 E1 165 193 I/O

A11 A11 13 6 8 A3 23 20 D1 137 151 D1 169 199 I/O

A8 A8 14 7 9 A2 24 21 D2 138 152 C1 170 200 I/O

A10 A10 15 8 10B325 22B1141155E3173203 I/O

A9 A9 16 9 11 A1 26 26 C2142156C2174204 I/O

All Others

X X X X XC3x20A etc.

X X X X X X X XC3x3 0A etc.

XXX XXX XC3x42A etc.

X** X X XC3x64A etc.

X** X X X X X XC3x90A etc.

Notes: X** X X X XC3195A

(I)

***

****

Note:

Generic I/O pins are not shown.

For a detailed description of the configuration modes, see page 25 through page 34.

For pinout details, see page 65 through page 76.

Represents a weak pull-up before and during configuration.

INIT is an open drain output during configuration.

Represents an input.

Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.

Peripheral mode and master parallel mode are not supported in the PC44 package.

Pin assignments for the XC3195A PQ208 differ from those shown.

Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.

The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.

November 9, 1998 (Version 3.1) 7-41

XC3000 Series Field Programmable Gate Arrays

XC3000A Switching Characteristics

Xilinx maintains test specifications for each product as controlled documents. T o insure the use of the most recently released

device per formance parameters, please request a copy of the c urrent test-specification revision.

XC3000A Operatin g Con dition s

Note: At junction temperatures above those listed as Operating Condi tions, all delay paramet ers increase by 0.3% per °C.

XC3000A DC Characteristics Over Operating Conditions

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA

device configured with a tie option.

2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed

100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC 3090A.

3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.

Symbol Description Min Max Units

VCC

Supply voltage relat ive to GND Comme rc ial 0°C to + 85°C junction 4.75 5.25 V

Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V

VIHT High-level input voltage — TTL configuration 2.0 VCC V

VILT Low-level input voltage — TTL configuration 0 0.8 V

VIHC High-level input voltage — CMOS configuration 70% 100% VCC

VILC Low-level input voltage — CMOS configuration 0 20% VCC

TIN Input signal transition time 250 ns

Symbol Description Min Max Units

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) Commercial 3.86 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) Industrial 3.76 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V

VCCPD Power-down sup ply volt age (PWRDW N must be Low) 2.30 V

ICCPD Power-down supply current

(VCC(MAX) @ TMAX) 3020A

3030A

3042A

3064A

3090A

100

160

240

340

500

µA

ICCO

Quiescent FPGA supply current in addition to ICCPD

Chip thresholds programmed as CMOS levels

Chip thresholds programmed as TTL levels 500

10 µA

µA

IIL Input Leakage Current –10 +10 µA

CIN

Inpu t capacitance, all packages except PGA 1 75

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 10

15 pF

Inp u t capacitance, PGA 175

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 16

20 pF

IRIN Pad pull-up (when selected) @ VIN = 0 V30.02 0.17 mA

IRLL Horizontal Longl ine pull-up (when selec ted) @ logic Low 3.4 mA

XC3000 Series Field Programmable Gate Arrays

7-42 November 9, 1998 (Version 3.1)

XC3000A Absolute Maximu m Ratings

Note: Stresses bey ond those list ed under Absolut e M axi m um Ratings may cause permanent damage to th e devi ce. These are

stress ra tings only, and functional operation of th e devi ce at these or any other con di tions beyond t hose listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended

periods of time may affect device reliability.

XC3000A Global Buffer Switching Characteristics Guidelines

Note: 1. Timing is based on the XC3042A, fo r other devices see t imi ng calculator.

Symbol Description Units

VCC Supply voltage r e lative to GND –0.5 to +7.0 V

VIN Inp ut voltage with respect to GND –0.5 to VCC +0.5 V

VTS Vol tage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum sold er ing tem p er at ur e (1 0 s @ 1/1 6 in.) +260 °C

TJJunc tion tem p er at ur e pla st i c +125 °C

Junction temperature ceramic +150 °C

Speed Grade -7 -6

Description Symbol Max Max Units

Global and Alternat e Clock Distribution1

Either: Normal IOB in put pad throug h clock buffer

to any CLB or IOB clock input

Or: Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input

TPID

TPIDC

7.5

6.0

7.0

5.7

TBUF driving a Horizontal Longline (L.L.)1

I to L.L. while T is Low (buffer ac tive)

T↓ to L.L. active and valid wi th sin g le pull-up resistor

T↓ to L.L. active and valid with pair of pull-up resistors

T↑ to L.L. High with single pull-up resistor

T↑ to L.L. High with pair of pull-up resistors

TIO

TON

TPUS

TPUF

4.5

9.0

11.0

16.0

10.0

4.0

8.0

10.0

14.0

8.0

BIDI Bidirectional buffer delay TBIDI 1.7 1.5 ns

November 9, 1998 (Version 3.1) 7-43

XC3000 Series Field Programmable Gate Arrays

XC3000A CLB Switching Chara cteristics Gu idelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is based on the XC3042A, fo r other devices see t imi ng calculator.

2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the

Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

Speed Grade -7 -6

Description Symbol Min Max Min Max Units

Combinatorial Delay

Logic Variab les A , B, C, D, E, to outpu ts X or Y

FG Mode

F and FGM Mode 1T

ILO 5.1

5.6 4.1

4.6 ns

Sequ e nt ial de lay

Clock k to outputs X or Y

Clock k to outputs X or Y when Q is returned

through function generators F or G to drive X or Y

FG Mode

F and FGM Mode

CKO

TQLO

4.5

9.5

10.0

4.0

8.0

8.5

Set-up time before clock K

Logic Varia bles A, B, C, D, E

FG Mode

F and FGM Mode

Data In DI

Enable Clock EC

TICK

TDICK

TECCK

4.5

5.0

4.0

4.5

3.5

4.0

3.0

4.0

Hold Time aft er clock K

Logic Varia bles A, B, C, D, E

Data In DI2

Enable Clock EC

TCKI

TCKDI

TCKEC

1.0

2.0

1.0

2.0

Clock

Clock Hi gh time

Clock Low time

Max. flip-flop toggle rate

12 TCH

TCL

FCLK

4.0

113.0

3.5

135.0

MHz

Reset Direct (RD)

RD width

delay from RD to outpu ts X or Y 13

9TRPW

TRIO

6.0 6.0 5.0 5.0 ns

Global Reset (RESET Pad)1

RESET width (Low)

delay from RESET pad to outputs X or Y TMRW

TMRQ

16.0 19.0 14.0 17.0 ns

XC3000 Series Field Programmable Gate Arrays

7-44 November 9, 1998 (Version 3.1)

XC3000A CLB Switching Chara cteristics Gu idelines (continued )

1TILO

CLB Output (X, Y)

(Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

CLB Input

(Direct In)

CLB Input

(Enable Clock)

CLB Output

(Flip-Flop)

CLB Input

(Reset Direct)

CLB Output

(Flip-Flop)

8TCKO

X5424

13 T

RPW

RIO

4TDICK

6TECCK

12 TCL

2TICK 3TCKI

11 TCH

5TCKDI

7TCKEC

November 9, 1998 (Version 3.1) 7-45

XC3000 Series Field Programmable Gate Arrays

XC3000A IOB Switching Cha racte ristics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is measured at pin threshold, wi th 50 pF external ca pacitive loads (incl. t est fixture). Typical slew rate limited output

rise/fal l ti m es are approximately f our times longer.

2. Voltage levels of unused (bonded and unbonded) pads must be vali d l ogic levels. Each can be configured with the inte rnal

pull-up resistor or alternatively configured as a driven output or driven from an external source.

3. In put pad set-u p time is specified with respect to the i nternal clock (ik). In order to calculate sys tem set-up time, subtra ct

clock delay (pad to ik) from the input pad set-up time val ue. Input pad hol dtime with respect to th e internal clock (ik) is

negative. This means that pad level changes immediatel y before the int ernal clock edge (ik) will no t be recognized.

4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.

Speed Grade -7 -6

Description Symbol Min Max Min Max Units

Propagation Delays (Input)

Pad to Direct In (I)

Pad to Registered In (Q) with latch transparent

Clock (IK) to Registered In (Q)

TPID

TPTG

TIKRI

4.0

15.0

3.0

14.0

2.5

Set-up Time (Input)

Pad to Clock (IK) set-up time 1 TPICK 14.0 12.0 ns

Propagation Delays (Output)

Clock (OK) to Pad (fast)

same (slew rate limited)

Output (O) to Pad (fast)

same (slew-rate limited)

3-state to Pad begin hi-Z (fast)

same (slew-rate limited)

3-state to Pad active and valid (fast)

same (slew -rate limited)

TOKPO

TOPF

TOPS

TTSHZ

TTSON

8.0

18.0

6.0

16.0

10.0

20.0

11.0

21.0

7.0

15.0

5.0

13.0

9.0

12.0

10.0

18.0

Set-up and Hold Times (Output)

Output (O) to clock (OK) set-up time

Output (O) to clock (OK) hold time 5

6TOOK

TOKO

8.0

07.0

0ns

Clock

Clock Hi gh time

Clock Low time

Max. fl ip-flop toggle rate

12 TIOH

TIOL

FCLK

4.0

113.0

3.5

135.0

MHz

Global Reset Delays (based on XC3042A)

RESET Pad to Registered In (Q)

RESET Pad to output pad (fast)

(slew-rate limited)

TRRI

TRPO

24.0

33.0

43.0

23.0

29.0

37.0

XC3000 Series Field Programmable Gate Arrays

7-46 November 9, 1998 (Version 3.1)

XC3000A IOB Switching Characteristics Guidelines (con tinu ed)

3TPID

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

5TOOK

12 TIOL

1TPICK

11 TIOH

4TIKRI

15 TRPO

13 TRRI

6TOKO

9TTSHZ

10 TOP

7TOKPO

8TTSON

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

November 9, 1998 (Version 3.1) 7-47

XC3000 Series Field Programmable Gate Arrays

XC3000L Switching Characteristics

Xilinx maintains test specifications for each product as controlled documents. T o insure the use of the most recently released

device per formance parameters, please request a copy of the c urrent test-specification revision.

XC3000L Oper ating Co nditions

Notes: 1. At junction temperatures above those list ed as Operating Con di ti ons, all dela y parameters increase by 0.3% per °C.

2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to

restrict operation to the 3.0 to 3.6 V rang e later, when smalle r devi ce geometries might pre clude operatio n at 5V. Operating

condit io ns are guaranteed in the 3.0 – 3.6 V V CC range.

XC3000L DC Charac teristics Over Operating Con dition s

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA

device configured with a tie option. ICCO is i n addition to ICCPD.

2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed

100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC30 90L.

3. Not tested. All ows an undriven pin to float High. For any other purpose, use an ext ernal pull-up.

Symbol Description Min Max Units

VCC Supp ly volta g e relat ive to GND Comm e rc ial 0°C to +85 °C junction 3.0 3.6 V

VIH High-level input voltage — TTL configuration 2.0 VCC+0.3 V

VIL Low-lev el inp ut voltage — TTL conf igu ratio n -0.3 0.8 V

TIN Input signal transition time 250 ns

Symbol Description Min Max Units

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) 2.40 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) VCC -0.2 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.2 V

VCCPD Power-down sup ply volt age (PWRDW N must be Low) 2.30 V

ICCPD Power- down supply current (VCC(MAX) @ TMAX)10µA

ICCO Quiescent FPGA supply current in addition to ICCPD1

Chip thresholds programmed as CMOS levels 20 µA

IIL Input Leakage Current –10 +10 µA

CIN

Inpu t capacitance, all packages except PGA 1 75

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 10

15 pF

Inp u t capacitance, PGA 175

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 15

20 pF

IRIN Pad pull-up (when selected) @ VIN = 0 V3 0.01 0.17 mA

IRLL Horizontal Longl ine pull-up (when selected) @ logic Lo w 2.50 mA

XC3000 Series Field Programmable Gate Arrays

7-48 November 9, 1998 (Version 3.1)

XC3000L Absolu te Maxim um Ratings

Note: Stresses bey ond those list ed under Absolut e M axi m um Ratings may cause permanent damage to th e devi ce. These are

stress ra tings only, and functional operation of th e devi ce at these or any other con di tions beyond t hose listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended

periods of time may affect device reliability.

XC3000L Global Buffer Switching Char acter istics Guide lines

Notes: 1. Timing is bas ed on the XC3042A, for other devi ces see timing cal culator.

2. The use of tw o pull-up resistors per Long line, avail abl e on other XC3000 devi ces, is not a va lid option for XC3000L device s.

Symbol Description Units

VCC Supply voltage r e lative to GND –0.5 to +7.0 V

VIN Inp ut voltage with respect to GND –0.5 to VCC +0.5 V

VTS Vol tage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum sold er ing tem p er at ur e (1 0 s @ 1/1 6 in.) +260 °C

TJJunc tion tem p er at ur e pla st i c +125 °C

Junction temperature ceramic +150 °C

Speed Grade -8

Description Symbol Max Units

Global and Alternat e Clock Distribution1

Either: Normal IOB in put pad throug h clock buffer

to any CLB or IOB clock input

Or: Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input

TPID

TPIDC

9.0

7.0

TBUF driving a Horizontal Longline (L.L.)1

I to L.L. while T is Low (buffer ac tive)

T↓ to L.L. active and valid wi th sin g le pull-up resistor

T↑ to L.L. High with single pull-up resistor

TIO

TON

TPUS

5.0

12.0

24.0

BIDI Bidirectional buffer delay TBIDI 2.0 ns

November 9, 1998 (Version 3.1) 7-49

XC3000 Series Field Programmable Gate Arrays

XC3000L CLB Switching Char acter istics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is based on t he XC3042L, for ot her devic es see timing calculator.

2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the

Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

Speed Grade -8

Description Symbol Min Max Units

Combinatorial Delay

Logic Variables A, B, C, D, E, to outputs X or Y

FG Mode

F and FGM Mode 1T

ILO 6.7

7.5 ns

Sequ e nt ial de lay

Clock k to outputs X or Y

Clock k to outputs X or Y when Q is returned

through function generators F or G to drive X or Y

FG Mode

F and FGM Mode

CKO

TQLO

7.5

14.0

14.8

Set-up time before clock K

Logic Varia bles A, B, C, D, E

FG Mode

F and FGM Mode

Data In DI

Enable Clock EC

TICK

TDICK

TECCK

5.0

5.8

5.0

6.0

Hold Time aft er clock K

Logic Varia bles A, B, C, D, E

Data In DI2

Enable Clock EC

TCKI

TCKDI

TCKEC

2.0

Clock

Clock Hi gh time

Clock Low time

Max. flip-flop toggle rate

12 TCH

TCL

FCLK

5.0

80.0

MHz

Reset Direct (RD)

RD width

delay from RD to outpu ts X or Y 13

9TRPW

TRIO

7.0

7.0 ns

Global Reset (RESET Pad)1

RESET width (Low)

delay from RESET pad to outputs X or Y TMRW

TMRQ

16.0 23.0 ns

XC3000 Series Field Programmable Gate Arrays

7-50 November 9, 1998 (Version 3.1)

XC3000L CLB Switching Char acter istics Guideline s (continue d)

1TILO

CLB Output (X, Y)

(Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

CLB Input

(Direct In)

CLB Input

(Enable Clock)

CLB Output

(Flip-Flop)

CLB Input

(Reset Direct)

CLB Output

(Flip-Flop)

8TCKO

X5424

13 T

RPW

RIO

4TDICK

6TECCK

12 TCL

2TICK 3TCKI

11 TCH

5TCKDI

7TCKEC

November 9, 1998 (Version 3.1) 7-51

XC3000 Series Field Programmable Gate Arrays

XC3000L IOB Switching Ch arac teristics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output

rise/fal l ti m es are approximately f our times longer.

2. Voltage levels of unused (bonded and unbonded) pads must be vali d l ogic levels. Each can be configured with the inte rnal

pull-up resistor or alternatively configured as a driven output or driven from an external source.

3. In put pad set-u p time is specified with respect to the i nternal clock (ik). In order to calculate sys tem set-up time, subtra ct

clock delay (pad to ik) from the input pad set-up time val ue. Input pad hol dtime with respect to th e internal clock (ik) is

negative. This means that pad level changes immediatel y before the int ernal clock edge (ik) will no t be recognized.

4. TPID, TPTG, and TPICK are 3 ns higher for X T L2 when the pin is conf i gured as a user input.

Speed Grade -8

Description Symbol Min Max Units

Propagation Delays (Input)

Pad to Direct In (I)

Pad to Registered In (Q) with latch transparent

Clock (IK) to Registered In (Q)

TPID

TPTG

TIKRI

5.0

24.0

6.0

Set-up Time (Input)

Pad to Clock (IK) set-up time 1 TPICK 22.0 ns

Propagation Delays (Output)

Clock (OK) to Pad (fast)

same (slew rate limited)

Output (O) to Pad (fast)

same (slew-rate limited)

3-state to Pad begin hi-Z (fast)

same (slew-rate limited)

3-state to Pad active and valid (fast)

same (slew -rate limited)

TOKPO

TOPF

TOPS

TTSHZ

TTSON

12.0

28.0

9.0

25.0

12.0

28.0

16.0

32.0

Set-up and Hold Times (Output)

Output (O) to clock (OK) set-up time

Output (O) to clock (OK) hold time 5

6TOOK

TOKO

12.0

0ns

Clock

Clock Hi gh time

Clock Low time

Max. fl ip-flop toggle rate

12 TIOH

TIOL

FCLK

5.0

80.0

MHz

Global Reset Delays (based on XC3042L)

RESET Pad to Registered In (Q)

RESET Pad to output pad (fast)

(slew-rate limited)

TRRI

TRPO

25.0

35.0

51.0

XC3000 Series Field Programmable Gate Arrays

7-52 November 9, 1998 (Version 3.1)

XC3000L IOB Switching Ch arac teristics Guidelines (continued )

3TPID

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

5TOOK

12 TIOL

1TPICK

11 TIOH

4TIKRI

15 TRPO

13 TRRI

6TOKO

9TTSHZ

10 TOP

7TOKPO

8TTSON

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

November 9, 1998 (Version 3.1) 7-53

XC3000 Series Field Programmable Gate Arrays

XC3100A Switching Characteristics

Xilinx maintains test specifications for each product as controlled documents. T o insure the use of the most recently released

device per formance parameters, please request a copy of the c urrent test-specification revision.

XC3100A Operatin g Con dition s

Note: At junction temperatures above those listed as Operating Condi tions, all delay paramet ers increase by 0.3% per °C.

XC3100A DC Characteristics Over Operating Conditions

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA

device configured with a tie option.

2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for

the XC3120 A in the PC84 package, to eight for t he XC 3195A in the PQ208 package .

3. Not tested. All ows an undriven pin to float High. For any other purpose, use an ext ernal pull-up.

Symbol Description Min Max Units

VCC Supply volta ge re lat ive to GND Comme rc ial 0°C to + 85°C junction 4.25 5.25 V

Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V

VIHT High-level input voltage — TTL configuration 2.0 VCC V

VILT Low-level input voltage — TTL configuration 0 0.8 V

VIHC High-level input voltage — CMOS configuration 70% 100% VCC

VILC Low-level input voltage — CMOS configuration 0 20% VCC

TIN Input signal transition time 250 ns

Symbol Description Min Max Units

VOH High-level output voltage (@ IOH = –8.0 mA, VCC min) Commercial 3.86 V

VOL Low-level output voltage (@ IOL = 8.0 mA, VCC min) 0.40 V

VOH High-level output voltage (@ IOH = –8.0 mA, VCC min) Industrial 3.76 V

VOL Low-level output voltage (@ IOL = 8.0 mA, VCC min) 0.40 V

VCCPD Power-down sup ply volt age (PWRDW N must be Low) 2.30 V

ICCO

Quiescent LCA supply current in addition to ICCPD1

Chip thresholds programmed as CMOS levels

Chip thresholds programmed as TTL levels 8

14 mA

IIL Input Leakage Current –10 +10 µA

CIN

Inpu t capacitance, all packages except PGA 1 75

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 10

15 pF

Inp u t capacitance, PGA 175

(sample tested)

All Pins except XTL1 and XTL2

XTL 1 an d X T L2 15

20 pF

IRIN Pad pull-up (when selected) @ VIN = 0 V30.02 0.17 mA

IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.20 2.80 mA

XC3000 Series Field Programmable Gate Arrays

7-54 November 9, 1998 (Version 3.1)

XC3100A Absolute Maximu m Ratings

Note: Stresses bey ond those list ed under Absolut e M axi m um Ratings may cause permanent damage to th e devi ce. These are

stress ra tings only, and functional operation of th e devi ce at these or any other con di tions beyond t hose listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended

periods of time may affect device reliability.

XC3100A Global Buffer Switching Characteristics Guidelines

Note: 1. Timing is bas ed on the XC3142A, fo r other devices see t iming calcula tor.

The use of two pull-up resis to rs per longli ne, availab l e on other XC3000 d evi ces, is not a val i d design optio n for XC3100A

devices.

Symbol Description Units

VCC Supply voltage r e lative to GND –0.5 to +7.0 V

VIN Inp ut voltage with respect to GND –0.5 to VCC +0.5 V

VTS Vol tage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum sold er ing tem p er at ur e (1 0 s @ 1/1 6 in.) +260 °C

TJJunc tion tem p er at ur e pla st i c +125 °C

Junction temperature ceramic +150 °C

Speed Grade-4-3-2-1-09

Description Symbol Max Max Max Max Max Units

Global and Alternate Clock Distribution1

Either: Normal IOB in put pad throug h clock buffer

to any CLB or IOB clock input

Or: Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input

TPID

TPIDC

6.5

5.1

5.6

4.3

4.7

3.7

4.3

3.5

3.9

3.1

TBUF driving a Horizontal Longline (L.L.)1

I to L.L. while T is Low (buffer active) (XC3100)

(XC3100A)

T↓ to L.L. active and v a lid with single pull-up resistor

T↓ to L.L. active and valid with pair of pull-up resistors

T↑ to L.L. High with single pull-up resistor

T↑ to L.L. High with pair of pull-up resistors

TIO

TON

TPUS

TPUF

3.7

3.6

5.0

6.5

13.5

10.5

3.1

4.2

5.7

11.4

8.8

3.1

4.2

5.7

11.4

8.1

2.9

4.0

5.5

10.4

7.1

2.1

3.1

4.6

8.9

5.9

BIDI Bidirectional buffer delay TBIDI 1.2 1.0 0.9 0.85 0.75 ns

Prelim

November 9, 1998 (Version 3.1) 7-55

XC3000 Series Field Programmable Gate Arrays

XC3100A CLB Switching Chara cteristics Gu idelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the

Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

2. TILO, TQLO and TICK are specified for 4- input funct i ons. For 5-i nput functions or base FGM func tions, eac h of t hese

specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and

0.30 ns (-09).

Speed Grade-4-3-2-1-09

Description Symbol Min Max Min Max Min Max Min Max Min Max Units

Combinatorial Delay

Logic Va ri abl es A, B, C, D, E,

to outputs X or Y 1T

ILO 3.3 2.7 2.2 1.75 1.5 ns

Sequential delay

Clock k to outputs X or Y

Clock k to outputs X or Y when Q is returned

through function generators F or G to drive

X or Y

CKO

TQLO

2.5

5.2

2.1

4.3

1.7

3.5

1.4

3.1

1.25

2.7

Set-up t i me before clock K

Logic Va ri abl es A, B, C, D, E

Data In DI

Enable Clock EC

Reset Di rect inact iv e RD

TICK

TDICK

TECCK

2.5

1.6

3.2

1.0

2.1

1.4

2.7

1.0

1.8

1.3

2.5

1.0

1.7

1.2

2.3

1.0

1.5

1.0

2.05

1.0

Hold Time after clock K

Logic Va ri abl es A, B, C, D, E

Data In DI

Enable Clock EC

TCKI

TCKDI

TCKEC

1.0

0.8

0.9

0.7

0.9

0.7

0.8

0.6

0.7

0.55

Clock

Clock Hi gh tim e

Clock Low time

Max. flip-flop toggle rate

12 TCH

TCL

FCLK

2.0

227

1.6

270

1.3

323

1.3

323

1.3

370

MHz

Reset Di rect (RD)

RD width

delay from RD to outputs X or Y 13

9TRPW

TRIO 3.2 3.7 2.7 3.1 2.3 2.7 2.3 2.4 2.05 2.15 ns

Global Reset (RESET Pad)1

RESET width (Low) (XC 3142A)

delay from RESET pad to outputs X or Y TMRW

TMRQ 14.0 14.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 ns

Prelim

XC3000 Series Field Programmable Gate Arrays

7-56 November 9, 1998 (Version 3.1)

XC3100A CLB Switching Chara cteristics Gu idelines (continued )

1TILO

CLB Output (X, Y)

(Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

CLB Input

(Direct In)

CLB Input

(Enable Clock)

CLB Output

(Flip-Flop)

CLB Input

(Reset Direct)

CLB Output

(Flip-Flop)

8TCKO

X5424

13 T

RPW

RIO

4TDICK

6TECCK

12 TCL

2TICK 3TCKI

11 TCH

5TCKDI

7TCKEC

November 9, 1998 (Version 3.1) 7-57

XC3000 Series Field Programmable Gate Arrays

XC3100A IOB Switching Cha racte ristics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is meas ured at pin thres hol d, with 50 pF external capaciti ve loads (inc l . t est fi xture). For larger capa ci tive loads, s ee

XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.

2. Voltage levels of unused (bonded and unbonded) pads must be vali d l ogic levels. Each can be configured with the inte rnal

pull-up resistor or alternatively configured as a driven output or driven from an external source.

3. In put pad set-u p time is specified with respect to the i nternal clock (ik). In order to calculate sys tem set-up time, subtra ct

clock delay (pad to ik) from the input pad set-up time val ue. Input pad hol dtime with respect to th e internal clock (ik) is

negative. This means that pad level changes immediatel y before the int ernal clock edge (ik) will no t be recognized.

4. TPID, TPTG, and TPICK are 3 ns higher for X T L2 when the pin is conf i gured as a user input.

Speed Grade-4-3-2-1-09

Description Symbol Min Max Min Max Min Max Min Max Min Max Units

Propagat io n Del ays (Input)

Pad to Direct In (I)

Pad to Registered In (Q)

with latch transpare nt(XC3100A)Clock (IK)

to Registered In (Q)

TPID

TPTG

TIKRI

2.5

12.0

2.5

2.2

11.0

2.2

2.0

11.0

1.9

1.7

10.0

1.7

1.55

9.2

1.55

Set-up Time (Input)

Pad to Clock (IK) set-up time

XC3120A, XC3130A

XC3142A

XC3164A

XC3190A

XC3195A

PICK 10.6

10.7

11.0

11.2

11.6

9.4

9.5

9.7

9.9

10.3

8.9

9.0

9.2

9.4

9.8

8.0

8.1

8.3

8.5

8.9

7.2

7.3

7.5

7.7

8.1

Propagat io n Del ays (Output)

Clock (OK) to Pad (fast)

same

(slew rate limited)

Output (O) to Pad (fast)

same

(slew-rate limited)

(XC3100A)

3-state to Pad

begi n hi-Z (fast)

same

(slew-rate limited)

3-state to Pad

active and valid (fast) (XC3100A)

same

(slew -rate limited)

TOKPO

TOPF

TOPS

TTSHZ

TTSON

5.0

12.0

3.7

11.0

6.2

10.0

17.0

4.4

10.0

3.3

9.0

5.5

9.0

15.0

3.7

9.7

3.0

8.7

5.0

8.5

14.2

3.4

8.4

3.0

8.0

4.5

6.5

11.5

3.3

6.9

2.9

6.5

4.05

5.0

8.6

Set-up and Hol d Times (O ut put)

Output (O) to clock (OK) set-up time

(XC3100A)

Output (O) to clock (OK) hold time 5

6TOOK

TOKO 4.5

03.6

03.2

02.9 ns

Clock

Clock High time

Clock Low time

Max. flip-flop toggle rate

12 TIOH

TIOL

FCLK

2.0

227

1.6

270

1.3

323

1.3

323

1.3

370

MHz

Global Reset Delays

RESET Pad to Regi stered In (Q)

(XC3142A)

(XC3190A)

RESET Pad to output pad (f ast )

(slew- rate limited)

TRRI

TRPO

15.0

25.5

20.0

27.0

13.0

21.0

17.0

23.0

13.0

21.0

17.0

23.0

13.0

21.0

17.0

22.0

14.4

21.0

17.0

21.0

Preliminary

XC3000 Series Field Programmable Gate Arrays

7-58 November 9, 1998 (Version 3.1)

XC3100A IOB Switching Characteristics Guidelines (con tinu ed)

3TPID

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

5TOOK

12 TIOL

1TPICK

11 TIOH

4TIKRI

15 TRPO

13 TRRI

6TOKO

9TTSHZ

10 TOP

7TOKPO

8TTSON

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

November 9, 1998 (Version 3.1) 7-59

XC3000 Series Field Programmable Gate Arrays

XC3100L Switching Characteristics

Xilinx maintains test specifications for each product as controlled documents. T o insure the use of the most recently released

device per formance parameters, please request a copy of the c urrent test-specification revision.

XC3100L Oper ating Co nditions

Notes: 1. At junction temperat ures above tho se li st ed as Operating Conditions, all delay parameters inc rease by 0.3% per °C.

2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right

to restrict operation to the 3.0 and 3.6 V ra nge l at er, when smaller device geometries might preclude operation @ 5 V.

Operating condition s are guarantee d in the 3.0 – 3.6 V VCC range.

XC3100L DC Charac teristics Over Operating Con dition s

Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and t he FPGA

configured with a tie option.

2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not

exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC319 0L.

3. Not tested. All ows undriven pins to float Hi gh. For any other purpose, use an exte rnal pul l -up.

Symbol Description Min Max Units

VCC Supply volta ge re lat ive to GND Comme rc ial 0°C to + 85°C junction 3.0 3.6 V

VIH High-lev el inp ut volta g e 2.0 VCC + 0.3 V

VIL Low-lev el inp ut voltage -0.3 0.8 V

TIN Input signal transition time 250 ns

Symbol Description Min Max Units

VOH High-level output vol tage (@ IOH = -4.0 mA, VCC min) 2.4 V

High-level output vol tage (@ IOH = -100.0 µA, VCC min) VCC -0.2 V

VOL Low-level output voltage (@ IOH = 4.0 mA, VCC min) 0.40 V

Low-level output voltage (@ IOH = +100.0 µA, VCC min) 0.2 V

VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V

ICCO Quiescent FPGA supply current

Chip thresh olds pr ogrammed as CMOS le vels11.5 mA

IIL Input Leakage Current -10 +10 µA

CIN

Input capaci tance

(sample tested)

All pins except XTL1 and XTL2

XTL1 and XTL2 10

15 pF

IRIN Pad pull-up (when selected) @ VIN = 0 V 3 0.02 0.17 mA

IRLL Horizontal long line pull-up (when selected) @ logic Low 0.20 2.80 mA

XC3000 Series Field Programmable Gate Arrays

7-60 November 9, 1998 (Version 3.1)

XC3100L Absolu te Maxim um Ratings

Note: Stresses bey ond those list ed under Absolut e M axi m um Ratings may cause permanent damage to th e devi ce. These are

stress ra tings only, and functional operation of th e devi ce at these or any other con di tions beyond t hose listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended

periods of time may affect device reliability.

XC3100L Global Buffer Switching Char acter istics Guide lines

Notes: 1. Timing is based on t he XC3142L, for ot her devic es see timing calculator.

2. The use of two pull-u p resistors per l ongl i ne, availa bl e on ot her XC3000 dev ices, is not a valid opt i on for XC3100L devi ces.

Symbol Description Units

VCC Supply voltage r e lative to GND –0.5 to +7.0 V

VIN Inp ut voltage with respect to GND –0.5 to VCC +0.5 V

VTS Vol tage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum sold er ing tem p er at ur e (1 0 s @ 1/1 6 in.) +260 °C

TJJunc tion tem p er at ur e pla st i c +125 °C

Junction temperature ceramic +150 °C

Speed Grade -3 -2

Description Symbol Max Max Units

Global and Alternate Clock Distribution1

Either:Normal IOB input pad through clock buffer

to any CLB or IOB clock input

Or: Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input

TPID

TPIDC

5.6

4.3

4.7

3.7

TBUF driving a Horizontal Longline (L.L.)1

I to L.L. while T is Low (buffer ac tive)

T↓ to L.L. active and valid wi th sin g le pull-up resistor

T↑ to L.L. High with single pull-up resistor

TIO

TON

TPUS

3.1

4.2

11.4

3.1

4.2

11.4

BIDI Bidirectional buffer delay TBIDI 1.0 0.9 ns

Advance

November 9, 1998 (Version 3.1) 7-61

XC3000 Series Field Programmable Gate Arrays

XC3100L CLB Switching Char acter istics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. The CLB K to Q delay (T CKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data

In hold time requirement (TCKDI, #5) of any CLB on the same die.

2. TILO, TQLO and TICK are specified f or 4-i nput functions. For 5-i nput functi ons or base FGM func tions, each of these

specif i cat i ons for the XC3100L family increase by 0.35 n s (-3) and 0.29 ns (- 2).

Speed Grade -3 -2

Description Symbol Min Max Min Max Units

Combinatorial Delay

Logic Variables A, B, C, D, E, to outputs X or Y 1 TILO 2.7 2.2 ns

Sequ e nt ial de lay

Clock k to outputs X or Y

Clock k to outputs X or Y when Q is returned

through function generators F or G to driv e X or Y

CKO

TQLO

2.1

4.3

1.7

3.5

Set-up time before clock K

Logic Va ria b les A , B, C, D, E

Data In DI

Enable Clock EC

Reset Direct Inactive RD

TICK

TDICK

TECCK

2.1

1.4

2.7

1.0

1.8

1.3

2.5

1.0

Hold Time aft er clock K

Logic Va ria b les A, B, C, D, E

Data In DI

Enable Clock EC

TCKI

TCKDI

TCKEC

0.9

0.7

0.9

0.7

Clock

Clock High time

Clock Low tim e

Max. flip-flop toggle rate

12 TCH

TCL

FCLK

1.6

270

1.3

325

MHz

Reset Direct (RD)

RD width

delay from RD to outputs X or Y 13

9TRPW

TRIO

2.7 3.1 2.3 2.7 ns

Global Reset (RESET Pad)

RESET width (Low) (XC3142L)

delay from RESET pad to outputs X or Y TMRW

TMRQ

12.0 12.0 12.0 12.0

Advance

XC3000 Series Field Programmable Gate Arrays

7-62 November 9, 1998 (Version 3.1)

XC3100L CLB Switching Char acter istics Guideline s (continue d)

1TILO

CLB Output (X, Y)

(Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

CLB Input

(Direct In)

CLB Input

(Enable Clock)

CLB Output

(Flip-Flop)

CLB Input

(Reset Direct)

CLB Output

(Flip-Flop)

8TCKO

X5424

13 T

RPW

RIO

4TDICK

6TECCK

12 TCL

2TICK 3TCKI

11 TCH

5TCKDI

7TCKEC

November 9, 1998 (Version 3.1) 7-63

XC3000 Series Field Programmable Gate Arrays

XC3100L IOB Switching Ch arac teristics Guidelines

Testing of the switching parame ters is modeled after testing methods speci fied b y MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simula to r.

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output

rise/fal l ti m es are approximately f our times longer.

2. Voltage levels of unused (bonded and unbonded) pads must be vali d l ogic levels. Each can be configured with the inte rnal

pull-up resistor or alternatively configured as a driven output or driven from an external source.

3. In put p ad set-up time is specifie d wi th respect to t he i nternal clock (IK). In order to calculate sys tem set-up tim e, subtract

clock delay (pad to ik) from the input pad set-up time val ue. Input pad hol dtime with respect to th e internal clock (IK) is

negative. This means that pad level ch anges immed i ately before the interna l clock edge (IK) will not be rec ognized.

Speed Grade -3 -2

Description Symbol Min Max Min Max Units

Propagation Delays (Input)

Pad to Direct In (I)

Pad to Regis tered In (Q) with latch (XC31 00L)

transparent

Clock (IK) to Registered In (Q)

TPID

TPTG

TIKRI

2.2

11.0

2.2

2.0

11.0

1.9

Set-up Time (Input)

Pad to Clock (IK) set-up time XC3142L

XC3190L

PICK 9.5

9.9 9.0

9.4 ns

Propagation Delays (Output)

Clock (OK) to Pad (fast)

same (slew rate limited)

Output (O) to Pad (fast)

same (slew-rate limited)(XC3100L)

3-state to Pad begin hi-Z (fast)

same (slew-rate limited)

3-state to Pad active and valid(fast)(XC3100L)

same (slew -rate limited)

TOKPOTOK

TOPF

TTSHZ

TTSON

4.4

10.0

3.3

9.0

5.5

9.0

15.0

4.0

9.7

3.0

8.7

5.0

8.5

14.2

Set-up and Hold Times (Output)

Output (O) to clock (OK) set-up time (XC3100L)

Output (O) to clock (OK) hold time 5

6TOOK

TOKO

4.0

03.6

0ns

Clock

Clock High time

Clock Low tim e

Export Control Maximum flip-flop toggle rate

12 TIOH

TIOL

FTOG

1.6

270

1.3

325

MHz

Global Reset Delays

RESET Pad to Registered In (Q)

(XC3142L)

(XC3190L)

RESET Pad to output pad (fast)

(slew-rate limited)

TRRI

TRPO

16.0

21.0

17.0

23.0

16.0

21.0

17.0

23.0

Advance

XC3000 Series Field Programmable Gate Arrays

7-64 November 9, 1998 (Version 3.1)

XC3100L IOB Switching Ch arac teristics Guidelines (continued )

3TPID

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

5TOOK

12 TIOL

1TPICK

11 TIOH

4TIKRI

15 TRPO

13 TRRI

6TOKO

9TTSHZ

10 TOP

7TOKPO

8TTSON

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

November 9, 1998 (Version 3.1) 7-65

XC3000 Series Field Programmable Gate Arrays

XC3000 Series Pin Assignments

Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package

types, with pin counts from 44 to 208.

Each chip is offe red in severa l package ty pes to acco mmodate th e available PC board space and man ufactur ing technol ogy .

Most package types are also offered with different chips to accommodate design changes without the need for PC board

chang es.

Note t ha t the re is no per fect ma tch b et we en t he num ber of bon di ng pad s on t he c hip and th e nu mbe r of pi n s on a pack ag e.

In some case s, th e chip ha s more pads t han th ere are pi ns on the pack age, a s ind icat ed by t he info rmati on (“ unused” pads)

below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified

prop agation delays and set -up ti mes are acceptable.

In oth er cases, the ch ip has fewer pads than t here are pin s on the pack age; ther efore, so me package pin s are not co nnected

(n.c.), as shown above the line in the following table.

XC3000 Series 44-Pin PLCC Pinouts

XC3000A, XC3000L, and XC3100A families have identical pinouts

Peri pheral mode and Master Parallel mode are not supported in the PC44 package

Pin No. XC3030A Pin No. XC3030A

1GND 23GND

2 I/O 24 I/O

3 I/O 25 I/O

4 I/O 26 XTL2(IN)-I/O

5 I/O 27 RESET

6 I/O 28 DONE-PGM

7PWRDWN 29 I/O

8 TCLKIN-I/O 30 XTL1(OUT)-BCLK-I/O

9 I/O 31 I/O

10 I/O 32 I/O

11 I/O 33 I/O

12 VCC 34 VCC

13 I/O 35 I/O

14 I/O 36 I/O

15 I/O 37 I/O

16 M1-RDATA 38 DIN-I/O

17 M0-RTRIG 39 DOUT-I/O

18 M2-I/O 40 CCLK

19 HDC-I/O 41 I/O

20 LDC-I/O 42 I/O

21 I/O 43 I/O

22 INIT-I/O 44 I/O

XC3000 Series Field Programmable Gate Arrays

7-66 November 9, 1998 (Version 3.1)

XC3000 Series 64-Pin Plastic VQFP Pinouts

XC3000A, XC3000L, and XC3100A families have identical pinouts

Pin No. XC3030A Pin No. XC3030A

1A0-WS

-I/O 33 M2-I/O

2 A1-CS2-I/O 34 HDC-I/O

3A2-I/O 35 I/O

4A3-I/O 36LDC

-I/O

5A4-I/O 37 I/O

6 A14-I/O 38 I/O

7A5-I/O 39 I/O

8GND 40 INIT-I/O

9 A13-I/O 41 GND

10 A6-I/O 42 I/O

11 A12-I/O 43 I/O

12 A7-I/O 44 I/O

13 A11-I/O 45 I/O

14 A8-I/O 46 I/O

15 A10-I/O 47 XTAL2(IN)-I/O

16 A9-I/O 48 RESET

17 PWRDN 49 DONE-PG

18 TCLKIN-I/O 50 D7-I/O

19 I/O 51 XTAL1(OUT)-BCLKIN-I/O

20 I/O 52 D6-I/O

21 I/O 53 D5-I/O

22 I/O 54 CS0-I/O

23 I/O 55 D4-I/O

24 VCC 56 VCC

25 I/O 57 D3-I/O

26 I/O 58 CS1-I/O

27 I/O 59 D2-I/O

28 I/O 60 D1-I/O

29 I/O 61 RDY/BUSY-RCLK-I/O

30 I/O 62 D0-DIN-I/O

31 M1-RDATA 63 DOUT-I/O

32 M0-RTRIG 64 CCLK

November 9, 1998 (Version 3.1) 7-67

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the

118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,

indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin

packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a

dash (—) in the 68 PLCC column, have no conn ection to the 68 PLCC, bu t are connected to the 84-pin pa ckages .

68 PLCC XC3020A, XC3030A,

XC3042A 84 PLCC

68 PLCC XC3020A, XC3030A,

XC3042A 84 PLCCXC3030A XC3020A XC3030A XC3020A

10 10 PWRDN 12 44 44 RESET 54

11 11 TCLKIN-I/O 13 45 45 DONE-PG 55

12 — I/O* 14 46 46 D7-I/O 56

13 12 I/O 15 47 47 XTL1(OUT)-BCLKIN-I/O 57

14 13 I/O 16 48 48 D6-I/O 58

— — I/O 17 — — I/O 59

15 14 I/O 18 49 49 D5-I/O 60

16 15 I/O 19 50 50 CS0-I/O 61

— 16 I/O 20 51 51 D4-I/O 62

17 17 I/O 21 — — I/O 63

18 18 VCC 22 52 52 VCC 64

19 19 I/O 23 53 53 D3-I/O 65

— — I/O 24 54 54 CS1-I/O 66

20 20 I/O 25 55 55 D2-I/O 67

— 21 I/O 26 — — I/O 68

21 22 I/O 27 — — I/O* 69

22 — I/O 28 56 56 D1-I/O 70

23 23 I/O 29 57 57 RDY/BUSY-RCLK-I/O 71

24 24 I/O 30 58 58 D0-DIN-I/O 72

25 25 M1-RDATA 31 59 59 DOUT-I/O 73

26 26 M0-RTRIG 32 60 60 CCLK 74

27 27 M2-I/O 33 61 61 A0-WS-I/O 75

28 28 HDC-I/O 34 62 62 A1-CS2-I/O 76

29 29 I/O 35 63 63 A2-I/O 77

30 30 LDC-I/O 36 64 64 A3-I/O 78

— 31 I/O 37 — — I/O* 79

— I/O* 38 — — I/O* 80

31 32 I/O 39 65 65 A15-I/O 81

32 33 I/O 40 66 66 A4-I/O 82

33 — I/O* 41 67 67 A14-I/O 83

34 34 INIT-I/O 42 68 68 A5-I/O 84

35 35 GND 43 1 1 GND 1

36 36 I/O 44 2 2 A13-I/O 2

37 37 I/O 45 3 3 A6-I/O 3

38 38 I/O 46 4 4 A12-I/O 4

39 39 I/O 47 5 5 A7-I/O 5

— 40 I/O 48 — — I/O* 6

— 41 I/O 49 — — I/O* 7

40 I/O* 50 6 6 A11-I/O 8

41 I/O* 51 7 7 A8-I/O 9

42 42 I/O 52 8 8 A10-I/O 10

43 43 XTL2(IN)-I/O 53 9 9 A9-I/O 11

XC3000 Series Field Programmable Gate Arrays

7-68 November 9, 1998 (Version 3.1)

XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed outputs are default slew-rate limited.

* In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin

definiti on than XC3020A/XC3030A/XC3042A.

PLCC Pin Number XC3064A, XC30 90A, XC 3195A PLCC Pin Number XC3064A, XC30 90A, XC 3195A

12 PWRDN 54 RESET

13 TCLKIN-I/O 55 DONE-PG

14 I/O 56 D7-I/O

15 I/O 57 XTL1(OUT)-BCLKIN-I/O

16 I/O 58 D6-I/O

17 I/O 59 I/O

18 I/O 60 D5-I/O

19 I/O 61 CS0-I/O

20 I/O 62 D4-I/O

21 GND* 63 I/O

22 VCC 64 VCC

23 I/O 65 GND*

24 I/O 66 D3-I/O*

25 I/O 67 CS1-I/O*

26 I/O 68 D2-I/O*

27 I/O 69 I/O

28 I/O 70 D1-I/O

29 I/O 71 RDY/BUSY-RCLK-I/O

30 I/O 72 D0-DIN-I/O

31 M1-RDATA 73 DOUT-I/O

32 M0-RTRIG 74 CCLK

33 M2-I/O 75 A0-WS-I/O

34 HDC-I/O 76 A1-CS2-I/O

35 I/O 77 A2-I/O

36 LDC-I/O 78 A3-I/O

37 I/O 79 I/O

38 I/O 80 I/O

39 I/O 81 A15-I/O

40 I/O 82 A4-I/O

41 INIT/I/O* 83 A14-I/O

42 VCC* 84 A5-I/O

43 GND 1 GND

44 I/O 2 VCC*

45 I/O 3 A13-I/O*

46 I/O 4 A6-I/O*

47 I/O 5 A12-I/O*

48 I/O 6 A7-I/O*

49 I/O 7 I/O

50 I/O 8 A11-I/O

51 I/O 9 A8-I/O

52 I/O 10 A10-I/O

53 XTL2(IN)-I/O 11 A9-I/O

November 9, 1998 (Version 3.1) 7-69

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 100-Pin QFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

* This t able de scrib es th e pin outs of thre e dif fer ent c hips i n three d if fer ent pac kage s. The pi n-de scri ption c olu mn lis ts 100 of

the 118 pads on th e X C304 2A t hat ar e c onnec t ed t o the 100 pac k ag e pin s. Two pads, i ndic at e d by dou bl e aste ri s ks, do not

exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads,

indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the c o rresponding pins

have no connections. (See table on page 65.)

Pin No. XC3020A

XC3030A

XC3042A

Pin No . XC3020A

XC3030A

XC3042A

Pin No. XC3020A

XC3030A

XC3042APQFP TQFP

VQFP PQFP TQFP

VQFP

16 13 GND 50 47 I/O* 84 81 I/O*

17 14 A13-I/O 51 48 I/O* 85 82 I/O*

18 15 A6-I/O 52 49 M1-RD 86 83 I/O

19 16 A12-I/O 53 50 GND* 87 84 D5-I/O

20 17 A7-I/O 54 51 MO-RT 88 85 CS0-I/O

21 18 I/O* 55 52 VCC* 89 86 D4-I/O

22 19 I/O* 56 53 M2-I/O 90 87 I/O

23 20 A11-I/O 57 54 HDC-I/O 91 88 VCC

24 21 A8-I/O 58 55 I/O 92 89 D3-I/O

25 22 A10-I/O 59 56 LDC-I/O 93 90 CS1-I/O

26 23 A9-I/O 60 57 I/O* 94 91 D2-I/O

27 24 VCC* 61 58 I/O* 95 92 I/O

28 25 GND* 62 59 I/O 96 93 I/O*

29 26 PWRDN 63 60 I/O 97 94 I/O*

30 27 TCLKIN-I/O 64 61 I/O 98 95 D1-I/O

31 28 I/O** 65 62 INIT-I/O 99 96 RDY/BUSY-RCLK-I/O

32 29 I/O* 66 63 GND 100 97 DO-DIN-I/O

33 30 I/O* 67 64 I/O 1 98 DOUT-I/O

34 31 I/O 68 65 I/O 2 99 CCLK

35 32 I/O 69 66 I/O 3 100 VCC*

36 33 I/O 70 67 I/O 4 1 GND*

37 34 I/O 71 68 I/O 5 2 AO-WS-I/O

38 35 I/O 72 69 I/O 6 3 A1-CS2-I/O

39 36 I/O 73 70 I/O 7 4 I/O**

40 37 I/O 74 71 I/O* 8 5 A2-I/O

41 38 VCC 75 72 I/O* 9 6 A3-I/O

42 39 I/O 76 73 XTL2-I/O 10 7 I/O*

43 40 I/O 77 74 GND* 11 8 I/O*

44 41 I/O 78 75 RESET 12 9 A15-I/O

45 42 I/O 79 76 VCC* 13 10 A4-I/O

46 43 I/O 80 77 DONE-PG 14 11 A14-I/O

47 44 I/O 81 78 D7-I/O 15 12 A5-I/O

48 45 I/O 82 79 BCLKIN-XTL1-I/O

49 46 I/O 83 80 D6-I/O

XC3000 Series Field Programmable Gate Arrays

7-70 November 9, 1998 (Version 3.1)

XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

* Indicate s unconnected package pins (14) for t he XC3042A.

PGA

Number XC3042A

XC3064A

PGA

Number XC3042A

XC3064A

PGA

Number XC3042A

XC3064A

PGA

Number XC3042A

XC3064A

C4 GND B13 M1-RD P14 RESET M3 DOUT-I/O

A1 PWRDN C11 GND M11 VCC P1 CCLK

C3 I/O-TCLKIN A14 M0-RT N13 DONE-PG M4 VCC

B2 I/O D12 VCC M12 D7-I/O L3 GND

B3 I/O C13 M2-I/O P13 XTL1-I/O-BCLKIN M2 A0-WS-I/O

A2 I/O* B14 HDC-I/O N12 I/O N1 A1-CS2-I/O

B4 I/O C14 I/O P12 I/O M1 I/O

C5 I/O E12 I/O N11 D6-I/O K3 I/O

A3 I/O* D13 I/O M10 I/O L2 A2-I/O

A4 I/O D14 LDC-I/O P11 I/O* L1 A3-I/O

B5 I/O E13 I/O* N10 I/O K2 I/O

C6 I/O F12 I/O P10 I/O J3 I/O

A5 I/O E14 I/O M9 D5-I/O K1 A15-I/O

B6 I/O F13 I/O N9 CS0-I/O J2 A4-I/O

A6 I/O F14 I/O P9 I/O* J1 I/O*

B7 I/O G13 I/O P8 I/O* H1 A14-I/O

C7 GND G14 INIT-I/O N8 D4-I/O H2 A5-I/O

C8 VCC G12 VCC P7 I/O H3 GND

A7 I/O H12 GND M8 VCC G3 VCC

B8 I/O H14 I/O M7 GND G2 A13-I/O

A8 I/O H13 I/O N7 D3-I/O G1 A6-I/O

A9 I/O J14 I/O P6 CS1-I/O F1 I/O*

B9 I/O J13 I/O N6 I/O* F2 A12-I/O

C9 I/O K14 I/O P5 I/O* E1 A7-I/O

A10 I/O J12 I/O M6 D2-I/O F3 I/O

B10 I/O K13 I/O N5 I/O E2 I/O

A11 I/O* L14 I/O* P4 I/O D1 A11-I/O

C10 I/O L13 I/O P3 I/O D2 A8-I/O

B11 I/O K12 I/O M5 D1-I/O E3 I/O

A12 I/O* M14 I/O N4 RDY/BUSY-RCLK-I/O C1 I/O

B12 I/O N14 I/O P2 I/O B1 A10-I/O

A13 I/O* M13 XTL2(IN)-I/O N3 I/O C2 A9-I/O

C12 I/O L12 GND N2 D0-DIN-I/O D3 VCC

November 9, 1998 (Version 3.1) 7-71

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 144-Pin Plastic TQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

* Indicate s unconnected package pins (24) for t he XC3042A.

Number

XC3042A

XC3064A

XC3090A

Number

XC3042A

XC3064A

XC3090A

Number

XC3042A

XC3064A

XC3090A

1PWRDN 49 I/O 97 I/O

2 I/O-TCLKIN 50 I/O* 98 I/O

3 I/O* 51 I/O 99 I/O*

4 I/O 52 I/O 100 I/O

5 I/O 53 INIT-I/O 101 I/O*

6 I/O* 54 VCC 102 D1-I/O

7 I/O 55 GND 103 RDY/BUSY-RCLK-I/O

8 I/O 56 I/O 104 I/O

9 I/O* 57 I/O 105 I/O

10 I/O 58 I/O 106 D0-DIN-I/O

11 I/O 59 I/O 107 DOUT-I/O

12 I/O 60 I/O 108 CCLK

13 I/O 61 I/O 109 VCC

14 I/O 62 I/O 110 GND

15 I/O* 63 I/O* 111 A0-WS-I/O

16 I/O 64 I/O* 112 A1-CS2-I/O

17 I/O 65 I/O 113 I/O

18 GND 66 I/O 114 I/O

19 VCC 67 I/O 115 A2-I/O

20 I/O 68 I/O 116 A3-I/O

21 I/O 69 XTL2(IN)-I/O 117 I/O

22 I/O 70 GND 118 I/O

23 I/O 71 RESET 119 A15-I/O

24 I/O 72 VCC 120 A4-I/O

25 I/O 73 DONE-PG 121 I/O*

26 I/O 74 D7-I/O 122 I/O*

27 I/O 75 XTL1(OUT)-BCLKIN-I/O 123 A14-I/O

28 I/O* 76 I/O 124 A5-I/O

29 I/O 77 I/O 125 I/O (XC3090 only)

30 I/O 78 D6-I/O 126 GND

31 I/O* 79 I/O 127 VCC

32 I/O* 80 I/O* 128 A13-I/O

33 I/O 81 I/O 129 A6-I/O

34 I/O* 82 I/O 130 I/O*

35 I/O 83 I/O* 131 I/O (XC3090 only)

36 M1-RD 84 D5-I/O 132 I/O*

37 GND 85 CS0-I/O 133 A12-I/O

38 M0-RT 86 I/O* 134 A7-I/O

39 VCC 87 I/O* 135 I/O

40 M2-I/O 88 D4-I/O 136 I/O

41 HDC-I/O 89 I/O 137 A11-I/O

42 I/O 90 VCC 138 A8-I/O

43 I/O 91 GND 139 I/O

44 I/O 92 D3-I/O 140 I/O

45 LDC-I/O 93 CS1-I/O 141 A10-I/O

46 I/O* 94 I/O* 142 A9-I/O

47 I/O 95 I/O* 143 VCC

48 I/O 96 D2-I/O 144 GND

XC3000 Series Field Programmable Gate Arrays

7-72 November 9, 1998 (Version 3.1)

XC3000 Series 160-Pin PQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed IOBs are default slew-rate limited.

* Indicate s unconnected package pins (18) for t he XC3064A.

PQFP Pin

Number XC3064A, XC3090A,

XC3195A

1 I/O*

2 I/O*

3 I/O*

4 I/O

5 I/O

6 I/O

7 I/O

8 I/O

9 I/O

10 I/O

11 I/O

12 I/O

13 I/O

14 I/O

15 I/O

16 I/O

17 I/O

18 I/O

19 GND

20 VCC

21 I/O*

22 I/O

23 I/O

24 I/O

25 I/O

26 I/O

27 I/O

28 I/O

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O*

39 I/O*

40 M1-RDATA

41 GND

42 M0–RTRIG

43 VCC

44 M2-I/O

45 HDC-I/O

46 I/O

47 I/O

48 I/O

49 LDC-I/O

50 I/O*

51 I/O*

52 I/O

53 I/O

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

59 INIT-I/O

60 VCC

61 GND

62 I/O

63 I/O

64 I/O

65 I/O

66 I/O

67 I/O

68 I/O

69 I/O

70 I/O

71 I/O

72 I/O

73 I/O

74 I/O

75 I/O*

76 XTL2-I/O

77 GND

78 RESET

79 VCC

80 DONE/PG

PQFP Pin

Number XC3064A, XC3090A,

XC3195A 81 D7-I/O

82 XTL1-I/O-BCLKIN

83 I/O*

84 I/O

85 I/O

86 D6-I/O

87 I/O

88 I/O

89 I/O

90 I/O

91 I/O

92 D5-I/O

93 CS0-I/O

94 I/O*

95 I/O*

96 I/O

97 I/O

98 D4-I/O

99 I/O

100 VCC

101 GND

102 D3-I/O

103 CS1-I/O

104 I/O

105 I/O

106 I/O*

107 I/O*

108 D2-I/O

109 I/O

110 I/O

111 I/O

112 I/O

113 I/O

114 D1-I/O

115 RDY/BUSY-RCLK-I/O

116 I/O

117 I/O

118 I/O*

119 D0-DIN-I/O

120 DOUT-I/O

PQFP Pin

Number XC3064A, XC3090A,

XC3195A 121 CCLK

122 VCC

123 GND

124 A0-WS-I/O

125 A1-CS2-I/O

126 I/O

127 I/O

128 A2-I/O

129 A3-I/O

130 I/O

131 I/O

132 A15-I/O

133 A4-I/O

134 I/O

135 I/O

136 A14-I/O

137 A5-I/O

138 I/O*

139 GND

140 VCC

141 A13-I/O

142 A6-I/O

143 I/O*

144 I/O*

145 I/O

146 I/O

147 A12-I/O

148 A7-I/O

149 I/O

150 I/O

151 A11-I/O

152 A8-I/O

153 I/O

154 I/O

155 A10-I/O

156 A9-I/O

157 VCC

158 GND

159 PWRDWN

160 TCLKIN-I/O

PQFP Pin

Number XC3064A, XC3090A,

XC3195A

November 9, 1998 (Version 3.1) 7-73

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

Pins A2, A3, A15, A16, T 1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.

PGA Pin

Number XC3090A, XC3195A

B2 PWRDN

D4 TCLKIN-I/O

B3 I/O

C4 I/O

B4 I/O

A4 I/O

D5 I/O

C5 I/O

B5 I/O

A5 I/O

C6 I/O

D6 I/O

B6 I/O

A6 I/O

B7 I/O

C7 I/O

D7 I/O

A7 I/O

A8 I/O

B8 I/O

C8 I/O

D8 GND

D9 VCC

C9 I/O

B9 I/O

A9 I/O

A10 I/O

D10 I/O

C10 I/O

B10 I/O

A11 I/O

B11 I/O

D11 I/O

C11 I/O

A12 I/O

B12 I/O

C12 I/O

D12 I/O

A13 I/O

B13 I/O

C13 I/O

A14 I/O

D13 I/O

B14 M1-RDATA

C14 GND

B15 M0-RTRIG

D14 VCC

C15 M2-I/O

E14 HDC-I/O

B16 I/O

D15 I/O

C16 I/O

D16 LDC-I/O

F14 I/O

E15 I/O

E16 I/O

F15 I/O

F16 I/O

G14 I/O

G15 I/O

G16 I/O

H16 I/O

H15 INIT-I/O

H14 VCC

J14 GND

J15 I/O

J16 I/O

K16 I/O

K15 I/O

K14 I/O

L16 I/O

L15 I/O

M16 I/O

M15 I/O

L14 I/O

N16 I/O

P16 I/O

N15 I/O

R16 I/O

M14 I/O

P15 XTL2(IN)-I/O

N14 GND

R15 RESET

P14 VCC

PGA Pin

Number XC3090A, XC3195A

R14 DONE-PG

N13 D7-I/O

T14 XTL1(OUT)-BCLKIN-I/O

P13 I/O

R13 I/O

T13 I/O

N12 I/O

P12 D6-I/O

R12 I/O

T12 I/O

P11 I/O

N11 I/O

R11 I/O

T11 D5-I/O

R10 CS0-I/O

P10 I/O

N10 I/O

T10 I/O

T9 I/O

R9 D4-I/O

P9 I/O

N9 VCC

N8 GND

P8 D3-I/O

R8 CS1-I/O

T8 I/O

T7 I/O

N7 I/O

P7 I/O

R7 D2-I/O

T6 I/O

R6 I/O

N6 I/O

P6 I/O

T5 I/O

R5 D1-I/O

P5 RDY/BUSY-RCLK-I/O

N5 I/O

T4 I/O

R4 I/O

P4 I/O

R3 D0-DIN-I/O

PGA Pin

Number XC3090A, XC3195A

N4 DOUT-I/O

R2 CCLK

P3 VCC

N3 GND

P2 A0-WS-I/O

M3 A1-CS2-I/O

R1 I/O

N2 I/O

P1 A2-I/O

N1 A3-I/O

L3 I/O

M2 I/O

M1 A15-I/O

L2 A4-I/O

L1 I/O

K3 I/O

K2 A14-I/O

K1 A5-I/O

J1 I/O

J2 I/O

J3 GND

H3 VCC

H2 A13-I/O

H1 A6-I/O

G1 I/O

G2 I/O

G3 I/O

F1 I/O

F2 A12-I/O

E1 A7-I/O

E2 I/O

F3 I/O

D1 A11-I/O

C1 A8-I/O

D2 I/O

B1 I/O

E3 A10-I/O

C2 A9-I/O

D3 VCC

C3 GND

PGA Pin

Number XC3090A, XC3195A

XC3000 Series Field Programmable Gate Arrays

7-74 November 9, 1998 (Version 3.1)

XC3000 Series 176-Pin TQFP Pinouts

XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

Number XC3090A

1PWRDWN

2 TCLKIN-I/O

3 I/O

4 I/O

5 I/O

6 I/O

7 I/O

8 I/O

9 I/O

10 I/O

11 I/O

12 I/O

13 I/O

14 I/O

15 I/O

16 I/O

17 I/O

18 I/O

19 I/O

20 I/O

21 I/O

22 GND

23 VCC

24 I/O

25 I/O

26 I/O

27 I/O

28 I/O

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 –

45 M1-RDATA

46 GND

47 M0-RTRIG

48 VCC

49 M2-I/O

50 HDC-I/O

51 I/O

52 I/O

53 I/O

54 LDC-I/O

55 –

56 I/O

57 I/O

58 I/O

59 I/O

60 I/O

61 I/O

62 I/O

63 I/O

64 I/O

65 INIT-I/O

66 VCC

67 GND

68 I/O

69 I/O

70 I/O

71 I/O

72 I/O

73 I/O

74 I/O

75 I/O

76 I/O

77 I/O

78 I/O

79 I/O

80 I/O

81 I/O

82 –

83 –

84 I/O

85 XTAL2(IN)-I/O

86 GND

87 RESET

88 VCC

Number XC3090A

89 DONE-PG

90 D7-I/O

91 XTAL1(OUT)-BCLKIN-I/O

92 I/O

93 I/O

94 I/O

95 I/O

96 D6-I/O

97 I/O

98 I/O

99 I/O

100 I/O

101 I/O

102 D5-I/O

103 CS0-I/O

104 I/O

105 I/O

106 I/O

107 I/O

108 D4-I/O

109 I/O

110 VCC

111 GND

112 D3-I/O

113 CS1-I/O

114 I/O

115 I/O

116 I/O

117 I/O

118 D2-I/O

119 I/O

120 I/O

121 I/O

122 I/O

123 I/O

124 D1-I/O

125 RDY/BUSY-RCLK-I/O

126 I/O

127 I/O

128 I/O

129 I/O

130 D0-DIN-I/O

131 DOUT-I/O

132 CCLK

Number XC3090A

133 VCC

134 GND

135 A0-WS-I/O

136 A1-CS2-I/O

137 –

138 I/O

139 I/O

140 A2-I/O

141 A3-I/O

142 –

143 –

144 I/O

145 I/O

146 A15-I/O

147 A4-I/O

148 I/O

149 I/O

150 A14-I/O

151 A5-I/O

152 I/O

153 I/O

154 GND

155 VCC

156 A13-I/O

157 A6-I/O

158 I/O

159 I/O

160 –

161 –

162 I/O

163 I/O

164 A12-I/O

165 A7-I/O

166 I/O

167 I/O

168 –

169 A11-I/O

170 A8-I/O

171 I/O

172 I/O

173 A10-I/O

174 A9-I/O

175 VCC

176 GND

Number XC3090A

November 9, 1998 (Version 3.1) 7-75

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 208-Pin PQFP Pinouts

XC3000A, and XC3000L families have identical pinouts

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.

Programmed ou tputs ar e default slew-rate limited.

* In PQ208, XC3090A and XC31 95A have different pinouts.

Pin Number XC3090A

1–

2GND

3PWRDWN

4 TCLKIN-I/O

5 I/O

6 I/O

7 I/O

8 I/O

9 I/O

10 I/O

11 I/O

12 I/O

13 I/O

14 I/O

15 –

16 I/O

17 I/O

18 I/O

19 I/O

20 I/O

21 I/O

22 I/O

23 I/O

24 I/O

25 GND

26 VCC

27 I/O

28 I/O

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 –

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 I/O

45 I/O

46 I/O

47 I/O

48 M1-RDATA

49 GND

50 M0-RTRIG

51 –

52 –

53 –

54 –

55 VCC

56 M2-I/O

57 HDC-I/O

58 I/O

59 I/O

60 I/O

61 LDC-I/O

62 I/O

63 I/O

64 –

65 –

66 –

67 –

68 I/O

69 I/O

70 I/O

71 I/O

72 –

73 –

74 I/O

75 I/O

76 I/O

77 INIT-I/O

78 VCC

79 GND

80 I/O

81 I/O

82 I/O

83 –

84 –

85 I/O

86 I/O

87 I/O

88 I/O

89 I/O

90 –

91 –

92 –

93 I/O

94 I/O

95 I/O

96 I/O

97 I/O

98 I/O

99 I/O

100 XTL2-I/O

101 GND

102 RESET

103 –

104 –

Pin Number XC3090A 105 –

106 VCC

107 D/P

108 –

109 D7-I/O

110 XTL1-BCLKIN-I/O

111 I/O

112 I/O

113 I/O

114 I/O

115 D6-I/O

116 I/O

117 I/O

118 I/O

119 –

120 I/O

121 I/O

122 D5-I/O

123 CS0-I/O

124 I/O

125 I/O

126 I/O

127 I/O

128 D4-I/O

129 I/O

130 VCC

131 GND

132 D3-I/O

133 CS1-I/O

134 I/O

135 I/O

136 I/O

137 I/O

138 D2-I/O

139 I/O

140 I/O

141 I/O

142 –

143 I/O

144 I/O

145 D1-I/O

146 RDY/BUSY-RCLK-I/O

147 I/O

148 I/O

149 I/O

150 I/O

151 DIN-D0-I/O

152 DOUT-I/O

153 CCLK

154 VCC

155 –

156 –

Pin Number XC3090A 157 –

158 –

159 –

160 GND

161 WS-A0-I/O

162 CS2-A1-I/O

163 I/O

164 I/O

165 A2-I/O

166 A3-I/O

167 I/O

168 I/O

169 –

170 –

171 –

172 A15-I/O

173 A4-I/O

174 I/O

175 I/O

176 –

177 –

178 A14-I/O

179 A5-I/O

180 I/O

181 I/O

182 GND

183 VCC

184 A13-I/O

185 A6-I/O

186 I/O

187 I/O

188 –

189 –

190 I/O

191 I/O

192 A12-I/O

193 A7-I/O

194 –

195 –

196 –

197 I/O

198 I/O

199 A11-I/O

200 A8-I/O

201 I/O

202 I/O

203 A10-I/O

204 A9-I/O

205 VCC

206 –

207 –

208 –

Pin Number XC3090A

XC3000 Series Field Programmable Gate Arrays

7-76 November 9, 1998 (Version 3.1)

XC3195A PQ208 Pinouts

Unprogram med IOBs have a default pul l-up. This pr events an un defined pad le vel for unbond ed or unuse d IOBs. Progr ammed output s are

default slew-rate limit ed.

In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected.

* In PQ208, XC3090 A and XC3195A have di ff erent pinouts.

Pin Description PQ208

A9-I/O 206

A10-I/O 205

I/O 204

I/O 203

I/O 202

I/O 201

A8-I/O 200

A11-I/O 199

I/O 198

I/O 197

I/O 196

I/O 194

A7-I/O 193

A12-I/O 192

I/O 191

I/O 190

I/O 189

I/O 188

I/O 187

I/O 186

A6-I/O 185

A13-I/O 184

VCC 183

GND 182

I/O 181

I/O 180

A5-I/O 179

A14-I/O 178

I/O 177

I/O 176

I/O 175

I/O 174

A4-I/O 173

A15-I/O 172

I/O 171

I/O 169

I/O 168

I/O 167

A3-I/O 166

A2-I/O 165

I/O 164

I/O 163

I/O 162

I/O 161

A1-CS2-I/O 160

A0-WS-I/O 159

GND 158

VCC 157

CCLK 156

DOUT-I/O 155

D0-DIN-I/O 154

I/O 153

I/O 152

I/O 151

I/O 150

RDY/BUSY-RCLK-I/O 149

D1-I/O 148

I/O 147

I/O 146

I/O 145

I/O 144

I/O 141

I/O 140

I/O 139

D2-I/O 138

I/O 137

I/O 136

I/O 135

I/O 134

CS1-I/O 133

D3-I/O 132

GND 131

VCC 130

I/O 129

D4-I/O 128

I/O 127

I/O 126

I/O 125

I/O 124

CS0-I/O 123

D5-I/O 122

I/O 121

I/O 120

I/O 119

I/O 118

I/O 117

I/O 116

I/O 115

D6-I/O 114

I/O 113

I/O 112

I/O 111

I/O 110

XTLX1(OUT)BCLKN-I/O 109

D7-I/O 108

D/P 107

VCC 106

RESET 105

GND 104

XTL2(IN)-I/O 103

Pin Description PQ208 I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

I/O 95

I/O 94

I/O 93

I/O 92

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

GND 79

VCC 78

INIT 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 63

I/O 62

I/O 61

I/O 60

LDC-I/O 59

I/O 58

I/O 57

I/O 56

HDC-I/O 55

M2-I/O 54

VCC 53

M0-RTIG 52

GND 51

M1/RDATA 50

I/O 49

Pin Description PQ208 I/O 48

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

I/O 31

I/O 30

I/O 29

I/O 28

VCC 27

GND 26

I/O 25

I/O 24

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 9

I/O 8

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

TCLKIN-I/O 2

PWRDN 1

GND 208

VCC 207

Pin Description PQ208

November 9, 1998 (Version 3.1) 7-77

XC3000 Series Field Programmable Gate Arrays

Product Availability

Pins 44 64 68 84 100 132 144 160 175 176 208

Type Plast.

PLCC Plast.

VQFP Plast.

PLCC Plast.

PLCC Cer.

PGA Plast.

PQFP Plast.

TQFP Plast.

VQFP Plast.

PGA Cer.

PGA Plast.

TQFP Plast.

PQFP Plast.

PGA Cer.

PGA Plast.

TQFP Plast.

PQFP

Code PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 PP132 PG132 TQ144 PQ160 PP175 PG175 TQ176 PQ208

XC3020A -7 CI CI CI

-6 C C C

XC3030A -7 CI CI CI CI CI CI

-6CCCC C C

XC3042A -7 CI CI CI CI CI CI

-6 C C C C C C

XC3064A -7 CI CI CI CI CI

-6 C C C C C

XC3090A -7 CI CI CI CI CI CI CI

-6 C C C C C C C

XC3020L -8 CI

XC3030L -8 CI CI CI

XC3042L -8 CI CI CI

XC3064L -8 CI CI

XC3090L -8 CI CI CI

XC3120A

-4 CI CI CI

-3 CI CI CI

-2 CI CI CI

-1 C C C

-09 C C C

XC3130A

-4 CI CI CI CI CI CI

-3 CI CI CI CI CI CI

-2 CI CI CI CI CI CI

-1CCCC C C

-09CCCCCC

XC3142A

-4 CI CI C CI

-3 CI CI CI CI

-2 CI CI CI CI

-1 CCC C

-09 CCC C

XC3164A

-4 CI CI CI

-3 CI CI CI

-2 CI CI CI

-1 C C C

-09 C C C

XC3190A

-4 CI CI CI CI CI CI CI

-3 CI CI CI CI CI CI CI

-2 CI CI CI CI CI CI CI

-1 C C C C C C C

-09 C CCCCCC

XC3195A

-4 CI CI CI CI CI

-3 CI CI CI CI CI

-2 CI CI CI CI CI

-1 C C C C C

-09 C C C C C

XC3000 Series Field Programmable Gate Arrays

7-78 November 9, 1998 (Version 3.1)

Number of Available I/O Pins

Ordering Information

Revision History

XC3142L CCC

CCC

XC3190L CCC

CCC

Notes: C = Commercial, TJ= 0° to +85°C I = Industrial, TJ = -40° to +100°C

Pins 44 64 68 84 100 132 144 160 175 176 208

Type Plast.

PLCC Plast.

VQFP Plast.

PLCC Plast.

PLCC Cer.

PGA Plast.

PQFP Plast.

TQFP Plast.

VQFP Plast.

PGA Cer.

PGA Plast.

TQFP Plast.

PQFP Plast.

PGA Cer.

PGA Plast.

TQFP Plast.

PQFP

Code PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 PP132 PG132 TQ144 PQ160 PP175 PG175 TQ176 PQ208

Number of Package Pins

Max I/O 44 64 68 84 100 132 144 160 175 176 208

XC3020A/XC3120A 64 58 64 64

XC3030A/XC3130A 80 34 54 58 74 80

XC3042A/3142A 96 74 82 96 96

XC2064A/XC3164A 120 70 110 120 120

XC3090A/XC3190A 144 70 122 138 144 144 144

XC3195A 176 70 138 144 176

XC3030A-3 PC44C

Example:

Device Type

Speed Grade Temperature Range

Number of Pins

Package Type

Date Revision

11/98 Revised version number to 3.1, removed XC3100A-5 obsolete packages.