1. General description
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
2. Features
nSymmetrical output impedance
nHigh noise immunity
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
uCDM JESD22-C101C exceeds 1000 V
nLow power dissipation
nBalanced propagation delays
nMultiple package options
nSpecified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Ordering information
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 02 — 20 January 2009 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC2G32DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm SOT505-2
74AHCT2G32DP
74AHC2G32DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74AHCT2G32DC
74AHC2G32GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2
74AHCT2G32GD
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 2 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
4. Marking
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking
Type number Marking code
74AHC2G32DP A32
74AHCT2G32DP C32
74AHC2G32DC A32
74AHCT2G32DC C32
74AHC2G32GD A32
74AHCT2G32GD C32
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mna733
1A
1B 1Y
2
17
2A
2B 2Y
6
53
mna734
7
≥ 1
≥ 1
2
1
3
6
5
mna166
B
A
Y
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U)
74AHC2G32
74AHCT2G32
1A VCC
1B 1Y
2Y 2B
GND 2A
001aaj504
1
2
3
4
6
5
8
7
001aaj505
74AHC2G32
74AHCT2G32
Transparent top view
8
7
6
5
1
2
3
4
1A
1B
2Y
GND
VCC
1Y
2B
2A
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 3 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
Table 3. Pin description
Symbol Pin Description
1A, 2A 1, 5 data input
1B, 2B 2, 6 data input
GND 4 ground (0 V)
1Y, 2Y 7, 3 data output
VCC 8 supply voltage
Table 4. Function table[1]
Input Output
nA nB nY
LL L
LH H
HL H
HH H
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VIinput voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current −0.5 V < VO <V
CC + 0.5 V - ±25 mA
ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[2] - 250 mW
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 4 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC2G32 74AHCT2G32 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 0 - 5.5 V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
∆t/∆V input transition rise
and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC2G32
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 µA
CIinput
capacitance - 1.5 10 - 10 - 10 pF
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 5 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
11. Dynamic characteristics
74AHCT2G32
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO=−50 µA 4.4 4.5 - 4.4 - 4.4 - V
IO=−8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 µA - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 µA
∆ICC additional
supply current per input pin; VI= 3.4 V;
other inputs at VCC or GND;
IO= 0 A; VCC = 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance - 1.5 10 - 10 - 10 pF
Table 7. Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC2G32
tpd propagation
delay nA, nB to nY; see Figure 6 [1]
VCC = 3.0 V to 3.6 V [2]
CL= 15 pF - 4.4 7.9 1.0 9.5 1.0 10.0 ns
CL= 50 pF - 6.3 11.4 1.0 13.0 1.0 14.5 ns
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.2 5.5 1.0 6.5 1.0 7.0 ns
CL= 50 pF - 4.6 7.5 1.0 8.5 1.0 9.5 ns
CPD power
dissipation
capacitance
per buffer;
CL= 50 pF; fi= 1 MHz;
VI= GND to VCC
[4] -16- - - - - pF
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 6 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
[1] tpd is the same as tPLH and tPHL.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
12. Waveforms
74AHCT2G32
tpd propagation
delay nA, nB to nY; see Figure 6 [1]
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.3 6.9 1.0 8.0 1.0 9.0 ns
CL= 50 pF - 4.8 7.9 1.0 9.0 1.0 10.0 ns
CPD power
dissipation
capacitance
per buffer;
CL= 50 pF; fi= 1 MHz;
VI= GND to VCC
[4] -17- - - - - pF
Table 8. Dynamic characteristics
…continued
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Fig 6. The input (nA and nB) to output (nY) propagation delays.
mna224
nA, nB input
nY output
tPLH
tPHL
GND
VI
VM
VM
VOH
VOL
Table 9. Measurement points
Type Input Output
VMVM
74AHC2G32 0.5VCC 0.5VCC
74AHCT2G32 1.5 V 0.5VCC
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 7 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Test circuit for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Table 10. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC2G32 VCC ≤ 3 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHCT2G32 3 V ≤ 3 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 8 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
13. Package outline
Fig 8. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 9 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Fig 9. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.85
0.60 0.27
0.17 0.23
0.08 2.1
1.9 2.4
2.2 0.5 3.2
3.0 0.4
0.1 8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
1
pin 1 index
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 10 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Fig 10. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.15 3.1
2.9 0.5 1.5 0.5
0.3 0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vMCw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 11 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT2G32_2 20090120 Product data sheet - 74AHC_AHCT2G32_1
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package).
74AHC_AHCT2G32_1 20040223 Product specification - -
74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 January 2009 12 of 13
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 January 2009
Document identifier: 74AHC_AHCT2G32_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
17 Contact information. . . . . . . . . . . . . . . . . . . . . 12
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
