_______________General Description
The MAX915/MAX916 high-speed, single and dual TTL
voltage comparators eliminate oscillation by separating the
comparator input and output stages with a negative edge-
triggered master/slave flip-flop. Comparator propagation
delay is typically 6ns, and is insensitive to input overdrive.
The MAX915 and MAX916 resolve input signals as small as
2mV and 2.4mV, respectively.
These comparators operate either from dual supplies or
from a single +5V supply. The input common-mode volt-
age range extends below the negative supply rail, allowing
ground-sensing applications with a single +5V supply.
The MAX915 is a single TTL comparator, available in 8-pin
DIP and SO packages. The MAX916 is a dual version
available in 16-pin DIP and SO packages. For equivalent
devices with complementary ECL outputs and 2ns propa-
gation delay, see the single/dual MAX905/MAX906.
________________________Applications
High-Speed A/D Converters
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
Synchronous Data Discriminators
____________________________Features
♦Oscillation Free: Clocked Architecture
♦6ns Propagation Delay
♦Propagation Delay Insensitive to Overdrive
♦Single +5V or Dual ±5V Supplies
♦2mV Input Resolution (MAX915)
♦Input Range Includes Negative Supply Rail
♦Low Power: 14mA (70mW) per Comparator, +5V
♦1.5ns Setup Time with 5mV Overdrive
♦No Minimum Requirement for Input Signal
Slew Rate
♦Complementary TTL Outputs
______________Ordering Information
* Contact factory for dice specifications.
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
________________________________________________________________
Maxim Integrated Products
1
IN+
IN-
CLK
DDTTL
OUTPUT
STAGE
SLAVE
D LATCH
MASTER
D LATCH
QQQ
OUTPUT STAGEMASTER/SLAVE FLIP-FLOPINPUT AMPLIFIER
CK CK
DQDQQ
________________Functional Diagram
1
2
3
4
8
7
6
5
Q
GND
CLK
V-
IN-
IN+
V+
MAX915
DIP/SO
Q
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
QB
GND
CLKB
CLKA
GND
QA
MAX916
N.C.
V+
INB-
INB+
INA+
INA-
V-
N.C.
DIP/Narrow SO
QA QB
_________________Pin Configurations
Call toll free 1-800-998-8800 for free samples or literature.
19-0183; Rev 0; 9/93
PART TEMP. RANGE PIN-PACKAGE
MAX915CPA 0°C to +70°C 8 Plastic DIP
MAX915CSA 0°C to +70°C 8 SO
MAX915C/D 0°C to +70°C Dice*
MAX915EPA -40°C to +85°C 8 Plastic DIP
MAX915ESA -40°C to +85°C 8 SO
MAX915MJA -55°C to +125°C 8 CERDIP
MAX916CPE 0°C to +70°C 16 Plastic DIP
MAX916CSE 0°C to +70°C 16 Narrow SO
MAX916C/D 0°C to +70°C Dice*
MAX916EPE -40°C to +85°C 16 Plastic DIP
MAX916ESE -40°C to +85°C 16 Narrow SO
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V+ to GND)....................................+6V
Negative Supply Voltage (V- to GND).....................................-6V
Differential Input Voltage......................(V- - 0.3V) to (V+ + 0.3V)
Common-Mode Input Voltage ..............(V- - 0.3V) to (V+ + 0.3V)
Clock Input Voltage..........................(GND - 0.3V) to (V+ + 0.3V)
Output Short-Circuit Duration
To V+, GND ............................................................Continuous
To V-................................................................................10sec
Output Current (Q or Q)......................................................20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW
8-Pin SO (derate 5.88mW/°C above +70°C).................471mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) ....842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C)..696mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature Range............................-65°C to +170°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER SYMBOL MIN TYP MAX UNITS
Common-Mode Rejection Ratio CMRR 90 120 µV/V
Input Common-Mode Range VCMR V- - 0.1 V+ - 2.2 V
Input Referred Noise Voltage en600 900 µV
Input Offset Current IOS 0.2 1.0 µA
Power-Supply Rejection Ratio PSRR 60 120 µV/V
Output High Voltage VOH 2.8 3.5 V
Output Low Voltage VOL 0.3 0.4 V
Clock Input Voltage High VIH 2 V
Input Offset Voltage VOS 0.5 1.5 mV
Input Bias Current IB510µA
Clock Input Voltage Low VIL 0.8 V
Clock Input Current High IIH 0.5 10 µA
14 18 µA
28 36
34
mA
68
Negative Supply Current
(Note 5)
85 115
mA
PD 170 230
Power Dissipation (Note 5)
68
mW
Propagation Delay
(Notes 6, 7, 9) tPD+ 68
ns
CONDITIONS
(Note 2)
(Note 1)
VCM = 0V
(Note 3)
(Note 4)
(Note 4)
MAX915
MAX916
VCM = 0V
MAX916
V+ = 5.25V,
V- = -5.25V
IB+ or IB-
Q, Qrising
Q, Qfalling
MAX915
MAX916
(Notes 6, 7, 8) 0.5 3.0Propagation-Delay Skew tSKEW VOD = 5mV 1.5 ns
2.5 10
I- MAX915
Clock Input Current Low IIL
Positive Supply Current
(Note 5) I+
Clock Setup Time (Notes 6, 9) tSU VOD = 10mV 1.0 2.0 ns
tPD-
0.5 2.0
MAX915
MAX916
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
_______________________________________________________________________________________ 3
Note 1: Guaranteed by design. Input referred noise voltage uncertainty is specified over the full bandwidth of the device.
Note 2: Common-mode rejection ratio is tested over the full common-mode range. The common-mode range for dual-supply
operation is from (V- - 0.1V) to (V+ - 2.2V). The common-mode range for single-supply operation is from -0.1V to
(V+ - 2.2V).
Note 3: Tested for 4.75V < V+ < 5.25V and -5.25V < V- < 0V.
Note 4: TTL output voltage high and low tested with V+ = 4.75V, IOH = 4mA, IOL = 8mA.
Note 5: I+, I-, and PD tested for worst-case condition of V+ = 5.25V and V- = -5.25V. Output not loaded.
Note 6: Guaranteed by design. Measured in a high-speed fixture with CL= 15pF, IQ= 2mA. See Figure 1 for timing parameter
definitions. Guaranteed for both single- and dual-supply operation.
Note 7: Propagation delay measured with an input signal of 100mV, with 5mV overdrive.
Note 8: Propagation delay skew is defined as the difference in tPD for the complementary outputs, Q and Q(see Figure 1).
Note 9: Clock input voltage rise and fall times should not exceed 100ns for correct triggering of comparator.
PARAMETER
Clock Input Voltage High
SYMBOL MIN TYP MAX
VIH 2
UNITS
Input Common-Mode Range VCMR
V
V- - 0.1 V+ - 2.2
Clock Input Voltage Low VIL
V
0.8
Input Referred Noise Voltage en600 900
V
µV
Input Offset Current IOS 0.2 2.0 µA
Clock Input Current High
Common-Mode Rejection Ratio CMRR 90 150 µV/V
Power-Supply Rejection Ratio PSRR 60 150 µV/V
IIH 0.5 15 µA
Clock Input Current Low
Output High Voltage
IIL
VOH 2.8 3.5
2.5 15
V
Output Low Voltage
µA
VOL 0.3 0.4 V
14 22
Positive Supply Current
(Note 5)
Input Offset Voltage
I+ 28 44 mA
36
Negative Supply Current
(Note 5) I- 612
mA
VOS 0.5 3.0 mV
85 150
Power Dissipation
(Note 5)
Input Bias Current
PD 170 300 mW
IB515µA
610
612t
PD+ 615
CONDITIONS
(Note 1)
VCM = 0V
(Note 2)
(Note 3)
(Note 4)
(Note 4)
MAX915
MAX916
MAX915
MAX916
VCM = 0V
V+ = 5.25V,
V- = -5.25V
IB+ or IB-
Q, Qrising
610
612
Propagation Delay
(Notes 6, 7, 9)
tPD- Q, Qfalling 615
ns
Propagation-Delay Skew tSKEW (Notes 6, 7, 8) 0.5 4.0
VOD = 5mV 1.5
ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V, TA= TMIN to TMAX, unless otherwise noted.)
Clock Setup Time
(Notes 6, 9) tSU VOD = 10mV 1.0 2.0
0.5 2.0MAX915
MAX916
MAX91_C
MAX91_E
MAX91_M
MAX91_C
MAX91_E
MAX91_M
ns
ns
MAX916
MAX915
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(V+ = +5V, V- = -5V, TA = +25°C, unless otherwise noted.)
3-55
PROPAGATION DELAY vs.
TEMPERATURE
5
13
MAX915-1
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
105
9
7
-15 65
11
25
C
L
= 15pF
V
OD
= 5mV
t
PD-
t
PD+
110 100 100k
CLOCK SETUP TIME vs. SOURCE
RESISTANCE
10
MAX915-2
SOURCE RESISTANCE (Ω)
tSU (ns)
100
1k 10k
VOD = 5mV
CL = 15pF
50
PROPAGATION DELAY vs.
CAPACITIVE LOAD
6
10
MAX915-3
CL (pF)
PROPAGATION DELAY (ns)
160
8
7
40 120 200
9
80
tPD+
tPD-
VOD = 5mV
1.0
0 100
CLOCK SETUP TIME vs. INPUT
OVERDRIVE
0.5
0.9
MAX915-4
INPUT OVERDRIVE (mV)
CLOCK SETUP TIME (ns)
60
0.7
0.6
20 40 80
0.8
CL = 15pF
0-55
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
50
MAX915-7
TEMPERATURE (°C)
PSRR (µV/V)
105
150
100
-15 65
200
25
0-55
CLOCK SETUP TIME vs. TEMPERATURE
0.5
MAX915-5
TEMPERATURE (°C)
CLOCK SETUP TIME (ns)
105
1.5
1.0
-15 65
2.0
25
VOD = 5mV
CL = 15pF
200
0-55
COMMON-MODE REJECTION RATIO
vs. TEMPERATURE
50
MAX915-6
TEMPERATURE (°C)
CMRR (µV/V)
105
100
-15 65
150
25
-55
INPUT OFFSET VOLTAGE vs.
TEMPERATURE
-100
100
MAX915-8
TEMPERATURE (°C)
VOS (µV)
105
0
-50
-15 65
50
25 0-55
INPUT OFFSET CURRENT vs.
TEMPERATURE
0.1
0.5
MAX915-10
TEMPERATURE (°C)
IOS (µA)
105
0.3
0.2
-15 65
0.4
25
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
_______________________________________________________________________________________
5
0-55
INPUT BIAS CURRENT vs.
TEMPERATURE
2
10
MAX915-9
TEMPERATURE (°C)
IB (µA)
105
6
4
-15 65
8
25 0-5 5
INPUT BIAS CURRENT vs.
COMMON-MODE INPUT VOLTAGE
2
10
MAX915-11
VCM (V)
IB (µA)
1
6
4
-3 -1 3
8
-4 -2 0 2 4 0-10 10
INPUT BIAS CURRENTS vs.
DIFFERENTIAL INPUT VOLTAGE
4
20
MAX915-12
DIFFERENTIAL INPUT VOLTAGE, VIN+ – VIN- (V)
IB (µA)
2
12
8
-6 -2 6
16
-8 -4 0 4 8
VIN+ +VIN- = 0V
IN-
IN+
00
OUTPUT VOLTAGE LOW vs.
SINK CURRENT
0.1
0.5
MAX915-13
IOL (mA)
VOL (V)
8
0.3
0.2
2610
0.4
4
GND
IN+
50mV/div
CLK
2V/div
Q
2V/div
Q
5ns/div
5mV
OVERDRIVE
CLOCK SETUP TIME AND PROPAGATION DELAY (Q RISING)
tSU
tPD+
tPD- tSKEW
3.0 0
OUTPUT VOLTAGE HIGH vs.
SOURCE CURRENT
3.2
4.0
MAX915-14
IOH (mA)
VOH (V)
8
3.6
3.4
2610
3.8
40
SUPPLY CURRENT PER COMPARATOR
vs. TEMPERATURE
5
MAX915-15
TEMPERATURE (°C)
I+, I- (mA)
65
15
10
-55 25 105
20
-15
I+
I-
CLOCK SETUP TIME AND PROPAGATION DELAY (Q FALLING)
IN+
50mV/div
CLK
2V/div
Q
2V/div
Q
5ns/div
-5mV
OVERDRIVE
tSU
tPD-
tPD+
tSKEW
____________________________Typical Operating Characteristics (continued)
(V+ = +5V, V- = -5V, TA = +25°C, unless otherwise noted.)
MAX915/MAX916
_______________Detailed Description
The MAX915 (single) and MAX916 (dual) are very high-
speed TTL-compatible comparators. Each has an inter-
nal negative edge-triggered master/slave D flip-flop, and
complementary TTL outputs. Unlike other TTL compara-
tors, this architecture breaks the input-to-output signal
path to accomplish the following:
1) Prevent oscillations caused by unwanted parasitic
feedback when the comparator is in its linear region.
No minimum input slew rate is required.
2) Maintain a constant propagation delay with varying
input overdrive.
The comparator can be divided into three stages, as
shown in the
Functional Diagram:
1) Input Amplifier
2) Master/Slave D Flip-Flop
3) TTL Output Stage
Input Amplifier
The comparator input amplifier is fully differential. Input
offset voltage is trimmed to less than 1.5mV (MAX915) or
2mV (MAX916) at +25°C. Input common-mode range
extends from 100mV below the negative supply rail (V-)
to 2.2V below the positive supply (V+). Total common-
mode input voltage range is 7.9V when operating from
±5V supplies.
The input amplifier has no built-in hysteresis. External
resistors should not be connected with the aim of creat-
ing hysteresis. The master/slave flip-flop makes hystere-
sis unnecessary, and impossible to add externally.
Resolution
A comparator’s ability to resolve small signal differences—
its resolution—is affected by various factors. The most sig-
nificant of these are: input offset voltage (VOS), input
referred noise (en), common-mode rejection error, and
power-supply rejection error. If the source has a high
impedance, input bias and offset currents may also impact
resolution. Avoid unbalanced source impedances.
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
6 _______________________________________________________________________________________
NAME FUNCTION
V+ Positive Supply
IN+ Noninverting Input
3 Inverting Input
PIN
1
2
V- Negative Supply. Connect to GND
for single-supply operation.
5 Clock Input
GND Ground
Q TTL Output
QComplementary TTL Output
6
7
8
_____________________________________________________________Pin Descriptions
IN-
CLK
GND
NAME FUNCTION
V-
QA TTL Output, Channel A
QAComplementary TTL Output,
Channel A
3 Ground
PIN
1
2
CLKA Clock Input, Channel A
N.C. No Connect. Not internally
connected.
6Negative Supply. Connect to GND
for single-supply operation.
INA- Inverting Input, Channel A
4
5, 12
INA+ Noninverting Input, Channel A
INB+ Noninverting Input, Channel B
7
8
9
MAX915 MAX916
4
10 INB- Inverting Input, Channel B
11 V+ Positive Supply
13 CLKB Clock Input, Channel B
14 GND Ground
15 QBComplementary TTL Output,
Channel B
16 QB TTL Output, Channel B
The MAX915 can compare input signals as small as
2.0mV over the entire common-mode voltage range
(TA= +25°C). Similarly, the MAX916 can resolve input
signals of less than 2.4mV (see Table 1).
Master/Slave D Flip-Flop
The negative edge-triggered master/slave D flip-flop
incorporates two D latches, which makes propagation
delay independent of input overdrive (VOD). When open,
the master latch samples the output of the input amplifier;
when closed, it holds the sampled data. When open, the
slave latch samples the output of the master latch; when
closed, it holds the sampled data. The master and slave
latches are open on opposite phases of the clock, pre-
venting a direct path from input to output at all times.
This makes the MAX915 and MAX916 different from
comparators with simple output latches, and delivers
high-speed performance without oscillations, even with
slow-moving input signals.
The input amplifier continuously monitors the input signal.
The master latch samples the output of the input amplifier
when the clock is high. The data is held by the master
latch and is transferred to the slave latch only on the
clock’s falling edge. The TTL outputs do not change on
the clock’s rising edge.
Clock Cycle
When the clock is high, the master stage is transparent,
and the data at the slave output is latched. On the
clock’s falling edge, the input data is latched into the
master stage, just before the slave stage becomes trans-
parent and the new data becomes valid at the output.
On the clock’s rising edge, the slave latches the data at
its input (which is also present at the flip-flop’s output),
just before the master becomes transparent to new data
at its input. Thus the comparator’s inputs are sampled
and the new data is transferred to the TTL outputs on the
falling edge of the clock.
TTL Output Stage
The complementary TTL outputs can drive high-speed
Schottky TTL with a fan-out of four.
__________Applications Information
Maximum Clock Rate
The maximum permitted clock rate exceeds 50MHz and
is a function of the device’s propagation delay. The max-
imum output toggle rate is half the clock frequency
because the comparator triggers only on the falling edge
of each clock cycle.
MAX915/MAX916
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
_______________________________________________________________________________________ 7
ERROR/RESOLUTION MAX915
2.0
Worst-case error 3.4
TEMPERATURE
DIFFERENTIAL
VIN
CLK
Q
VOD
tSU
VOS
tPD+
tSKEW
tPD-
50%
50%
50%
Q
MAX916
2.4
3.9
UNITS
mV
mV
Table 1. Input-Referred Error/Resolution
Figure 1. Timing Diagram
*RSOURCE is the balanced source resistance that will contribute the same input-referred error as the sum of the worst-case errors
from the other four sources (VOS, CMRR, en, PSRR)
RMS error
TA= +25°C
RSOURCE* 3.4 3.9 kΩ
RMS error 2.5 3.4 mV
Worst-case error 4.2 5.2 mV
TA= TMIN to TMAX
RSOURCE* 2.1 2.6 kΩ
MAX915/MAX916
Power Supplies
The MAX915/MAX916 are tested while operating from ±5V
supplies, providing an input common-mode voltage range
(VCMR) of 7.9V (-5.1V to +2.8V) (see Figure 2). Operation
from a single +5V supply provides a VCMR from -0.1V to
+2.2V below V+ (-0.1V to +2.8V). Connect V- to GND for
single-supply operation (see Figure 3).
The V+ supply provides power to the analog input stage
and to the digital circuitry, whereas the V- supply only pow-
ers the analog section. Pay special attention to bypassing
the V+ pin if the V+ supply is noisy.
Input Slew Rate
The MAX915/MAX916’s master/slave architecture elimi-
nates the minimum input slew-rate requirement common to
standard comparator architectures. As long as the com-
parator is clocked after the minimum data-to-clock setup
time requirement, and the input is greater than the com-
parator’s total DC error, the output will be valid without
oscillations. It is not necessary to bypass the input, even if
the input signal is very slow moving.
Board Layout and Bypassing
As with all high-speed components, careful high-speed
board layout and bypassing are essential for optimal per-
formance; although forgiving, the clocked architecture is
not a substitute for good layout and decoupling. A printed
circuit board with an unbroken ground plane is recom-
mended. Pay close attention to the bandwidth of the
bypass components, and keep ground leads short. Avoid
sockets; solder the IC and other components directly to the
board to minimize unwanted parasitic capacitance.
Bypass V+ and V- to GND with 100nF ceramic capacitors
placed very close to the IC supply pins. Keep the leads of
through-hole capacitors as short as possible. Do not con-
nect bypass capacitors directly from V+ to V-.
Ultra High-Speed, High-Resolution,
Single-/Dual-Supply TTL Comparators
MAX915
V+
IN+
IN-
CLK GND
Q
Q
+5V 100nF
V-
-5V 100nF
CLK, Q, Q ARE TTL SIGNALS REFERRED TO GND.
MAX915
V+
IN+
IN-
CLK V- GND
Q
Q
+5V 100nF
CLK, Q, Q ARE TTL SIGNALS REFERRED TO GND (V- = GND).
Figure 2. Dual-Supply Operation Figure 3. Single-Supply Operation
___________________Chip Topography
GND
GND
QA
INB-
INA-(V-)
0.085"
(2.159mm)
0.072"
(1.829mm)
CLKA
(IN+)
V-
INB+
(CLK)
INA+
V+
(GND)
CLKB
(Q)
(V+)
QA(Q)QB QB
(IN-)
( ) INDICATE MAX915 CALLOUTS.
TRANSISTOR COUNT: MAX915–82; MAX916–164;
SUBSTRATE CONNECTED TO V-.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
