*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
October 1995COPYRIGHT ©INTEL CORPORATION, 1995 Order Number: 272335-003
87C51/80C51BH/80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C51/80C51BH/80C51BHP/80C31BH
*See Table 1 for Proliferation Options
YHigh Performance CHMOS EPROM
Y24 MHz Operation
YImproved Quick-Pulse Programming
Algorithm
Y3-Level Program Memory Lock
YBoolean Processor
Y128-Byte Data RAM
Y32 Programmable I/O Lines
YTwo 16-Bit Timer/Counters
YExtended Temperature Range
(b40§Ctoa
85§C)
Y5 Interrupt Sources
YProgrammable Serial Port
YTTL- and CMOS-Compatible Logic
Levels
Y64K External Program Memory Space
Y64K External Data Memory Space
YONCE Mode Facilitates System Testing
YPower Control Modes
Ð Idle
Ð Power Down
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel’s reliable CHMOS III-E technology. Being a member of the MCSÉ51 controller family, the
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-
pin compatible with the existing MCS 51 controller family of products.
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,
unless information applies to a specific device.
87C51/80C51BH/80C31BH
Table 1. Proliferation Options
*Standard -1 -2 -24
80C31BH X X X X
80C51BH X X X X
80C51BHP X X X X
87C51 X X X X
NOTES:
*3.5 MHz to 12 MHz; VCC e5V g20%
-1 3.5 MHz to 16 MHz; VCC e5V g20%
-2 0.5 MHz to 12 MHz; VCC e5V g20%
-24 3.5 MHz to 24 MHz; VCC e5V g20%
272335–1
Figure 1. 87C51/BH Block Diagram
2
87C51/80C51BH/80C31BH
PROCESS INFORMATION
The 87C51/BH is manufactured on the CHMOS III-E
process. Additional process and reliability informa-
tion is available in Intel’s
Components Quality and
Reliability Handbook,
Order No. 210997.
PACKAGES
Part Prefix Package Type
87C51/BH P 40-Pin Plastic
DIP (OTP)
D 40-Pin CERDIP
(EPROM)
N 44-Pin PLCC (OTP)
S 44-Pin QFP (OTP)
272335–2
DIP
272335–3
PLCC
272335–4
*Do not connect reserved pins. QFP
Figure 2. Pin Connections
3
87C51/80C51BH/80C31BH
PIN DESCRIPTION
VCC:Supply voltage during normal, Idle and Power
Down operations.
VSS:Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1’s written to them
float, and in that state can be used as high-imped-
ance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emit-
ting 1’s.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the internal pull-
ups.
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the internal pull-
ups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1’s.
During accesses to external Data Memory that use
8-bit addresses (MOVX @Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Pin Name Alternate Function
P3.0 RXD Serial input line
P3.1 TXD Serial output line
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
P3.4 T0 Timer 0 external input
P3.5 T1 Timer 1 external input
P3.6 WR External Data Memory Write strobe
P3.7 RD External Data Memory Read strobe
Port 3 also receives some control signals for
EPROM programming and program verification.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
tion when a minimum VIH1 voltage is applied wheth-
er the oscillator is running or not. An internal pull-
down resistor permits a power-on reset with only a
capacitor connected to VCC.
ALE/PROG:Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming for
the 87C51.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no effect if
the microcontroller is in external execution mode.
4
87C51/80C51BH/80C31BH
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
PSEN:Program Store Enable is the Read strobe to
External Program Memory. When the 87C51/BH is
executing from Internal Program Memory, PSEN is
inactive (high). When the device is executing code
from External Program Memory, PSEN is activated
twice each machine cycle, except that two PSEN
activations are skipped during each access to Exter-
nal Data Memory.
EA/VPP:External Access enable. EA must be
strapped to VSS in order to enable the 87C51/BH to
fetch code from External Program Memory locations
starting at 0000H up to FFFFH. Note, however, that
if either of the Lock Bits is programmed, the logic
level at EA is internally latched during reset.
EA must be strapped to VCC for internal program
execution.
This pin also receives the programming supply volt-
age (VPP) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifi-
er.
272335–5
Figure 3. Using the On-Chip Oscillator
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require-
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the data
sheet must be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not ex-
ceed 20 pF.
272335–6
Figure 4. External Clock Drive
5
87C51/80C51BH/80C31BH
IDLE MODE
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset.
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes pro-
gram execution, from where it left off, up to two ma-
chine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminat-
ed by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is transmitted.
On the 87C51/BH either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down.
Reset redefines all the SFR’s but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
To properly terminate Power Down, the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level, and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RET1 will be the one following the instruction that
put the device into Power Down.
DESIGN CONSIDERATIONS
#Exposure to light when the device is in operation
may cause logic errors. For this reason, it is sug-
gested that an opaque label be placed over the
window when the die is exposed to ambient light.
#The 87C51/BH now have some additional fea-
tures. The features are: asynchronous port reset,
4 interrupt priority levels, power off flag, ALE dis-
able, serial port automatic address recognition,
serial port framing error detection, 64-byte en-
cryption array, and 3 program lock bits. These
features cannot be used with the older versions
of 80C51BH/80C31BH. The newer version of
80C51BH/80C31BH will have change identifier
‘‘A’’ appended to the lot number.
Table 2. Status of the External Pins during Idle and Power Down
Mode Program ALE PSEN PORT0 PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
6
87C51/80C51BH/80C31BH
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) mode facilitates
testing and debugging of systems using the
87C51/BH without the 87C51/BH having to be re-
moved from the circuit. The ONCE mode is invoked
by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains ac-
tive. While the 87C51/BH is in this mode, an emula-
tor or test CPU can be used to drive the circuit. Nor-
mal operation is restored when a normal reset is ap-
plied.
87C51/BH EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS-51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
temperature.
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of 0§Cto70
§
C. With the extend-
ed temperature range option, operational character-
istics are guaranteed over the range of b40§Cto
a
85§C.
The optional burn-in is dynamic for a minimum time
of 160 hours at 125§C with VCC e6.9V g0.25V,
following guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 3.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
Table 3. Prefix Identification
Prefix Package Temperature Burn-in
Type Range
P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No
S QFP Commercial No
TP Plastic Extended No
TD Cerdip Extended No
TN PLCC Extended No
TS QFP Extended No
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
NOTE:
Contact distributor or local sales office to match EXPRESS
prefix to proper device.
Examples:
P87C51 indicates 87C51 in a plastic package and
specified for commercial temperature range, without
burn-in.
LD87C51 indicates 87C51 in a cerdip package and
specified for extended temperature range with burn-
in.
7
87C51/80C51BH/80C31BH
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias Àb40§Ctoa
85§C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa
150§C
Voltage on EA/VPP Pin to VSS ÀÀÀÀÀÀÀ0V to a13.0V
Voltage on Any Other Pin to VSS ÀÀb0.5V to a6.5V
Maximum IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(Based on package heat transfer limitations, not de-
vice power consumption.)
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol Description Min Max Unit
TAAmbient Temperature Under Bias
Commercial 0 a70 §C
Express b40 a85 §C
VCC Supply Voltage 4.5 5.5 V
fOSC Oscillator Frequency MHz
87C51/BH 3.5 12
87C51-1/BH-1 3.5 16
87C51-2/BH-2 0.5 12
87C51-24/BH-24 3.5 24
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol Parameter Min Typ(1) Max Unit Test Conditions
VIL Input Low Voltage
Commercial b0.5 0.2 VCC b0.1 V
Express b0.5 0.2 VCC b0.15 V
VIL1 Input Low Voltage EA
Commercial 0 0.2 VCC b0.3 V
Express b0.5 0.2 VCC b0.35 V
VIH Input High Voltage
(Except XTAL1, RST)
Commercial 0.2 VCC a0.9 VCC a0.5 V
Express 0.2 VCC a1V
CC a0.5 V
VIH1 Input High Voltage
(XTAL1, RST)
Commercial 0.7 VCC VCC a0.5 V
Express 0.7 VCC a0.1 VCC a0.5 V
VOL Output Low Voltage(6) 0.3 V IOL e100 mA(2)
(Ports 1, 2, 3) 0.45 V IOL e1.6 mA(2)
1.0 V IOL e3.5 mA(2)
8
87C51/80C51BH/80C31BH
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
Symbol Parameter Min Typ(1) Max Unit Test Conditions
VOL1 Output Low Voltage(6) 0.3 V IOL e200 mA(2)
(Port 0, ALE, PSEN) 0.45 V IOL e3.2 mA (2)
1.0 V IOL e7.0 mA(2)
VOH Output High Voltage VCC b0.3 V IOH eb
10 mA(3)
(Ports 1, 2, 3, ALE, PSEN) VCC b0.7 V IOH eb
30 mA(3)
VCC b1.5 V IOH eb
60 mA(3)
VOH1 Output High Voltage VCC b0.3 V IOH eb
200 mA(3)
(Port 0 in External Bus Mode) VCC b0.7 V IOH eb
3.2 mA(3)
VCC b1.5 V IOH eb
7.0 mA(3)
IIL Logical 0 Input Current VIN e0.45V
(Ports 1, 2, 3)
Commercial b50 mA
Express b75 mA
ILI Input Leakage Current g10 mA 0.45 kVIN kVCC
(Port 0)
ITL Logical 1-to-0 Transition Current VIN e2V
(Ports 1, 2, 3)
Commercial b650 mA
Express b750 mA
RRST RST Pulldown Resistor 40 225 kX
CIO Pin Capacitance 10 pF @1 MHz, 25§C
ICC Power Supply Current (Note 4)
Active Mode
@12 MHz (Figure 5) 11.5 20 mA
@16 MHz 26 mA
@24 MHz 38 mA
Idle Mode
@12 MHz (Figure 5) 3.5 7.5 mA
@16 MHz 9.5 mA
@24 MHz 13.5 mA
Power Down Mode 5 50 mA
9
87C51/80C51BH/80C31BH
NOTES:
1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specifi-
cation when the address bits are stabilizing.
4. See Figures 6 through 8 for ICC test conditions. Minimum VCC for Power Down is 2V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit portÐ
Port 0: 26 mA
Ports 1, 2, and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
272335–26
Figure 5. 87C51/BH ICC vs Frequency
10
87C51/80C51BH/80C31BH
272335–10
Figure 6. ICC Test Condition, Active Mode. All other pins are disconnected.
272335–8
Figure 7. ICC Test Condition, Idle Mode.
All other pins are disconnected.
272335–9
Figure 9. ICC Test Condition, Power Down
Mode. All other pins are disconnected.
VCC e2V to 5.5V.
272335–11
Figure 8. Clock Signal Waveform for ICC Tests in Active and Idle Modes
TCLCH eTCHCL e5ns
11
87C51/80C51BH/80C31BH
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:Address.
C:Clock.
D:Input data.
H:Logic level HIGH.
I:Instruction (program memory contents).
L:Logic level LOW, or ALE.
P:PSEN.
Q:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
For example,
TAVLL eTime from Address Valid to ALE Low.
TLLPL eTime from ALE Low to PSEN Low.
AC CHARACTERISTICS: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and
PSEN e100 pF; Load Capacitance for All Other Outputs e80 pF)
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2.
Symbol Parameter
Oscillator
Units12 MHz 24 MHz Variable
Min Max Min Max Min Max
1/TCLCL Oscillator Frequency
87C51/BH 3.5 12 MHz
87C51-1/BH-1 3.5 16 MHz
87C51-2/BH-2 0.5 12 MHz
87C51-24/BH-24 3.5 24 MHz
TLHLL ALE Pulse Width 127 43 2TCLCLb40 ns
TAVLL Address Valid to ALE Low
87C51/BH 43 TCLCLb40 ns
87C51-24/BH-24 12 TCLCLb30 ns
TLLAX Address Hold After ALE Low 53 12 TCLCLb30 ns
TLLIV ALE Low to Valid Instr In
87C51/BH 234 4TCLCLb100 ns
87C51-24/BH-24 91 4TCLCLb75 ns
TLLPL ALE Low to PSEN Low 53 12 TCLCLb30 ns
TPLPH PSEN Pulse Width 205 80 3TCLCLb45 ns
TPLIV PSEN Low to Valid Instr In
87C51/BH 145 3TCLCLb105 ns
87C51-24/BH-24 35 3TCLCLb90 ns
12
87C51/80C51BH/80C31BH
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued)
Symbol Parameter
Oscillator
Units
12 MHz 24 MHz Variable
Min Max Min Max Min Max
TPXIX Input Instr Hold After PSEN 00 0 ns
TPXIZ Input Instr Float After PSEN
87C51/BH 59 TCLCLb25 ns
87C51-24/BH-24 21 TCLCLb20 ns
TAVIV Address to Valid Instr In 312 103 5TCLCLb105 ns
TPLAZ PSEN Low to Address Float 10 10 10 ns
TRLRH RD Pulse Width 400 150 6TCLCLb100 ns
TWLWH WR Pulse Width 400 150 6TCLCLb100 ns
TRLDV RD Low to Valid Data In
87C51/BH 252 5TCLCLb165 ns
87C51-24/BH-24 113 5TCLCLb95 ns
TRHDX Data Hold After RD 00 0 ns
TRHDZ Data Float After RD 107 23 2TCLCLb60 ns
TLLDV ALE Low to Valid Data In
87C51/BH 517 8TCLCLb150 ns
87C51-24/BH-24 243 8TCLCLb90 ns
TAVDV Address to Valid Data In
87C51/BH 585 9TCLCLb165 ns
87C51-24/BH-24 285 9TCLCLb90 ns
TLLWL ALE Low to RD or WR Low 200 300 75 175 3TCLCLb50 3TCLCLa50 ns
TAVWL Address to RD or WR Low
87C51/BH 203 4TCLCLb130 ns
87C51-24/BH-24 77 4TCLCLb90 ns
TQVWX Data Valid to WR Transition
87C51/BH 33 TCLCLb50 ns
80C51-24/BH-24 12 TCLCLb30 ns
13
87C51/80C51BH/80C31BH
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued)
Symbol Parameter
Oscillator
Units
12 MHz 24 MHz Variable
Min Max Min Max Min Max
TWHQX Data Hold After WR
87C51/BH 33 TCLCLb50 ns
87C51-24/BH-24 7 TCLCLb35 ns
TQVWH Data Valid to WR High
87C51/BH 433 7TCLCLb150 ns
87C51-24/BH-24 222 7TCLCLb70 ns
TRLAZ RD Low to Address Float 0 0 0 ns
TWHLH RD or WR High to ALE High
87C51/BH 43 123 TCLCLb40 TCLCLa40 ns
87C51-24/BH-24 12 71 TCLCLb30 TCLCLa30 ns
EXTERNAL PROGRAM MEMORY READ CYCLE
272335–12
EXTERNAL DATA MEMORY READ CYCLE
272335–13
14
87C51/80C51BH/80C31BH
EXTERNAL DATA MEMORY WRITE CYCLE
272335-14
EXTERNAL CLOCK DRIVE
All parameter values apply to all devices unless otherwise indicated. In this
table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2.
Symbol Parameter Min Max Units
1/TCLCL Oscillator Frequency
87C51/BH 3.5 12 MHz
87C51-1/BH-1 3.5 16 MHz
87C51-2/BH-2 0.5 12 MHz
87C51-24/BH-24 3.5 24 MHz
TCHCX High Time
87C51/BH 20 ns
8751-24/BH-24 0.35TCLCL 0.65TCLCL ns
TCLCX Low Time
87C51/BH 20 ns
87C51-24/BH-24 0.35TCLCL 0.65TCLCL ns
TCLCH Rise Time
87C51/BH 20 ns
87C51-24/BH-24 10 ns
TCHCL Fall Time
87C51/BH 20 ns
87C51-24/BH-24 10 ns
EXTERNAL CLOCK DRIVE WAVEFORM
272335–15
15
87C51/80C51BH/80C31BH
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
12 MHz 24 MHz Variable Oscillator
Symbol Parameter Oscillator Oscillator Units
Min Max Min Max Min Max
TXLXL Serial Port Clock 1.0 0.500 12TCLCL ms
Cycle Time
TQVXH Output Data Setup 700 284 10TCLCLb133 ns
to Clock Rising Edge
TXHQX Output Data Hold ns
After Clock
Rising Edge
87C51/BH 50 2TCLCLb117
87C51-24/BH-24 34 2TCLCLb34
TXHDX Input Data Hold 0 0 0 ns
After Clock
Rising Edge
TXHDV Clock Rising Edge 700 283 10TCLCLb133 ns
to Input Data Valid
SHIFT REGISTER MODE TIMING WAVEFORMS
272335–18
AC TESTING INPUT, OUTPUT WAVEFORMS
272335–19
AC inputs during testing are driven at VCC b0.5 for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0.’’ Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’.
FLOAT WAVEFORMS
272335–20
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH eg20 mA.
16
87C51/80C51BH/80C31BH
PROGRAMMING THE 87C51
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines. Control and program signals must
be held at the levels indicated in Table 4. Normally
EA/VPP is held at logic high until just before
ALE/PROG is to be pulsed. The EA/VPP is raised to
VPP, ALE/PROG is pulsed low and then EA/VPP is
returned to a high (also refer to timing diagrams).
NOTE:
#Exceeding the VPP maximum for any amount of
time could damage the device permanently. The
VPP source must be well regulated and free of
glitches.
DEFINITION OF TERMS
ADDRESS LINES: P1.0– P1.7, P2.0– P2.5, P3.4 re-
spectively for A0– A14.
DATA LINES: P0.0– P0.7 for D0– D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7.
PROGRAM SIGNALS: ALE/PROG,EA/VPP.
Table 4. EPROM Programming Modes
Mode RST PSEN ALE/ EA/ P2.6 P2.7 P3.3 P3.6 P3.7
PROG VPP
Program Code Data H L ß12.75V L HHHH
Verify Code Data H L H H L L L H H
Program Encryption H L ß12.75V L H H L H
Array Address 0– 3F
Program Lock Bits Bit 1 H L ß12.75V HHHHH
Bit 2 H L ß12.75V H H H L L
Bit 3 H L ß12.75V H L H H L
Read Signature Byte H L H H LLLLL
272335–21
*See Table 4 for proper input on these pins
Figure 10. Programming the EPROM
17
87C51/80C51BH/80C31BH
272335–22
*For compatibility, 25 pulses may be used.
Figure 11. Programming Waveforms
PROGRAMMING ALGORITHM
Refer to Table 4 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control sig-
nals.
4. Raise EA/VPP from VCC to 12.75V g0.25V.
5. Pulse ALE/PROG 5 times*for the EPROM array,
and 25 times for the encryption table and the lock
bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
Program Verify
Verification may be done after programming either
one byte or a block of bytes. In either case a com-
plete verify of the array will ensure reliable program-
ming of the 87C51.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their fea-
tures are enabled.
ROM and EPROM Lock System
The program lock system, when programmed, pro-
tects the onboard program against software piracy.
The 80C51BH has a one level program lock system
and a 64-byte encryption table. If program protection
is desired, the user submits the encryption table with
their code and both the lock bit and encryption array
are programmed by the factory. The encryption array
is not available without the lock bit. For the lock bit
to be programmed, the user must submit an encryp-
tion table. The 87C51 has a 3-level program lock
system and a 64-byte encryption array. Since this is
an EPROM device, all locations are user-program-
mable. See Table 5.
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1’s). Every
time that a byte is addressed during a verify, 6 ad-
dress lines are used to select a byte of the Encryp-
tion Array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un-
programmed state (all 1’s), will return the code in its
original, unmodified form. For programming the En-
cryption Array, refer to Table 4 (Programming the
EPROM).
When using the encryption array, one important fac-
tor needs to be considered. lf a code byte has the
value 0FFH, verifying the byte will produce the en-
cryption byte value. lf a large block (l64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH, and not
all of them the same value. This will ensure maxi-
mum program protection.
18
87C51/80C51BH/80C31BH
Program Lock Bits
The 87C51 has 3 programmable lock bits that when
programmed according to Table 5 will provide differ-
ent levels of protection for the on-chip code and
data.
Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 87C51 and 80C51BH have 3 signature bytes in
locations 30H, 31H, and 60H. To read these bytes
follow the procedure for EPROM verify, but activate
the control lines provided in Table 4 for Read Signa-
ture Byte.
Location Device Contents
30H All 89H
31H All 58H
60H 87C51 51H
80C51BH 11H
Erasure Characteristics
(Windowed Devices Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an ex-
tended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadver-
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 mW/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1’s state.
Table 5. Program Lock Bits and the Features
Program Lock Bits Protection Type
LB1 LB2 LB3
1 U U U No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
2 P U U MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3 P P U Same as 2, also verify is disabled.
4 P P P Same as 3, also external execution is disabled.
19
87C51/80C51BH/80C31BH
EPROM PROGRAMMING, EPROM AND ROM VERIFICATION
CHARACTERISTICS:
(TAe21§Cto27
§
C, VCC e5V g10%, VSS e0V)
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 12.5 13.0 V
IPP Programming Supply Current 75 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to VPP 48TCLCL
TSHGL VPP Setup to PROG Low 10 ms
TGHSL VPP Hold After PROG 10 ms
TGLGH PROG Width 90 110 ms
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float After ENABLE 0 48TCLCL
TGHGL PROG High to PROG Low 10 ms
EPROM PROGRAMMING, EPROM AND ROM VERIFICATION WAVEFORMS
272335–23
*For programming conditions see Figure 10.
**5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
20
87C51/80C51BH/80C31BH
Thermal Impedance
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operating conditions and ap-
plications. See the Intel Packaging Handbook (Order
No. 240800) for a description of Intel’s thermal im-
pedance test methodology.
Package iJA iJC Device
P45
§
C/W 16§C/W 87C51
75§C/W 23§C/W BH
D45
§
C/W 15§C/W 87C51
36§C/W 13§C/W BH
N46
§
C/W 16§C/W All
S98
§
C/W 24§C/W All
DATA SHEET REVISION HISTORY
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices.
The following differences exist between this data-
sheet (272335-003) and the previous version
(272335-002):
1. Removed b20 and b3 spec, replaced with b24
spec.
2. Added b24 spec.
3. 80C51BHP is replaced by 80C51BH with 64-byte
encryption table submitted and lock bit 1 set.
4. 80C51BH/80C31BH are now having some addi-
tional features as 87C51.
5. Revised PRST value and ICC idle values.
6. Added P3.3 control pin to programming and veri-
fication.
7. Added 80C51BH signature byte.
The following differences exist between the ‘‘-002’’
and the ‘‘-001’’ version of the 87C51/80C51BH/
80C31BH datasheet.
1. Removed bL, IOL eg10 mA from Float Wave-
forms figure.
2. Removed QP, QD and QN (commercial with ex-
tended burn-in) from Table 3. Prefix Identification.
This data sheet (272335-001) replaces the following:
80C51BH/80C31BH Express 270218-003
80C51BHP 270603-004
87C51/80C51BH/80C31BH 270147-008
87C51 Express 270430-002
87C51-20/-3 272082-002
21
