Intel-Celeron-Processor - Intel

Mobile Intel® Celeron® Processor

(0.13µ) in Micro-FCBGA Package

at Low Voltage 650 MHz

Datasheet

October 2001

Order Number: 298517-001

Mobile Intel® Celeron® Processor (0.13µ) in Micr o- FCB G A Pac kage D atashe e t

2 Datasheet 298517-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to an y intell ect ual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liabilit y or warra nti e s relati ng to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended

for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Mobil e Intel  Celeron™ Processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporati on

www.intel.com

or call 1-800-548-4725

Intel®, Pentium®, Celeron®, and SpeedStep™ are registered trademarks or trademarks of Intel Corporation in the United States and ot her count ri es .

*Other names and brands may be claimed as the property of others.

Mobile Intel® Celeron® Processor (0.13µ) in Micr o- FCB G A Pac kage D atashe e t

298517-001 Datasheet 3

Contents

1. Introduction.......................................................................................................................................9

1.1 Overview.................................................................................................................9

1.2 Terminology..........................................................................................................10

1.3 References...........................................................................................................11

2. Mobil e Intel Celeron Proc e ss or Features.......................................................................................12

2.1 New Features in the Mobile Intel Celeron Processor...........................................12

2.1.1 256K On-die Integrated L2 Cache ..........................................................12

2.1.2 Data Prefetc h Logic.................................................................................12

2.1.3 Signal Differences Between the Mobile Intel Celeron Processor (0.18µ) (in

BGA2 and Micro-PGA2 Packages) and the Mobile Intel Celeron Processor

(0.13µ) (in Micro-FCBGA Package)........................................................13

2.2 Power Manag eme nt .............................................................................................13

2.2.1 Clock Control Architecture.......................................................................13

2.2.2 Normal State ...........................................................................................13

2.2.3 Auto Halt State........................................................................................13

2.2.4 Quick Start State .....................................................................................14

2.2.5 HALT/Grant Snoop State ........................................................................15

2.2.6 Deep Slee p State ....................................................................................15

2.2.7 Operati ng Sys tem Imp lications of Low-power Stat es .............................16

2.3 AGTL Signals .......................................................................................................16

2.4 Mobil e Intel Celeron Proc es s or CPUID................................................................16

3. Electrical Sp ecific a tio ns..................................................................................................................18

3.1 Processor System Signals ...................................................................................18

3.1.1 Power Seque nc in g Requ ire ments...........................................................19

3.1.2 Test Access Port (TAP) Connection .......................................................19

3.1.3 Catastrophic Thermal Protection.............................................................20

3.1.4 Unused S ignals .......................................................................................20

3.1.5 Signal State in Low-power States ...........................................................20

3.1.5.1 Sy s tem Bus Sig nals ..............................................................20

3.1.5.2 CMO S and Open- dra in S ignals.............................................20

3.1.5.3 Other Signals.........................................................................21

3.2 Power Supp ly Require ment s................................................................................21

3.2.1 Decoupling Guidelines ............................................................................21

3.2.2 Voltage Planes ........................................................................................21

3.2.3 Voltage Identification...............................................................................22

3.3 System Bus Clock and Processor Clocking.........................................................23

3.4 Maximum Ratings.................................................................................................23

3.5 DC Specifications.................................................................................................24

3.6 AC Speci ficat ions .................................................................................................29

3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drai n AC

Specifications ..........................................................................................29

4. Sys tem Sig na l Simulati ons.............................................................................................................42

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4.1 System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal Quality

Specifications....................................................................................................... 42

4.2 AGTL AC Signal Quality Specifications............................................................... 44

4.3 Non-AGTL Signal Quality Specifications............................................................. 45

4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications....................... 46

5. Mechanical Specifications.............................................................................................................. 47

5.1 Surface Mou nt Micr o-FCB GA Pack age............................................................... 47

5.2 Signal Listings...................................................................................................... 51

6. VCC Thermal Specifications............................................................................................................ 58

6.1 Thermal Diode ..................................................................................................... 58

7. Processor Initialization and Configuration ..................................................................................... 60

7.1 Description........................................................................................................... 60

7.1.1 Quick Start Enable.................................................................................. 60

7.1.2 Syst em Bus Frequenc y........................................................................... 60

7.1.3 APIC Enable ........................................................................................... 60

7.2 Clock Frequencies and Ratios.............................................................................60

8. Processor Interface........................................................................................................................ 61

8.1 Alpha bet ic al Si gna l Refere nce.............................................................................61

8.2 Signal Summaries................................................................................................ 71

Appendix A. PLL RLC Filter Specification .................................................................................................. 73

A1. Introduction .........................................................................................................73

A2. Filter Specification............................................................................................... 73

A3. Recommendation for Mobile Systems................................................................ 74

A4. Comments........................................................................................................... 75

Mobile Intel® Celeron® Processor (0.13µ) in Micr o- FCB G A Pac kage D atashe e t

298517-001 Datasheet 5

Figures

Figure 1. Clock Control States ..........................................................................................14

Figure 2. PLL RLC Filter....................................................................................................22

Figure 3. VTTPWRGD Sy stem- Leve l Connec t ions...........................................................23

Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.15V)....................26

Figure 5. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting =

1.15V)................................................................................................................26

Figure 6. BCLK/PICCLK/TCK Generic Clock Timing Waveform ......................................34

Figure 7. Valid Delay Timin gs ...........................................................................................34

Figure 8. Setup and Hold Timings.....................................................................................35

Figure 9. Cold/Warm Reset and Configuration Timings ...................................................35

Figure 10. Power-on Seque nc e and Reset Timin gs .........................................................36

Figure 11. Power Down Se quencing and Timings (VCC Leadi ng)...................................37

Figure 12. Power Down Sequencing and Timings (VCCT Leading) ....................................38

Figure 13. Test Timings (Boundary Scan) .........................................................................39

Figure 14. Test Reset Timings..........................................................................................39

Figure 15. Quick Start/Deep Sleep Timing (BCLK Stopping Method)...............................40

Figure 16. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method).........................41

Figure 17. BCLK/ PICC LK G eneric Clock Wavefor m.........................................................43

Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform................................44

Figure 19. Micro-FCBGA Pac k age – Top and Bottom Is ometr ic Vie ws ............................48

Figure 20. Micro-FCBGA Pac k age – Top and Side Views ...............................................49

Figure 21. Micro-FCBGA Pac kage - Bottom Vie w............................................................50

Figure 22. Pin/Bal l Map - Top View...................................................................................51

Figure 23. PLL Filter Spec if icati ons ..................................................................................74

Mobile Intel® Celeron® Processor (0.13µ) in Micr o- FCB G A Pac kage D atashe e t

6 Datasheet 298517-001

Tables

Table 1. New and Revised Mob il e Intel Cel eron Pr oce s s or (0.13 µ) Signals.................... 13

Table 2. Clock State Characteristics................................................................................. 16

Table 3. Mobile Intel Celeron Processor CPUID .............................................................. 17

Table 4. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors................. 17

Table 5. System Signa l Gro ups........................................................................................ 18

Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals............... 19

Table 7. Mobile Intel Celeron Processor VID Values ....................................................... 22

Table 8. Mobile Intel Celeron Processor Absolute Maximum Ratings ............................. 24

Table 9. Power Specifications for Mobile Intel Celeron Processor...................................25

Table 10. VCC Tolerances for the Low Voltage Mobile Intel Celeron Processor: VID

= 1.15V .............................................................................................................27

Table 11. VCC Tolerances for the Low Voltage Mobile Intel Celeron Processor in the Deep

Sleep State: VID = 1.15 V ................................................................................. 27

Table 12. AGTL Signal Group DC Specifications............................................................. 28

Table 13. AGTL Bus DC Specifications............................................................................ 28

Table 14. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC

Specifications ................................................................................................... 29

Table 15. System Bus Clock AC Specifications ...............................................................30

Table 16. Valid Mobile Intel Celeron Processor Frequencies........................................... 30

Table 17. AGTL Signal Groups AC Specifications ........................................................... 31

Table 18. CMOS and Open-drain Signal Groups AC Specifications................................ 31

Table 19. Reset Configuration AC Specifications and Power On/Power Down Timings . 32

Table 20. APIC Bus Signa l AC Spec i ficat ions.................................................................. 32

Table 21. TAP Signal AC Specifications........................................................................... 33

Table 22. Quick Start/Deep Sleep AC Specifications....................................................... 33

Table 23. BCLK DC Speci fi c ations and AC Si gna l Qu al ity Spec if ic ati ons ....................... 42

Table 24. PICCLK DC Specifications and AC Signal Quality Specifications.................... 43

Table 25. 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the

Processor Core................................................................................................. 45

Table 26. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor

Core.................................................................................................................. 45

Table 27. Micro-FCBGA Package Mechanical Specifications.......................................... 47

Table 28. Signal Listing in Order by Pin/Ball Number ...................................................... 52

Table 29. Signal Listing in Order by Signal Name............................................................ 55

Table 30. Voltage and No-Connect Pin/Ball Locations.....................................................57

Table 31. Power Specifications for Mobile Intel Celeron Processor................................. 58

Table 32. Thermal Diode Interface................................................................................... 59

Table 33. Thermal Diode Specifications........................................................................... 59

Table 34. BSEL[1:0] Encoding.......................................................................................... 63

Table 35. Input Signals..................................................................................................... 71

Table 36. Output Signals .................................................................................................. 71

Table 37. Input/Output Signals (Single Driver)................................................................. 72

Table 38. Input/Output Signals (Multiple Driver)............................................................... 72

Table 39. PLL Filter Inductor Recommendations .............................................................74

Table 40. PLL Filter Capacitor Recommendations........................................................... 74

Table 41. PLL Filter Resistor Recommendations............................................................. 75

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298517-001 Datasheet 7

Revision History

Date Revision Updates

October 2001 298517-001 Initial release

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8 Datasheet 298517-001

Low Voltage Mobile Intel ® Celeron®

Processor (0.13µ) in Micro-FCBGA

Package

Product Features

! Low Voltage Mobile Intel Celero n P r ocessor

(0.13µ) with the following Processor core/bus

speed s:

 650/100 MHz at 1.15V

! Supports the Intel Architecture with Dynamic

Execution

! On-die primary 16-Kbyte instruction cache and

16-Kbyte write-back data cache

! On-die second level cache (256-Kbyte) with

Advanced Transfer Cache Architecture

! Data Prefetch Logic

! Integrated AGTL termination

! Integrated math co-processor

! Micro-FCBGA packaging te chnol ogies

 Supports thin form factor notebook

designs

 Exposed die enables more efficient

heat dissipation

! Fully compatible with previo us Intel

microprocessors

 Binary compatible with all

applications

 Support for MMX™ technology

 Support for Streaming SIMD

Extensions

! Po wer Management Featur es

 Quick Start and Deep Sleep modes

provide low power dissipation

! On-die thermal diode

Mobile Intel® Celeron® Processor (0.13µ) in Micr o- FCB G A Pac kage D atashe e t

298517-001 Datasheet 9

1. Introduction

Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Mobile Intel®

Celeron® Processor offers high-performance and low-power consumption. The Mobile Intel Celeron

Processor (0.13µ) in Micro-FCBGA package (hereafter referred to as “the Mobile Intel Celeron

Processor”) is based on the same core as existing mobile Intel® Pentium® III-M processors. Key

performance features include Internet Streaming SIMD instructions, an Advanced Transfer Cache

architecture, and a processor system bus speed of 100 MHz. These features are offered in Micro-

FCBGA package for surface mount boards. All of these technologies make outstanding performance

possible for mobile PCs in a variety of shapes and sizes.

The 256-KB integrated L2 cache based on the Advanced Transfer Cache architecture runs at full speed

and is designed to help improve performance. It complements the system bus by providing critical data

faster and reducing total system power consumption. The processor also features Data Prefetch Logic

that speculatively fetches data to the L2 cache, resulting in improved performance. The Mobile Intel

Celeron processor’s 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus provides a

glue-less, point-to-point interface for a memory controller hub.

This document covers the electrical, mechanical, and thermal specifications for the following:

• The Low Voltage Mobile Intel Celeron P r ocessor at the following frequency and voltage:

650 MHz at 1.15V.

• Unless explicitly stated, all references to the Mobile Intel Celeron Processor (0.13µ) in Micro-

FCBGA package in this do cument also ap ply to the Low Voltage Mobile Intel Celeron Processor

(0.13µ) in the Micro-FCBGA package.

1.1 Overview

• Performance features

— Supports the Intel Architecture with Dynamic Execution

— Supports the Intel Architecture MMX™ technology

— Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance

— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard

— Data Prefetch Logic

• On-die primary (L1) instruction and data caches

— 4-way set associative, 32-byte line size, 1 line per sector

— 16-Kbyte instruction cache and 16-Kbyte write-back data cache

— Cacheable range controlled by processor programmable registers

• On-die second level (L2) cache

— 8-way set associative, 32-byte line size, 1 line per sector

— Operates at full core speed

— 256-Kbyte ECC protected cache data array

• AGTL system bus interface

— 64-bit data bus, 100-MHz operation

— Uniprocessor, two loads only (processor and chipset)

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— Integrated termination

• Processor clock control

— Quick Start for low power, low exit latency clock “throttling”

— Deep Sleep mode for lower power dissipation

• Thermal diode for measuring processor temperature

1.2 Terminology

Term Definition

# A “#” symbol following a signal name indicates that the signal is active low. This means that when the signal

is asserted (bas ed on the name of the signal) it is in an electrical lo w state. Otherwise, signals are driven in

an electrical high state when they are asserted. In state machine diagrams, a signal name in a condition

indicates the condition of that signal being asserted

! Indicates t he condition of t hat signal not bei ng assert ed. For example, the condition “!STPCLK # and HS” is

equivalent to “the act ive l ow signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.”

L Electri cal low signal levels

H Electri cal high signal levels

0 Logical low. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” =

“LHLH” also refers to a hexadecimal “A.”

1 Logical high. For example, BD[3:0] = “1010” = “HLHL” refers t o a hexadecimal “A,” and D[3:0]# = “1010” =

“LHLH” also refers to a hexadecimal “A.”

TBD Specificat i ons that are yet to be determined and will be updated in future revi sions of the document.

X Don’t care conditi on

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298517-001 Datasheet 11

1.3 References

• P6 Family of Processors Hardware Developer’s Manual (Order Number 244001)

• Intel® Architecture Software Developer’s Manual

— Volume I: Basic Architecture (Order Number 245470)

— Volume II: Instruction Set Reference (Order Number 245471)

— Volume III: System Programming Guide (Order Number 245472)

• CK-408(CK-Titan) Clock Synthesizer/Driver Specification (Contact your Intel Field Sales

Representative)

• Mobile Intel® Pentium® III Processor-M I/O Buffer Models, IBIS Format (Contact your Intel Field

Sales Representative)

• Mobile Intel® Pentium® III Processor-M / 440MX Platform Design Guide (Contact your Intel

Field Sales Representative)

• Intel Processor Identification and the CPUID Instruction Application Note AP-485 (Order

Number 241618-009)

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12 Datasheet 298517-001

2. Mobile Intel Celeron Processor

Features

2.1 New Features in the Mobile Intel Celeron Processor

2.1.1 256K On-die Integrated L2 Cache

The 256K on die integrated L2 cache on the Mobile Intel Celeron Processor is double the L2 cache size

on the Mobile Intel Celeron Processor (0.18µ). The L2 cache runs at the processor core speed and the

increased cache size provides superior processing power.

2.1.2 Data Prefetch Logic

The Mobile Intel Celeron Processor features Data Prefetch Logic that speculatively fetches data to the

L2 cache before an L1 cache request occurs. This reduces transactions between the cache and system

memory reducing or eliminating bus cycle penaltie s, result ing in improved performance. T he processor

also includes extensions to memory order and reorder buffers that boost performance.

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298517-001 Datasheet 13

2.1.3 Signal Differences Between the Mobile Intel Celeron Processor

(0.18u) (in BGA2 and Micro-PGA2 Packages) and the Mobile

Intel Celeron Processor (0.13µ

µµ

µ) (in Micro-FCBGA Package)

A list of new and changed signals is shown in Table 1.

Table 1. New and Revised Mobile Intel Celeron Processor (0.13µ

µµ

µ) Signals

Signals Function

BSEL[1: 0] Signals are output only i nst ead of I/O. Please refer to the Appendix for details.

DPSLP# Deep Sleep pin (replaces S LP# pin on the mobile Celeron proc essor (0.18u))

NCTRL AGTL output buffer pull down impedance control.

VID[4:0] Voltage Identif ication (different implementati on from mobile Celeron process or (0.18u).

Please refer t o Section 3.2.3 for details.

VTTPWRGD Power Good signal for V CCT, which i ndic at es that, the VID signals are st abl e. Please refer to

Figure 3 for VTTPWRGD System-Level Connections.

2.2 Power Management

2.2.1 Clock Control Architecture

The Mobile Intel Celeron Processor clock control architecture (Figure 1) has been optimized for leading

edge mobile computer designs. The clock control architecture consists of six different clock states:

Normal, Auto Halt, Quick Start, HALT/Grant Snoop and Deep Sleep states. The Auto Halt state

provides a low-power clock state that can be controlled through the software execution of the HLT

instruction. The Quick Start state provides a ver y low power and low exit latency clock sta te that can be

used for hardware controlled “idle” computer states. The Deep Sleep state provides extremely low-

power states that can be used for “Power-On-Suspend” computer states, which is an alternative to

shutting off the processor’s power. The exit latency of the Deep Sleep state is 30 msec in the Mobile

Intel Celeron Processor. Performing state transitions not sho wn i n Fi gure 1 is neither recommended nor

supported. Figure 2 provides the clock state characteristics, which are described in detail in the following

sections.

2.2.2 Normal State

The Normal state of the processor is the normal operating mode where the processor’s core clock is

running and the processor is actively executing instructions.

2.2.3 Auto Halt State

This is a low-power mode entered by the processor through the execution of the HLT instruction. A

transition to the Normal state is made by a halt break event (one of the following signals going active:

NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).

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Asserting the STP CLK# si gnal while in the Auto Halt state will cause the processor to transit ion to the

Quick Start state. Deasserting STPCLK# will cause the processor to return to the Auto Halt state

without issuing a new Halt bus cycle.

The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel®

Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more

information. No Halt bus c ycl e is issued when returning to the Auto Halt state from the System

Management Mode (SMM).

The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have been

flushed, the processor will return to the Auto Halt state without issuing a Halt bus c ycle. Transitions in

the A20M# and PREQ# signals are recognized while in the Auto Halt state.

Figure 1. Clock Control States

Quick Start

Normal

HS=false Deep Sleep 2

HALT/Grant

Snoop

Auto Halt

HS=true

STPCLK#1BCLK stopped

or DPSLP#

snoop

occurs

BCLK on

and !DPSLP#

(!STPCLK# and !HS)

or RESET#

snoop

serviced

HLT

instruction1

snoop

serviced snoop

occurs

STPCLK#1

!STPCLK#

and HS

halt

break

V0001-022

NOTES:

1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycl e complet es

Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

HLT – HLT instruction executed

HS – Processor Halt State

2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description

for details.

2.2.4 Quick Start State

The processor is required to be configured for the Quick Start state by strapping the A15# signal low. In

the Quick Start state the processor is only capable of acting on snoop transactions generated by the

system bus priority device. Because of its snooping behavior, Quick Start can only be used in a

unipr ocessor (U P) configuration.

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298517-001 Datasheet 15

A transition to the Deep Sleep state can be made by stopping the clock input to the processor or asserting

the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made only if the

STPCLK# signal is deasserted.

While in this state the processor is limited in its ability to respond to input. It is incapable of latching any

interrupts, servicing snoop transactions from symmetric bus masters, or responding to FLUSH# or

BINIT# assertions. While the processor is in the Quick Start state, it will not respond pro perly to any

input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal changes, then the

behavior of the processor will be unpredictable. No serial interrupt messages may begin or be in progress

while the processor is in the Quick Start state.

RESET# assertio n will cause the processor to immediatel y i nitialize itself, but the processor will sta y i n

the Quick Start state after initia lization until STP CLK# is deasserted .

2.2.5 HALT/ Gr ant Snoop State

The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick Start

state. When a snoop transaction is presented on the system bus the processor will enter the HALT/Grant

Snoop state. The processor will re main in this state until the snoop has been serviced and the system bus

is quiet. After the snoop has been serviced, the processor will return to its previous state. If the

HALT/Grant Snoop state is entered from the Quick Start state, then the input signal restrictions of the

Quick Start state still apply in the HALT/Grant Snoop state, except for those signal transitions that are

required to perform the snoop.

2.2.6 Deep Sleep State

The Deep Sleep state is a very low power state that the processor can enter while maintaining its context.

The Deep Sleep state is entered by stopping the BCLK input to the processor or by asserting the

DPSLP# signal, while it is in the Quick Start state. Note that either one of the methods can be used to

enter Deep Sleep but not both at the same time. When BCLK is stopped, it must obey the DC levels

specified in Table 23.

The processor will return to the Quick Start state from the Deep Sleep state when the BCLK input is

restarted or the DPSLP# signal is d easserted. Due to the PLL lock latency, there is a delay of up to 30

µsec after the clocks have started before this state transition happens. PICCLK may be removed in the

Deep Sleep state. PICCLK should be designed to turn on when BCLK turns on or DPSLP# is deasserted

when transitioning out of the Deep Sleep state.

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16 Datasheet 298517-001

Table 2. Clock State Characteristics

Clock State Exit Latency Snooping? System Uses

Normal N/A Yes Normal program ex ecution

Auto Halt 10 µsec Yes S/W controlled entry i dl e mode

Quick Start Through snoop, to

HALT/Grant Snoop state:

immediate

Through STPCLK#, to

Normal stat e: 10 µsec

Yes

H/W controlled entry/exit mobile throttling

HALT/Grant

Snoop A few bus clocks aft er

snoop completion Yes Supports snooping in the low power states

Deep Sleep 30 µsec No H/W controlled entry/exit mobile powered-on

suspend support

2.2.7 Operating System Implications of Low-power States

The time-stamp counter and the performance monitor counters are not guaranteed to count in the Quick

Start state. The local APIC timer and performance monitor counter interrupts should be disabled before

entering the Deep Sleep state or the resultin g behavior will be unpredictable.

2.3 AGTL Signals

The Mobile Intel Celeron Processor system bus signals use a variation of the low-voltage swing GTL

signal ing t echnology. T he AGTL syste m bus depends on inci dent wave switc hing and uses flight time

for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel recommends analog

signal simulation of the system bus including trace lengths. Contact your field sales representative to

receive the IBIS models for the Mobile Intel Celeron Processor (these are the same models as the Mobile

Pentium III Processor-M).

The AGTL system bus of the Mobile Intel Celeron Processor is designed to support high-speed data

transfers with multiple loads on a long bus that behaves like a transmission line. Ho wever, in mobile

systems the system bus only has two loads (the processor and the chipset) and the bus traces are short. It

is possible to change t he layout and termination of the system bus to take advantage of the mobile

environment using the same AGT L I/O buffers. This ter minatio n is provided on the processor core

(except for the RESET # signal).

2.4 Mobile Intel Celeron Processor CPUID

When the CPUID version information is loaded with EAX=01H, the EAX and EBX registers contain the

values shown in Table 3. After a power-on RESET, the EDX register contains the processor version

information (type, family, model, stepping). Table 4 shows the CPUID Cache and TLB descriptor

values after the L2 cache is initialized. See Intel® Processor Identification and the CPUID Instruction

Application Note AP-485 for further information.

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298517-001 Datasheet 17

Table 3. Mobile Intel Celeron Processor CPUID

EAX[31:0] EBX[7:0]

Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] Brand ID

X 0 6 B X 03

Table 4. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors

Cache and TLB Descriptors 01H, 02H, 03H, 04H, 08H, 0CH, 83H

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18 Datasheet 298517-001

3. Electrical Specifications

3.1 Processor System Signals

Table 5 lists the pro c essor s ystem sig na ls by type. All AGTL signals are synchrono us with the BCLK

signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS input signals

can be applied asynchronously.

Table 5. System Signal Groups

Group Name Signals

AGTL Input BPRI#, DEFER#, RESET#, RSP#

AGTL Output PRDY#

AGTL I/O A[35:3]#, ADS#, AERR #, AP[1:0]# , BER R # , BINIT#, BNR# , BP[3:2]#, BPM[1 :0]#,

BREQ0#, D[ 63:0]#, DBSY#, DEP[7: 0]#, DRDY#, HIT#, HIT M #, LOCK#, REQ[ 4:0] #, RP#,

RS[2:0]#, TRDY#

1.5V CMOS Input A20M#, DPSLP#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#,

STPCLK#

1.8V CMOS Input PWRGOOD

1.5V Open Drain Output FERR#, IE RR#

3.3V Open Drain Output BSEL[1:0], VID[4: 0]

1.25V input VTTPWRGD

2.5V Clock Input BCLK

APIC Clock PICCLK

APIC I/O PICD[1:0]

Thermal Diode THERMDC, THERMDA

TAP Input TCK, TDI, TMS, TRST#

TAP Output TDO

Power/Other CLKREF , CMOSREF, EDGECTRLP, NC, NCTRL, PLL1, PLL2, RTTIMPEDP, VCC, VCCT,

VREF, VSS,

NOTES:

1. VCC is the power supply for the core logic.

2. PLL1 and PLL2 are power/ground for the PLL analog section. See Section 3.2.2 for details.

3. VCCT is the power supply for the system bus buffers.

4. VREF is the voltage reference for the AGTL input buffers.

5. VSS is system ground.

The APIC data and TAP outputs are Open-drain and should be pulled up to 1.5V using resistors with the

values shown in Table 6. If Open-drain drivers are used for input signals, then they should also be pulled

up to the appropriate voltage using resistors with the val ues shown in Table 6.

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298517-001 Datasheet 19

Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals

Recommended

Resistor Value (Ω

ΩΩ

Ω) Mobile Intel Celeron Processor Signal 1, 2

10 pull-down BREQ0#3

14 pull-up NCTRL

39 pull-up TMS

39 pull-down TCK

56.2 pull-up PRDY#, RESET #4

56.2 pull-down RTTIMPEDP

110 pull-down EDGECTRLP

150 pull-up PICD[1:0] , TDO

200-300 pull-up PREQ#, TDI

500 pull-down TRST#

1K pull-up BSEL[1: 0], TESTHI, VID[ 4:0], VTTPWRGD

1K pull-down TESTLO

1.5k pull-up FERR#, IERR#, PWRGOOD

3K pull-up FLUSH#

Additional Pullup/Pulldown Resistor Recommendations5

270 pull-up SMI#

680 pull-up STPCLK#

1.5k pull-up A20M#, DPSLP#, I NIT#, IGNNE#, LINT0/I NTR, LI NT1/NMI

NOTES:

1. The recommendations above are only for signal s that are being used. These recommendations are maximum

values only; stronger pull -ups may be used. Pull-ups for the signals driven by the chipset should not violate the

chipset specification. Refer to Section 3.1. 4 for the required pul l -up or pull-down resis tors for signals that are not

being used.

2. Open-drain signals must never violate the undershoot speci fication in Section 4.3. Use stronger pull -ups if there

is too much undershoot.

3. A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.

4. A 56.2Ω 1% terminating resistor connected to VCCT is required.

5. These pull up recommendations apply to syst ems on which these signals are not actively pulled high such as

those utilizing the 82443MX chipset.

3.1.1 Power Sequencing Requirements

Unlike the Mobile Intel Celero n Pr ocessor (0.18µ), the Mobile Intel Celeron Processor (0.13µ) does

have specific power sequencing requirements. The power on sequencing and timings are shown in

Figure 10 and Table 19. Power down timing requirements are shown in Figure 11, Figure 12, and

Table 19. The VCC power plane must not rise too fast. At least 200 µsec (TR) must pass from the time

that VCC is at 10% of its no minal value until the time that VCC is at 90% of its nominal value. For more

details, Contact your Inte l Field Sales Representa tive.

3.1.2 Test Access Port (TAP) Connection

The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage

levels supported by the TAP interface, Intel recommends that the Mobile Intel Celeron Processor and the

other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any devices with

3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer should be used to reduce the

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20 Datasheet 298517-001

TDO output voltage of the last 3.3/5.0V device down to the 1.5V range that the Mobile Intel Celeron

Processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level.

A Debug Port and connector may be placed at the start and end of the JTAG chain containing the

processor, wi th TDI to the first component coming from the Debug Port and TDO from the last

component going to the Debug Port. There are no requirements for placing the Mobile Intel Celeron

Processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP

signals.

3.1.3 Catastr ophi c Thermal Protection

The Mobile Intel Celeron Processor does not support catastrophic thermal protection or the

THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the system

against excessive temperatures. If the external thermal sensor detects a processor junction temperature of

101 °C (maximum), both the VCC and VCCT supplies to the processor must be reduced to at least 50% of

the nominal values within 500 ms and recommended to be turned off completely within 1s to prevent

damage to the processor. Processor temperature must be monitored in all states including low power

states.

3.1.4 Unused Signals

All signals named NC must be unconnected. Unused AGTL inputs, outputs and bi-directional signals

should be unconnected. Unused CMOS active low inputs should be connected to 1.5V and unused active

high inputs should be connected to VSS. Unused Ope n-dr ain outputs should be unconnected. When tying

any signal to po wer or ground, a resistor will allow for system testability. For unused signals, Intel

suggests that 1.5- kΩ resistors are used for pull-ups and 1.0-kΩ resisto rs are use d for pull-downs.

PICCLK must be driven with a clock that meets specification and the PICD[1:0] signals must be pulled

up separately to 1.5V with 150-Ω resistors, even if the local APIC is not used.

If the TAP signals are not used then the inputs should be pulled to ground with 1-kΩ resistors and TDO

should be left unconnected.

3.1.5 Signal State in Low-power States

3.1.5.1 System Bus Signals

All of the system bus sig nals have AGTL input, output, or input/output drivers. Except when servicing

snoops, the system bus signals are tri-stated and pulled up by the termination resistors. Snoops are not

permitted in the Deep Sleep state.

3.1.5.2 CMOS and Open-drain Signals

The CMOS input signals are allowed to be in either the logic high or low state when the processor is in a

low-power state. In the Auto Halt state these signals are allowed to toggle. These input buffers have no

internal pull-up or pull-down resistors and system logic can use CMOS or Open-drain drivers to drive

them.

The Open-drain output signals have open drain drivers and external pull-up resistors are required. One of

the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the

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298517-001 Datasheet 21

processor is functioning normally. The FERR# output can be either tri-stated or driven to VSS whe n the

processor is in a low-power state depending on the condition of the floating-point unit. Since this signal

is a DC current path when it is dr iven to VSS, Intel recommends that the software clears or masks any

floating-point error condition before putting the processor in to the Deep Sleep state.

3.1.5.3 Other Signals

The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep state.

The APIC clock (PICCLK) must be driven whenever BCLK is driven. Otherwise, it is permitted to turn

off PICCLK b y hold ing it at VSS. BCLK should obey the DC levels in Table 23.

In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus messages.

These signals are required to be tri-stated and pulled-up when the processor is in the Quick Start or Deep

Sleep states.

3.2 Power Supply Requirements

3.2.1 Decoupling Guidelines

The Mobile Intel Celeron Pr o cessor in Micro-FCBGA package has six 0. 6 8-µF capacitors on VCC and

two 0.68-µF capacitors on VCCT. In addition to the package capacitors, sufficient board level capacitors

are also necessary for power supply decoupling. These guidelines are as follows:

• High and Mid Frequency VCC decoupling – Place twenty-four 0.22-µF 0603 capacitors directly

under the package on the solder side of the motherboard using at least two vias per capacitor

node. Ten 10-µF X7 6.3V 1206-size ceramic capacitors should be placed around the package

periphery near the balls. Trace lengths to the vias should be designed to minimize inductance.

Avoid bending traces to minimize ESL.

• High and Mid Frequency VCCT decoupling – Place ten 1-µF X7R 0603 ceramic capacitors close to

the package. Via and trace guidelines are the same as above.

• Bulk VCC decoupling – Minimum of 1200 µF capacitance with Equivalent Series Resistance

(ESR) less than or eq ual to 3.5 mΩ.

• Bulk VCCT decoupling – Platform dependent but recommendation is minimum of 660 µF with

ESR less than or equal to 7 mΩ.

Please refer to the appropriate platform design guidelines for bulk decoupling recommendations.

3.2.2 Voltage Planes

All VCC and VSS pins/balls must be connected to the appropriate voltage plane. All VCCT and VREF

pins/balls must be connected to the appropriate traces on the system electronics. In addition to the main

VCC, VCCT, and VSS power supply signals, PLL1 and PLL2 provide analog decoupling to the PLL

section. PLL1 and PLL2 should be connected according to Figure 2. Do not c onnect PLL2 directly to

VSS. Appendix A contains the RLC filter specification.

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22 Datasheet 298517-001

Figure 2. PLL RLC Filter

PLL1

PLL2

VCCT

V0027-01

3.2.3 Voltage Identification

There are five voltage identification balls/pins on the Mobile Intel Celeron Processor. T hese si gnals can

be used to support automatic selection of VCC voltages. They are needed to cleanly support voltage

specification variations on current and future processors. VID[4:0] are defined in Table 7. The voltages

specified in the VID table are the Battery Optimized Mode VCC volt ages. The V ID[4:0] signals ar e open

drain on the processor and need pullup resistors to 3.3V on the motherboard. Please refer to the mobile

VR guidelines provided by Intel for additional information.

Table 7. Mobile Intel Celeron Processor VID Values

VID[4:0] VCC (V) VID[4:0] VCC (V) VID[4:0] VCC (V) VID[4:0] VCC (V)

00000 1.750 01000 1.350 10000 0.975 11000 0.775

00001 1.700 01001 1.300 10001 0.950 11001 0.750

00010 1.650 01010 1.250 10010 0.925 11010 0.725

00011 1.600 01011 1.200 10011 0.900 11011 0.700

00100 1.550 01100 1.150 10100 0.875 11100 0.675

00101 1.500 01101 1.100 10101 0.850 11101 0.650

00110 1.450 01110 1.050 10110 0.825 11110 0.625

00111 1.400 01111 1.000 10111 0.800 11111 0.600

Figure 3 shows the system level connections for the VT TPWRGD signal. Please refer to the appro priate

VR and system level guidelines provided by Intel for more details.

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298517-001 Datasheet 23

Figure 3. VTTPWRGD System-Level Connections

Voltage Regulator Processor

Clock Generator

Vcct

Vttpwrgd

(output) Vttpwrgd

(input)

Vttpwrgd#

(input)

Vcct

10k

Vcct

3.3V

100k

1.2V to 3.3V Level Shifter

3.3 System Bus Clock and Processor Clocking

The BCLK clock input directly controls the operating speed of the system bus interface. All system bus

timing parameters are specified with respect to the rising edge of the BCLK input. The Mobile Intel

Celeron Processor core frequency is a multiple of the BCLK frequency. The processor core frequency is

configur ed during manufacturing. The confi gured bus r atio i s visible to software i n the Po we r-on

configuration register. See Section 7.2 for d etails.

Multiplying the bus clock frequency is necessary to increase performance while allowing for easier

distribution of si gnals within the system. Clock multiplication within the processor is provided by the

internal Phase Lock Loop (PLL), which requires a constant frequency BCLK, input. During Reset or on

exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase of BCLK.

This time is called the PLL lo ck latency, which is specified in Section 3.6, AC timin g parameters T18

and T47.

3.4 Maximum Ratings

Table 8 contains the Mobile Intel Celeron Processor stress ratings. Functional operation at the abso lute

maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock

while subjected to these conditions. Functio nal operating conditions are provided in the AC and DC

tables. Extended exposure to the maximum ratings ma y affect device reliability. Furthermore, although

the processor contains protective circuitry to resist damage from static electric discharge, one should

always take precautions to avoid high static voltages or electric fields.

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24 Datasheet 298517-001

Table 8. Mobile Intel Celeron Processor Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

TStorage Storage Temperature –40 85 °C Note 1

VCC(Abs) Supply Voltage wi th respect to VSS –0.5 1.75 V

VCCT Syste m Bu s Buffer Vo lta g e with re sp e c t to VSS –0.3 1.75 V

VIN GTL System Bus Buffer DC Input Voltage with respect to VSS –0.3 1.75 V Notes 2, 3

VIN125 1.25V Buffer DC Input Voltage with respect to VSS –0.3 1.75 V Note 4

VIN15 1.5V Buffer DC Input Voltage with respect to VSS –0.3 2.0 V Note 5

VIN18 1.8V Buffer DC Input Voltage with respect to VSS –0.3 2.0 V Note 6

VIN20 2.0V Buffer DC Input Voltage with respect to VSS –0.3 2.4 V Note 7

VIN25 2.5V Buffer DC Input Voltage with respect to VSS –0.3 3.3 V Note 9

VINVID VID ball/pin DC Input Voltage with respect to VSS — 3.465 V Note 8

IVID VID Current -0.3 3.6 mA Note 8

NOTES:

1. The shipping container is only rated for 65°C.

2. Parameter applies to the AGTL signal groups only. Compliance with both VIN GTL specific ations is required.

3. The voltage on the AGTL signals must never be below –0.3 or above 1.75V with respect to ground.

4. Parameter appli es to CLKREF, TESTHI, VTTPWRGD signals .

5. Parameter applies to CMOS, Open-drain, APIC, TESTLO and TAP bus signal groups only.

6. Parameter applies to PWRGOOD signal.

7. Parameter applies to PICCLK signal.

8. Parameter applies to each VID pin/ball individual ly.

9. Parameter applies to BCLK signal in Single Ended Clocking Mode.

3.5 DC Specifications

Table 9 t hrough Tabl e 14 l ist the DC specificatio ns for the Mobil e Intel Celeron Pr ocessor.

Specifications are valid only while meeting specifications for the junction temperature, clock frequency,

and input voltages. The junction temperature range for all DC specifications is 0°C to 100°C. Care

should be taken to read all notes associated with each parameter. Unlike the mobile Intel Pentium III

processor, the Vcc tolerances for the Mobile Intel Celeron Processor are not specified as a percentage of

nominal. The tolerances are instead specified in the form of load lines for the static and transient cases

in Table 10 and Table 11. Illustration of the load lines is shown in Figure 4 and Figure 5.

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298517-001 Datasheet 25

Table 9. Power Specifications for Mobile Intel Celeron Processor1

Symbol Parameter Min Typ Max Unit Notes

VCC Transient VCC for core logic

1.15

Notes 10, 11

VCC,DC Static VCC for core logic

1.15

Notes 10, 11

VCCT V

CC for System Bus Buffers, Transient tolerance 1. 138 1.25 1.362 V ± 9%, Notes 8,11

VCCT,DC V

CC for System Bus Buffers, Static tolerance 1.188 1.25 1.312 V ±5%, Notes 2,11

ICC

Current for VCC at core frequency

650 MHz & 1.15V

10.52 A Note 4

ICCT Current for VCCT 2.7 A Notes 3, 4

ICC,AH Processor Aut o Halt current at

1.15V

5.42 A Note 4

ICC,QS Processor Quick Start current at

1.15V

5.16 A Note 4

ICC,DSLP Processor Deep Sleep Leakage current at

1.15V

4.79 A Note 4

ILVID VID leakage current 0.5 mA Note 9

dICC/dt VCC power supply current slew rate 400 A/µs Notes 6, 7

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Processors will comply

with the ICCx,max specification for the current mode of operation.

2. Static volt age regul ation i ncludes: DC output initial voltage set point adjust, output ripple and noise, temperature

and warm up.

3. ICCT is the current supply for the system bus buffers, including the on-die termination.

4. ICCx,max specifications are specified at VCC static (typical) derived from the tolerances in Table 10 through Table

15, VCCT,max, Tjmax, and under maximum signal loading conditions.

5. Maximum ICC,DPRSLP specified at VCC = 0.85V.

6. Based on simulations and averaged over the duration of any change in current. Use to compute the maximum

inductance and react i on time of the voltage regulator. This parameter is not tested.

7. Maximum values speci fied by design/characteri zation at nominal VCC and VCCT.

8. VCCx must be within this range under all operating conditions, including maximum current transients . VCCx must

return to within the static voltage specification, VCCx,DC, within 100 µs after a transient event.

9. VID leakage current is < 100 uA for VID voltages under 3.0V.

10. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification

shown in Table 10 through Table 13.

11. Voltages are measured at the package ball on the Micro-FCBGA part.

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Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.15V)

0.950

1.000

1.050

1.100

1.150

1.200

1.250

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0

ICC

Transient Maximum

Static Maximum

Static Typical

Sta t ic Min im um

Transient Minimum

Figure 5. Illustration of Deep Sleep VCC Stat ic and T ran sient To lerances ( VI D Settin g = 1. 15 V)

0.980

1.000

1.020

1.040

1.060

1.080

1.100

1.120

1.140

1.160

1.180

0 1 2 3 4 5 6

ICC

Transient Maximum

Static Maximum

Static Typical

Static Minimum

Transient Minimum

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298517-001 Datasheet 27

Table 10. VCC Tolerances for the Low Voltage Mobile Intel Celeron Processor: VID = 1.15V

ICC (A) VCC (V)

Static Transient

Typ Min Max Min Max

0.0 1.150 1.125 1.175 1.105 1.195

1.0 1.146 1.121 1.171 1.101 1.191

2.0 1.142 1.117 1.167 1.097 1.187

3.0 1.138 1.113 1.163 1.093 1.183

4.0 1.134 1.109 1.159 1.089 1.179

5.0 1.130 1.105 1.155 1.085 1.175

6.0 1.126 1.101 1.151 1.081 1.171

7.0 1.122 1.097 1.147 1.077 1.167

8.0 1.118 1.093 1.143 1.073 1.163

9.0 1.114 1.089 1.139 1.069 1.159

10.0 1.110 1.085 1.135 1.065 1.155

11.0 1.106 1.081 1.131 1.061 1.151

12.0 1.102 1.077 1.127 1.057 1.147

13.0 1.098 1.073 1.123 1.053 1.143

14.0 1.094 1.069 1.119 1.049 1.139

15.0 1.090 1.065 1.115 1.045 1.135

Table 11. VCC Tolerances for the Low Voltage Mobile Intel Celeron Processor in the Deep Sleep

State: VID = 1.15V

ICC (A) VCC (V)

Static Transient

Typ Min Max Min Max

0.0 1.114 1.089 1.139 1.069 1.159

1.0 1.110 1.085 1.135 1.065 1.155

2.0 1.106 1.081 1.131 1.061 1.151

3.0 1.102 1.077 1.127 1.057 1.147

4.0 1.098 1.073 1.123 1.053 1.143

5.0 1.094 1.069 1.119 1.049 1.139

6.0 1.090 1.065 1.115 1.045 1.135

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28 Datasheet 298517-001

Table 12. AGTL Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

VIL Input Low Voltage -0.15 VREF-0.2 V

VIH Input High Voltage VREF+0.2 VCCT V See VCCT,max in Table 17

VOH Output High Voltage — — V See VCCT,max in Table 17

RON Output Low Drive Strength 16.67 Ω Note 2

IL Leakage Current f or Inputs, Out puts and I/Os 100 µA Note 1

NOTES:

1. Specificat i on applies to leakage high only, for pins with on die RTT, (0 < VIN/OUT ≤ VCCT).

2. Refer to IBIS models for I/V characteristics.

Table 13. AGTL Bus DC Specifications

Symbol Parameter Min Typ Max Unit Notes

VCCT Bus Termination Voltage 1.25 V Note 1

VREF Input Reference Voltage 2/3VCCT – 2% 2/3VCCT 2/3VCCT + 2% V ±2%, Note 2

RTT Bus Termination Strength 50 56 65 Ω On-die RTT, Note 3

NOTES:

1. P l ease refer to Table 9 for minimum and maximum values.

2. VREF should be created from VCCT by a volt age div i der.

3. The RES E T # signal does not hav e an on-die RTT. It requires an off-die 56.2Ω ±1% terminating resistor

connect ed to VCCT.

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Table 14. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

VIL15 Input Low Voltage, 1.5V CMOS –0.15 VCMOSREFmin

– 300 mV V

VIL18 Input Low Voltage, 1.8V CMOS –0. 36 0.36 V Notes 1, 2

VIH15 Input High Voltage, 1.5V CMOS V CMOSREFmax +

250 mV 2.0 V Note 10

VIH15PICD Input Hi gh Voltage, 1.5V PICD[1:0] VCMOSREFmax +

200 mV 2.0 V Note 11

VIH18 Input High Voltage, 1.8V CMOS 1. 44 2.0 V Notes 1, 2

VOH15 Output High Voltage, 1.5V CMOS N/ A 1.615 V All outputs are Open-drain

VOH33 Output High Voltage, 3.3V signals 2.0 3.465 V 3.3V + 5%

VOL33 Output Low Voltage, 3.3V signals 0.8 V

VOL Output Low Voltage 0.3 V Note 8

VCMOSREF CMOSREF Voltage 0.90 1.10 V Note 4

VCLKREF CLKREF Voltage 1.187 1.312 V Note 9

VILVTTPWR Input Low Voltage, VTTPWRGD 0.4 V Note 7

VIHVTTPWR Input High Voltage, VTTPWRGD 1.0 V Note 7

RON 30 Ω Note 3

IOL Output Low Current 10 mA Note 6

IL Leakage Current f or Inputs, Out puts

and I/Os ±100

µA Note 5

NOTES:

1. Parameter applies to the PWRGOOD signal only.

2. VILx,min and VIHx ,max only apply when BCLK and PICCLK are stopped. PICCLK should be stopped in the low state.

See Table 23 for DC levels when BCLK is stopped.

3. Measured at 9 mA.

4. VCMOSREF should be created from a stable 1. 5V supply usi ng a voltage divider. It must track the voltage supply

to maintain noise immunity. The same 1.5V supply should be used to power the chipset CMOS I/O buffers that

drive these signals.

5. (0 ≤ VIN/OUT ≤ VIHx,max).

6. Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL,max cannot

be guaranteed if this specif ic ation is exceeded.

7. Parameter appl i es to VTTPWRGD signal only.

8. Applies t o non-AGTL signals except BCLK, PWRGOOD, PI CCLK, BSEL[1:0], VID[4:0].

9. ±5% DC tolerance. CLKREF must be generated from the 2.5V supply used to generate the BCLK signal. AC

Tolerance must be less than -40dB @ 1 MHz.

10. Applies to all TAP and CMOS signals (not to APIC signals).

11. Applies to PICD[ 1:0].

3.6 AC Specifications

3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC

Specifications

All system bus AC specifications for the AGTL signal group are relative to the rising edge of the BCLK

input. All AGTL timings are r eferenced to VREF for bo th “0” and “1” logic levels unless otherwise

specified. All APIC, TAP, CMOS, and Op en-drain signals except PWRGOOD are referenced to 1. 0 V.

All minimum and maximum specifications are at points within the power supply ranges shown in Tables

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30 Datasheet 298517-001

9-13 and junction temperatur es ( Tj) in the range 0°C to 100°C. Tj must be less than or equal to 100°C

for all functional processor states.

Table 15. System Bus Clock AC Specifications1

Symbol Parameter Min Typ Max Unit Figure Notes

System Bus Frequency 100 MHz

T1S1 BCLK Period 10 ns 6 Note 2

T1S1abs BCLK Period – Instantaneous

Minimum 9.75 ns Note 2

T2S1 BCLK Period Stability ±250 ps Notes 2, 3, 4

T3S1 B CLK Hi gh Time 2.70 ns 6 at>2.0V

T4S1 BCLK Low Time 2.45 ns 6 at<0.5V

T5S1 BCLK Rise Time 0.4 1.6 ns 6 Note 5

T6S1 BCLK Fall Time 0.4 1.6 ns 6 Note 5

NOTES:

1. All AC timings for AGTL and CMOS signals are referenc ed to the BCLK rising edge at 1.25V.

2. Period, jitter, skew and offset measured at 1.25V.

3. Not 100% tested. Spec ifi ed by design/ characterizati on.

4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be account ed for as a

component of BCLK skew between devices.

5. Measured between 0.5V and 2.0V

Table 16. Valid Mobile Intel Celeron Processor Frequencies

BCLK Frequency

(MHz) Frequenc y Multiplier Core Frequency

(MHz) Power-on Configuration

bits [27,25:22]

100 6.5 650 0, 1111

NOTE: While other combinations of bus and core frequencies are defined, operation at frequenc i es other t han thos e

listed above will not be validated by Intel and are not guaranteed. The frequency multiplier is programmed

into the process or when it is manufactured and it cannot be changed.

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298517-001 Datasheet 31

Table 17. AGTL Signal Groups AC Specifications1

RTT = 56Ω internally terminated to VCCT; VREF = 2/3VCCT; load = 50 ohms

Symbol Parameter Min Max Unit Figure Notes

T7 A GTL Output Vali d Delay 0.40 3.25 ns 9

T8 A GTL Input Setup Time 1.30 ns 10 Notes 2, 3, 6

T9 A GTL Input Hold Time 1 ns 10 Note 4

T10 RE SET# Pulse Width 1 ms 11,12 Note 5

NOTES:

1. All AC timings for AGTL signals are referenced to the BCLK rising edge at 1.25V. All AGTL signals are

referenced at VREF. Unless ot her spec if i ed, all timi ngs appl y to 100-MHz bus frequency.

2. RESET# can be asserted (active) asynchronously, but must be deasserted synchronous l y.

3. Specification is for a minimum 0.40V swing from Vref-200 mV to Vref+200 mV.

4. Specification is for a maximum 0.8V swing from Vcct-0.8V to Vcct.

5. After VCC, VCCT, and BCLK become stable and PWRGOOD is asserted.

6. Applies t o all processors supporting 100 MHz bus clock frequency.

Table 18. CMOS and Open-drain Signal Groups A C Specifications1, 2

Symbol Parameter Min Max Unit Figure Notes

T14 1.5V Input Pulse Width, except PWRGOOD and

LINT[1:0] 2 BCLKs 9 A ct ive and i nactive

states

T14B LINT[1:0] Input Pulse Width 6 BCLKs 9 Not e 3

T15 PWRGOOD Inactive Pulse Width 2 µs 12 Note 4, 5

NOTES:

1. All AC timings for CMOS and Open-drain signals are ref erenced to the rising edge of BCLK at 1.25V. All

CMOS and Open-drain signals are referenced at 1.0V.

2. Minimum output pulse width on CMOS outputs is 2 BCLKs.

3. This specification onl y appl i es when the APIC is enabled and the LINT1 or LINT0 signal is configured as an

edge triggered int errupt with fixed delivery, otherwise specification T14 applies.

4. When driven inactive, or aft er VCC, VCCT, and BCLK become stable. PWRGOOD must remain below VIL18,MAX

until all the voltage pl anes meet the voltage t ol erance spec ific at i ons in Tables 9-11 and BCLK has met the AC

specificat i ons in Table 23 for at least 2 µs. PWRGOOD must rise error-free and monotonically to 1.8V.

5. If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD

Inactive P ulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.

PWRGOOD must still remain below VIL18,max until all the voltage pl anes m eet the volt age tole rance

specificat i ons.

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32 Datasheet 298517-001

Table 19. Reset Configuration AC Specifications and Power On/Power Down Timings

Symbol Parameter Min Typ Max Unit Figure Notes

T16 Reset Configuration Signals (A[15:5]#,

BREQ0# , FLU SH #, INIT#, PICD0 ) Setup

Time

4 BCLKs

Before deassertion of

RESET#

T17 Reset Configuration Signals (A[15:5]#,

BREQ0#, F LUSH#, INIT#, PICD0) Hold Time 2 20 BCLKs

11 After clock that

deasserts RESET#

T18 RESET#/PWRGOOD Setup Time 1 ms 12 Before deassertion of

RESET# 1

T18A VCCT to VTTPWRGD Setup Time 1 ms 12

T18B VCC to PWRGOOD Setup Time 10 ms 12

T18C BSEL, VID valid time before VTTPWRGD

assertion 1 µs 12

T18D RESET# inactive to Valid Outputs 1 BCLK 11

T18E RESET# inactive to Drive Signals 4 BCLKs 11

T19A Time from VCC(nominal)-12% to PWRGOOD

low 0 ns 13 VCC(nominal) is the VID

voltage setting

T19B All outputs valid after PWRGOOD low 0 ns 13

T19C All inputs required valid after PWRGOOD low 0 ns 13

T20A Ti m e from VCCT-12% to VTTPWRGD low 0 ns 14

T20B All outputs valid after VTTPWRGD low 0 ns 14

T20C All inputs required valid after VTTPWRGD low 0 ns 14

T20D VID, BSEL signals valid after VTTPWRGD

low 0 ns 14

NOTE: At least 1 ms must pass after PWRGOOD rises above VIH18min and BCLK meets the AC timing specification

until RESET# may be deasserted.

Table 20. APIC Bus Signal AC Specifications 1

Symbol Parameter Min Max Unit Figure Notes

T21 PICCLK Frequency 2 33.3 MHz Note 2

T22 PICCLK Period 30 500 ns 6

T23 PI CCLK High Time 10.5 ns 6 at>1.6V

T24 PI CCLK Low Time 10.5 ns 6 at<0.4V

T25 PI CCLK Rise Time 0.25 3.0 ns 6 (0.4V – 1.6V)

T26 PI CCLK Fall Time 0.25 3.0 ns 6 (1.6V – 0.4V)

T27 PICD[1:0] Setup Time 8.0 ns 9 Note 3

T28 PI CD[ 1:0] Hol d Time 2.5 ns 9 Note 3

T29 PICD[1:0] Valid Delay (Rising

Edge)

PICD[1:0] Valid Delay (Falling

Edge)

1.5

8.7

12.0

ns 8 Notes 3, 4

NOTES:

1. All AC timings for APIC signals are referenc ed to t he PICCLK ris i ng edge at 1.0V. All CMOS signals are

referenced at 1.0V.

2. The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset Referenced to PICCLK Rising Edge.

3. For Open-drain signals, Valid Del ay is synonymous with Float Del ay.

4. Valid delay timings for these signals are specif i ed into 150Ω to 1.5V and 0 pF of external load. For real system

timings these specifications must be derated for external capacitance at 105 ps/pF.

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298517-001 Datasheet 33

Table 21. TAP Signal AC Specifications1

Symbol Parameter Min Max Unit Figure Notes

T30 TCK Frequency — 16.67 MHz

T31 TCK Period 60 — ns 6

T32 TCK High Time 25.0 ns 6 ≥ VCMOSREF+0.2V, Note 2

T33 TCK Low Time 25.0 ns 6 ≤ VCMOSREF-0.2V, Note 2

T34 TCK Rise Time 5.0 ns 6 (VCMOSREF-0.2V) –

(VCMOSREF+0.2V),

Notes 2, 3

T35 TCK Fall Time 5.0 ns 6 (VCMOSREF+0.2V) –

(VCMOSREF-0.2V) ,

Notes 2, 3

T36 TRST# Pulse Width 40.0 ns 16 Asynchronous, Note 2

T37 TDI, TMS Setup Time 5.0 ns 15 Note 4

T38 TDI, TMS Hold Time 14.0 ns 15 Note 4

T39 TDO Valid Delay 1.0 10.0 ns 15 Notes 5, 6

T40 TDO Float Delay 25.0 ns 15 Not es 2, 5, 6

T41 All Non-Test Outputs Valid Delay 2.0 25.0 ns 15 Notes 5, 7, 8

T42 All Non-Test Outputs Float Delay 25.0 ns 15 Notes 2, 5, 7, 8

T43 All Non-Test Inputs Set up Time 5.0 ns 15 Notes 4, 7, 8

T44 All Non-Test Inputs Hold Time 13.0 ns 15 Notes 4, 7, 8

NOTES:

1. All AC timings for TAP signals are referenced to the TCK rising edge at 1.0V. All TAP and CMOS signals are

referenced at 1.0V.

2. Not 100% tested. Spec ifi ed by design/ characterizati on.

3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.

4. Referenced t o TCK rising edge.

5. Referenced to TCK falling edge.

6. Valid delay timing f or this signal is specif i ed into 150Ω terminated to 1.5V and 0 pF of external load. For real

system timings these spec ific at i ons must be derated for external capacitance at 105 ps/pF.

7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and TMS).

These timings corres pond to the response of these signals due t o boundary scan operat i ons.

8. During Debug Port operat i on use the normal specifi ed timings rat her than t he TAP signal timings.

Table 22. Quick Start/Deep Sleep AC Specificatio ns1

Symbol Parameter Min Max Unit Figure Notes

T45 Quick Start Cycle Completi on to Clock St op or

DPSLP# assertion 100 BCLKs 17, 18

T46 Quick Start Cycle Completi on to Input Signals Stable 0 µs 17, 18

T47 Deep S l eep PLL Lock Lat ency 0 30 µs 17, 18 Note 2

T48 S T P CLK# Hold Time from PLL Lock 0 ns 17, 18

T49 I nput Signal Hold Time from STPCLK# Deassertion 8 BCLKs 17, 18

NOTES:

1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.

2. The BCLK Settling Time specification (T60) appli es to Deep Sleep state exit under all conditions.

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34 Datasheet 298517-001

Figure 6. BCLK/PICCLK/TCK Generic Clock Timing Waveform

CLK VH

VLVTRIP

D0003-01

NOTES: Tr=T5S, T5S1 , T3 4, T2 5 (Ri se Ti m e)

Tf=T6S, T6S1 , T3 5, T2 6 (Fall Time)

Th=T3S, T3S 1, T3 2, T2 3 (Hi gh Ti me )

Tl=T4S, T4S1, T3 3, T24 (Low Ti me )

Tp=T1S, T1S1, T31, T22 (Period)

VTRIP=1.25V for BCLK;1.0V for PICCLK; 1.0V for TCK

VL=0.5V for BCLK; 0.4V for PICCLK; (VCMOSREF-0.2V) for TCK

VH= 2.0V for BCLK; 1.6V for PICCLK; (VCMOSREF+0.2V) for TCK

Figure 7. Valid Delay Timings

CLK

Signal

TXTx

TPW

V Valid Valid

D0004-00

Vc Vc

NOTES: Tx = T7, T11, T29 (Valid Delay)

Tpw = T14, T14B (Pulse Width)

V = VREF for AGTL signal group; 1.0V for CMOS, Open-drain, APIC, and TAP signal groups

Vc = 1.25V

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298517-001 Datasheet 35

Figure 8. Setup and Hold Timings

Signal VVali

D0005-0

NOTES: Ts = T8, T27 (Setup Time)

Th = T9, T28 (Hold Time)

V = VREF for AGTL signals; 1.0V for CMOS, APIC, and TAP signals

Vc = 1.25V

Figure 9. Cold/Warm Reset and Configuration Timings

BCLK

RESET#

D0006-02

Configuration

(A[15:5 ], BREQ0#,

FLUSH#, INIT#,

PICD0)

Valid

PICD[1:0]

AGTL/non-AGTL

outputs

Non-configuration

inputs

Valid

Active

NOTES: Tt = T9 (AGTL Input Hold Time)

Tu = T8 (AGTL Input Setup Time)

Tv = T10 (RESET# Pulse Width)

Tw= T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)

Tx = T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)

Ty = T18D (RESET# inactive to Valid Outputs)

Tz = T18E (RESET# inactive to Drive Signals)

Vc= 1.25V

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36 Datasheet 298517-001

Figure 10. Power-on Sequence and Reset Timings

VCCT

Valid

VTTPWRGD

VID[4:0]/

BSEL[1:0]

CMOSREF/

CLKREF/VREF

PWRGOOD

RESET#

BCLK

VIH18,min

VIL18,max

VIHVTTPWR,min

VILVTTPWR,max

VCC

V0040-00

NOTES: Ta = T15 (PWRGOOD Inactive Pulse Width)

Tb = T18 (RESET#/PWRGOOD Setup Time)

Tc = T18B (Setup time from VCC valid until PWRGOOD assertion)

Td = T18A (Setup time from VCCT valid to VTTPWRGD assertion)

Te = T18C(VID, BSEL valid time before VTTPWRGD assertion)

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298517-001 Datasheet 37

Figure 11. Power Down Sequencing and Timings (VCC Leading)

VTTPWRGD

BCLK

V0044-00

VCCT, VREF

VCCMOS,

CMOSREF,

CLKREF

VID[4:0]

BSEL[1:0]

VCC

PICCLK

PWRGOOD

RESET#

PICD[1:0]

AG TL OU TPUT S

OTHER CMO S OUTPUTS

ALL INPUTS

VCC-12%

VIL18

Valid

NOTES: Ta = T19A (Time from VCC(nominal)-12% to PWRGOOD low)

Tb = T19B (All outputs valid after PWRGOOD low)

Tc = T19C (All inputs required valid after PWRGOOD low)

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38 Datasheet 298517-001

Figure 12.Power Down Sequencing and Timings (VCCT Leading)

VTTPWRGD

BCLK

V0045-00

VCCT, VREF

VCMOS,

CMOSREF,

CLKREF

VID[4:0]

BSEL[1:0]

VCC

PICCLK

PWRGOOD

RESET#

PICD[1:0]

AGTL OU TPUTS

OTHER CMOS OUTPUTS

ALL INPUTS

Tb, T c, T d

VCCT-12%

VILVTTPWR

Valid

NOTES: Ta = T20A (Time from VCCT-12% to VTTPWRGD low)

Tb = T20B (All outputs valid after VTTPWRGD low)

Tc = T20C (All inputs required valid after VTTPWRGD low)

Td = T20D (VID, BSEL signals valid after VTTPWRGD low)

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298517-001 Datasheet 39

Figure 13.Test Timings (Boundary Scan)

TCK

TDI, TMS

Input

Signals

TDO

Output

Signals

0.75V

TvTw

TrTs

TxTu

TyTz

D0008-01

NOTES: Tr=T43 (All Non-Test Inputs Setup Time)

Ts=T44 (All Non-Test Inputs Hold Time)

Tu=T40 (TDO Float Delay)

Tv=T37 (TDI, TMS Setup Time)

Tw=T38 (TDI, TMS Hold Time)

Tx=T39 (TDO Valid Delay)

Ty=T41 (All Non-Test Outputs Valid Delay)

Tz=T42 (All Non-Test Outputs Float Delay)

Figure 14. Test Reset Timings

TRST# 0.75V

TqD0009-01

NOTE: Tq=T36 (TRST# Pulse Width)

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40 Datasheet 298517-001

Figure 15.Quick Start/Deep Sleep Timing (BCLK Stopping Method)

stpgnt

StoppedBCLK

STPCLK#

CPU bus

DPSLP#

Compatibility

Signals Changing

Normal Quic k S tart Deep Sleep Quick Start Normal

Frozen

V00102-00

NOTES:

Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)

Tw=T46 (Setup Time to Input Signal Hold Requirement)

Tx=T47 (Deep Sleep PLL Lock Latency)

Ty=T48 (PLL lock to STPCLK# Hold Time)

Tz=T49 (Input Signal Hold Time)

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298517-001 Datasheet 41

Figure 16. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)

stpgnt

BCLK

STPCLK#

CPU bus

DPSLP#

Compatibility

Signals Changing

Normal Quic k S tart Deep Sleep Quick Start Normal

Frozen

V00103-00

NOTES:

Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)

Tw=T46 (Setup Time to Input Signal Hold Requirement)

Tx=T47 (Deep Sleep PLL Lock Latency)

Ty=T48 (PLL lock to STPCLK# Hold Time)

Tz=T49 (Input Signal Hold Time)

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42 Datasheet 298517-001

4. System Signal Simulations

Systems must be simulated using IBIS models to determine if they are compliant with this specification.

4.1 System Bus Clock (BCLK) and PICCLK DC

Specifications and AC Signal Quality Specifications

Table 23. BCLK DC Specifications and AC Signal Quality Specifications

Symbol Parameter Min Max Unit Figure Notes

V1 VIL,BCLK 0.3 V 20 Note 1

V2 VIH,BCLK 2.2 V 20 Note 1

V3 VIN Absolute Volt age Range -0.5 3.1 V 20 Undershoot/Overshoot, Note 2

V4 BCLK Rising Edge Ringback 2.0 V 20 Absolute Value, Note 3

V5 BCLK Falling Edge Ringback 0.5 V 20 Absolute Value, Note 3

NOTES:

1. The clock must rise/fall monotonicall y bet ween VIL,BCLK and VIH,BCLK . BCLK must be stopped in the low state.

2. These specifications apply only when BCLK is running. BCLK may not be above VIH,BCLK,max or below VIL,BCLK,min

for more than 50% of the clock cycl e.

3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the BCLK signal can go to after passi ng the VIH,BCLK (rising) or VIL,BCLK (falling) voltage limits.

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Table 24. PICCLK DC Specifications and AC Signal Quality Specifications

Symbol Parameter Min Max Unit Figure Notes

V1 VIL20 0.4 V 20 Note 1

V2 VIH20 1.6 V 20 Note 1

V3 VIN Absolute Volt age Range -0.5 2. 4 V 20 Undershoot , Overshoot, Note 2

V4 PICCLK Rising Edge Ringback 1.6 V 20 Ab solute Value, Note 3

V5 PICCLK Falling Edge Ringback 0.4 V 20 Absolute Value, Note 3

NOTES:

1. The clock must rise/fall monotonicall y bet ween VIL20 and VIH20.

2. These specifications apply only when PICCLK is running. See the DC specifications for when PICCLK is

stopped. PICCLK may not be above VIH20,max or below VIL20,min for more than 50% of the clock cycle.

3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the PICCLK signal can go to after passing the VIH20 (rising) or VIL20 (falling) voltage limits.

Figure 17. BCLK/PICCLK Generic Clock Waveform

V0012-01

V3max

V3min

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4.2 AGTL AC Signal Quality Specifications

Ringback specifications for the AGTL signals are as follows: Ringback below VREF,max + 200 mV i s not

authorized during low to high transitions. Ringback above VREF,min – 200 mV is not authorized during

high to low transitions.

Overshoot and undershoot specifications are documented in Table 25 and illustrated in Figure 18.

Figure 18. Maximum Acceptable Over shoot/Undershoot Waveform

Max

Vss

Time dependant Overshoot

Time dependant Undershoot

Min

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Table 25. 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core

Allowed Pulse Duration (ns) [Tj=100C]

Max VCCT + Overshoot/Undershoot

Magnitude (volts) Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1

1.78 1.6 0.16 0.016

1.73 4.5 0.45 0.045

1.68 9.5 0.95 0.095

1.63 20 2.0 0.2

1.58 20 4.2 0.42

1.53 20 8.5 0.85

1.48 20 19 1.9

NOTES:

1. Under no circumstances should the sum of the Max VCCT and absol ute value of the Overshoot/ Undershoot

voltage exceed 1.78V.

2. Activity factor of 1 represents the same toggl e rate as the 100-MHz clock.

3. Ringbacks below VCCT cannot be subtracted from overshoots. Less er undershoot does not allocate longer or

larger overshoot.

4. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocat e longer or

larger undershoot.

5. System designers are enc ouraged to foll ow Intel provided A G TL layout guideli nes.

6. All values are specified by design characterization and are not t ested.

4.3 Non-AGTL Signal Quality Specifications

Signals driven to the Mobile Intel Celeron Processor should meet signal quality specifications to ensure

that the processor reads data properly and that incoming signals do not affect the long-term reliability of

the processor. The overshoot and undershoot specifications for non-AGTL signals are shown in

Table 26. Ringback must not exceed the CMOS VIH and VIL specification levels in Table 14.

Table 26. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core

Allowed Pulse Duration (ns) [Tj=100C]

Max VCmos + Overshoot/Undershoot

Magnitude (volts) Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1

2.38 6.5 0.65 0.065

2.33 13 1.3 0.13

2.28 29 2.9 0.29

2.23 60 6 0.6

2.18 60 12 1.2

2.13 60 26 2.6

2.08 60 56 5.6

NOTES:

1. VCMOS(nominal) = 1.5V.

2. Under no circumstances should the sum of the Max VCMOS and absolute value of t he Overshoot /Undershoot

voltage exceed 2.38V.

3. Activity factor of 1 represents a toggle rate of 33 MHz.

4. System designers are enc ouraged to foll ow Intel provided non-A GTL layout gui del i nes.

5. All values are specified by design characterization, and are not tested.

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46 Datasheet 298517-001

4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications

The processor requires PWRGOOD to be a clean indication that clocks and the power supplies (VCC,

VCCT, etc.) are stable and within their specifications. Clean implies t hat the signal will remain below

VIL18 and without errors from the time that the power supplies are turned on, until they come within

specification. The signal will then transitio n monotonically to a high (1.8V) state. The VTTPWRGD

signal must also transition monotonicall y.

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298517-001 Datasheet 47

5. Mechanical Specifications

5.1 Surface Mount Micro-FCBGA Package

The Low Voltage Mobile Intel Celeron P r ocessor will also be available in a surface mount, 4 79-ball

Micro-FCBGA package. The Low Voltage processor will be available only in this package. Mechanical

specifications are shown in Table 27. Figure 19 through 22 illustrate different views of the package.

The Micro-FCBGA package may have capacitors placed in the area surrounding the die. Because the

die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should

be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short

the capacitors, and possibly damage the device or render it inactive. The use of an insulating material

between the capacitors and any thermal solution should be considered to prevent capacitor shorting.

Table 27. Micro-FCBGA Package Mechanical Specifications

Symbol Parameter Min Max Unit

A Ov eral l hei ght, as delivered (1) 2.27 2.77 m m

A2 Die height 0.854 mm

b Ball diameter 0.78 mm

D Package substrate length 34.9 35.1 mm

E Package substrate width 34.9 35.1 mm

D1 Die length 11.18 mm

E1 Die width 7.19 mm

e Ball pitch 1.27 mm

N Ball count 479 each

K K eep-out outline from edge of package 5 mm

K1 K eep-out outline at corner of package 7 mm

K2 Capacitor keep-out height - 0.7 mm

S P ackage edge to first ball center 1.625 mm

-- Solder ball coplanarity 0.2 mm

Pdie All owabl e pressure on the die for thermal solution - 689 kPa

W Package weight 4.5 g

NOTES:

1. All dimensions are subject to change.

2. Overall height as deli vered. Val ues were based on design specifications and tolerances. Final height after

surfac e mount depends on OEM motherboard design and SMT process.

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Figure 19. Micro-FCBGA Package – Top and Bottom Isometric Views

TOP VIEW BOTTOM VIEW

LABEL DIE

PACKAGE KEEPOUT

CAPACITOR AREA

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298517-001 Datasheet 49

Figure 20. Micro-FCBGA Package – Top and Side Views

35 (E)

35 (D)

PIN A1 CORNER

Ø0.78 (b)

479 places

SUBSTR AT E KEEPOUT ZONE

DO NOT CONTACT PACKAGE

INSIDE THIS LINE

7 (K1)

8 places

5 (K)

4 places

NOTE: All dimensions in millimeters. Values shown are for reference only. See T able 2 7 for specific details

0.20

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50 Datasheet 298517-001

Figure 21. M icro -F CBG A Package - Bott om View

1 2 34 6 810 12 14 16 18 20 22 24 26

5 7 9 11 13 15 17 19 21 23 25

F G

H J

K L

M N

P R

V W

Y AA

AB AC

AD AE

NOTE

: All dimensions in millimeters. Values shown are for referenceonly. See Table 27 for specific details.

25X 1.27

(e)

25X 1.27

(e)

1.625 (S)

4 places

1.625 (S)

4 places

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

298517-001 Datasheet 51

5.2 Signal Listings

Figure 22 is a top-side view of the ball or pin map of the Mobile Intel Celeron Processor with the voltage

balls/pins called out. Table 28 lists the signals in ball/pin number order. Table 29 lists the signals in

signal name order.

Figure 22. Pin/Ball Map - Top View

A10# VREF NC A31# BREQ0# A23# A27# A24# NC A35# A26# A33# A32# D0# D2# D15# D9# D7# VREF D8# D10# D11# VSS VCCT

NC VSS A25# VSS A17# VSS A21# VSS A20# VSS A18# VSS A34# VSS RESET# VSS D1# VSS D4# VSS D17# VSS D18# D14# D24# VSS

NC A16# A28# NC VCCT A19# VCCT A22# VCCT A30# VCCT A29# VCCT BERR# VCCT D6# VCCT D12# VCCT D5# VCCT NC VSS D20# VSS D30#

NC VSS A13# VSS VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D3# D13# D22# NC

NC TESTHI VCCT VCC VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D16# D23# VSS D19#

NC VSS A14# VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D21# D36# D27#

A9# A5# A15# VCCT VCC VSS VCC VSS VCCT D25# VSS D32#

A12# VSS A8# VSS VSS VCC VSS VCC VSS D26# D29# VREF

A4# A7# A11# VCCT VCC VSS VCC VSS VCCT D34# VSS D38#

A3# VSS A6# VSS VSS VCC VSS VCC VSS D31# D33# D35#

REQ4# BNR# REQ1# VCCT NC VSS VCC VSS VCCT D28# VSS D42#

VSS VSS VSS RSP# VCC VSS VCC VSS D39# D45# D48#

VREF PLL2 PLL1 NC VCC VSS VCC VSS VCCT NC VSS D37#

NC VSS API# NC NC VCC VSS VCC VSS D49# D41# NC

REQ0# BPRI# VID4 VSS VCC VSS VCC VSS VCCT D43# VSS D44#

REQ2# VSS DEFER# RP# VSS VCC VSS VCC VSS D47# D57# D51#

REQ3# HITM# RS2# VSS VCC VSS VCC VSS VCCT D52# VSS D40#

RS1# VSS LOCK# VCCT VSS VCC VSS VCC VSS D63# D46# D55#

TRDY# AERR# DBSY# VSS VCC VSS VCC VSS VCCT D59# VSS D54#

DRDY# VSS RS0# VSS VCC VSS VCC VSS D58# D53# D60#

VREF HIT# ADS# VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCCT D62# VSS D50#

VID0 VSS AP0# PWR

GOOD VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D61# D56# VREF

BCLK VID1 A20M# VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCCT DEP3# VSS DEP6#

CLKREF VSS SMI# NC CMOS

REF VCCT TDI VCCT IGNNE# TCK TDO VCCT NC VCCT LINT0 NCTRL PICD1 VCCT PICD0 VCCT BPM1# BPM0# NC DEP7# DEP1# DEP5#

VSS VID2 VCCT STPCLK# VSS INIT# VSS NC VSS NC VSS BSEL0 VSS LINT1 VSS RTT

IMPEDP VSS VCCT VSS BP3# VSS PRDY# VSS DEP0# DEP2# VSS

VCCT VCCT VID3 IERR# FLUSH# FERR# TMS DPSLP# VREF BSEL1 TESTHI CMOS

REF THRMDATHRMDC TRST# EDGE

CTRLP NC NC PREQ# PICCLK VREF BP2# BINIT# DEP4# VSS VSS

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526

VTT

PWRGD

1234567891011121314151617181920212223242526

VCC VSS OtherVCCT

TESTLO

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

52 Datasheet 298517-001

Table 28. Signal Listing in Order by Pin/Ball Number

No. Signal Name No. Signal Name No. Signal Name No. Signal Name

A3 A10# B18 VSS D7 VSS E22 VSS

A4 VREF B19 D4# D8 VCC E23 D16#

A5 NC B20 VSS D9 VSS E24 D23#

A6 A31# B21 D17# D10 VCC E25 VSS

A7 BREQ0# B22 VSS D11 VSS E26 D19#

A8 A23# B23 D18# D12 VCC F1 NC

A9 A27# B24 D14# D13 VSS F2 VSS

A10 A24# B25 D24# D14 VCC F3 A14#

A11 NC B26 VSS D15 VSS F4 VSS

A12 A35# C1 NC D16 VCC F5 VSS

A13 A26# C2 A16# D17 VSS F6 VCC

A14 A33# C3 A28# D18 VCC F7 VSS

A15 A32# C4 NC D19 VSS F8 VCC

A16 D0# C5 VCCT D20 VCC F9 VSS

A17 D2# C6 A19# D21 VSS F10 VCC

A18 D15# C7 VCCT D22 VCC F11 VSS

A19 D9# C8 A22# D23 D3# F12 VCC

A20 D7# C9 VCCT D24 D13# F13 VSS

A21 VREF C10 A30# D25 D22# F14 VCC

A22 D8# C11 VCCT D26 NC F15 VSS

A23 D10# C12 A29# E1 NC F16 VCC

A24 D11# C13 VCCT E2 TESTHI F17 VSS

A25 VSS C14 BERR# E3 VTTPWRGD F18 VCC

A26 VCCT C15 VCCT E4 VCCT F19 VSS

B1 NC C16 D6# E5 VCC F20 VCC

B2 VSS C17 VCCT E6 VCCT F21 VSS

B3 A25# C18 D12# E7 VCC F22 VCC

B4 VSS C19 VCCT E8 VSS F23 VSS

B5 A17# C20 D5# E9 VCC F24 D21#

B6 VSS C21 VCCT E10 VSS F25 D36#

B7 A21# C22 NC E11 VCC F26 D27#

B8 VSS C23 VSS E12 VSS G1 A9#

B9 A20# C24 D20# E13 VCC G2 A5#

B10 VSS C25 VSS E14 VSS G3 A15#

B11 A18# C26 D30# E15 VCC G4 VCCT

B12 VSS D1 NC E16 VSS G5 VCC

B13 A34# D2 VSS E17 VCC G6 VSS

B14 VSS D3 A13# E18 VSS G21 VCC

B15 RESET# D4 VSS E19 VCC G22 VSS

B16 VSS D5 VCCT E20 VSS G23 VCCT

B17 D1# D6 VCC E21 VCC G24 D25#

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

298517-001 Datasheet 53

No. Signal Name No. Signal Name No. Signal Name No. Signal Name

G25 VSS L4 VCCT P23 VSS V2 VSS

G26 D32# L5 NC P24 D49# V3 LOCK#

H1 A12# L6 VSS P25 D41# V4 VCCT

H2 VSS L21 VCC P26 NC V5 VSS

H3 A8# L22 VSS R1 REQ0# V6 VCC

H4 VSS L23 VCCT R2 BPRI# V21 VSS

H5 VSS L24 D28# R3 VID4 V22 VCC

H6 VCC L25 VSS R4 VSS V23 VSS

H21 VSS L26 D42# R5 VCC V24 D63#

H22 VCC M1 TESTLO R6 VSS V25 D46#

H23 VSS M2 VSS R21 VCC V26 D55#

H24 D26# M3 VSS R22 VSS W1 TRDY#

H25 D29# M4 VSS R23 VCCT W2 AERR#

H26 VREF M5 RSP# R24 D43# W3 DBSY#

J1 A4# M6 VCC R25 VSS W4 VSS

J2 A7# M21 VSS R26 D44# W5 VCC

J3 A11# M22 VCC T1 REQ2# W6 VSS

J4 VCCT M23 VSS T2 VSS W21 VCC

J5 VCC M24 D39# T3 DEFER# W22 VSS

J6 VSS M25 D45# T4 RP# W23 VCCT

J21 VCC M26 D48# T5 VSS W24 D59#

J22 VSS N1 VREF T6 VCC W25 VSS

J23 VCCT N2 PLL2 T21 VSS W26 D54#

J24 D34# N3 PLL1 T22 VCC Y1 DRDY#

J25 VSS N4 NC T23 VSS Y2 VSS

J26 D38# N5 VCC T24 D47# Y3 RS0#

K1 A3# N6 VSS T25 D57# Y4 TESTLO

K2 VSS N21 VCC T26 D51# Y5 VSS

K3 A6# N22 VSS U1 REQ3# Y6 VCC

K4 VSS N23 VCCT U2 HITM# Y21 VSS

K5 VSS N24 NC U3 RS2# Y22 VCC

K6 VCC N25 VSS U4 VSS Y23 VSS

K21 VSS N26 D37# U5 VCC Y24 D58#

K22 VCC P1 NC U6 VSS Y25 D53#

K23 VSS P2 VSS U21 VCC Y26 D60#

K24 D31# P3 API# U22 VSS AA1 VREF

K25 D33# P4 NC U23 VCCT AA2 HIT#

K26 D35# P5 NC U24 D52# AA3 ADS#

L1 REQ4# P6 VCC U25 VSS AA4 VCCT

L2 BNR# P21 VSS U26 D40# AA5 VCC

L3 REQ1# P22 VCC V1 RS1# AA6 VSS

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

54 Datasheet 298517-001

No. Signal Name No. Signal Name No. S ignal Name No. Signal Name

AA7 VCC AB22 VCC AD11 TDO AE26 VSS

AA8 VSS AB23 VSS AD12 VCCT AF1 VCCT

AA9 VCC AB24 D61# AD13 NC AF2 VCCT

AA10 VSS AB25 D56# AD14 VCCT AF3 VID3

AA11 VCC AB26 VREF AD15 LINT0 AF4 IERR#

AA12 VSS AC1 BCLK AD16 NCTRL AF5 FLUSH#

AA13 VCC AC2 VID1 AD17 PICD1 AF6 FERR#

AA14 VSS AC3 A20M# AD18 VCCT AF7 TMS

AA15 VCC AC4 VCCT AD19 PICD0 AF8 DPSLP#

AA16 VSS AC5 VCC AD20 VCCT AF9 VREF

AA17 VCC AC6 VSS AD21 BPM1# AF10 BSEL1

AA18 VSS AC7 VCC AD22 BPM0# AF11 TESTHI

AA19 VCC AC8 VSS AD23 NC AF12 CMOSREF

AA20 VSS AC9 VCC AD24 DEP7# AF13 THRMDA

AA21 VCC AC10 VSS AD25 DEP1# AF14 THRMDC

AA22 VSS AC11 VCC AD26 DEP5# AF15 TRST#

AA23 VCCT AC12 VSS AE1 VSS AF16 EDGECTRLP

AA24 D62# AC13 VCC AE2 VID2 AF17 NC

AA25 VSS AC14 VSS AE3 VCCT AF18 NC

AA26 D50# AC15 VCC AE4 STPCLK# AF19 PREQ#

AB1 VID0 AC16 VSS AE5 VSS AF20 PICCLK

AB2 VSS AC17 VCC AE6 INIT# AF21 VREF

AB3 AP0# AC18 VSS AE7 VSS AF22 BP2#

AB4 PWRGOOD AC19 VCC AE8 NC AF23 BINIT#

AB5 VSS AC20 VSS AE9 VSS AF24 DEP4#

AB6 VCC AC21 VCC AE10 NC AF25 VSS

AB7 VSS AC22 VSS AE11 VSS AF26 VSS

AB8 VCC AC23 VCCT AE12 BSEL0

AB9 VSS AC24 DEP3# AE13 VSS

AB10 VCC AC25 VSS AE14 LINT1

AB11 VSS AC26 DEP6# AE15 VSS

AB12 VCC AD1 CLKREF AE16 RTTIMPEDP

AB13 VSS AD2 VSS AE17 VSS

AB14 VCC AD3 SMI# AE18 VCCT

AB15 VSS AD4 NC AE19 VSS

AB16 VCC AD5 CMOSREF AE20 BP3#

AB17 VSS AD6 VCCT AE21 VSS

AB18 VCC AD7 TDI AE22 PRDY#

AB19 VSS AD8 VCCT AE23 VSS

AB20 VCC AD9 IGNNE# AE24 DEP0#

AB21 VSS AD10 TCK AE25 DEP2#

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

298517-001 Datasheet 55

Table 29. Signal Listing in Order by Signal Name

No. Signal Name Signal Buffer Type No. S ignal Name S i gnal Buffer Type

K1 A3# AGTL I/O AF23 BINIT# AGTL I/O

J1 A4# AGTL I/O L2 BNR# AGTL I/O

G2 A5# AGTL I/O AF22 BP2# AGTL I/O

K3 A6# AGTL I/O AE20 BP3# AGTL I/O

J2 A7# AGTL I/O AD22 BPM0# AGTL I/O

H3 A8# AGTL I/O AD21 BPM1# AGTL I/O

G1 A9# AGTL I/O R2 BPRI# AGTL Input

A3 A10# AGTL I/O A7 BREQ0# AGTL I/O

J3 A11# AGTL I/O AE12 BSEL0 3. 3V CMOS Output

H1 A12# AGTL I/O AF10 BSEL1 3. 3V CMOS Output

D3 A13# AGTL I/O AD5 CMOSREF CMOS Reference Voltage

F3 A14# AGTL I/O AF12 CMOSREF CMOS Reference Voltage

G3 A15# AGTL I/O A16 D0# AGTL I/O

C2 A16# AGTL I/O B17 D1# AGTL I/O

B5 A17# AGTL I/O A17 D2# AGTL I/O

B11 A18# AGTL I/O D23 D3# AGTL I/O

C6 A19# AGTL I/O B19 D4# AGTL I/O

B9 A20# AGTL I/O C20 D5# AGTL I/O

B7 A21# AGTL I/O C16 D6# AGTL I/O

C8 A22# AGTL I/O A20 D7# AGTL I/O

A8 A23# AGTL I/O A22 D8# AGTL I/O

A10 A24# AGTL I/O A19 D9# AGTL I/O

B3 A25# AGTL I/O A23 D10# AGTL I/O

A13 A26# AGTL I/O A24 D11# AGTL I/O

A9 A27# AGTL I/O C18 D12# AGTL I/O

C3 A28# AGTL I/O D24 D13# AGTL I/O

C12 A29# AGTL I/O B24 D14# AGTL I/O

C10 A30# AGTL I/O A18 D15# AGTL I/O

A6 A31# AGTL I/O E23 D16# AGTL I/O

A15 A32# AGTL I/O B21 D17# AGTL I/O

A14 A33# AGTL I/O B23 D18# AGTL I/O

B13 A34# AGTL I/O E26 D19# AGTL I/O

A12 A35# AGTL I/O C24 D20# AGTL I/O

AC3 A20M# 1. 5V CMOS Input F24 D21# AGTL I/O

AA3 ADS# AGTL I/O D25 D22# AGTL I/O

W2 AERR# AGTL I/O E24 D23# AGTL I/O

AB3 AP0# AGTL I/O B25 D24# AGTL I/O

P3 AP1# AGTL I/O G24 D25# AGTL I/O

AC1 BCLK Clock Input H24 D26# AGTL I/O

AD1 CLKREF Clock Input F26 D27# AGTL I/O

C14 BERR# AGTL I/O L24 D28# AGTL I/O

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

56 Datasheet 298517-001

No. Signal Name Signal Buffer Type No. S ignal Name S ignal Buffer Type

H25 D29# AGTL I/O AF24 DEP4# AGTL I/O

C26 D30# AGTL I/O AD26 DEP5# AGTL I/O

K24 D31# AGTL I/O AC26 DEP6# AGTL I/O

G26 D32# AGTL I/O AD24 DEP7# AGTL I/O

K25 D33# AGTL I/O Y1 DRDY# AGTL I/O

J24 D34# AGTL I/O AF8 DPSLP# 1.5V CMOS Input

K26 D35# AGTL I/O AF16 EDGECTRLP AGTL Control

F25 D36# AGTL I/O AF6 FERR# 1.5V Open Drain Output

N26 D37# AGTL I/O AF5 FLUSH# 1. 5V CMOS Input

J26 D38# AGTL I/O AA2 HIT# AGTL I/O

M24 D39# AGTL I/O U2 HITM# AGTL I/O

U26 D40# AGTL I/O AF4 IE RR# 1.5V Open Drain Output

P25 D41# A GTL I/ O AD9 I GNNE # 1.5V CMOS Input

L26 D42# AGTL I/O AE6 INIT# 1. 5V CMOS Input

R24 D43# AGTL I/O AD15 INTR/ LI NT0 1.5V CMOS Input

R26 D44# AGTL I/O V3 LOCK# AGTL I/O

M25 D45# AGTL I/O AE14 NMI/LINT1 1.5V CMOS Input

V25 D46# AGTL I/O AD16 NCTRL AGTL impedance control

T24 D47# AGTL I/O AF20 PICCLK 1.8V APIC Clock Input

M26 D48# AGTL I/O AD19 PI CD0 1.5V Open Drain I/O

P24 D49# A GTL I/ O AD17 PI CD1 1.5V Open Drain I/O

AA26 D50# AGTL I/O N3 P LL1 PLL Analog Voltage

T26 D51# AGTL I/O N2 PLL2 PLL Anal og Voltage

U24 D52# AGTL I/O AE22 PRDY# AGTL Output

Y25 D53# A GTL I/ O AF19 P RE Q# 1. 5V CMOS Input

W26 D54# AGTL I/O AB4 PWRGOOD 1.8V CMOS Input

V26 D55# AGTL I/O R1 REQ0# AGTL I/O

AB25 D56# AGTL I/O L3 REQ1# AGTL I/O

T25 D57# AGTL I/O T1 REQ2# AGTL I/O

Y24 D58# AGTL I/O U1 REQ3# AGTL I/O

W24 D59# AGTL I/O L1 REQ4# AGTL I/O

Y26 D60# AGTL I/O B15 RESET# AGTL Input

AB24 D61# AGTL I/O T4 RP# AGTL I/O

AA24 D62# AGTL I/O Y3 RS0# AGTL I/O

V24 D63# AGTL I/O V1 RS1# AGTL I/O

W3 DBSY# AGTL I/O U3 RS2# AGTL I/O

T3 DEFER# AGTL Input M5 RSP# AGTL Input

AE24 DEP0# AGTL I/O AE16 RTTIMPEDP AGTL Pull-up Control

AD25 DEP1# A GTL I/ O AD3 SM I# 1.5V CMOS Input

AE25 DEP2# AGTL I/O AE4 STPCLK# 1. 5V CMOS Input

AC24 DEP3# AGTL I/O

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

298517-001 Datasheet 57

No. Signal Name Signal Buffer Type No. Signal Name Si gnal Buffer Type

AD10 TCK 1.5V JTAG Clock Input AC2 VID1 Voltage Identification

AD7 TDI JTAG Input AE2 VID2 Voltage Identification

AD11 TDO JTAG Output AF3 VID3 Voltage Identification

E2 TESTHI Test Use Only R3 VID4 Voltage Identification

AF11 TESTHI Test Use Only A4 VREF AGTL Reference Voltage

M1 TESTLO Test Use Only A21 VREF AGTL Reference Voltage

Y4 TESTLO Test Use Only N1 VREF AGTL Reference Voltage

AF13 THE RM DA Thermal Diode Anode AF9 VREF AGTL Referenc e Volt age

AF14 THERMDC Thermal Diode Cathode AF21 VREF AGTL Reference Voltage

AF7 TMS JTAG Input AA1 VREF AGTL Reference Voltage

W1 TRDY# AGTL I/O AB26 VREF AGTL Reference Voltage

AF15 TRST# JTAG Input H26 VREF AGTL Reference Voltage

AB1 VID0 Voltage Identificat i on E3 VTTPWRGD VCCT power good signal

Table 30. Voltage and No-Connect Pin/Ball Locations

Signal

Name Pin/Ball Numb ers

NC A2, A5, A11, B1, C1, C4, C22, D1, D26, E1, F1, L5, N4, N24, P1, P4, P5, P26, AD4, AD13, AD23, AE8,

AE10, AF17, AF18

VCC D6, D8, D10, D12, D14, D16, D18, D20, D22, E5, E7, E9, E11, E13, E15, E17, E19, E21, F6, F8,

F10, F12, F14, F16, F18, F20, F22, G5, G21, H6, H22, J5, J21, K6, K22, L21, M6, M22, N5, N21,

P6, P22, R5, R21 , T6 , T2 2 , U5, U21 , V6 , V2 2 , W5, W21 , Y6 , Y22, A A5 , AA7, AA9, AA11 , AA1 3,

AA15, AA17, AA19, AA21, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC5,

AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21

VCCT A26, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, E4, E6, G4, G23, J4, J23, L4, L23, N23, R23, U23,

V4, W23, AA4, AA23, AC4, AC23, AD6, AD8, AD12, AD14, AD18, AD20, AE3, AE18, AF1, AF2

VSS A25, B2, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, B26, C23, C25, D2, D4, D7, D9, D11, D13,

D15, D17, D19, D21, E8, E10, E12, E14, E16, E18, E20, E22, E25, F2, F4, F5, F7, F9, F11, F13, F15,

F17, F19, F21, F23, G6, G22, G25, H2, H4, H5, H21, H23, J6, J22, J25, K2, K4, K5, K21, K23, L6, L22,

L25, M2, M3, M4, M21, M23, N6, N22, N25, P2, P21, P23, R4, R6, R22, R25, T2, T5, T21, T23, U4, U6,

U22, U25, V2, V5, V21, V23, W4, W6, W22, W25, Y2, Y5, Y21, Y23, AA6, AA8, AA10, AA12, AA14,

AA16, AA18, AA20, AA22, AA25, AB2, AB5, AB7, AB9, AB11, AB13, AB15, AB17, AB19, AB21, AB23,

AC6, AC8, AC10, AC12, AC14, AC16, AC18, AC20, AC22, AC25, AD2, AE1, AE5, AE7, AE9, AE11,

AE13, AE15, AE17, AE19, AE21, AE23, AE26, AF25, AF26

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

58 Datasheet 298517-001

6. VCC Thermal Specifications

In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or

other heat transfer system) must make firm contact to the exposed processor die. The processor die must

be clean before the thermal solution is attached o r the processor may be damaged.

Table 31 provides the Thermal Design Power (TDP) dissipation and the minimum and maximum TJ

temperatures for the Mobile Intel Celeron Pr o c essor. The thermal solution should b e d e signed to ensure

the junction temperature never exceeds the 100°C TJ specification while operating at the Thermal Design

Power. Additionally, a secondary failsafe mec hanism in hardware should be provided to shutdown the

processor at 101°C to prevent permanent damage, as described in Section 3.1.3. TDP is a thermal

design power specification based on the worst case power dissipation of the processor while executing

publicly available software under normal operating conditions at nominal voltages. Contact your Intel

Field Sales Representative for further information.

Table 31. Power Specifications for Mobile Intel Celeron Processor

Symbol Core Frequency/Voltage Thermal Design

Power Unit Notes

TDP 650 MHz & 1.15V 10.6 W At 100°C, Note 1

Symbol Parameter Min Max Unit Notes

PAH Auto Halt power at:

1.15V

3.6

At 50°C, Note 2

PQS Quick Start power at

1.15V

3.2

At 50°C, Note 2

PDSLP Deep Sleep power at

1.15V

2.4

W At 35°C, Note 2

TJ Junction Temperature 0 100 °C Note 3

NOTES:

1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software

under normal operating conditions at nominal voltages that meet the load line specificati ons. The TDP number

show is a specification based on Icc(maxim um ) and indirect l y test ed by Ic c(maximum) testing. TDP definiti on is

synonymous with the Thermal Design Power (typical) specification referred to in previous Intel dat asheet s. The

Intel TDP specification is a recommended design point and is not representati ve of the absolute maximum

power the processor may dissipate under worst case conditions.

2. Not 100% tested. These power specifications are det erm i ned by charact eri zation of the processor currents at

higher temperat ures and ext rapol ating the values for the temperature indicated.

3. TJ is measured with the on-die thermal diode.

6.1 Thermal Diode

The Mobile Intel Celeron Processor has an on-die thermal diode that should be used to monitor the die

temperature(TJ). A thermal sensor located on the motherboard, or a stand-alone measurement kit,

should monitor the die temperature of the processor for thermal management or instrumentation

purposes. Table 32 and Table 33 provide the diode interface and specifications.

Mobile Intel® Celeron® Proc es s or (0.13µ) in Micr o- FCB G A Pack age D atashe et

298517-001 Datasheet 59

Note: The reading of the thermal sensor connected to the thermal d io de will not necessarily reflect the

temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-die

temperature gradients between the location of the thermal diode and the hottest location on the die, and

time based variations in the die temperature measurement. Time based variations can occur when the

sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ

temperature can change.

Table 32. Thermal Diode Interface

Signal Name Pin/Ball Number Signal Description

THERMDA AF13 Thermal diode anode

THERMDC AF14 Thermal diode cathode

Table 33. Thermal Diode Specifications

Symbol Parameter Min Typ Max Unit Notes

n Diode Ideality Factor (5-150uA) 1.0011 1.0067 1.0122 Notes 1, 2, 3, 4, 6

n Diode Ideality Factor (5-300uA) 1.0003 1.0091 1.0178 Notes 1, 2, 3, 5, 6

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support

or recommend operation of the therm al diode when the processor power supplies are not within t hei r specif i ed

tolerance range.

2. Characterized at 100°C.

3. Not 100% tested. Spec ifi ed by design/ characterizati on.

4. Specified for Forward Bias Current = 5 µA (min) and 150 µA (max).

5. Specified for Forward Bias Current = 5 µA (min) and 300 µA (max).

6. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:

Where Is = saturation current, q = electronic charge, Vd = voltage across the diode, k = Boltzmann Constant,

and T = absolute temperature (Kelvin).











−⋅= 1

SFW nkT

eII

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7. Processor Initialization and

Configuration

7.1 Description

The Mobile Intel Celeron Pro cessor has so me configuration optio ns that are deter mined b y hardware and

some that are determined by software. The processor samp les its hardware configuration at reset on the

active-to-inactive transitio n of RESET#. The P6 Family of Processors Developer’s Manual describes

these configuration options. Some of the co nfiguration options for the Mobile Intel Celeron Pro cessor

are described in the remainder of this section.

7.1.1 Quick Start Enable

Quick Start enabling is manda to r y on the Mobile Intel Celeron Pro cesso r by strapping A15# low. When

the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled active on the

RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops from the bus

priority device but it does not support symmetric master snoops nor is the latching of interrupts

supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick Start

state has been enabled.

7.1.2 System Bus Frequency

The Low Voltage Mobile Intel Celeron Processor supports 100-MHz bus frequency. Bit positions 18 to

19 of the Power-on Configuration register indicates at which speed a processor will run.

7.1.3 APIC Enable

The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to 1.5V

and supplying an active PICCLK to the processor. Software can be used to disable the APIC if it is not

being used, after PICD[1:0] are sampled high when RESET # is deasserted and the processor has started

executing instructions.

7.2 Clock Frequencies and Ratios

The Mobile Intel Celeron Processor uses a clock design in which the bus clock is multip lied by a ratio to

produce the processor’s internal (or “core”) clock. The ratio used is programmed into the processor

during manufacturing. The bus ratio pr ogrammed into the processor is visible in bit positio ns 22 to 25

and 27 of the Power-on Configuration register. Table 16 shows the 5-bit codes in the Power-on

Configuratio n register and their corresponding bus ratios.

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8. Processor Interface

8.1 Alphabetical Signal Reference

A[35:3]# (I/O – AGTL)

The A[35:3]# (Address) signals define a 236-byte physical me mory address space. When ADS# is active,

these signals transmit the address of a transaction; when ADS# is inactive, these signals transmit

transaction information. These signals must be connected to the appropriate pins/balls of both agents on

the system bus. The A[35:24]# signals are protected with the AP1# parity signal, and the A[23:3]#

signals are protected with the AP0# parity signal.

On the active-to-inactive tra ns ition of RESET#, each processor bus agent samples A[35:3]# signals to

determine its power-on configuration. See P6 Family of Processors Developer’s Manual for details.

A20M# (I - 1.5V Tolerant)

If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20

(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary.

Assertion of A20M# is only supported in Real mode.

ADS# (I/O - AGTL)

The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on the

A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop or deferred reply ID match operations associated with the new

transaction. This si gnal must be connected to the appro priate pins/balls on both agents on the system bu s.

AERR# (I/O - AGTL)

The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and if used,

must be connected to the appropriate pins/balls of both agents on the system bus. AERR# observation is

optionally enabled during power-on configuratio n; i f enabled, a valid assertion of AERR# abor ts the

current transaction.

If AERR# observation is di sabled during p ower-on configuratio n, a ce nt ral agent may handl e an

assertion of AERR# as appropriate to the error handling architecture of the system.

AP[1:0]# (I/O - AGTL)

The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:3]#,

REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if

an even number of covered signals is low and low if an odd number of covered signals are low. This

allows parity to be high when all the covered signals are high. AP[1:0]# should be connected to the

appropriate pins/balls on both agents on the system bus.

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BCLK

The BCLK signal deter mines the system bus frequency.

Both system bus agents must receive the BCLK signal to drive their outputs and latch their inputs on the

BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal.

BERR# (I/O - AGTL)

The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol

violation. It may be driven by either system bus agent and must be connected to the appropriate

pins/balls of both agents, if used. However, the Mobile Intel Celeron Pr o cessors do not observe

assertions of the BERR# signal.

BERR# assertion conditions are defined by the system configuration. Configuration option s enable the

BERR# driver as follows:

• Enabled or disabled

• Asserted optionally for internal erro rs along with IERR#

• Asserted optionally by the request initiator of a bus transaction after it observes an error

• Asserted by any bus agent when it observes an error in a bus transaction

BINIT# (I/O - AGTL)

The BINIT# (Bus Initialization) si gnal ma y be observed and d r iven by both system bus agents and must

be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is enabled during

the power-on configuration, BI NIT# is asserted to signal any bus condition t hat pr events reliable future

information.

If BINIT# is enabled during power-on configuration, and B INIT# is sampled asserted, all bus state

machines are reset and any data which was in transit is lost. All agents reset their rotating ID for bus

arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches are not

affected.

If BINIT # is di sable d during power-on confi gurat ion, a central agent may handle an a ssertion o f BINIT#

as appropriate to the Machine Check Architecture (MCA) of the system.

BNR# (I/O - AGTL)

The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable to

accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal t hat

must be connected to the appropriate pins/balls of both agents on the system bus. In order to avoid wire-

OR glitches asso ciated with simultaneous edge transitions driven by multiple drivers, BN R# is activated

on specific clock edges and sampled on specific clock edges.

BP[3:2]# (I/O - AGTL)

The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are outputs

from the processor that indicate the status of breakpoints.

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BPM[1:0]# (I/O - AGTL)

The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are

outputs from the processor that indicate the status of breakpoints and programmable counters used for

monitoring processor performance.

BPRI# (I - AGTL)

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It must be

connected to the appropriate pins/balls on both agents on the system bus. Observing BPRI# active (as

asserted by the priority agent) causes the processor to stop issuing new requests, unless such requests are

part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are

completed and then releases the bus by deasserting BPRI#.

BREQ0# (I/O - AGTL)

The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates that it

wants ownership of the system bus by asserting the BREQ0# signal.

During power-up configuration, the central agent must assert the BREQ0# bus signal. The processor

samples BREQ0# on the active-to-inactive transitio n of RESET#. Optio nally, this signal may be

grounded with a 10-ohm resistor.

BSEL[1:0] (O – 3.3V Tolerant)

The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for the

system bus frequency. The chipset and system clock generator also uses the BSEL signals. T he

VTTPWRGD signal info rms the processor to output the BSEL signals. During power up the BSEL

signals will be indeterminate for a small period of time. The chipset and clock generator should not

sample the BSEL signals until the VTTPWRGD signal is asserted. The assertion of the VTTPWRGD

signal indicates that the BSEL signals are stable and driven to a final state by the processor. Please refer

to Figure 10 for the timing relationship between the BSEL and VTTPWRGD signals.

Table 34 sho ws the encoding scheme for BSEL[1:0]. The Low Voltage Mobile Intel Celeron Processors

will support 100-MHz bus frequency. If another frequency is used then the processor is not guaranteed

to function properly.

Table 34. BSEL[1:0] Encoding

BSEL[1:0] System Bus Frequency

01 100 MHz

CLKREF (Analog)

The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip point

for the BCLK signal. This signal should be connected to a resistor divider to generate 1.25V from the

2.5-V supply. A minimum of 1-uF decoupling capacitance is recommended on CLKREF.

CMOSREF (Analog)

The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the CMOS

input buffers. CMOSREF must be generated from a stable 1.5V supply and must meet the VCMOSREF

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specification. The same 1.5V supply should be used to power the chipset CMOS I/O buffers that drive

the CMOS signals. Please refer to the platform design guidelines for resistor divider recommendations.

D[63:0]# (I/O - AGTL)

The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between both

system bus agents, and must be connected to the appropriate pins/balls on both agents. The data driver

asserts DRDY# to indicate a valid data transfer.

DBSY# (I/O - AGTL)

The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system

bus to indicate that the data bus is in use. The data bus is released after DBSY# is d easserted. This signal

must be connected to the appropriate pins/balls on both agents on the system bus.

DEFER# (I - AGTL)

The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be guaranteed

in-order completion. Assertion of DEFER# is nor mall y the resp onsibility of the addressed memory agent

or I/O agent. This signal must be connected to the appropr iate pins/balls on both a gents on the system

bus.

DEP[7:0]# (I/O - AGTL)

The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus.

They are driven by the agent responsible for driving D[63:0]#, and must be connected to the appropriate

pins/balls on both agents on the system bus if they are used. During power-on configuration, DEP[7:0]#

signals can be enabled for ECC checking or disabled for no checking.

DRDY# (I/O - AGTL)

The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid

data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks. This

signal must be connected to the appropriate pins/balls on both agents on the system bus.

DPSLP# (I - 1.5V Tolerant)

The DPSLP# (Deep Sleep) signal, when asserted in the Quick Start state, causes the processor to enter

the Deep Sleep state. In order to return to the Quick Start state BCLK must be running and the DPSLP#

pin must be deasserted.

EDGCTRLP (I-Analog)

The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output

buffers. Connect the signal to VSS with a 110-Ω, 1% resistor.

FERR# (O - 1.5V Tolerant Open-drain)

The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-

point error. FERR# is similar to the ERROR# signal on the Intel 387 co-processor, and it is included for

compatibility with systems using DOS-t ype floating-point error reporting.

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FLUSH# (I - 1.5V Tolerant)

When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache lines in

the Modified state and invalidates all internal cache lines. At the completion of a flush operatio n, the

processor issues a Flush Acknowledge transaction. The processor stops caching any new data while the

FLUSH# signa l remains asserted.

On the active-to-inactive transition of RESET# , each processor bus agent samples FLUSH# to determine

its power-on configuration.

HIT# (I/O - AGTL), HITM# (I/O - AGTL)

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results,

and must be connected to the appropriate pins/balls on both agents on the system bus. Either bus agent

can assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be

conti nued by reasserting HIT# and HI TM# t ogether.

IERR# (O - 1.5V Tolerant Open-drain)

The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error. Assertion

of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This transaction

may optionally be converted to an external error signal (e.g., NMI) by system logic. T he processor will

keep IERR# asserted until it is handled in software or with the assertion of RESET#, BI NIT, or INIT#.

IGNNE# (I - 1.5V Tolerant)

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error

and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor

freezes on a non-control floating-point instruction if a previous instruction caused an error. IGNNE# has

no affect when the NE bit in control register 0 (CR0) is set.

INIT# (I - 1.5V Tolerant)

The INIT# (Initialization) signal is asserted to reset integer registers in side the processor without

affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins execution at

the power -on rese t vec t or configur ed during powe r-on configura t ion. The pro cessor conti nues to handle

snoop requests during INIT# assertion. INIT# is an asynchronous input.

If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes its

built-in self test (BIST ) .

INTR (I - 1.5V Toler ant)

The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes the

LINT0 signal when the APIC is enabled. The interrupt is maskable u sing the IF bit in the EFLAGS

instruction execution. Upon recognizing the interrupt request, the processor issues a single Interrupt

Acknowledge (INTA) bus transaction. INTR must remain active until the INTA bus transactio n to

guarantee its recognition.

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LINT[1:0] (I - 1.5V Tolerant)

The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of all

APIC bus agents, including the processor and the system logic or I/O APIC component. When APIC is

disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes

NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the same signals for the

Pentium pro cessor. Both signals a re as ynchronous inp uts.

Both of these signals must be software configured by programming the APIC register space to be used

either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then LINT[1:0] is the

default configuratio n.

LOCK# (I/O - AGTL)

The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur atomically.

This signal must be connected to the appropriate pins/balls on both agents on the system bus. For a

locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction through

the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes LOCK#

deasserted. This enables the processor to retain bus ownership throughout the bus locked operation and

guarantee the atomicity of lock.

NCTRL (I - Analog)

The NCTRL signal pro vides the AGTL pull do wn impeda nce control. The processor samples this input

to determine the N-channel pull-down device strength when it is the driving agent. An external 14 oh m

(1% tolerance) pull-up resistor to VCCT is required for this signal. Please refer to platform design guide

for implementation details.

NMI (I - 1.5V Tolerant)

The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI

becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an

internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If

NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized

after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending.

NMI is rising edge sensitive.

PICCLK (I – 1.8V Toler a nt)

The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC that is

required for operation of the processor, system logic, and I/O AP IC components on the APIC bus.

PICD[1:0] (I/O - 1. 5V Tolerant Open-drain)

The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus.

They must be connected to the appropriate pins/balls of all APIC bus agents, including the processor and

the system logic or I/O APIC components. If the PICD0 signal is sampled low on the active-to-inactive

transition of the RESET# sig nal, then the APIC is hardware disabled. For the Mob ile Intel Celeron

Processor, the APIC is required to be hardware enabled as described in Section 7.1.3.

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PLL1, PLL2 (Analog)

The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL. See

Section 3.2.2 for a description of the analog decoupling circuit.

PRDY# (O - AGTL)

The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor

debug readiness.

PREQ# (I - 1.5V Tolerant)

The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processor.

PWRGOOD (I – 1.8V Tolerant)

PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean

indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their specifications.

Clean implies that the sig nal will remain low, (capable of sinking leakage current) and without glitches,

from the time that the power supplies are turned on, until they come within speci fication. The signal will

then tra nsition monotonically to a high (1. 8V) state. Figure 1 0 through Figure 1 2 illustra te the

relationship of PWRGOOD to other system signals. PWRGOOD can be driven inactive at any time, but

clocks and power must again be stable b e fore the rising edge o f PWRGOOD. It must also meet the

minimum pulse width specified in.

Table 18 (Section 3.6) and be followed by a 1 ms RESET# pulse. PWRGOOD ma y be asserted before

BCLK is active (see Table 18, Note 5)

The PWRGOOD si gnal, which must be supplied to the processor, is used to protect internal circuits

against voltage sequencing iss ues. The PWRGOOD signal should be driven high throughout boundar y

scan operation.

REQ[4:0]# (I/O - AGTL)

The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on both

agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]# to define

the currently active transaction type.

RESET# (I - AGTL)

Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2 caches

without writing back Modified (M state) lines. For a power-on type reset, RESET# must stay active for

at least 1 ms after VCC and BCLK have reached their proper DC and AC specifications and after

PWRGOOD has been asserted. When observing active RES ET#, all bus agents will deassert their

outputs within two clocks. RESET# is the only AGTL signal that does not have on-die AGTL

termination. A 56.2Ω 1% te rminating resisto r connected to V CCT is required.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on

configur ation. The configur ation op t ions ar e described in Section 4 and in the P6 Family of Processors

Developer’s Manual.

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Unless its outputs are tri-state d during power-on configuration, after an active-to-inactive transition of

RESET#, the pro cessor optionally executes its built-in self-test (BIST) and begins program execution at

reset-vector 000FFFF0H o r FFFFFFF0H. RESET# must be co nnected to the appropriate pins/balls on

both agents on the system bus.

RP# (I/O - AGTL)

The RP# (Request Parity) signal is driven by the request initi ator and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the

system bus.

A correct parity signal is high if an even number of covered signals is low and low if an odd number of

covered signals are low. This de finition allows parity to be high when all covered signals are high.

RS[2:0]# (I/O - AGTL)

The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for

completion of the current transaction) and must be connected to the appropriate pins/balls on both agents

on the system bus.

RSP# (I - AGTL)

The RSP# (Resp onse Parity) signal is driven by the response agent (the agent responsible for completion

of the current transaction) during assertion of RS[2:0]#. RSP# provides parity protection for RS[2:0 ]#.

RSP# should be connec ted to the appropriate pins/balls on both agents on the system bus.

A correct parity signal is high if an even number of covered signals are low, and it is low if an odd

number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high

since it is not driven by any agent guaranteeing correct parity.

RTTIMPEDP (I-Analog)

The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die AGTL termination.

Connect the RT TIMPEDP signal to VSS with a 56.2-Ω, 1% resistor.

SMI# (I - 1.5V Tolerant)

The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a

System Management Interrupt, the proce ssor saves the c urrent state and enters System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution

from the SMM handler .

STPCLK# (I - 1.5V Tolerant)

The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Quick

Start state. The processor issues a Stop Grant Acknowledge special transaction and stops providing

internal clock signals to all units except the bus and APIC units. The processor continues to snoop bus

transactions and service interrupts while in the Quick Start state. When STPCLK# is deasserted and

other conditions in are met, the processo r restarts its internal clock to all units and resumes execution.

The assertion of STPCLK# has no affect on the bus clock.

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TCK (I - 1.5V Tolerant)

The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access

port).

TDI (I - 1.5V Toleran t)

The TDI (Test Data In) signal transfers serial test data to the processor. T DI pro vides the se rial input

needed for JTAG support.

TDO (O - 1.5V Tolerant Open-drain)

The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the serial

output needed for JTAG support.

TESTHI[2:1] (I - 1.25V Tolerant)

The TESTHI[2:1] (Test input High) signals are used during processor test and need to be pulled high

during normal operation.

TESTLO[2:1] (I - 1.5V Tolerant)

The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to

ground during normal operation.

THERMDA, THERMDC (Anal og)

The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals connect to

the anode and cathode of the on-die thermal diode.

TMS (I - 1.5V Tolerant)

The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.

TRDY# (I/O - AGTL)

The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to receive

write or implicit write-back data transfer. TRDY# must be connected to the appropr iate p ins/balls on

both agents on the system bus.

TRST# (I - 1.5V Tolerant)

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The Mobile Intel Celeron

Processors do not self-reset during power on; therefore, it is necessary to drive this signal low during

power-on reset.

VID[4:0] (O – Open-drain)

The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply

voltages. Please refer to Section 3.2.3 for details.

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70 Datasheet 298517-001

VREF (Analog)

The VREF (AGTL Reference Vo ltage) si gnal provides a DC level reference voltage for the AGTL input

buffers. A voltage divider should be used to divide VCCT by 2/3. Resistor values of 1.00 kΩ and 2.00 kΩ

are recommended. Decouple the VREF signal with three 0.1-µF high-frequency capacitors close to the

processor.

VTTPWRGD (I – 1.25V)

The VTTPWRGD signal informs the processor to output the VID signals. During power up, the VID

signals will be in an indeterminate state for a small period o f ti me. The voltage regulator should not

sample and/or latch the VID signals unti l the VTTPWRGD signal is asserted . The assertion of the

VTTPWRGD signal indicates that the VID signals are stable and are driven to the final state by the

processor. Please refer to Figure 10 for the power up sequence.

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298517-001 Datasheet 71

8.2 Signal Summaries

Table 35. Input Signals

Name Active Level Clock Signal Group Qualified

A20M# Low Asynch CMOS Always

BCLK High — System Bus Always

BPRI# Low BCLK System Bus Always

DEFER# Low BCLK System Bus Always

FLUSH# Low Asynch CMOS Always

IGNNE# Low Asynch CMOS Always

INIT# Low Asynch System Bus Always

INTR High Asynch CMOS APIC disabled mode

LINT[1:0] High Asynch APIC APIC enabled mode

NMI High Asynch CMOS APIC dis abl ed m ode

NCTRL High Asynch

PICCLK High — APIC Always

PREQ# Low Asynch Implementation Always

PWRGOOD High Asynch Implementation Always

RESET# Low BCLK System Bus Always

RSP# Low BCLK System Bus Always

BSEL[1:0] High Asynch Implementation Always

DPSLP# Low Asynch Implementation Quick Start state

SMI# Low Asynch CMOS Always

STPCLK# Low Asynch Implementation Always

TCK High — JTAG

TDI TCK JTAG

TMS TCK JTAG

TRST# Low Asynch JTAG

VTTPWRGD High Asynch Power/Other

Table 36. Output Signals

Name Active Level Clock Signal Group

BSEL[1:0] High Asynch Open-drain

FERR# Low Asynch Open-drain

IERR# Low Asynch Open-drain

PRDY# Low BCLK Implementation

TDO High TCK JTAG

VID[4:0] High Asynch Power/Other

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72 Datasheet 298517-001

Table 37. Input/Output Signals (Single Driver)

Name Active Level Clock Signal Group Qualified

A[35:3]# Low BCLK System Bus ADS#, ADS#+1

ADS# Low BCLK System Bus Always

AP[1:0]# Low BCLK System Bus ADS#, ADS#+1

BREQ0# Low BCLK System Bus Always

BP[3:2]# Low BCLK System Bus Always

BPM[1:0]# Low BCLK System Bus Always

D[63:0]# Low BCLK System Bus DRDY#

DBSY# Low BCLK System Bus Always

DEP[7:0]# Low BCLK System Bus DRDY#

DRDY# Low BCLK System Bus Always

LOCK# Low BCLK System Bus Always

REQ[4:0]# Low BCLK System Bus ADS#, ADS#+1

RP# Low BCLK System Bus ADS#, ADS#+1

RS[2:0]# Low BCLK System Bus Always

TRDY# Low BCLK System Bus Response phase

Table 38. Input/Output Signals (Multiple Driver)

Name Active Level Clock Signal Group Qualified

AERR# Low BCLK System Bus ADS#+3

BERR# Low BCLK System Bus Always

BINIT# Low BCLK System Bus Always

BNR# Low BCLK System Bus Always

HIT# Low BCLK System Bus Always

HITM# Low BCLK System Bus Always

PICD[1:0] High PICCLK APIC Always

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298517-001 Datasheet 73

Appendix A. PLL RLC Filter Specification

A1. Introduction

All Mobile Intel Celeron Processors have internal PLL clock generators, which are analog in nature and

require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it degrades external

I/O timings as well as internal core timings (i.e. maximum frequency). The PLL RLC filter

specifications for the Mobile Intel Celero n Processor are the same as those for the mobile Intel Penti um

III-M processor. The general desired topology is shown in Figure 2. Excluded from the external circuitry

are parasitics associated with each component.

A2. Filter Specification

The function of the filter is two fold. It pro tects the PLL from external noise through low-pass

attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the low-

pass descriptio n forms an adequate description for the filter.

The AC low-pass specification, with input at VCCT and output measured across the capacitor, is as

follows:

• < 0.2-dB gain in pass band

• < 0.5-dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)

• 34-dB attenuation from 1 MHz to 66 MHz

• 28-dB attenua tion from 66 MHz to core fre quency

• The filter specification (AC) is graphically shown in Figure 23.

Other requirements:

• Use a shielded type inductor to minimize magnetic pickup

• The filter should support a DC current of at least 30 mA

• The DC voltage drop from VCCT to PLL1 should b e less than 60 mV, which in practice implies

series resistance of less than 2Ω. This also means that the pass band (from DC to 1 Hz)

attenuation below 0.43 dB for VCCT = 1.25V.

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74 Datasheet 298517-001

Figure 23. PLL Filter Specifications

0 dB

-28 dB

-34 dB

0.2 dB

forbidden

zone

x dB

forbidden

zone

1 MHz 66 MHz fcore fpeak1 Hz

assband high frequency

band

x = 20.lo

g[(

Vcct-60 mV

)

/ Vcct

]

NOTES:

Diagram is not to scale

No specification for frequencies beyond fcore.

Fpeak, if existent, should be less than 0.05 MHz.

A3. Recommendation for Mobile Systems

The following LC components are recommended. The tables will be updated as o ther suitable

components and specifications are identified.

Table 39. PLL Filter Inductor Recommendations

Inductor Part Number Value Tol SRF Rated I DCR Min Damping R Needed

L1 TDK MLF2012A4R7KT

4.7 µH10% 35 MHz 30 mA 0.56Ω (1Ω ma x) 0Ω

L2 Murata LQG21N4R7K10 4.7 µH10% 47 MHz 30 mA 0.7Ω (+/-50% ) 0Ω

L3 Murata LQG21C4R7N00 4.7 µH30% 35 MHz 30 m A 0.3Ω max 0.2Ω (assumed)

NOTE: Minim um dampi ng resistance is calculated from 0.35Ω – DCRmin. From vendor provided data, L1 and L2

DCRmin is 0.4Ω and 0.5Ω respectively, qualifying them for zero requi red trace resistance. DCRmin for L3 is

not known and is assumed to be 0.15Ω. Products with equivalent specifications may also be used.

Table 40. PLL Filter Capacitor Recommendations

Capacitor Part Number Value Tolerance ESL ESR

C1 Kemet T495D336M016AS

33 µF 20% 2.5 nH

0.225Ω

C2 AVX TPSD336M020S0200

33 µF 20% unknown

0.2Ω

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298517-001 Datasheet 75

Table 41. PLL Filter Resistor Recommendations

Resistor Part Number Value Tolerance Power

R1 Various 1Ω 10% 1/16W

To satisfy damping requirements, total series resista nce i n the filter (from VCCT to the top plate of the

capacitor) must be at least 0.35Ω. This resistor can be in the form of a discrete component, or routing, or

both. For example, if the picked inductor has minimum DCR of 0.25Ω, then a routing resistance of at

least 0.10Ω is required. Be careful not to exceed the maximum resistance rule (2Ω). For example, if

using discrete R1, the maximum DCR of the L should be less than 2.0 - 1.1 = 0.9Ω, which precludes

using L2 and possibly L1.

Other rout ing requir ements i nclude:

• The capacitor should be close to the PLL1 and PLL2 pins, with less tha n 0.1Ω per route (These

rout es do not co unt to wa rds the minimum damping resistance requir ement).

• The PLL2 route should be parallel and next to the PLL1 route (minimize loop area).

• The inductor should be close to the capacitor; any routing resistance should be inserted between

VCCT and the inductor.

• Any discrete resistor should be inserted between VCCT and the inductor.

A4. Comments

• A magnetically shielded inductor protects the circuit from picking up external flu x noise. This

should provide better timing margins than with an unshielded inductor.

• A discrete or routed resistor is required because the LC filter by nature has an under-damped

response, which can cause resonance at the LC pole. Noise amplification at this band, although

not in the PLL-sensitive spectrum, could cause a fatal headroom reduction for analog circuitry.

The resistor serves to dampen the response. Systems with tight space constraints should consider

a discrete resistor to provide the required damping resistance. Too large of a damping resistance

can cause a large IR drop, which means less analog headroom and lower frequency.

• Ceramic capacitors have very high self-resonance frequencies, but they are not available in large

capacitance values. A high self-resonant frequency coupled with low ESL/ESR is crucial for

sufficient rejection in the PLL and high frequency band. The recommended tantalum capacitors

have acceptably low ESR and ESL.

• The capacitor must be close to the PLL1 and PLL2 pins; otherwise the value of the low ESR

tantalum capacitor is wasted. Note the distance constraint should be translated from the 0.1-Ω

requirement.