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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS560200

SLVSC81C –SEPTEMBER 2013–REVISED FEBRUARY 2016

TPS560200 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With

Advanced Eco-Mode™

1 Features

1• Integrated Monolithic 0.95-ΩHigh-Side and 0.33-

ΩLow-Side MOSFETs

• 500-mA Continuous Output Current

• Output Voltage Range: 0.8 V to 6.5 V

• 0.8-V Voltage Reference With ±1.3% Accuracy

Over Temperature

• Auto-Skip Advanced Eco-Mode™ for High

Efficiency at Light Loads

• D-CAP2™ Mode Enables Fast Transient

Responses

• No External Compensation Needed

• 600-kHz Switching Frequency

• 2-ms Internal Soft-Start

• Safe Start-Up into Prebiased VOUT

• Thermal Shutdown

• –40°C to 125°C Operating Junction Temperature

Range

• Available in 5-Pin SOT-23 Package

2 Applications

• Set Top Boxes

• Modems

• DTBs

• ASDLs

3 Description

The TPS560200 is an 17-V, 500-mA, low-Iq, adaptive

on-time D-CAP2 mode synchronous monolithic buck

converter with integrated MOSFETs in easy-to-use 5-

pin SOT-23 package.

The TPS560200 lets system designers complete the

suite of various end-equipment power bus regulators

with a cost-effective, low component count and low

standby current solution. The main control loop for

the device uses the D-CAP2 mode control that

provides a fast transient response with no external

compensation components. The adaptive on-time

control supports seamless transition between PWM

mode at higher load conditions and advanced Eco-

Mode operation at light loads.

The TPS560200 also has a proprietary circuit that

enables the device to adopt to both low equivalent

series resistance (ESR) output capacitors, such as

POSCAP or SP-CAP, and ultra-low ESR ceramic

capacitors. The device operates from 4.5-V to 17-V

VIN input. The output voltage can be programmed

between 0.8 V and 6.5 V. The device also features a

fixed 2-ms soft-start time. The device is available in

the 5-pin SOT-23 package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS560200 SOT (5) 2.90 mm × 1.60 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Schematic

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 4

6.6 Typical Characteristics.............................................. 6

7 Detailed Description.............................................. 7

7.1 Overview................................................................... 7

7.2 Functional Block Diagram......................................... 7

7.3 Feature Description................................................... 7

7.4 Device Functional Modes.......................................... 9

8 Application and Implementation ........................ 10

8.1 Application Information............................................ 10

8.2 Typical Application ................................................. 10

9 Power Supply Recommendations...................... 14

10 Layout................................................................... 14

10.1 Layout Guidelines ................................................. 14

10.2 Layout Example .................................................... 14

11 Device and Documentation Support................. 15

11.1 Device Support...................................................... 15

11.2 Trademarks........................................................... 15

11.3 Electrostatic Discharge Caution............................ 15

11.4 Glossary................................................................ 15

12 Mechanical, Packaging, and Orderable

Information........................................................... 15

4 Revision History

Changes from Revision B (February 2015) to Revision C Page

• Deleted SWIFT™ from the data sheet title ........................................................................................................................... 1

Changes from Revision A (Janurary 2015) to Revision B Page

• Removed note from ENABLE (EN PIN) to indicate that the parameters are production tested ........................................... 5

Changes from Original (September 2013) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

GND

VSENSE

VIN

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5 Pin Configuration and Functions

DBV Package

5-Pin SOT-23

(Top View)

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

EN 1 I Enable pin. Float to enable

GND 2 — Return for control circuitry and low-side power MOSFET

PH 3 O The switch node

VIN 4 I Supplies the control circuitry of the power converter

VSENSE 5 I Converter feedback input. Connect to output voltage with feedback resistor divider

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT

Input voltage VIN –0.3 20

EN –0.3 7

VSENSE –0.3 3

Output voltage PH –0.6 20

PH 10-ns transient –2 20

Source current EN ±100 µA

PH Current limit A

Sink current PH Current limit A

Operating junction temperature –40 125 °C

Storage temperature, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIInput voltage range 4.5 17 V

TJOperating junction temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TPS560200

UNITDBV

5 Pins

RθJA Junction-to-ambient thermal resistance 166.8

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 100

RθJB Junction-to-board thermal resistance 75.5

ψJT Junction-to-top characterization parameter 29.2

ψJB Junction-to-board characterization parameter 3.7

RθJC(bot) Junction-to-case (bottom) thermal resistance 28.7

6.5 Electrical Characteristics

TJ= –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

VIN Operating input voltage 4.5 17 V

VIN Internal UVLO threshold VIN Rising 3.9 4.35 4.5 V

VIN Internal UVLO hysteresis 200 mV

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Electrical Characteristics (continued)

TJ= –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) Not production tested

(2) Measured at pins

VIN Shutdown supply current EN = 0 V, VIN = 12 V 2.0 3.7 9 µA

VIN Operating– non switching supply current VSENSE = 850 mV, VIN = 12 V 35 60 95 µA

ENABLE (EN PIN)

Enable threshold Rising 1.16 1.29 V

Falling 1.05 1.13 V

Internal Soft-Start VSENSE ramps from 0 V to 0.8 V 2 ms

OUTPUT VOLTAGE

Voltage reference

25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 5

mA, Pulse-Skipping 0.796 0.804 0.812 V

25°C, VIN = 12 V, VOUT = 1.05 V, IOUT =

100 mA, Continuous current mode 0.792 0.800 0.808 V

VIN = 12 V, VOUT = 1.05 V, IOUT = 100

mA, Continuous current mode 0.789 0.800 0.811 V

MOSFET

High-side switch resistance(1)(2) VIN = 12 V 0.50 0.95 1.50 Ω

Low-side switch resistance(1) VIN = 12 V 0.20 0.33 0.55 Ω

CURRENT LIMIT

Low-side switch sourcing current limit LOUT = 10 µH, Valley current, VOUT = 1.05

V550 650 775 mA

THERMAL SHUTDOWN

Thermal shutdown 170 °C

Thermal shutdown hysteresis 10 °C

ON-TIME TIMER CONTROL

On time VIN = 12 V 130 165 200 ns

Minimum off time 25°C, VSENSE = 0.5 V 250 400 ns

OUTPUT UNDERVOLTAGE PROTECTION

Output UVP threshold Falling 56 63 69 %VREF

Hiccup time 15 ms

100

200

300

400

500

600

700

800

0.0 0.1 0.2 0.3 0.4 0.5

fsw - Switching Frequency (kHz)

IO - Output Current (A)

C005

VOUT = 1.05 V

VOUT = 1.8 V

VOUT = 3.3 V

0.794

0.796

0.798

0.800

0.802

0.804

0.806

±50 0 50 100 150

VSENSE Voltage (V)

TJ Junction Temperature (ƒC)

C006

IO = 100 mA

±10

0 2 4 6 8 10

EN Input Current (µA)

EN Input Voltage (V)

C003

500

525

550

575

600

625

650

675

700

4 6 8 10 12 14 16 18

Switching Frequency (kHz)

VIN - Input Voltage (V)

C004

IOUT = 500 mA

VOUT = 3.3 V

VOUT = 1.8 V

VOUT = 1.05 V

100

±50 0 50 100 150

ICC - Supply Current (µA)

TJ Junction Temperature (ƒC)

C001

±50 0 50 100 150

Ivccsdn - Shutdown Current (µA)

TJ Junction Temperature (ƒC)

C002

EN = 0 V

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6.6 Typical Characteristics

VIN = 12 V, TA= 25°C (unless otherwise noted).

Figure 1. Supply Current vs Junction Temperature Figure 2. Shutdown Current vs Junction Temperature

Figure 3. EN Input Current vs EN Input Voltage Figure 4. Switching Frequency vs Input Voltage

Figure 5. Switching Frequency vs Output Current Figure 6. VSENSE Voltage vs Junction Temperature

VIN

GND

Drive

XCON

Control

Logic

UVLO

AGND

PGND

Soft

Start

VREF

VSS

SSDONE

VSENSE

VREF

VIN

TON

One-Shot

ZCD

OCP

VREF

PGND

ZCD

VIN

START

VREF

Thermal

Shutdown

Bandgap

Reference

VTHERMAL

BGOK

VREF

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7 Detailed Description

7.1 Overview

The TPS560200 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel MOSFETs.

It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low-

ESR output capacitors including ceramic and special polymer types.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 PWM Operation

The main control loop of the TPS560200 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an

internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal

one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VOUT, to

maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The

one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the

reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need

for ESR induced output ripple from D-CAP2 mode control.

( )

IN OUT OUT

OUT(LL)

OUT IN

V -V ×V

I = ×

2×L ×fsw V

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Feature Description (continued)

7.3.2 PWM Frequency and Adaptive On-Time Control

TPS560200 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS560200 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output voltage to

set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

7.3.3 Advanced Auto-Skip Eco-Mode Control

The TPS560200 is designed with advanced auto-skip Eco-Mode to increase higher light-load efficiency. As the

output current decreases from heavy-load condition, the inductor current is also reduced. If the output current is

reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between

continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when

its zero inductor current is detected. As the load current further decreases the converter run into discontinuous

conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time

increases as it takes more time to discharge the output capacitor to the level of the reference voltage with

smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in

Equation 1.

(1)

7.3.4 Soft-Start and Prebiased Soft-Start

The TPS560200 has an internal 2-ms soft-start. When the EN pin becomes high, internal soft-start function

begins ramping up the reference voltage to the PWM comparator.

The TPS560200 contains a unique circuit to prevent current from being pulled from the output during start-up if

the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft-start

becomes greater than feedback voltage VVSENSE), the controller slowly activates synchronous rectification by

starting the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VOUT) starts and

ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to

normal mode operation.

7.3.5 Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The

switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This

voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,

VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current

decreases linearly. The average value of the switch current is the load current Iout. The TPS560200 constantly

monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.

If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented

per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below

the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching

cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in

the same manner.

There are some important considerations for this type of overcurrent protection. The peak current is the average

load current plus one half of the peak-to-peak inductor current. The valley current is the average load current

minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent

threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the

output voltage tends to fall as the demanded load current may be higher than the current available from the

converter. This protection is nonlatching. When the VSENSE voltage becomes lower than 63% of the target

voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts

after hiccup time.

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Feature Description (continued)

When the overcurrent condition is removed, the output voltage returns to the regulated value.

7.3.6 Thermal Shutdown

TPS560200 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),

the device is shut off. This is nonlatch protection.

7.4 Device Functional Modes

7.4.1 Normal Operation

When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the

TPS560200 can operate in its normal switching modes. Normal continuous conduction mode (CCM) occurs when

the minimum switch current is above 0 A. In CCM, the TPS560200 operates at a quasi-fixed frequency of 600

kHz.

7.4.2 Eco-Mode Operation

When the TPS560200 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS560200

begins operating in pulse-skipping Eco-Mode. Each switching cycle is followed by a period of energy-saving

sleep time. The sleep time ends when the VFB voltage falls below the Eco-Mode threshold voltage. As the output

current decreases the perceived time between switching pulses increases.

7.4.3 Standby Operation

When the TPS560200 is operating in either normal CCM or Eco-Mode, it may be placed in standby by asserting

the EN pin low.

F =

OUT OUT

2 L x Cp

OUT

R1 0.8 V

R2 =

V -0.8V

10µF

10µHL1

10µF

VIN 4.5-17V VOUT 1.05V, 0.5 A

0.1µF

C2 C3

TPS560200

VIN

VSENSE

5GND 2

PH 3

10µF

6.19k

20.0k

open

TPS560200

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS560200 is used as a step-down converter which converts a voltage of 4.5 V to 17 V to a lower voltage.

WEBENCH®software is available to aid in the design and analysis of circuits.

8.2 Typical Application

Figure 7. Typical Application Schematic

8.2.1 Design Requirements

To begin the design process, the user must know a few application parameters:

Table 1. Design Parameters

PARAMETER VALUES

Input voltage range 4.5 V to 17 V

Output voltage 1.05 V

Output current 500 mA

Output voltage ripple 10 mV/pp

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%

tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.

To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to

noise, and the voltage errors from the VSENSE input current are more noticeable.

(2)

8.2.2.2 Output Filter Selection

The output filter used with the TPS560200 is an LC circuit. This LC filter has double pole at:

(3)

OUT

OUT OUT

C (RMS)

IN OUT

V x (V - V )

I12 x V x L x fsw

2 2

OUT

=LPP

L (RMS) OUT

I I + I

LPP

= I +

LPEAK OUT 2

V V

VIN(max) OUT

OUT

= x

LPP V L x fsw

IN(max) OUT

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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal

gain of the TPS560200. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain

rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that

reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the

zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole

of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the

high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the

values recommended in Table 2.

Table 2. Recommended Component Values

Output Voltage

(V) R1

(kΩ)R2

(kΩ)C5

(pF)

(µH) C3 + C4

(µF)

MIN TYP MAX

1.0 4.99 20.0 10 10 + 10

1.05 6.19 20.0 10 10 + 10

1.2 10.0 20.0 10 10 + 10

1.5 17.4 20.0 10 10 + 10

1.8 24.9 20.0 optional 10 10 + 10

2.5 42.2 20.0 optional 10 10 + 10

3.3 61.9 20.0 optional 10 10 + 10

5.0 105 20.0 optional 10 10 + 10

Because the DC gain is dependent on the output voltage, the required inductor value increases as the output

voltage increases. Additional phase boost can be achieved by adding a feed-forward capacitor (C5) in parallel

with R1. The feed-forward capacitor is most effective for output voltages at or above 1.8 V.

The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4,

Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak

current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for

fSW.

Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS

current of Equation 6.

(4)

(5)

(6)

For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The

inductor used is a Würth 744777910 with a peak current rating of 2.6 A and an RMS current rating of 2 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS560200 is intended for

use with ceramic or other low-ESR capacitors. The recommended values are given in Table 2. Use Equation 7 to

determine the required RMS current rating for the output capacitor.

(7)

For this design two MuRata GRM32DR61E106KA12L 10-µF output capacitors are used. The typical ESR is 2

mΩeach. The calculated RMS current is 0.047 A and each output capacitor is rated for 3 A.

V = 50 mV/div (ac coupled)

OUT

I = 200 mA/div

OUT

Time = 200 µs/div

125 mA to 375 mA load step

slew rate = 500 mA / µsec

-180

-120

-60

120

180

-60

-40

-20

100 1000 10000 100000 1000000

Phase - Degrees

Gain - dB

Frequency - Hz

C019

Gain

Phase

±1.5

±1.0

±0.5

0.0

0.5

1.0

1.5

0.0 0.1 0.2 0.3 0.4 0.5

Load Regulation - %

Output Current - A

VIN = 5 V

VIN = 12 V

C017

±0.50

±0.40

±0.30

±0.20

±0.10

0.00

0.10

0.20

0.30

0.40

0.50

4 6 8 10 12 14 16 18

Line Regulation - %

Input Voltage - V

C018

IOUT = 0.25 A

100

0.0 0.1 0.2 0.3 0.4 0.5

Efficiency - %

Output Current - A

VIN = 12 V

VIN = 5 V

C015

0.001 0.01 0.1 1

Efficiency - %

Output Current - A

C016

VIN = 12 V

VIN = 5 V

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8.2.2.3 Input Capacitor Selection

The TPS560200 requires an input decoupling capacitor and a bulk capacitor is needed depending on the

application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF

capacitor (C2) from pin 4 to ground is optional to provide additional high frequency filtering. The capacitor voltage

rating must be greater than the maximum input voltage.

8.2.3 Application Curves

VIN = 12 V, VOUT = 1.05 V, TA= 25°C (unless otherwise noted).

Figure 8. Efficiency Figure 9. Light-Load Efficiency

Figure 10. Load Regulation Figure 11. Line Regulation

Figure 12. Loop Response, IOUT = 0.25 A Figure 13. Transient Response, 25% to 75% Load Step

V = 20 mV/div (ac coupled)

OUT

Time = 2 ms/div

PH = 5 V/div

V = 20 mV/div (ac coupled)

OUT

Time = 1 µs/div

PH = 5 V/div

V = 20 mV/div (ac coupled)

OUT

Time = 5 µs/div

PH = 5 V/div

V = 500 mV/div

OUT

Time = 2 ms/div

EN = 5 V/div

V = 5 V/div

V = 50 mV/div (ac coupled)

OUT

I = 200 mA/div

OUT

Time = 200 µs/div

10 mA to 250 mA load step

slew rate = 500 mA / µsec

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Figure 14. Transient Response, 2% to 50% Load Step Figure 15. Start-Up Relative to EN

Figure 16. Output Ripple, IOUT = 500 mA Figure 17. Output Ripple, IOUT = 30 mA

Figure 18. Output Ripple, IOUT = 0 mA

VSENSE

GND

VIN PH VOUT

VIA to Ground Plane

OUTPUT

INDUCTOR

OUTPUT

FILTER

CAPACITOR

OPTIONAL

FEED FORWARD

CAPACITOR

VIN

FEEDBACK

RESISTORS

TO ENABLE

CONTROL

GND

VIN

HIGH FREQENCY

BYPASS

CAPACITOR

VIN

INPUT

BYPASS

CAPACITOR

GND

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9 Power Supply Recommendations

The TPS560200 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters

require the input voltage to be higher than the output voltage for proper operation. The maximum recommended

operating duty cycle is 65%. Using that criteria, the minimum recommended input voltage is VO / 0.65.

10 Layout

10.1 Layout Guidelines

The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Take care to minimize the

loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical

recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is

closest to the VIN and GND pins of the device. An additional high-frequency bypass capacitor may be added.

See Figure 19 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the

IC. The PH pin should be routed to a small copper area directly adjacent to the pin. Make the circulating loop

from PH to the output inductor, output capacitors and back to GND as tight as possible while preserving

adequate etch width to reduce conduction losses in the copper. Connect the exposed thermal pad to bottom or

internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top-side

copper to the internal or bottom layer copper. The additional external components can be placed approximately

as shown. It may be possible to obtain acceptable performance with alternate layout schemes; however, this

layout produced good results and is intended as a guideline.

10.2 Layout Example

Figure 19. Layout Schematic

TPS560200

www.ti.com

SLVSC81C –SEPTEMBER 2013–REVISED FEBRUARY 2016

Product Folder Links: TPS560200

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Trademarks

Eco-Mode, D-CAP2 are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS560200DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L562

TPS560200DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L562

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Feb-2016

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS560200 :

•Automotive: TPS560200-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS560200DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

TPS560200DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS560200DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0

TPS560200DBVT SOT-23 DBV 5 250 180.0 180.0 18.0

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Feb-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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TPS560200DBVT TPS560200DBVR