Ware ae ere ee Ne Vectron International's TRU-050 module Is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming, frequency translation and clock smoothing applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter performance. This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop Filter Op-Amp, a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2" divided output. The ASIC and quartz resonator are housed in a hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount leads. The VCXO frequency (OUT1) and division factor (OUT2) are factory set in accordance with customer specifications. PLL response is optimized for each application by the selection of three external passive components. Software Is available from Vectron to ald in loop filter component selection and loop response modeling. reatures. Benefits. Tae nner PLL with quartz stabilized VCXO Flexible modular solution MMA Output jitter less than 20 ps Reduce design time PRs Loss of signal (LOS) alarm Increase circuit reliability | RUC RO UL Return to nominal clock upon LOS Less board space 7 Y : Quartz Stabilized Input data rates from 8 kb/s to 65 Mb/s Reduces component count Tn Surface mount option in-state output User defined PLL loop response Whats Inside? NRZ data compatible What Does It Do? How Is It Used? Robust hermetic ceramic package rages J-9 Pages 19-Te Single or +5.0 V supply (+3.3V option available) How Is It Built How Is It Packaged rages 6-11 How Is It Ordered? Page 19 How Does It Perform? Pages 12-14 Vectron International | 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 1 of 17Parameter 7110/0) ee 2) Input NRZ Data Rates . DATAIN 2 0.008 . 65,936 1 MHz Input RZ Data and Clock Rates " | DATAIN + 0.008 + 32.768 ' Miz Nominal Output Frequency 2 2 2 : . For input RZ data, Manchester encoded data, Output 1 2 OUT 1 12.0 . 65.536 : MHz and input clock recovery applications, the Output 2 2 . NUT? 2 0.05 . 32 768 3 V7 output clock must run at two times the input Supply Voltage 3 2 Vn : 15 se! / rate to ensure that the input is clocked 7 3 correctly. Since the output clock has a max- Supply Current (Vp = 9.9 V) 1 a 2 1 03 2 mn imum frequency of 65.536 MHz, these inputs Output Voltage Levels (Vpp = 4.5 V) 2 . 2 : are limited to a maximum rate of 32.768 MHz Output Logic High # . OH . 2.9 . . V - QUT2 is a binary submultiple of OUTI, or Output Logic Low # | tn 1 05 it may be disabled. Franstion Times: 4 ! 2 ! ! _ A 3.3 volt supply option is also available. Rise Time (0.5 Vito 2.5 V . R 3 09 . } : Fall Time (2.5 V to 0.5 V) : (F 1 05S 5 I ns . Figure 1 defines these parameters. Figure 2 Symmetry or Duty cycle 3 1 | ilustrates the equivalent five-gate MTTL yinimety or UY CY : : . load and operating conditions under which utput 7 omM I ! #0 ! OY : these parameters are specified and tested. Output 2 3 SYM 2 1 49 3 7) . Z _ Symmetry is the ON TIME/PERIOD in Necovered Cock 2 cu a percent with Vo = 1.4 V for TIL, per figure 7. Input Data . . 1 . | oo Input Logic High 1 Vy! 29! ! V . Aloss of signal (LOS) indicator is set to a I logic high if no transitions are detected at mput Logic [ow 3 il ! ! Ue ! / DATAIN after 256 clock cycles. As soon Control Voltage Bandwith (-3 dB, VC = 2.50 V) ! BW 0 2 . kHZ as a transition occurs at DATAIN, LOS is Sensitivity @ VC = VO . AF/AVe ! See Figure 11 , ppm/V set to a logic low. Loss of Signal Indication b . Los 2 2 : 7. Accuracy at room temperature. Stability Output Logic righ 1 OH 3 Zo 3 3 V over temperature is typically + 20 ppm. Output Logic Low . Vol 2 2 0.5 : V Nominal Output Frequency on Loss of Signal: / . : : . Output 7 1 OUT 2 79 ppm 2 75 ppm 2 ppm from fo 7 Output 2 . OUT2 : 79 ppm . /5 ppm , ppm from fo 2 Phase Detector Gain ! Kp 2 0,53 x Data Density 3 V/rad lable 1. B60 0 <2 i Lewel Vpn CLK, RDATA |}@ & (7) 5.0V "Level T "c tos eno | =P On Time ) fo mene = 4 Period P].. 0 ov M= 10x Sa (4 | 0.10 LF +t i e i ix Figure 1. = Figure 2. 2 of 1/7 Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.commaton ae eM UE FO OKs ORs eam Ceucmeoni een count, conserve ] Ve Control voltage input to internal voltage controlled crystal oscillator (VCXO). 2 OPN Negative input terminal to internal operational amplifier. 3 OPOUT Output terminal of internal operational amplifier. 4 OPP Positive input terminal to internal operational amplifier. 45 LOSIN With LOSIN set to a logic high, the external input to the VCXO (VC) is disabled and the VCXO returns to it's nominal center frequency. With LOSIN set to logic low, the external input to the VCXO is enabled. The LOSIN input has an internal pull-down resistor. 6 PHO Output signal produced by phase detector. 7 DATAIN Input data stream to phase detector (TLL switching thresholds). 8 GND Circuit and cover ground g CLKIN Input clock signal to phase detector (TTL switching thresholds). 10 LOS Loss of signal indicator is set to a logic high if no transitions are detected at DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS ts set to a logic low. 17 RCLK TTL compatible recovered clock. 12 RDATA TTL compatible recovered data stream. 13 OUI2 Divided version of internal VCXO output clock (TTL). 14 HIZ When set to a logic low, output pins OUT1, OUT2, RCLK, and RDATA buffers are set to high-impedance state. When set to a logic high or no connect, the device functions and output pins OUT, OUT2, RCLK, and RDAIA are active. This input has an internal pull-up resistor. 15 OUTT Output clock of internal VCXO (TTL). 16 ih +5.0 V +10% supply voltage (+3.3 V option available). Vectron International Figure 3. 267 Lowell Road, Hudson, NH 03051 OPE (OY ee} lable 2. and optimize MeO IRA iAH aY lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 3 Of 17Oe eed The TRU-050 is a user-configured phase-locked loop (PLL) integrated circuit. It includes a voltage controlled crystal oscillator (VCXO), an operational amplifier, a phase detector, and additional integrated functions for use In digital synchronization applications. [hese applications include timing recovery and data pulse restoration for data signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis. aR am UT [RU-050 Elements eRe (a Cans IOUS O Nem AMON IT MUR RLM Aa) conditions, and is nominally 2.5 Volts. The phase error (which ts typically a pulse for digital phase detectors) is converted to a DC level, making it easy to design em OU CE Preset Detctre Oueut OC. Signed Aoportond t Detetlock Aiese Grov. LOS: LOE IA Compliment Quiput High afer 2o6 Gok Cycles [pin 3) wh oo input Trenerions [pint } na ile We the LOS LOS Compliment hputhghs6 VOCRO & Cente Peqency (4495 pom] Diude Greut Opionel 2? MW Oude Croutte Frequency Trenton oo FE Oopiatons [RU-050 take to detect sop Fite Cp sp: Forcive leap Fite a loss of signal? If there are no transitions on p h ase De [ eC [ OF DAIAIN for a period of 256 clock The phase detector is designed to accept an NRZ data stream at DATAIN (Pin 7- refer to figure 5), but may be used SRR for clock signals and other data types. The input buffers are designed to switch at a TTL switching threshold of 1.4 V. LOS is reset to logic 0 as soon as - Ihe phase detectors Inputs are: there are DAIAIN transitions. + DATAIN (Pin 7) - the input clock or NRZ data signal CLKIN (Pin 9) - the clock signal feedback from the VCXO output OUT or OUT2 And the outputs are: RCLK (Pin 11) - the regenerated clock signal RDATA (Pin 12) - the retimed data signal PHO (Pin 6) - the phase detector output LOS (Pin 10) - a loss of signal detector The phase relationship between the regenerated clock signal, RCLK (Pin 11), and the regenerated data signal, RDATA (Pin 12), is shown in figure 6. 4 of 1/7 Vectron international 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.comPHO 8 =6OPN) 86 OPT Wr. Pine) (Pinz) (Pn) (Pin) LOS (Pin 10} LOSIM (Pin 5} Bante] Soe EE ER aE a BAU Bh Ea @- OUTS (Pin 13) a pee eee cekesecass UM ofa o's o's o's oe 8 Sree eae . RCLK ADA OP GN Wy He Figure 5. init) (Pn 12) Pind) (An) ([(An16) [Pin #8) nO ae cuning | LP LPL EP LILI manufactured? The falling edge of RCLK Is coincident with the center of the regenerated NRZ RDAIA pulse. Figure 6 shows a 1010 data stream with a 100% data transition density. In RaKEPintty | FE | | | ri} yt [yd RIOR OSORT general, this will not be the case and input RDATA(Pin 12] VOPR pata 3 | data will have fewer data transitions. Phase . figment Figure 6. EASA OOM IA However, the phase detector will still seek BG (CO moe to align the falling edge of the RCLK signal with the center of each RDAIA pulse. WE KSMn OORTTOMA EAS For applications where the input clock or data signal, DATAIN, is very low in frequency (<200kHz), clock information may pass through the phase detector because of its finite low pass characteristic. In applications 0) 000 clean such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to the VCXO input. Please contact Vectrons Applications Engineering staff for further detail. (O0IS mY leaaing CUOMO DATAIN (Fin #} CLEIN - automation equip: Relative Phase (,) MORON Ace ANYCOOL Figure /. asin <5! 9m Gain Slope = 5 Volts /2 7 Figure 8. Phase Detector Gain Calculation The schematic diagram (figure 7) shows a simplified representation of the phase detector's basic error generation function. The actual circuit is more complex and includes circuitry to reduce the IRU-050's dependence on input data duty-cycle. In general, the [RU-O50 Is insensitive to duty cycle and duty cycle changes. This circuit provides a output (Vp) DC level which is proportional to the relative phase of DATAIN (Pin 7) and CLKIN (Pin 9). A plot of the output (Vp) versus relative phase is shown in figure 8. The slope of the output (Vp ) versus relative phase (0) is SV/27. The phase detector block also includes an output gain stage which should be considered when calculating the gain of the complete phase detector block. This gain stage has a gain of 2/3, and converts the differential signal to a single-ended DC output. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 5 of 17DATAIN > Gain =SV 2 0 Gain = 2/3 Pin?) Figure 9. 5 3 20k | 30k ) c ! PHO : Pin Phase Detector Gain = [5V/2n] * [2/3] *D = 0.53 * D Where D = input data transition density. For example D = 1 for 100% transition density (e.g., clock signal) and D = 0.5 for 50% transition density (e.g., balanced NRZ data). LOS and LOSIN The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is set logic high after 256 consecutive CLKIN periods with no DATAIN transitions. This signal can then be used to either flag external alarm circuits and/or drive the TRU-050's LOSIN circuit. When the LOSIN input is set logic high, the loop filter op-amp output Is set mid supply to facilitate fast lockup when DAIAIN ts restored. In addition, the VCXO control voltage Is internally set to hold the VCXO at its nominal frequency (+75 ppm). When LOSIN is low or has no connection, the VCXO's control voltage input is enabled (LOSIN has an internal pull-down resistor). Loop Filter Although various loop filter configurations may be considered, most TRU-050 applications use the basic integrator filter of figure 10. This type of filter provides high DC gain to ensure proper clock and data alignment. The ratio of R1 to RF sets midband gain and can be used to adjust the loop bandwidth. Ihe time constant, set by RF and CF, should be selected to be about one decade below the open loop bandwidth to provide good phase margin. he reference for the non- CF | | ft G1 (Pin 41) inverting input is set at midsupply by R2 and R3. Software Is available to help in the selection of R1, CF and RF. Figure 10. Rd RS 6 of 17 Vectron International | 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com! Figure 11. FREQUENCY (ppm from fo) UE AY EIST CONTROL VOLTAGE (Vc) In addition to [RU-050 VCXO Frequency Deviation vs. Control Voltage AYA TES IAM LG} VCXO EUS The TRU-050's VCXO Is a varactor-tuned crystal oscillator which produces an output frequency controlled by a control consists of a few voltage, V-. The tracking range of the VCXO is specified as absolute pull range (APR) when ordered. An APR of +50 | | ppm guarantees that the [RU-050 can track an input source frequency with +50 ppm stability over all operating ely eel al) conditions, incluaing temperature, time, power supply and load variations. Ihe value of Me IS varied petween 0.5 robust com 1 onents: to 4.5 V to achieve the specified APR. A typical frequency versus V,. curve for the VCXO in the TRU-050 Is shown in figure 11. When designing PLLs, the VCXO gain (kV in Hz/V or rad/Vs) is an important parameter. As a rule of quality emia thumb, the frequency deviation for the IRU-050 VCXO Is 300 ppm over the 1 V to 4 V range Vp. assured by advanced For example, a 10 MHz VCXO has an average gain of 1000 Hz/V. The peak value of kV is about twice this value at approximately 2.5 V, and one half this value at 1 V and 4 V. KATA vata eeliaTe For many loop calculations, the gain is expressed in rad/Vs which would be 27 (100 ppm * fo/Vs) for the and fully ETE previous example. Aan, Oscillator Aging Any crystal stabilized oscillator typically exhibits a small shift in output frequency during aging. Ihe major factors which lead to this shift are changes In the mechanical Stress on the crystal and mass-loading of foreign material on the crystal. As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the crystal mounting arrangement can lead to frequency variations. Vectron has minimized these two effects through the use of a miniature Al-cut strip resonator crystal which allows a superior mounting arrangement and results in minimal relaxation and almost negligible environmental stress transfer. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com / of 17Mass-loading on the crystal generally results in a frequency decrease and Is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-hermetic package. Vectron has minimized the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number of internal components through the use of ASIC technology. Under normal operating conditions with an operating temperature of 40C, the IRU-O50 will typically exhibit 2 ppm aging in the first year of operation. Ihe device will then exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter. MELINA OTTO aL more detail? APR Is the guaranteed frequency error (in ppm) the VCXO can track. This takes the guesswork out of the total pull range which drifts and Is affected by UVM let VO omy) (mop Mn Oe Cmax (ctm OI pull range over the operating (UVa aC mL AOm eee of the most reliable devices on Mee TF ee Tas between OQUT1 and OUT2? QUIT is the direct output from the VCXO and Is limited to frequencies in the 12 MHz to 65 MHz range. QUT2 is an optional 2" divided VCXO output. The divide ratio is FO AS aa ee a Tine) 6} 8 of 17 Vectron International Absolute Pull kange Absolute pull range (APR) is specified by the fourth character of the product code (see figure 26). APR is the minimum guaranteed frequency shift from fq over variations in temperature, aging, power supply and load. Both irequency and environment limit the specified APR. The total pull range for the VCXO contained in the [RU-050 is typically between 200 ppm and 400 ppm. A 50 ppm APR IRU-050 fully tracks a 50 ppm source oscillator or any other 50 ppm reference over the operating temperature range, life of the product, power supply and measurement variations. Output Divider Circuit An internal 2" divided output is available at OUT2. The value of n varies from 1 to 8 and is set during manufacture. Ihis provides divide ratios from 2 to 256. A no output option may also be selected to minimize power usage and jitter. Divider Note: The frequency of OUT is the fundamental frequency of the VCXO used in the TRU-050. The lowest frequency VCXO (OUT1) available in the TRU-050 is 12 MHz, and the highest frequency is 65.536 MHz. [herefore, the frequency range of OUTT is between 12 MHz and 65.536 Mhz. Since OUI2 Is a division of QUTT and can vary from OUTI = 2 to OUTT = 256, OUT2 ranges from 46.875 kHz (12 MHz = 256) to 32.768 MHz (65.536 MHz = 2). Lower frequency inputs may be supplied to the phase detector of the TRU- 050, but an external divider in the feedback loop is required. With an external divider in the feedback loop, clock and data signals down to & kHz can be used as phase detector inputs. 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.comhandling Precautions nM Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure cd ng handl ackaged? to electrostatic discharge (ESD) during handling and mounting. Vectron employs a human body model (HBM) and a iY g charged device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the mode. Although no industry-wide standard has been [he GH OG Is fa adopted for CDM, a standard HBM (resistance = 1500 2, capacitance = 100 pF) is widely used and therefore can bust oraduct be used for comparison purposes. The HBM ESD threshold presented here was obtained using these circuit parameters. ed en Y ee WAS er (a0) MODEL VIOLA Sr rea Ce Charged Device 2000 V Me ELRC OR The Human Body 2000 V It is MELE ae * MIL-STD-883D, Method 3015, Class 1 lable 3. SV Ac Clem Ui Ue a ete CUNO eMt al ecliN sealed for long term EI ARO UOT IACMR and surface mount terminals and an extended temper- ature range. ape OM Ccom e000 eI Orel Ze) (0) Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 9 of 17How Does It Perform? A typical PLL \s illustrated in figure 12. Be advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are based on ideal systems. such equations may not be accurate for real systems with nonlinearities, DC offsets and noise. A PLL Is a feedback system which forces the output frequency to lockin both phase and frequency to the fundamental frequency of the input signal. When Initially out of lock, the output of the phase detector Is proportional to the difference in frequency between the two phase detector inputs. Inis beat note varies the Output frequency of the VCXO, and in a properly designed phase-locked loop, the loop action forces V; to the correct value to bring the system into lock. Phase-Locked Loop FIgUI e717, lat ets RGLK RDATA tt DATAIN Phase Detector Divide idee Phase Locked Loop Block Diagrarn | OUTPUT A designer's primary concern Is to select a loop filter that ensures lockin and stability, while providing adequate filtering of Input signal noise or jitter. An initial design starts with a Known DAIAIN signal and an output specification. An initial analysis of the open loop gain response provides Insight into the response of the system. Using figure 12, the open loop gain Is: G(s) Kp kV AV(s) SN Where: Kp Is the phase detector gain in V/rad (-0.53 x Data Density). kV is the VCXO gain constant in Rad/Vs. AV(s) ts the loop filter transfer function. N is the divide ratio. 1/s converts the VCXO frequency output to a phase output. The open loop gain may be plotted and varied using the SPICE model provided in figure 13. The gain, frequency, and loop filter configurations may be varied to producedesired responses. In the first-order phase-locked loop, where AV(s) and N equal 1, the gain curve has a 20 dB/decade slope with unity gain at: pr. KV Kp where kV is in rad/Vs. 27 10 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.comThe first-order open loop gain has a constant phase shift of 90 degrees. However, other frequency poles are present in the loop due to the op-amps limited bandwidth and gain, the phase detector and the VCXO modulation bandwidth (these poles are included in the SPICE model). The loop's bandwidth is approximately equal to the closed loop bandwidth and can be used to assess the stability, lockin range and filtering characteristics of the loop. The loop acts as a bandpass filter centered at the clock frequency, just as if a tank circuit were used to filter the input clock or data stream. however, the filter Q of the [RU-O50 Is much greater than that of a tank circuit and typically ranges from 1,000 to 20,000. Ihe PLL tracks Input phase jitter inside the loop bandwidth while jitter Is attenuated outside the loop bandwidth. Converting the SPICE model (figure 13) to a closed loop illustrates the jitter transfer function shown in figure 15. In general, the PLL rapidly locks those signals with an initial frequency difference (relative to CLKIN) that IS within the loop s banawiath. Lockin time ts longer for lower bandwidth loops and may be degraded Dy jitter or by poor input duty cycle. Simulated Results Ihe SPICE model just described can be used to determine the component values necessary to produce a desired loop fiiter bandwicth, its jitter transfer function and its open loop response for a given application. Alternatively, simulation results can be obtained using Vectron's |RU-050 Loop rilter Calculation software. Ihis software runs from DOS and will also provide the user with loop filter component values R1, RF and CF (see figure 15) based on desired loop filter Dandwidth, data type, data density, damping factor and data frequency. For assistance with your specific application, or to receive a copy of Vectrons IRU-O50 Loop Filter Calculation software, please contact Vectron's Application Engineering staff. Fie Fit RF. cr CS 1 : 3 4 B atek ac oS AB a 12 - Unjind o 11 i Ele) C1 CJ) e2 Et = es) | Cd + esd. e AUT ac PHOSE De EC TOR DOOPFILTER 700 RODEL TN=025 F1= Summa ton B= OPAMP Chin FSCS) ES Nel C1 Medel dc Gain = 10,000 = d Altr RS, CA Wbdeb " PLRESCF Corel lh ee tee oe RE Gain Fla Gain in reds Gein = 053% Dat ne Figure 13. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com SPICE Model *kKXAKKTRUOSO ac Loop Model v1 1 O ac l ri 10 lk *kKKKKXPhase Detector eh 2 OLOI (for closed loop response use: e, 2 O11 le bh) re 2 3 30k cl 3 0 bLOp *kxkxkKKPhase Detector Gain 0-53 * Data Density e? 4030 -cbS *KX *kKKKKKLOOD Filter rl 4 5 10k ce 5 O 10p rF 5 & 4Ok cP & ? -bu e3 ? O 5 O-1L0000 KKKKKKVCXO *xkKKKXINDUt Bandwidth = 50 kHz rS ? & LbOk c4 4 0 20p *KKKKKVCXO Gain 27 HZ/V *KXKXXEXample LOO ppm x 30-?2 MHz * 2 *T ef 9 0 4 O 15300 *KKKKK]L/S Model rb 9 10 1000 c5 10 11 -OU1 e5 ll O 1U O-leb *kKKKKKXDivide by N eb l?e O 110 1 r6 ile O lk 11 of 17Phase margin is 47-0 at 1000-0 Hz Open loop gain margin is -3-9ee+01 at LOOO0-0 Hz Closed loop jitter bandwidth (-3 dB) is 1500 Hz- The maximum value of the closed loop gain is O-11b14 dB at a frequency of 65-000 Hz Damping factor = 4.0 RL = 13-5 k ohm RF = ?9-6 k ohm CF = 0-10 IF Data density = 1002 VCXO FRE@ = 32-?b& MHz Feedback divider = 4 12 of 17 Vectron International SPICE Simulated Results L 50) _ a oo OPER LOOP Gal (dB) Ln o Open Loop Response L0 LOOO Frequency (Hz) Closed Loop Response CLOSER LOOP GAIN {dB} U 267 Lowell Road, Hudson, NH 03051 3cefbd MAZ YOR -450 PH ASE 00 ih P 120 i al . 1,40 Figure 14. 4-06 MHz Feedback Loop| TRU-OS0-6CCF ia Oe CLOSER LOOP GAIN LO LO00 Frequency (Hz! lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com LOS Figure 15. OPEN LOOP PHa se (DEGREES }How Is It Used? Applications Ihe three key applications for the IRU-050 are clock recovery of digital data, frequency translation and clock smoothing. Ihese timing needs are required by a wide variety of markets such as telecommunications, datacommunications, digital video and audio, telemetry, test equipment and sensing. Clock Recovery and Data Retiming The TRU-050 was designed to recover a clock imbedded in an NRZ data signal, and retime it with a data pattern. In this application, the VCXO frequency is exactly the same as the NRZ data rate and the outputs are taken off Pin 11 (Recovered Clock) and Pin 12 (Recovered Data). The diagram below shows a typical circuit. Figure 17 shows the relationship between DATAIN (Pin 7) and CLKIN (Pin 9) under locked conditions. The rising edge Ki Werntg Onl | s) 4 uaa of the CLKIN Is centered to the DAIAIN pulse. PHO OPN OPOLT Ve. ah Pin6) (Fin?) (Pn 3) (Find) | LOSIN (Fin 4) Yes! Vectron 61840 Mis MRZ | 0 1.84 Mee DATAIN Pin 7) F Be > OUTI (Pin 15 WTS CUMS Fed ercem OMe _ ees 9001 in October 1996. 41.940 Wee CLKIN (Fin 9) ROLE (Fin 11) RDATA (Fin 12) Figure 16 Relationship of RCLK (Pin 11) and RDATA (Pin 12). The falling edge of the Recovered Clock is in the middle of the data pattern and should be used to clock the data into the next part of the circuit. Ihere is a one and a half cycle delay (frequency of Pin 9) between DATAIN and RDATA. Therefore a 10 MHz signal would have a 150 nS delay between DATAIN and RDAIA plus additional circuit delays, which are typically 9 ns. DATAIN Data 1 3 oun LL RDATA ed Selock cycles +| Daal LJ | ___ ROLE EL LLL LI Figure 17. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 13 of 1714 of 17 RDAIA 16.000 ns 31.0000 ns 46.0000 ns Lye Diagram for TRU-050 @ 51.84 MHz Ihe falling edge of RCLK TTT scr wit espe Se oon A Ch. 1 Ch. 2 Timebase Vectron International 1.000 1.000 3.000 Volts/div Offset = 9/6.2 + mvVolts Volts/div Offset = 951.2 mvVolts ns/div Delay = 16.0000 ns Figure 16. liming Recovery Using OUI2 ue to the limitations in crystal size, the lowest frequency from QUIT Is 12 MHz. For applications below this frequency, the internal divide-by can be used (Note: an additional external divide-by can also be used). An application for 1.544 Mhz clock recovery |s shown in figure 19. PHO OPN OPOUT Ve (Finb) (Pin?) (Fin3) [Fin 1} LOS mi LOSIN (Fin 3) --- {}--(+---- 1544 Mhis NRZ 24.704 MHE DATAIN (Fin 7) 2 OUT1 (Pint 4) > 1.544 NHe OUT! (Fin 13) 1 544 MHe CLEIN (Fin 4) a al aaa FF F RCLK (Fin 11) RDATA(Pin 12) Figure 19. rrequency Iranslation The IRU-O50 Is most commonly used for frequency translation. For example, in a telecommunications application, when a 2.048 Mhz reference clock Is multiplied to 32.768 Mhz, a very clean 32.768 Mhz clock would then be output to other circults. Generally, the IRU-O50 Is specified in terms of NRZ input. Since the IRU-050's phase detector was designed for NRZ data, other inputs such as a clock signal should be considered as an equivalent 1010...NRZ pattern. 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.comIf the DAIAIN input to the phase detector is a clock signal, the VCXO, or the divided VCXO output fed back to CLKIN, must be twice the DATAIN rate. In figure 20, the 2.048 MHz system reference clock can be treated as a 4.096 Mhz NRZ data stream with a data density of 100%. Therefore, the feedback frequency in the PLL would be 4.096 Mhz (the 32.768 MHz clock frequency divided by 8). PHO OPN OPOUT Vie | LOS (Fin "| Pin6) (Fin?) (Pin 3) (Pin't) | LOSIN (Pin 5 T(40 ht: eeeeeeedisstsaeseeeaee secre cies ces se 99 769 Mie DATAIN(Pin f) & ei OUT) (Pin 15 | 4()96 Ke CLKIN (Fin 9} OUT2 (Fin 13: a RCLE (Fin TT) DATA (fin 12) Figure 20 YU eee UL FIXYA GI Mees | rr re 2768 ot LLL LLL Absolutely! Just call The Timing diagram above shows a 2.040 MHe clock input being translated to 32.720 MH clock output. iF ten Vaeelt J Figure 21. Another example would be to translate 8.000 khz to 51.840 Mhz. PHO OPN OPOUT Ye oT Pi (Pin 6) (Pin?) (Pin 3) [Pind] LOSIN (Pin 5] 0 non Le He See i. 5 | . . Ai) iH DATAINM [Pin #) OWT) [Pin 15) 3.240 WH 16.00 kHz OUT2 [Pin 13) GLEIM [Pin 3] Bate oe ati te Figure 22. Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 15 of 17For applications where the DATAIN is very low in frequency (roughly <200 kHz), clock information may pass through the phase detector because of its finite low pass characteristics. In applications such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to the VCXO input (note the capacitor to ground in figure 22). Please contact Vectrons Applications Engineering staff for further detail Clock Smoothing Example Ihe third common application of the IRU-050 Is for the Regeneration or Smoothing of a degraded Input clock signal. In this application, the IRU-O50 accepts a degraded input clock signal and regenerates the signal to square up the rising and falling edges and remove unwanted jitter. The output is then a clean quartz locked representation of the degraded input signal. Figure 23 illustrates a common example of a clock signal regeneration application. In this example, a degraded 16.384 Mhz clock signal is smoothed using the TRU-050. The 16.384 MHz clock is fed into DATAIN (Pin 7). The signal is then regenerated, and a smoothed representation of the signal is available at RDATA (Pin 11). It is important to note that the signal fed back from OUT1 (Pin 15) to CLKIN (Pin 9) is twice the frequency of the degraded input signal at DATAIN (Pin 7). This is because the IRU-O50 was originally designed for input NRZ data patterns. Since an NRZ data pattern has one transition per bit, and Its associated clock has two transitions per bit, the TRU-050 phase detector requires twice as many transitions at CLKIN (Pin 9) when compared to DAIAIN (Pin 7). In the case of an input clock signal, CLKIN (Pin 9) must be twice the frequency of DATAIN (Pin 7). For a 16.384 MHz clock smoothing application, a TRU-O50 with a 32.768 MHz OUT should be specified. PHO OPA OPOUT = Vf. LOS (Pm 10) Pine) (Pn2) (Pins) (Pini) LOSIN (PM 5) ---O-4--4----4}-4-4+---. 16.364 MHz : 32.765 MHe2 , i OUT1 (Pints DAT AN (Pin 7) pe (Pints J $2,768 MHZ r CLKIN (Pin 9) | 16.384 MHz 240 07 ON | | | OUT (Pin 13} I 52.76% MHZ 16.3% MHz RCLK (Pini) ROATA(Pin 12) 16.354 MHz] Degaded DAT AIM [Pir 77] fF LF VL Le Input Chock RDATS (Pin iz) > Pely Output Clock Figure 23. 16 of 17 Vectron International 267 Lowell Road, Hudson, NH 03051 lel: 1-88-VECTRON-1 e-mail: vectron@vectron.comHow Is It Packaged? TRUOSO 1, LCA0, Oo 1.o40 (25.0 20 ane ene0t 1.17005 3 T0005 ne T0135] TRUOS0 6.0 LA o 1.040 (25.5 20 P| | ! eT How Is It Ordered? TRUO50 TL B C C A 51.840 12.960 | L OUT 2 Frequency OUT 1 Frequency Version Number Package Type 16-Pin Ceramic Dip Absolute Pull Range Leads C +20 ppm T Thru-Hole F +32 ppm G Surface Mount G +50 ppm H +100 ppm Second Output Temperature Range (C) A Divide by 2 E Divide by 32 C 0 to 70 B Divide by 4 F Divide by 64 L -40 to 85 C Divide by8 G Divide by 128 D Divide by 16 __H Divide by 256 K OUT2 Disabled Vectron International 267 Lowell Road, Hudson, NH 030517 Figure 25. Figure 24, Questions? GNI eh 1-88-VECTRON-1 3102010 rara25) Surface Mount 19 he nee J O55 = 005 [i4atl. B] Mil 005 0 Hall BY Standard frequencies* (MHz) Using OUT1 12.032 12.288 12.624 13.824 16.000 16.128 16,384 16.777 16.896 17.920 18.432 18.936 20.000 20.480 22.1184 22.579 24.576 24.704 25.000 25.248 + 28.000 30.720 32.000 32.768 33.330 34.368 + 38.880 40.000 41.2416 41.943 44.736 47.457 49.152 49.408 50.000 51.840 65.536 19.440 40.960 Standard frequencies * (MHz) Using OUT2 1.000 1.024 1.544 2.048 3.088 3.240 4.032 4.096 4.1925 4224 5592 6.016 6144 6312 6.480 6912 7.680 8000 8192 8448 8.960 9.486 9.720 10.000 10.240 11.0592 12352 12.500 12.960 14.000 16.000 16.384 16.665 19.440 20.000 20.6208 20.9715 22.368 23.7285 24.576 24.704 25.920 32.768 Other frequencies available upon request. lable 4. lel: 1-88-VECTRON-1 e-mail: vectron@vectron.com 17 of 17