12-Bit, Integrated, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
ADV7403
Rev. SpA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Four Noise Shaped Video® 12-bit ADCs sampling up to
140 MHz (140 MHz speed grade only)
12 analog input channel mux
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan support
720p-/1080i-component HDTV support
Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)
(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range (−40°C to +85°C)
12-bit 4:4:4/10-/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
VBI data slicer (including teletext)
APPLICATIONS
LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receiver
GENERAL DESCRIPTION
The ADV7403 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-video into a digital ITU-R BT.656
format. The ADV7403 also supports the decoding of a
component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
1250i, and many other HD and SMPTE standards. Graphic
digitization is also supported by the ADV7403; it is capable of
digitizing RGB graphics signals from VGA to SXGA rates and
converting them into a digital RGB or YCrCb pixel output
stream. SCART and overlay functionality are enabled by the
ADV7403’s ability to simultaneously process CVBS and
standard definition RGB signals. The mixing of these signals is
controlled by the fast blank pin.
The ADV7403 contains two main processing sections. The first
is the standard definition processor (SDP), which processes all
PAL, NTSC, and SECAM signal types. The second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For more specific
descriptions of the ADV7403 features, see the Detailed
Functionality and Detailed Description sections.
ADV7403
Rev. SpA | Page 2 of 24
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Electrical Characteristics ................................................................. 4
Video Specifications ......................................................................... 6
Timing Characteristics..................................................................... 7
Analog Specifications....................................................................... 8
Absolute Maximum Ratings............................................................ 9
Stress Ratings ................................................................................ 9
Package Thermal Performance................................................... 9
Thermal Specifications ................................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Timing Diagrams............................................................................ 12
Detailed Functionality ................................................................... 13
Analog Front End....................................................................... 13
SDP Pixel Data Output Modes ................................................. 13
CP Pixel Data Output Modes ................................................... 13
Composite and S-Video Processing......................................... 13
Component Video Processing.................................................. 14
RGB Graphics Processing ......................................................... 14
Digital Video Input Port............................................................ 14
General Features......................................................................... 14
Detailed Description...................................................................... 15
Analog Front End....................................................................... 15
Standard Definition Processor ................................................. 15
Component Processor ............................................................... 15
Pixel Input/Output Formatting .................................................... 17
Recommended External Loop Filter Components.................... 19
Typical Connection Diagram ....................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
9/05—Rev. Sp0 to Rev. SpA
Deleted EDTV.....................................................................Universal
Added AVR Receiver to Applications Section.............................. 1
Change to Crystal Normal Frequency Typ Value in Table 3 ...... 7
Changes to Figure 2 ....................................................................... 10
Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11
Change Pin 70 Type........................................................................ 11
Change to Crystal MHz Unit Value ............................................. 13
Added Pixel Input Information to Table 9 and Table 10 ........... 17
Changes to Figure 9........................................................................ 20
4/05—Revision Sp0: Initial Version
ADV7403
Rev. SpA | Page 3 of 24
FUNCTIONAL BLOCK DIAGRAM
INPUT
MUX
DATA
PREPROCESSOR
DECIMATION
AND
DOWNSAMPLING
FILTERS
STANDARD DEFINITION PROCESSOR
LUMA
FILTER
OUTPUT FIFO AND FORMATTER
AIN1
TO
AIN12
ADV7403
SERIAL INTERFACE
CONTROL AND VBI DATA
SCLK
SDA
ALSB
SYNC
EXTRACT
20
HS
8
8P29–P20
P19–P10
P9–P0
PIXEL
DATA
VS
FIELD/DE
LLC1
SFL/
SYNCOUT
CVBS
S-VIDEO
YPrPb
SCART–
(RGB + CVBS)
GRAPHICS RGB
12
CHROMA
FILTER
CHROMA
DEMOD
F
SC
RECOVERY
INT
LUMA
RESAMPLE LUMA
2D COMB
(5H MAX)
RESAMPLE
CONTROL
CHROMA
RESAMPLE CHROMA
2D COMB
(4H MAX)
FAST
BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
FB
Y
Cb
Cr
VBI DATA RECOVERY
MACROVISION
DETECTION STANDARD
AUTODETECTION
CVBS/Y
C
Cb
Cr
Cb
Y
COLORSPACE
CONVERSION
CVBS
Cr
8
COMPONENT PROCESSOR
SCLK2
SDA2
SSPD STDI
SYNC PROCESSING AND
CLOCK GENERATION
DCLK_IN
DE_IN
HS_IN
VS_IN
SOG
SOY
DIGITAL INPUT
PORT
DVI or HDMI
XTAL XTAL1
24
8
8
8
DIGITAL
FINE
CLAMP
GAIN
CONTROL OFFSET
CONTROL AV CODE
INSERTION
30
12
12
12
12
12
12
12
ACTIVE PEAK
AND
AGC MACROVISION
DETECTION CGMS DATA
EXTRACTION
P40–P31
P29–P20
P11–P10
P1–P0
12
A/DCLAMP ANTI-
ALIAS
FILTER
12
A/DCLAMP ANTI-
ALIAS
FILTER
12
A/DCLAMP ANTI-
ALIAS
FILTER
12
A/DCLAMP ANTI-
ALIAS
FILTER
05431-001
Figure 1.
ADV7403
Rev. SpA | Page 4 of 24
ELECTRICAL CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, a otherwise noted.
Table 1.
Parameter1, , 2 3 Symbol Test Conditions Min Typ Max Unit
STATIC PERFORMANCE4, 5
Resolution (each ADC) N 12 Bits
Integral Nonlinearity INL BSL at 27 MHz (at a 12-bit level) ±2.0 ±8.0 LSB
Integral Nonlinearity INL BSL at 54 MHz (at a 12-bit level) −2.0/+2.5 LSB
Integral Nonlinearity INL BSL at 74 MHz (at a 10-bit level) ±1.0 LSB
Integral Nonlinearity INL BSL at 110 MHz (at a 10-bit level) −3.0/+3.0 LSB
Integral Nonlinearity INL BSL at 135 MHz (at an 8-bit level)6 ±1.3 LSB
Differential Nonlinearity DNL At 27 MHz (at a 12-bit level) −0.7/+0.85 −0.99/+2.5 LSB
Differential Nonlinearity DNL At 54 MHz (at a 12-bit level) −0.75/+0.9 LSB
Differential Nonlinearity DNL At 74 MHz (at a 10-bit level) ±0.75 LSB
Differential Nonlinearity DNL At 110 MHz (at a 10-bit level) −0.7/+5.0 LSB
Differential Nonlinearity DNL At 135 MHz (at an 8-bit level)6 −0.8/+2.5 LSB
DIGITAL INPUTS
Input High Voltage7VIH 2 V
Input Low Voltage8VIL 0.8 V
Input High Voltage VIH HS_IN, VS_IN low trigger mode 0.7 V
Input Low Voltage VIL HS_IN, VS_IN low trigger mode 0.3 V
Input Current IIN Pins listed in Note 9−60 +60 μA
All other input pins −10 +10 μA
Input Capacitance10 CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage11 VOH ISOURCE = 0.4 mA 2.4 V
Output Low Voltage11 VOL ISINK = 3.2 mA 0.4 V
High Impedance Leakage Current ILEAK Pins listed in Note 12 60 μA
All other output pins 10 μA
Output Capacitance10 COUT 20 pF
POWER REQUIREMENTS10
Digital Core Power Supply DVDD 1.65 1.8 2 V
Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA
Graphics RGB sampling at 135 MHz 137 mA
SCART RGB FB sampling at 54 MHz 106 mA
Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA
Graphics RGB sampling at 135 MHz 19 mA
PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA
Graphics RGB sampling at135 MHz 12 mA
Analog Supply Current13 IAVDD CVBS input sampling at 54 MHz 99 mA
Graphics RGB sampling at 135 MHz 242 mA
SCART RGB FB sampling at 54 MHz 269 mA
Power-Down Current IPWRDN 2.25 mA
Green Mode Power-Down IPWRDNG Sync bypass function 16 mA
Power-Up Time TPWRUP 20 ms
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.
ADV7403
Rev. SpA | Page 5 of 24
4 All ADC linearity tests performed at input range of full scale − 12.5%, and at zero scale + 12.5%.
5 Max INL and DNL specifications obtained with part configured for component video input.
6 Specification for ADV7403KSTZ-140 only.
7 To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIH on Pin 38 = 1.2 V.
8 To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIL on Pin 38 = 0.4 V.
9 Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 78, 79, 83, 84, 87, 88, 95, 96, 97, 100.
10 Guaranteed by characterization.
11 VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
12 Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45.
13 Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1, and ADC2 powered up only, for SCART FB, all ADCs powered up.
ADV7403
Rev. SpA | Page 6 of 24
VIDEO SPECIFICATIONS
@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 2.
Parameter1, , 2 3 Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated 5 step 0.4 degree
Differential Gain DG CVBS input, modulated 5 step 0.4 %
Luma Nonlinearity LNL CVBS input, 5 step 0.4 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 61 64 dB
SNR Unweighted Luma flat field 64 65 dB
Analog Front End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40 70 Hz
FSC Subcarrier Lock Range ±1.3 kHz
Color Lock in Time 60 line
Sync Depth Range4 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 field
Horizontal Lock Time 100 line
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 degree
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.4 %
Chroma Phase Error 0.3 degree
Chroma Luma Intermodulation 0.1 %
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 1 V input 1 %
Luma Contrast Accuracy CVBS, 1 V input 1 %
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 Guaranteed by characterization.
4 Nominal sync depth is 300 mV at 100% sync depth range.
ADV7403
Rev. SpA | Page 7 of 24
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter1, , 2 3 Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
Horizontal Sync Input Frequency 14.8 110 kHz
LLC1 Frequency Range4 12.825 140 MHz
I2C PORT5
SCLK Frequency 400 kHz
SCLK Min Pulse Width High t1 0.6 μs
SCLK Min Pulse Width Low t2 1.3 μs
Hold Time (Start Condition) t3 0.6 μs
Setup Time (Start Condition) t4 0.6 μs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Time t6 300 ns
SCLK and SDA Fall Time t7 300 ns
Setup Time for Stop Condition t8 0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio t9:t10 45:55 55:45
% duty
cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)6t11 Negative clock edge to start of
valid data
3.6 ns
Data Output Transition Time SDR (SDP)6t12 End of valid data to negative
clock edge
2.4 ns
Data Output Transition Time SDR (CP)7t13 End of valid data to negative
clock edge
2.8 ns
Data Output Transition Time SDR (CP)7t14 Negative clock edge to start of
valid data
0.1 ns
Data Output Transition Time DDR (CP)7, 8t15 Positive clock edge to end of
valid data
−4 + TLLC1/4 ns
Data Output Transition Time DDR (CP)7, 8t16 Positive clock edge to start of
valid data
0.25 + TLLC1/4 ns
Data Output Transition Time DDR (CP)7, 8t17 Negative clock edge to end of
valid data
−2.95 + TLLC1/4 ns
Data Output Transition Time DDR (CP)7, 8t18 Negative clock edge to start of
valid data
−0.5 + TLLC1/4 ns
DATA and CONTROL INPUTS5
Input Setup Time (Digital Input Port) t19 HS_IN, VS_IN 9 ns
DE_IN, data inputs 2.2 ns
Input Hold Time (Digital Input Port) t20 HS_IN, VS_IN 7 ns
DE_IN, data inputs 2 ns
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
5 TTL input values are 0 V to 3 V, with rise/fall times ≥3 ns, measured between the 10% and 90% points.
6 SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.
7 CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.
8 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
ADV7403
Rev. SpA | Page 8 of 24
ANALOG SPECIFICATIONS
@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature
range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6V , typically 1 V p-p.
Table 4.
Parameter1, , 2 3 Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 μF
Input Impedance4Clamps switched off 10 MΩ
Input Impedance of Pin 51 (FB) 20 kΩ
CML 1.86 V
ADC Full-Scale Level CML + 0.8 V V
ADC Zero-Scale Level CML − 0.8 V V
ADC Dynamic Range 1.6 V
Clamp Level (When Locked) CVBS input CML − 0.292 V V
SCART RGB input (R, G, B signals) CML − 0.4 V V
S-Video input (Y signal) CML − 0.292 V V
S-Video input (C signal) CML – 0 V V
Component input (Y, Pr, Pb signals) CML – 0.3 V V
PC RGB input (R, G, B signals) CML − 0.3 V V
Large Clamp Source Current SDP only 0.75 mA
Large Clamp Sink Current SDP only 0.9 mA
Fine Clamp Source Current SDP only 17 μA
Fine Clamp Sink Current SDP only 17 μA
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX:−40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 Guaranteed by characterization.
4 Except Pin 51 (FB).
ADV7403
Rev. SpA | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
STRESS RATINGS
Table 5.
Parameter Rating
AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD −0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to
DGND
DGND − 0.3 V to DVDDIO + 0.3 V
Digital Outputs Voltage to
DGND
DGND − 0.3 V to DVDDIO + 0.3 V
Analog Inputs to AGND AGND − 0.3 V to AVDD + 0.3 V
Maximum Junction
Temperature (TJ MAX)
125°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering
(20 sec)
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs .
The junction temperature must always stay below the
maximum junction temperature (TJ MAX) of 125°C. This
equation shows how to calculate the junction temperature:
TJ = TA Max + (θJA × WMax)
where:
TA Max = 85°C.
θJA = 30°C/W.
WMax = ((AV D D × IAV D D )+(DVDD × IDVDD)+ (DVDDIO ×
IDVDDIO) + (PVDD × IPVDD)).
THERMAL SPECIFICATIONS
Table 6.
Thermal Characteristics Symbol Test Conditions Typ Unit
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7 °C/W
Junction-to-Ambient Thermal Resistance θJA 4-layer PCB with solid ground plane (still air) 30 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADV7403
Rev. SpA | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
26
P6
27
P5
28
P4
29
P26
30
P25
31
P24
32
P23
33
P22
34
P21
35
DCLK_IN
36
LLC1
37
XTAL1
38
XTAL
39
DVDD
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
74
73
72
69
70
71
75
68
67
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
65
40
DGND
41
P3
42
P2
43
P1
44
P0
45
P20
46
ELPF
47
PVDD
48
PVDD
49
AGND
50
AGND
05431-002
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
ADV7403
LQFP
TOP VIEW
(Not to Scale)
P11
P32
P31
INT
CS/HS
DGND
DVDDIO
P15
P14
P13
P12
DGND
DVDD
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P10
P9
P8
P27
P7
AIN2
AIN8
AIN1
AIN7
SOG
AIN9
AIN3
TEST1
AGND
CAPY1
CAPY2
AVDD
REFOUT
CML
AGND
BIAS
CAPC1
CAPC2
TEST0
AIN10
AIN4
AIN11
AIN5
AIN12
FB
FIELD/DE
DE_IN
SOY
AIN6
ALSB
SDA1
SCLK1
P40
P39
VS_IN
HS_IN/CS_IN
P38
P37
DGND
DVDD
P19
P17
P16
P36
P35
P34
VS
P33
P18
RESET
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type Function
5, 11, 17, 40, 89 DGND G Digital Ground.
49, 50, 60, 66 AGND G Analog Ground.
6, 18 DVDDIO P Digital I/O Supply Voltage (3.3 V).
12, 39, 90 DVDD P Digital Core Supply Voltage (1.8 V).
63 AVDD P Analog Supply Voltage (3.3 V).
47, 48 PVDD P PLL Supply Voltage (1.8 V).
51 FB I Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
54, 56, 58, 72, 74,
76, 53, 55, 57, 71,
73, 75
AIN1 to AIN12 I Analog Video Input Channels.
42, 41, 28, 27, 26,
25, 23, 22, 10, 9, 8,
7, 94, 93, 92, 91
P2 to P9, P12 to P19 O Video Pixel Output Port.
44, 43, 21, 20, 45,
34, 33, 32, 31, 30,
29, 24, 14, 13
P0 to P1, P10 to P11,
P20 to P21, P22 to
P25, P26 to P29
I/O Video Pixel Input/Output Port.
2, 1, 100, 97, 96,
95, 88, 87, 84, 83
P31 to P40 I Video Pixel Input Port.
ADV7403
Rev. SpA | Page 11 of 24
Pin No. Mnemonic Type Function
3 INT O Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin triggers. The set of events that triggers an interrupt is under user control.
4 HS/CS O
HS is a Horizontal Synchronization Output Signal (SDP and CP modes). CS is a Digital
Composite Synchronization Signal (and can be selected while in CP mode).
99 VS O Vertical Synchronization Output Signal (SDP and CP modes).
98 FIELD/DE O
FIELD is a Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
81, 19 SDA1, SDA2 I/O I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port, and
SDA2 is the data line for the VBI readback port.
82, 16 SCLK1, SCLK2 I I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the
Control port and SCLK2 is the clock line for the VBI data readback port.
80 ALSB I
This pin selects the I2C address for the ADV7403 control and VBI readback ports. ALSB
set to Logic 0 sets the address for a write to control port of 0x40 and the readback
address for the VBI port of 0x21. ALSB set to a logic high sets the address for a write to
control port of 0x42 and the readback address for the VBI port of 0x23.
78 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7403 circuitry.
36 LLC1 O
LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz to 140 MHz
for ADV7403KSTZ-140; 12.825 MHz to 110 MHz for ADV7403BSTZ-110.
38 XTAL I
Input Pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7403.
37 XTAL1 O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an
external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7403. In
crystal mode the crystal must be a fundamental crystal.
46 ELPF O The recommend external loop filter must be connected to this ELPF pin.
70 TEST0 NC This pin should be left unconnected or alternaltely tie to AGND.
59 TEST1 O This pin should be left unconnected.
15 SFL/SYNC_OUT O
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream, which can
be used to lock the subcarrier frequency when this decoder is connected to any
Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal
available only in CP mode.
64 REFOUT O Internal Voltage Reference Output.
65 CML O Common-Mode Level Pin (CML) for the internal ADCs.
61, 62 CAPY1, CAPY2 I ADC Capacitor Network.
68, 69 CAPC1, CAPC2 I ADC Capacitor Network.
67 BIAS O
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between pin
and ground.
86 HS_IN/CS_IN I
Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal used to extract timing in a 5-wire or 4-wire RGB mode.
85 VS_IN I VS Input Signal. Used in CP mode for 5-wire timing mode.
79 DE_IN I
Data Enable Input Signal. Used in 24-bit digital input port mode (for example,
processing 24-bit RGB data from a DVI Rx IC).
35 DCLK_IN I
Clock Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit
RGB data from a DVI Rx IC) and also in digital CVBS input mode.
52 SOG I Sync on Green Input. Used in embedded sync mode.
77 SOY I Sync on Luma Input. Used in embedded sync mode.
ADV7403
Rev. SpA | Page 12 of 24
TIMING DIAGRAMS
SDA1/SDA2
SCLK1/SCLK2
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
05431-003
Figure 3. I2C Timing
05431-004
LLC1
P0–P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
t
9
t
10
t
12
t
11
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
LLC1
P0–P29, VS,
HS, FIELD/DE
t
14
t
9
t
13
t
10
05431-005
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
05431-006
LLC1
P6–P9,
P10–P19
t
16
t
18
t
15
t
17
Figure 6. Pixel Port and Control DDR Output Timing (CP Core)
t9t10 t20
t19
DCLK_IN
DE_IN
HS_IN
VS_IN
CONTROL
INPUTS
05431-008
P0–P1, P10–P11,
P20–P21, P22–P29,
P31–P32, P33–P40
Figure 7. Digital Input Port and Control Input Timing
ADV7403
Rev. SpA | Page 13 of 24
DETAILED FUNCTIONALITY
ANALOG FRONT END
• Four 140 MHz (ADV7403KSTZ-140), Noise Shaped Video,
12-bit ADCs enable true 10-bit video decoder
• 12 analog input channel mux enables multisource
connection without the requirement of an external mux
• Four current and voltage clamp control loops ensure any
dc offsets are removed from the video signal
• SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
• Four antialias filters to remove out of band noise on
standard definition input video signals.
SDP PIXEL DATA OUTPUT MODES
• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
• 16-/20-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
• 24-/30-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
CP PIXEL DATA OUTPUT MODES
• Single data rate (SDR) 8-/10-bit 4:2:2 YCrCb for 525i, 625i
• Single data rate (SDR) 16-/20-bit 4:2:2 YCrCb for all
standards
• Single data rate (SDR) 24-/30-bit 4:4:4 YCrCb/RGB for all
standards
• Double data rate (DDR) 8-/10-bit 4:2:2 YCrCb for all
standards
• Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all
standards
COMPOSITE AND S-VIDEO PROCESSING
• Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,
60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video
• Superadaptive 2D 5-line comb filters for NTSC and PAL
give superior chrominance and luminance separation for
composite video
• Full automatic detection and autoswitching of all
worldwide standards (PAL/NTSC/SECAM)
• Automatic gain control with white peak mode ensures
the video is always processed without loss of the video
processing range
• Adaptive digital line length tracking (ADLLT™)
• Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
• IF filter block compensates for high frequency luma
attenuation due to tuner SAW filter
• Chroma transient improvement (CTI)
• Luminance digital noise reduction (DNR)
• Color controls include hue, brightness, saturation, contrast,
and Cr and Cb offset controls
• Certified Macrovision copy protection detection on
composite and S-video for all worldwide formats
(PAL/NTSC/SECAM)
• 4× oversampling (54 MHz) for CVBS, S-video, and YUV
modes
• Line-locked clock output (LLC)
• Letterbox detection supported
• Free-run output mode provides stable timing when no
video input is present
• Vertical blanking interval data processor
• Tel eTe xt
• Video Programming System (VPS)
• Vertical Interval Time Codes (VITC)
• Closed captioning (CC) and extended data service
(EDS)
• Wide screen signaling (WSS)
• Copy generation management system (CGMS)
• Gemstar™ 1×/2× electronic program guide compatible
• Clocked from a single 28.63636 MHz crystal
• Subcarrier frequency lock (SFL) output for downstream
video encoder
• Differential gain typically 0.4%
• Differential phase typically 0.4°
ADV7403
Rev. SpA | Page 14 of 24
COMPONENT VIDEO PROCESSING
• Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
• Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
• Support for analog component YPrPb/RGB video formats
with embedded sync or with separate HS, VS, or CS
• Any-to-any, 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
• Standard identification (STDI) enables system level
component format detection
• Synchronization source polarity detector (SSPD) deter-
mines the source and polarity of the synchronization
signals that accompany the input video
• Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
• Free-run output mode provides stable timing when no
video input is present
• Arbitrary pixel sampling support for nonstandard video
sources
RGB GRAPHICS PROCESSING
• 140 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion
rate for ADV7403BSTZ-110)
• Automatic or manual clamp and gain controls for graphics
modes
• Contrast and brightness controls
• 32-phase DLL allows optimum pixel clock sampling
• Automatic detection of sync source and polarity by SSPD
block
• Standard identification is enabled by STDI block
• RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend
IC interfacing
• Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
• Arbitrary pixel sampling support for nonstandard video
sources
DIGITAL VIDEO INPUT PORT
• Supports raw 8-/10-bit CVBS data from digital tuner
• Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
• Support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p,
625p, 1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
GENERAL FEATURES
• HS, VS, and FIELD output signals with programmable
position, polarity, and width
• Programmable interrupt request output pin, INT, signals
SDP/CP status changes
• Supports two I2C host port interfaces (control and VBI)
• Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
• Industrial temperature range (−40°C to +85°C)
(ADV7403BSTZ-110)
• 140 MHz speed grade (ADV7403KST-140)
• 100-lead, 14 mm × 14 mm, Pb-free LQFP
ADV7403
Rev. SpA | Page 15 of 24
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7403 analog front end comprises four Noise Shaped
Video, 12-bit ADCs that digitize the analog video signal before
applying it to the SDP or CP (See Table 8 for sampling rates).
The analog front end uses differential channels to each ADC to
ensure high performance in a mixed-signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7403. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping either in the CP or SDP.
Optional antialiasing filters are positioned in front of each
ADC. These filters can be used to band-limit standard
definition video signals, removing spurious, out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
The ADV7403 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compat-
ibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under control of I2C
registers and the fast blank pin.
Table 8: Maximum ADC Sampling Rates
Model Maximum ADC Sampling Rate
ADV7403BSTZ-110 110 MHz
ADV7403KSTZ-140 140MHz
STANDARD DEFINITION PROCESSOR
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-video and YUV
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC
4.43, and SECAM B/D/G/K/L. The ADV7403 can automatically
detect the video standard and process it accordingly.
The SDP has a 5-line super adaptive 2-D comb filter that gives
superior chrominance and luminance separation when decod-
ing a composite video signal. This highly adaptive filter auto-
matically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7403 implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7403 to track and decode poor quality video sources such as
VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the edge
rate on chroma transitions, resulting in a sharper video image.
The SDP can process a variety of VBI data services, such as
TeleText, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), Gemstar
1×/2×, and extended data service (XDS). The ADV7403 SDP
section has a Macrovision 7.1 detection circuit that allows it to
detect Types I, II, and III protection levels. The decoder is also
fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA @ 75 Hz, (ADV7403KSTZ-140
only) and many other standards not listed here.
The CP section of the ADV7403 contains an AGC block.
When no embedded sync is present, the video gain can be set
manually. The AGC section is followed by a digital clamp
circuit that ensures the video signal is clamped to the correct
blanking level. Automatic adjustments within the CP include
gain (contrast) and offset (brightness); manual adjustment
controls are also supported.
A fully programmable any-to-any, 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In
these modes, HS, VS, and FIELD/DE (where applicable) timing
reference signals are provided. In DDR mode, the ADV7403 can
be configured in an 8-/10-bit 4:2:2 YcrCb or 12-bit 4:4:4 RGB/
YcrCb pixel output interface with corresponding timing signals.
ADV7403
Rev. SpA | Page 16 of 24
The ADV7403 is capable of supporting an external DVI/
HDMI receiver. The digital interface expects 24-bit 4:4:4 or
16-/20-bit 4:2:2 bit data (either graphics RGB or component
video YcrCb), accompanied by HS, VS, DE, and a fully
synchronous clock signal. The data is processed in the CP and
output as 16-bit 4:2:2 YcrCb data.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7403 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the
I2C interface. For more detailed product information about the
ADV7403, contact your local ADI sales office or email
video.products@analog.com.
ADV7403
Rev. SpA | Page 17 of 24
PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Processor, Format, Pixel Port Pins P[19:0]
and Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDP Video out, 8-bit,
4:2:2
YcrCb[7:0]OUT - - - - - - - - - - - -
SDP Video out, 10-bit,
4:2:2
YcrCb[9:0] OUT - - - - - - - - - -
SDP Video out,
16-bit, 4:2:2
Y[7:0]OUT - - CrCb[7:0]OUT - -
SDP Video out,
20-bit, 4:2:2
Y[9:0]OUT CrCb[9:0]OUT
SDP Video out,
24-bit, 4:4:4
Y[7:0]OUT - - Cb[7:0]OUT - -
SDP Video out,
30-bit, 4:4:4
Y[9:0]OUT Cb[9:0]OUT
SM-SDP Digital tuner
input[1]
Output choices are the same as video out 16-/20-bit or pseudo 8-/10-bit DDR
CP 8-bit, 4:2:2, DDR D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - - -
CP 10-bit, 4:2:2, DDR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - -
CP 12-bit, 4:4:4, RGB
DDR
D7 D6 D5 D4 D3 D2 D1 D0 - - D11 D10 D9 D8 - - - - - -
CP Video out,
16-bit, 4:2:2
CHA[7:0]OUT (for example, Y[7:0]) - - CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) - -
CP Video out,
20-bit, 4:2:2
CHA[9:0]OUT (for example, Y[9:0]) CHB/C[9:0]OUT (for example, Cr/Cb[9:0])
CP Video out,
24-bit, 4:4:4
CHA[7:0]OUT (for example, G[7:0]) - - CHB[7:0]OUT (for example, B[7:0]) - -
CP Video out,
30-bit, 4:4:4
CHA[9:0]OUT (for example, G[9:0]) CHB[9:0]OUT (for example, B[9:0])
SM-CP HDMI receiver
support, 24-bit,
4:4:4 input
CHA[7:0]OUT (for example, Y[7:0]) R[5:4]IN CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) R[1:0]IN
SM-CP HDMI receiver
support 16-bit
pass-through
CHA[7:0]OUT (for example, Y[7:0]) - - CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) - -
SM-CP HDMI receiver
support, 20-bit,
pass-through
CHA[9:0]OUT (for example, Y[9:0]) CHB/C[9:0]OUT (for example, Cr/Cb[9:0])
ADV7403
Rev. SpA | Page 18 of 24
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
Processor, Format, Pixel Port Pins P[40:31], P[29:20]
and Mode 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20
SDP Video out, 8-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
SDP Video out, 10-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
SDP Video out, 16-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
SDP Video out, 20-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
SDP Video out, 24-bit,
4:4:4
- - - - - - - - - - Cr[7:0]OUT - -
SDP Video out, 30-bit,
4:4:4
- - - - - - - - - - Cr[9:0]OUT
SM-SDP Digital tuner
input[1]
DCVBS[9:0]IN - - - - - - - - - -
CP 8-bit, 4:2:2, DDR - - - - - - - - - - - - - - - - - - - -
CP 10-bit, 4:2:2, DDR - - - - - - - - - - - - - - - - - - - -
CP 12-bit, 4:4:4, RGB
DDR
- - - - - - - - - - - - - - - - - - - -
CP Video out, 16-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
CP Video out, 20-bit,
4:2:2
- - - - - - - - - - - - - - - - - - - -
CP Video out, 24-bit,
4:4:4 input
- - - - - - - - - - CHC[7:0]OUT (for example, R[7:0]) - -
CP Video out, 30-bit,
4:4:4 input
- - - - - - - - - - CHC[9:0]OUT (for example, R[9:0])
SM-CP HDMI receiver
support, 24-bit,
4:4:4 input
G[7:0]IN R[7:6]IN B[7:0]IN R[3:2]IN
SM-CP HDMI receiver
support, 16-bit,
pass-through
CHA[7:0]IN(for example, Y[7:0]) - - CHB/C[7:0]IN(for example, Cr/Cb[7:0]) - -
SM-CP HDMI receiver
support, 20-bit,
pass-through
CHA[9:0]IN(for example, Y[9:0]) CHB/C[9:0]IN(for example, Cr/Cb[9:0])
ADV7403
Rev. SpA | Page 19 of 24
RECOMMENDED EXTERNAL LOOP
FILTER COMPONENTS
The external loop filter components for the ELPF pin should
be placed as close as possible to the respective pins. Figure 8
shows the recommended component values.
05431-007
1.69kΩ
82nF
10nF
PVDD = 1.8V
PIN 46–ELPF
Figure 8. ELPF Components
ADV7403
Rev. SpA | Page 20 of 24
TYPICAL CONNECTION DIAGRAM
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
56
Ω
AGND
10nF
0.1
μ
F
10nF
0.1
μ
F
10nF
0.1
μ
F
DVDD_1.8V
DGND
U1 BYPASS CAPACITORS
10nF
0.1
μ
F
10nF
0.1
μ
F
DVDDIO
DGND
U1 BYPASS CAPACITORS
10nF
0.1
μ
F
AGND
PVDD_1.8V
10nF
0.1
μ
F
AGND
AVDD_3.3V
75
Ω
GREEN
BLUE
RED
RGB
GRAPHICS
P5–2
P5–3
P5–1
P5–13
P5–14
P6–5
P6–6
P5–7
P5–8
P5–10
HS_IN
VS_IN
1
3
5
21
2
4
6
P4
SCART_21_PIN
20 19
18 17
16 15
14 13
12 11
10 9
87
65
43
21
43
21
P8
MINI-DIN-4
S-VIDEO
SOG
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SOY
AIN10
AIN11
AIN12
AIN7
AIN8
AIN9
CAPC2
CAPC1
CAPY2
CAPY1
CML
REFOUT
BIAS
XTAL
XTAL1
ELPF
SDA
SCLK
SDA2
SCLK2
ALSB
RESET
1
3
2
4
19Ω
19Ω
20 CVBS/Y
CVBS
P9
AGND
19Ω
56Ω
0.1μF
PVDD
PVDD
AVDD
DVDD
DVDD
DVDD
DVDDIO
DVDDIO
DE_IN
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
INT
DCLK_IN
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
LLC1
HS
VS
FIELD
HREF/HS_IN
VREF/VS_IN
SFL/SYNC_OUT
FB
TEST1
TEST0
AVSS
AVSS
PVSS
PVSS
DVSSIO
DVSSIO
DVSS
DVSS
DVSS
ADV7403
33
Ω
VP4179 33
Ω
VP4083 33
Ω
VP3984 33
Ω
VP3887 33
Ω
VP3788 33
Ω
VP3695 33
Ω
VP3596 33
Ω
VP3497 33
Ω
VP33100 33
Ω
VP32133
Ω
VP31233
Ω
VP303
33
Ω
VP2913 33
Ω
VP2814 33
Ω
VP2724 33
Ω
VP2629 33
Ω
VP2530 33
Ω
VP2431 33
Ω
VP2332 33
Ω
VP2233 33
Ω
VP2134 33
Ω
VP2045
33
Ω
VP1991 33
Ω
VP1892 33
Ω
VP1793 33
Ω
VP1694 33
Ω
VP15733
Ω
VP14833
Ω
VP13933
Ω
VP1210 33
Ω
VP1120 33
Ω
VP1021 33
Ω
VP0922 33
Ω
VP0823 33
Ω
VP0725 33
Ω
VP0626 33
Ω
VP0527 33
Ω
VP0428
VP[00:41]
INT
DCLCK_IN
33
Ω
VP0341 33
Ω
VP0242 33
Ω
VP0143 33
Ω
VP0044
100
Ω
4100
Ω
99 100
Ω
98 100
Ω
86 100
Ω
85
33
Ω
15
HS
VS
FIELD
HS_IN
VS_IN
SFL/SYNC_OU
T
100
Ω
36
10nF
0.1
μ
F10
μ
F
0.1
μ
F
AGND
10nF
0.1
μ
F10
μ
F
0.1
μ
F
AGND 0.1
μ
F10
μ
F
10
μ
F
0.1
μ
F
2.7k
Ω
2.7k
Ω
Y2
28.63636MHz
1MΩ
47pF
1
47pF
1
DGND
10nF
82nF
PVDD_1.8V
1.69kΩ
100Ω
100Ω
5.6kΩ
SDA
SCLK
RESET
DVDDIO
K1
K2
BAT54C DVDDIO
PVDD_1.8V DVDD_1.8V
AVDD_3.3V
DVDDIO
U1
47
48
63
12
39
90
6
18
C22 1nF
C94 1nF
D1
BZX399-C3V3
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
Y
C
AGND
1
LOAD CAP VALUES ARE DEPENDANT ON CRYSTAL ATTRIBUTES
AGND
Pr/Pb
Pb/Pr
Y
RED/C
GREEN
F_BLNK
BLUE
PHONO3
AGND
05431-009
U1 BYPASS CAPACITORS
10kΩ
35
70
66
60
49
50
5
17
11
40
89
LLC1
52
54
56
58
72
74
76
77
71
73
75
53
55
57
69
68
62
61
65
64
67
38
37
46
81
82
19
16
80
78
51
59
AGND
+
+
P7
16
2
11
15
AGND DGND
Figure 9. ADV7403 Typical Connection Diagram
ADV7403
Rev. SpA | Page 21 of 24
OUTLINE DIMENSIONS
COMP LIANT TO JEDEC STANDARDS MS - 026- BE D
TOP V IEW
(PINS DOWN)
1
2526 51
50
75
76100
0.50
BSC
LEAD P ITCH
0.27
0.22
0.17
1.60 M A X
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
14.20
14.00 SQ
13.80
16.20
16.00 S Q
15.80
051706-A
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADV7403BSTZ-1102 −40°C to +85°C 100-Lead Low Profile Quad Flat Package (LQFP) ST-100
ADV7403KSTZ-1402 0°C to 70°C 100-Lead Low Profile Quad Flat Package (LQFP) ST-100
EVAL-ADV7403EBM Evaluation board
1 The ADV7403 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition,
it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at
conventional reflow temperatures of 220°C to 235°C.
2 Z = Pb-free part.
ADV7403
Rev. SpA | Page 22 of 24
NOTES
ADV7403
Rev. SpA | Page 23 of 24
NOTES
ADV7403
Rev. SpA | Page 24 of 24
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05431–0–9/05(SpA)
