15
EL2125C
Ultra-Low Noise, Low Power, Wideband Amplifier
EL2125C
The total noise due to the amplifier seen at the output of
the amplifier can be calculated by using the following
equation:
As the above equation shows, to keep noise at a mini-
mum, small resistor values should be used. At higher
amplifier gain configuration where R
2
is reduced, the
noise due to IN-, R
2
, and R
1
decreases and the noise
caused by IN+, VN, and R
3
starts to dominate. Because
noise is summed in a root-mean-squares method, noise
sources smaller than 25% of the largest noise source can
be ignored. This can greatly simplify the formula and
make noise calculation much easier to calculate.
Output Drive Capability
The EL2125C is designed to drive low impedance load.
It can easily drive 6V
P-P
signal into a 100Ω load. This
high output drive capability makes the EL2125C an
ideal choice for RF, IF, and video applications. Further-
more, the EL2125C is current-limited at the output,
allowing it to withstand momentary short to ground.
However, the power dissipation with output-shorted
cannot exceed the power dissipation capability of the
package.
Driving Cables and Capacitive Loads
Although the EL2125C is designed to drive low imped-
ance load, capacitive loads will decreases the amplifier's
phase margin. As shown the in the performance curves,
capacitive load can result in peaking, overshoot and pos-
sible oscillation. For optimum AC performance,
capacitive loads should be reduced as much as possible
or isolated with a series resistor between 5Ω to 20Ω.
When driving coaxial cables, double termination is
always recommended for reflection-free performance.
When properly terminated, the capacitance of the coax-
ial cable will not add to the capacitive load seen by the
amplifier.
Power Supply Bypassing And Printed Circuit
Board Layout
As with any high frequency devices, good printed circuit
board layout is essential for optimum performance.
Ground plane construction is highly recommended.
Lead lengths should be kept as short as possible. The
power supply pins must be closely bypassed to reduce
the risk of oscillation. The combination of a 4.7µF tanta-
lum capacitor in parallel with 0.1µF ceramic capacitor
has been proven to work well when placed at each sup-
ply pin. For single supply operation, where pin 4 (V
S
-) is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor
across pins 7 (V
S
+) and pin 4 (V
S
-) will suffice.
For good AC performance, parasitic capacitance should
be kept to a minimum. Ground plane construction again
should be used. Small chip resistors are recommended to
minimize series inductance. Use of sockets should be
avoided since they add parasitic inductance and capaci-
tance which will result in additional peaking and
overshoot.
Supply Voltage Range and Single Supply
Operation
The EL2125C has been designed to operate with supply
voltage range of ±2.5V to ±15V. With a single supply,
the EL2125C will operate from +5V to +30V. Pins 4 and
7 are the power supply pins. The positive power supply
is connected to pin 7. When used in single supply mode,
pin 4 is connected to ground. When used in dual supply
mode, the negative power supply is connected to pin 4.
As the power supply voltage decreases from +30V to
+5V, it becomes necessary to pay special attention to the
input voltage range. The EL2125C has an input voltage
range of 0.4V from the negative supply to 1.2V from the
positive supply. So, for example, on a single +5V sup-
ply, the EL2125C has an input voltage range which
spans from 0.4V to 3.8V. The output range of the
EL2125C is also quite large, on a +5V supply, it swings
from 0.4V to 3.6V.
V
ON
BW=VN
2
1
R
1
R
2
------
+
2
×IN-
2
R
1
2
IN+
2
R
3
2
1
R
1
R
2
------
+
2
××+×4KTR
1
4KTR
2
R
1
R
2
------
2
××××+××× 4KTR
3
1
R
1
R
2
------
+
2
××××++ +
×