TFA9879HN/N1,157 - NXP SEMICONDUCTORS

1. Introduction

The TFA9879 is a high-efficiency filter-free mono class-D audio amplifier with two

separate digital inputs for mobile applications.

2. General description

The TFA9879 contains a processor that supports a range of sound processing features

including a 5-band parametric equalizer, separate bass and treble control, a dynamic

range compressor, soft clip control and volume control. Excellent audi o performance

combined with high Power Supply Rejection Ratio (PSRR) is achieved through the use of

a closed loop configuration.

Two independent digital audio inputs (I2S-bus / PCM / IOM2) are available for connecting

both a baseband and a multimedia processor.

The TFA9879 is available in a HVQFN24 package.

3. Features and benefits

3.1 General features

Closed loop amplifier for:

High power supply rejection ratio

Excellent audio performance

Digital input for high RF immunity

High efficiency for maximizing battery life

Wide supply voltage range (fully op er a tion a l from 2.5 V to 5.5 V)

Delivers high output power into 4 Ω and 8 Ω load impedances

Phase-Locked Loop (PLL); no system clock required

Protection including diagnostics via I2C-bus:

OverCurrent Protection (OCP) to protect against short circuits across the speaker,

to the supply line or to ground

OverTemperature Protection (OTP)

Digital inpu ts protected with UnderFrequency Protection (UFP), OverFrequency

Protection (OFP) and Invalid Bit-clock Protection (IBP)

‘Pop noise’ free at power-up/power down, during sample rate switching and when

switching between digital inputs

Four separate I2C-bus addresses for multi-channel applications

TFA9879

Mono BTL class-D audio amplifier for portable applications

with digital input

Rev. 02 — 15 October 2010 Product data sheet

Product data sheet Rev. 02 — 15 October 2010 2 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

1.8 V / 3.3 V tolerant digital inputs

Only three exter n al com p on e nts required

3.2 Programmable Digital Sound Processor (DSP)

Digital volume control (−70 dB to +24 dB)

Digital parametric 5-band equalizer

Bass and treble control (−18 dB to +18 dB)

Dynamic range compressor:

Programmable attack and release levels

Programmable attack and release rates

Soft and hard mute control

Programmable DC blocking via high-pass filter

Power limiter (0 dB to −124 dB in 0.5 dB steps)

Zero crossing volume control

Stereo-to-mono down-mix function

3.3 Interface format support for digital audio inputs

I2S formats (fs = 8 kHz to 96 kHz):

Philips standard I2S-bus

Japanese I2S-bus MSB-justified

Sony I2S-bus LSB-justified

PCM / IOM2 formats (fs = 8 kHz or fs = 16 kHz):

Long frame sync

Short frame sync

4. Applications

Mobile phones

Portable Navigation Devices (PND)

PDAs

Notebooks

Portable gaming devices

MP3 and MP4 pla yers

Product data sheet Rev. 02 — 15 October 2010 3 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

5. Quick reference data

[1] After switching from Off/Amplifier mode to Power-down mode.

6. Ordering information

Table 1. Quick reference data

All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8

; LL = 44

H; fi = 1 kHz; fs = 48 kHz; clip control off;

Tamb = 25

C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VDDP power supply voltage on pin VDDP 2.5 - 5.5 V

VDDD digital supply voltage on pin VDDD 1.65 1.8 1.95 V

IPsupply current on pin VDDP; Amplifier mode with load; soft

mute on -5.7- mA

on pin VDDP; Power-down mode - - 20 μA

IDDD digital supply current on pin VDDD; Amplifier mode - 1.2 - mA

on pin VDDD; Power-down mode [1] -515μA

Po(RMS) RMS outpu t po w e r RL=8Ω

THD + N = 1 % 0.65 0.7 - W

THD + N = 10 % - 0.85 - W

RL=4Ω

THD+N=1% - 1.2 - W

THD+N=10% - 1.5 - W

RL=8Ω; VDDP = 4.2 V

THD+N=1% - 0.9 - W

THD+N=10% - 1.1 - W

RL=4Ω; VDDP = 4.2 V

THD+N=1% - 1.6 - W

THD + N = 10 % - 1.95 - W

RL=8Ω; VDDP = 5.0 V

THD+N=1% - 1.35 - W

THD+N=10% - 1.6 - W

RL=4Ω; VDDP = 5.0 V

THD+N=1% - 2.35 - W

THD + N = 10 % - 2.75 - W

ηpo output power efficiency Po(RMS) = 850 mW - 92 - %

Table 2. Ordering information

Type number Package

Name Description Version

TFA9879HN HVQFN24 plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm SOT616_3

Product data sheet Rev. 02 — 15 October 2010 4 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

7. Block diagram

Fig 1. Block diagram

I2C

CONTROL

DIGITAL

AUDIO

RECEIVER

HIGH

PASS

FILTER

BAND

EQUALIZER

BASS

TREBLE

BOOST

POWER

LIMITER

MUX

PWM

VDDP

OUTA

OUTB

7, 8

PLL

2nd

ORDER

LOOP

VOLUME

CONTROL

DRC

DSP

VDDD

TFA9879

SCL

SDI1

SCK1

LRCK1

SDI2

SCK2

LRCK2

ADSEL1

SDA

PROTECTION

CIRCUITS:

OCP

OTP

OFP

UFP

IBP

6, 14

n.c.

GNDD

STABA

H-BRIDGE

GNDP11, 12

2nd

ORDER

LOOP

010aaa542

TEST1

TEST2

TEST3

ADSEL2

DAP

Product data sheet Rev. 02 — 15 October 2010 5 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

8. Pinning information

8.1 Pinning

8.2 Pin description

(1) Exposed Die Attach Paddle (DAP)

Fig 2. Pin configuration

010aaa58

TFA9879

Transparent top view

STABA

TEST3

n.c.

ADSEL2 TEST2

TEST1 ADSEL1

SCL SDI2

SDA SCK2

VDDP

OUTB

OUTA

GNDP

GNDD

VDDD

LRCK1

SCK1

SDI1

LRCK2

terminal 1

index area

613

514

4 15

3 16

2 17

118

DAP(1)

Table 3. Pin description

Symbol Pin Pin Type Description

SDA 1 IO I2C-bus data input/output

SCL 2 I I2C-bus bit clock input

TEST1 3 I test signal input 1; for test purposes only; connect to PCB ground

ADSEL2 4 I address selection input 2

TEST3 5 I test signal input 3; for test purposes only; connect to PCB ground

n.c. 6 - not connected; connect to PCB ground

VDDP 7, 8 P analog supply voltage (2.5 V to 5.5 V)

OUTB 9 O output B (negative)

OUTA 10 O output A (positive)

GNDP 11, 12 P analog ground, PCB ground reference

STABA 13 O 1.8 V analog stabilizer output

n.c 14 - not connected; connect to PCB ground

TEST2 15 I test signal input 2; for test purposes only; connect to PCB ground

ADSEL1 16 I address selection input 1

SDI2 17 I digital audio data input 2

SCK2 18 I digital audio bi t cl ock i np u t 2

LRCK2 19 I digital audio word select input 2

SDI1 20 I digital audio data input 1

SCK1 21 I digital audio bi t cl ock i np u t 1

LRCK1 22 I digital audio word select input 1

Product data sheet Rev. 02 — 15 October 2010 6 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9. Functional description

The TFA9879 is a high-efficiency mono Bridge Tied Load (BTL) class-D amplifier with

digital audio inputs. It supports all commonly used formats.

The key functional blocks of th e TFA9879 are shown in Figure 1. In the digit al domain, the

audio signal is processed and converted into a Pulse Width Modulated (PWM) signal

using a 3-level modulation. In the analog domain, the PWM signal is amplified using a

second order feedback loop.

The audio signal-processing path is described below:

1. The MUX selects the serial interface input to be used.

2. The digital audio receiver translates the serial input signal into a standard internal

mono audio stream.

3. The programmable high-pass filter blocks DC signals and low frequency signals.

4. The volume control provides both gain an d attenuation functionality and can be

adjusted by the user or dynamically via the Dynamic Range Compressor (DRC). The

volume control can be used to adjust the signal level between −70 dB and +24 dB.

5. The 5-band parametric equalizer can be used to equalize the mono audio stream. It

can be used for speaker transfer curve compensation to optimize the audio

performance of the speakers.

6. The bass and treble boost function provides another way to adjust the sound.

7. The power limiter limits the maximum output signal of t he TFA9879. The power limiter

settings are 0 dB to −124 dB in steps of 0.5 dB. This function can be used to limit the

maximum output power delivered to the speakers at a fixed supply voltage and

speaker impedance.

8. The PWM controller block converts the audio signal into a 3-level modulated PWM

signal. The 3-level modulation provid es a high signal-to-noise perfo rm a nc e an d

eliminates clock jitter noise.

9. The second order feedback loop ensures excellent audio performance and high

power supply rejection ratio.

10. The H-BRIDGE allows the TFA9879 to deliver the required output power between

terminals OUTA and OUTB.

The internal clocks of the TFA9879 are derived from the digital audio interface (SCK1 and

SCK2) using a PLL. The reference input for the PLL is selected via the digital input MUX.

The audio signal p ath can be selected via the I2C-bus interface.

The PLL block generates the system clock.

VDDD 23 P digital supply voltage (1.8 V)

GNDD 24 P digital ground, PCB ground reference

DAP - P exposed Die Attached Paddle (DAP); connect to PCB ground

Table 3. Pin description …continued

Symbol Pin Pin Type Description

Product data sheet Rev. 02 — 15 October 2010 7 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The following protection circuits are built into the TFA9879:

•OverTemperature Protection (OTP)

•OverCurrent Protection (OCP)

•UnderFrequency Protection (UFP)

•OverFrequency Protection (OFP)

•Invalid Bit-clock Prot ec tio n (IBP )

•DC-blocking

9.1 Operating modes

The TFA9879 supports the following operating modes, which are controlled via the

I2C-bus interface:

•Power-down mode, used to switch off the device; current consumption is reduced to

a minimum; the I2C-bus remains operational; the PWM outputs are disabled.

•Off mode, in which the class-D amplifier is switched off; the TFA9879 is completely

biased and the PWM outputs are disabled.

•Amplifier mode, in which the digital inputs are used to generate a signal between

OUTA an d OUTB.

The TFA9879 device control settings are detaile d in Table 21.

9.1.1 Power-up/power-down

The power-up and power-down timing of the TFA9879 is illustrated in Figure 3. The

external powe r supp ly leve ls, V DDP and VDDD, should be within the specified operating

ranges before the operating mode is selected. Bit POWERUP in the Device control

OPMODE. After the tu rn -o n de lay (t d(on)), the device automatically generates a soft

un-mute function. A soft mute function is generated when OPMODE is set to 0. The

TFA9879 should be set to Power-down mode before the powe r supplies are disconnecte d

or turned off.

Product data sheet Rev. 02 — 15 October 2010 8 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9.1.2 Supported Digital audio data formats

The TFA9879 supports a commonly used range of I2S, PCM and IOM2 digital audio data

formats. The I2S formats, selected via bit s I2S_SET in the Serial interface control register

(Table 22), are listed in Table 4. The PCM/IOM2 formats are listed in Table 5. The

TFA9879 automatically detects the number of slots by measuring the ratio between the

sync frequency (8 kHz) and the data clock. Table 24 details the I2C settings for the

PCM/IOM2 formats.

Fig 3. Power-up/power-down timing

filtered BTL

output signal

OUTA, OUTB

serial interface

input signals

I2C POWERUP

(00h, bit 0)

VDDP, VDDD

I2C OPMODE

(00h, bit 3)

operating td(soft_mute)

010aaa65

td(on)

td(mute_off)

Product data sheet Rev. 02 — 15 October 2010 9 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Table 4. I2S-supported digital audio data formats

SCK frequency Interface format (MSB first) Supported data format

32 fsI2S (Philips) standard up to 16-bit data

32 fsMSB-justified up to 16-bit data

32 fsLSB-justified - 16 bits 16-bit data

64 fsI2S (Philips) standard up to 24-bit data

64 fsMSB-justified up to 24-bit data

64 fsLSB-justified - 16 bits 16-bit data

64 fsLSB-justified - 18 bits 18-bit data

64 fsLSB-justified - 20 bits 20-bit data

64 fsLSB-justified - 24 bits 24-bit data

Fig 4. I2S-supported digital audio data formats

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB MSBB2

2112 3

LEFT

I2S-BUS FORMAT

BCK

DATA

RIGHT

MSB B2

010aaa45

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB B2 B3 B4

LEFT

LSB-JUSTIFIED FORMAT 18 BITS

BCK

DATA

RIGHT

1518 17 2 1

MSB B2 B3 B4

B17 LSB

16 1518 17 2 1

B17 LSB

MSB-JUSTIFIED FORMAT

WS LEFT RIGHT

321321

MSB B2 MSBLSB LSB MSB B2B2

BCK

DATA

Product data sheet Rev. 02 — 15 October 2010 10 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Table 5. PCM/IOM2-supported audio data formats

Number of slots fs (kHz) Sync frequency

(kHz) on LRCK

Supported data

formats Data clock (kHz)

on SCK pin

2 8 or 16 8 8-bit data 128

4 8 or 16 8 8-bit data 256

6 8 or 16 8 8-bit data 384

8 8 or 16 8 8-bit data 512

12 8 or 16 8 8-bit data 768

16 8 or 16 8 8-bit data 1024

reserved

2 8 or 16 8 16-bit data 256

3 8 or 16 8 16-bit data 384

4 8 or 16 8 16-bit data 512

6 8 or 16 8 16-bit data 768

8 8 or 16 8 16-bit data 1024

12 8 or 16 8 16-bit data 1536

Fig 5. PCM/IOM2-supported digital audio data formats

MSB

LRCK

SCK

SDI LSB MSB B2B2 LSB MSB

SHORT SYNC PCM/IOM2 FORMAT

Slot 0 Slot 1 Slot 2 Slot N − 1 Slot N

B2 LSB MSB B2 LSB

MSB

LRCK

SCK

SDI LSB MSB B2B2 LSB MSB

LONG SYNC PCM/IOM2 FORMAT

Slot 0 Slot 1 Slot 2 Slot N − 1 Slot N

010aaa65

B2 LSB MSB B2 LSB

Product data sheet Rev. 02 — 15 October 2010 11 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9.2 Digital Signal Processor (DSP) features

9.2.1 Serial interface selection

The TFA9879 contains two serial interfaces. The active interface is selected via bit

INPUT_SEL in the Device control register (see Table 21). When this bit is toggled, the

following sequence is initiated:

•Soft mute is activated for 128/fs seconds

•The TFA9879 switches to Off mode and the serial interface input is toggled

•The TFA9879 switches back to Operating mode and soft mute is released

9.2.2 Mono selection

Mono selection is used to select the digital audio input channel to be amplified. The

options are:

•Left channel

•Right channel

•Left + right channels (sum divided by two)

Separate Mono selection is provided for the two serial interfaces via bits MONO_SEL in

the Serial interface control registers (addresses 01h and 03h; see Table 22).

9.2.3 Programmable high-pass filter

The TFA9879 features a first-order high-pass filter on the digital audio input to block DC

and low frequency signals. DC values at the output can damage the speaker.

The high-pass filte r cut-off frequency is determined by:

•The high-pass filter control setting (bits HP_CTRL, see Table 30)

•The sample frequency, fs

The relationship between these parameters and the cut-off frequency is defined in

Equation 1:

(1)

HP_CTRL can be programmed to any integer value between 0 and 511 (see Table 30).

The high-pass filter is bypassed if HP_CTRL = 0 or bit HPF_BP in the Bypass control

9.2.4 De-emphasis

Digital de-emphasis is sometimes needed, especially with older recordings. Emphasis

and de-emphasis originate in the FM transmission, in which the Signal-to-Noise Ratio

(SNR) is not flat over the signal band (in fact the SNR gets worse as the signal frequency

increases) . To achieve good SNR over the complete audio band, the high frequency

components of the audio signal were amplified prior to transmission (this is called

Emphasis).

fhigh 3dB–()

f–s4096 HP_CTRL–4096

---------------------------------------------

⎝⎠

⎛⎞

ln×

2π

----------------------------------------------------------------------

Product data sheet Rev. 02 — 15 October 2010 12 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The de-emphasis filter is a simple first order filter. The cut-off frequency of the

de-emphasis low-pass filter is approximately 3.5 kHz. The TFA9879 de-emphasis filter is

supported for four sample frequencies, as detailed in Table 6.

[1] Value selected via bits DE_PHAS in the De-emphasis, soft/hard mute and power limiter control register

(see Table 32).

[2] Default value.

9.2.5 Equalizer

The equalizer can be used for speaker curve compensation or for customer equalizer

settings, such as jazz, pop, rock or classical music. The equalizer function can be

bypassed or configured as 5-band.

9.2.5.1 Equalizer band function

The shape of each parametric equalizer band is determined by the following three filter

parameters:

•(Relative) center frequency

•Quality factor Q

•Gain factor G

In the above equation, fc is the center fr equency and fs is the sample frequency.

The definition of th e quality factor is the center frequency divided by the 3 dB bandwidth

(see Equation 2). In parametric equalizers this is only valid when the gain is set very low

(−30 dB).

(2)

Each band filter can be programmed to perform a band-suppression (G < 1) or a

band-amplification (G > 1) function around the center frequency.

Each band of the TFA9879 equalizer has a second order Regalia-Mitra all-pass filter

structure. The structure is shown in Figure 6.

Table 6. De-emphasis control

[1:0] Control value[1] fs (kHz)

00[2] de-emphasis inactive

01 32

10 44.1

11 48

ω2πfcfs

⁄()=

Qfc

f2f1

–

--------------;=

f1:20 Af1

Afc

-------

⎝⎠

⎜⎟

⎛⎞

log 3dB fcf1

f2:20 Af2

Afc

-------

⎝⎠

⎜⎟

⎛⎞

log 3dB f2fc

>,=

Product data sheet Rev. 02 — 15 October 2010 13 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The transfer function of this all-pass filter is given in Equation 3:

(3)

A(z) is the second order filter structure. The transfer functio n of A(z) is given in

Equation 4:

(4)

Z−1 equals one fs delay period. The relationship between the programmable parameters

K0, K1 and K2 and the filter p ara meters G, ω and Q is shown in Equation 5 and Equation 6.

Equation 5 can be used to calculate band suppression (G < 1) functions.

(5)

Equation 6 can be used to calculate band amplification (G ≥ 1) functions.

(6)

The ranges of the parametric equalizer settings for each ba nd are:

•The gain, G, is from −30 dB to +12 dB.

•The center frequen cy, fc, is from 0.00 04 ´ fs to 0.49 ´ fs.

•The quality factor, Q, is from 0.001 to 8.

Filter coefficient s need to be entered for each filter stage via the I2C-bus interface to

configure the filters (see Section 10.4.3).

Figure 7, Figure 8 and Figure 9 illustrate some possible equalizer band transfer functions.

The relationships are symmetrical for the suppression and amplification functions. A

skewing effect can be observed at higher frequencies.

Fig 6. Regalia-Mitra filter flow diagram

X(z)

A(z)

Y(z)

−

010aaa40

K0/2

Hz() 12⁄1Az()+()K02⁄1Az()–()⋅+⋅=

Az() K1K21K

+()Z1–Z2–

+⋅⋅+

21K

+()Z1–K1Z2–

⋅+⋅⋅+

-------------------------------------------------------------------------------

K0G=

K1ωcos–=

K22Q G ωsin–⋅()2Q G ωsin+⋅()⁄=G1<

K0G=

K1ωcos–=

K22Q ωsin–()2Q ωsin+()⁄=G1≥

Product data sheet Rev. 02 — 15 October 2010 14 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

For optimum numeri cal noise performance, different configurations are available for a

given filter tran sfer function. T he binary filter con figuration p arameters t 1 and t2 control the

actual configu ra tio n an d shou ld be cho se n ac co rd ing to Equation 7.

(7)

A maximum of 12 dB amplification, with respect to the input signal, can be achieved per

equalizer stage. The equalizer band signals are processed in sequence, from the highest

(Band A) to the lowest (Band E). Each band can attenuate the signal by 6 dB so, in order

to prevent numerical clipping at filter settings of over 6 dB amplification, band filters can

be scaled by 0 dB or −6 dB. For optimum numerical noise performance, steps of −6 dB

amplification should be applied to the ban ds in sequence, starting with B and A, as long as

they are able to amplify the signal without clipping.

A filter scale factor, s, is associated with each of the equalizer bands and is set via the

relevant EQx_s control bit (see Table 25).

9.2.5.2 Equalizer band control

For compact represen tation with po sitive signed parameters, parame te rs k1’ and k2’ are

introduced in Equation 8.

(8)

Parameters K0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1

and word2 (see Table 24 and Table 25), using the format shown in Table 8. Parameters k1'

and k2' are unsigned floating-point representations in Equation 8.

(9)

In Equation 9, M is the unsigned mantissa and E th e negative signed exponent. For

example, in word2 bits [14:8] = [0111 010] represent k2' = (7/24) × 2−2 = 1.09375 × 10−1.

Table 7. Equalizer filter scale factor settings

sscale factor (dB)

1−6

t10K

10≤

10>

⎝

⎜

⎛

20≥

20<

⎝

⎜

⎛

k0′K0

k1′1K

–t10=

+t11=

⎝

⎜

⎛

k2′1K

–t20=

+t21=

⎝

⎜

⎛

kx′M2

E–

⋅M1<

Product data sheet Rev. 02 — 15 October 2010 15 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Table 8. Equalizer control word construction

Word Section Data

word1 15 t1

word1 [14:4] 11 mantissa bits of k1’

word1 [3:0] four exponent bits of k1’

word2 15 t2

word2 [14:11] four mantissa bits of k2’

word2 [10:8] three exponent bits of k2’

word2 [7:1] k0’

word2 0 s

Fig 7. Transfer fun ctions for selected values of Q, the quality factor

Fig 8. Transfer fun ctio ns for selecte d values of fc, the center frequency

010aaa222

(dB)

f (Hz)

10 105

104

102103

Q1 = 0.27

Q2 = 0.61

Q3 = 1.65

010aaa223

f (Hz)

10 105

104

102103

(dB)

Product data sheet Rev. 02 — 15 October 2010 16 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9.2.6 Bass and treble control

The TFA9879 contains first order shelving filters for bass and treble control. The device

can attenuate or boost the bass and high frequency signals independently in 2 dB steps

within a −18 dB to +18 dB range. Attenuation and boosting are dependent on the audio

signal zero crossing settings (see Section 9.2.9 for further details). The bass and treble

corner freque ncie s ar e ad justable.

The bass and treble corner frequencies, as a function of the I2C control settings and the

sample rate, are giv en in Table 9.

[1] Value selected via bits F_BASS in the Bass and treble control register (see Table 29).

[2] Value selected via bits F_TREBLE in the Bass and treble control register (see Table 29).

[3] Default value.

Fig 9. Transfer fun ctions for selected values of G, the gain fac tor

010aaa224

f (Hz)

10 105

104

102103

-6

(dB)

-12

Table 9. Corner frequency settings for bass and treble control

Control value fs (kHz) Corner frequency (Hz)

Bass[1] Treble[2]

00 8, 16, 32, 64 181 1090

11.025, 22.05, 44.1, 88.2 250 1500

12, 24, 48, 96 272 1630

01[3] 8, 16, 32, 64 218 2180

11.025, 22.05, 44.1, 88.2 300 3000

12, 24, 48, 96 326 3260

10 8, 16, 32, 64 300 3000

11.025, 22.05, 44.1, 88.2 413 4130

12, 24, 48, 96 450 4500

11 reserved

Product data sheet Rev. 02 — 15 October 2010 17 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Figure 10 shows the bass function for a rang e of atte nu a tio n an d bo o st set t ings with a

sample rate of 48 kHz and a corner frequency of 272 Hz.

Figure 11 shows the treble function for a range of attenuation and boost settings with a

sample rate of 48 kHz and a corner frequ ency of 1630 Hz.

9.2.7 Muting

The TFA9879 support two muting options, which are controlled via the I2C-bus interface:

•Soft muting

•Hard muting

VDDP = 3.7 V, 2 ×8Ω BTL configuration, treble control = 0 dB, clip control on

Fig 10. Bass functio n in 2 dB steps; the treble control is set to flat

VDDP = 3.7 V, 2 ×8Ω BTL configuration, bass control = 0 dB, clip control on

Fig 11. Treble function in 2 dB steps; the bass control is set to flat

010aaa650

f (Hz)

10 105

104

102103

−10

−20

010aaa649

f (Hz)

10 105

104

102103

−10

−20

Product data sheet Rev. 02 — 15 October 2010 18 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Soft muting prevents audible pops. The function smoothly reduces the gain setting of the

audio channel to the mute level according to a raised cosine shape. Soft muting is

performed in 128 / fs step s. Soft de-mute result s in a similar gain increase. Bit S_MUTE in

Table 32 enables and disables the soft mute function.

The hard mute function immediately switches the outputs to 50 % duty-cycle pulses. As a

result, the input signals are abruptly blocked. Hard mute takes priority over soft mute.

Hard mute is enabled and disabled via bit H_MUTE in Table 32.

9.2.8 Digital volume control

The digital volume control has a range of −70 dB to + 24 dB, programmable in 0.5 dB

steps. The default setting is mute (0 ×BD). Attenuation and boosting behavior is affected

by the zero crossing volume setting (see Section 9.2.9 for further details).

The volume control settings, and the resulting amplification or suppression factors, are

detailed in Table 10.

[1] Control value is selected via bits VOL in the Volu me control register (see Table 31).

[2] Default value.

9.2.9 Zero-crossing volume control

The TFA9879 employs zero-cr ossing volume control to minimize pop noise when the

volume or bass/treble control is changing .

When zero-crossing volume control is enabled (ZR_CRSS = 1; see Table 31), the

TFA9879 increases or decreases the gain only when the audio signal passes a zero

crossing.

9.2.10 Dynamic Range Compressor (DRC)

The TFA9879 provides a DRC to automatically adjust power levels according to

programmable attack and release levels. The attack level is related to the peak value of

the signal; the release level is related to the RMS value of the signal. The attack level is

programmable using 16 available levels in the range −12 dB to +10 dB. The release level

is programmable using 16 available levels in the range −29 dB to 0 dB relative to the

attack level. The signal level is measured after Equa lizer , Bass and T reble pr ocessing, but

before it reaches the power limiter.

The DRC can be bypassed via bit DRC_BP in Table 27.

Table 10. Volume control amplification and sup pr ession

Control value [1] Gain (dB)

00h +24

01h +23.5

.. .... steps of 0.5 dB

BBh −69.5

BCh −70

BDh[2] mute

.. .... mute

FFh mute

Product data sheet Rev. 02 — 15 October 2010 19 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9.2.10.1 Functional description

The DRC compresses the dynamic range of the audio stream. The volume control,

equalizer or bass/treble controls can be set so that the audio stream exceeds the 0 dBFs

clip level. The DRC can be programmed to compress the louder audio content when this

occurs, while quieter sounds remain unaffected, i.e. the DRC soft clips the audio stream.

This is useful when background noise overpowers quiet audio passages. Increasing the

volume using the volume contro l can make quiet audio passages audible but can cause

louder audio passages to be distorted by clipping. The DRC prevents this distortion

happening by reducin g the volume during loud audio passages and increasing it again for

quiet passages.

The design of the DRC feedback loop, incorporating the equalizer and bass and treble

controls, is illustrated in Figure 12.

9.2.10.2 DRC control

The DRC has four programmable control settings:

•Attack level

•Attack rate

•Release level

•Release rate

The DRC reduces the volume when the audio signal level exceeds the attack level. The

attack level is based on th e audio peak value. When the audio signal level drops below

the attack level, the DRC stops reducing the volume. The rate of decrease is

programmable via the attack rate. The DRC increases the audio signal level again when it

drops below the release level. This level is based on the audio RMS-value and is related

to the attack level. The rate of increase is programmable via the release level. The DRC

stops increasing the volume when the audio signal leve l rea ches the release level or the

DRC volume falls to 0 dB.

Figure 13 shows the attack and release behavior of the DRC.

Fig 12. DRC feedback design

010aaa55

PARAMETRIC

5-BAND

EQUALIZER

BASS AND

TREBLE

CONTROL

LIMITER

RMS

volume control

setting

audio in

DRC volume

DRC

Product data sheet Rev. 02 — 15 October 2010 20 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

[1] The control value is selected via bits AT_LVL in the DRC control register (see Table 28).

[2] The control value is selected via bits RL_LVL in the DRC control register (see Table 28).

[3] 0 dB (RMS) release level equals 0 dB (peak) attack level.

[4] Default value.

Fig 13. DRC attack and release behavior

release level (RMS-value)

audio in

audio out RMS value

release rate (dB/ms)

attack level (peak value)

attack rate (dB/ms)

attack level (peak value)

010aaa65

Table 11. DRC att ack and release levels

Control value:

attack level[1] Attack level based on

peak value; absolute

value (dBFS)

Control value:

release level[2] Release level based on RMS

value (relative to the attack

level[3]) (dB)

0000 −12 0000 −29

0001 −10 0001 −26

0010 −8 0010 −23

0011 −6 0011 −20

0100 −5 0100 −18

0101 −4 0101 −16

0110 −30110−14

0111 −2 0111 −12

1000 −1 1000 −10

1001[4] 0 1001 −8

1010 1 1010 −6

1011 2 1011[4] −4

1100 4 1100 −3

1101 6 1101 −2

1110 8 1110 −1

1111 10 1111 0

Product data sheet Rev. 02 — 15 October 2010 21 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

[1] The control value is selected via bits AT_RATE in the DRC control register (see Table 28).

[2] The control value is selected via bits RL_RATE in the DRC control register (see Table 28).

[3] Default value.

9.2.11 Power limiter

The power limiter contro ls the maximum output voltage in Amplifier mode. This featur e

makes it possible to limit the output voltage across a peripheral (speaker) when

necessary.

The TFA9879 output voltage is dependent on:

•The analog supply voltage on pin VDDP

•The gain of the power limiter (G)

•The power limiter input signal (Xi)

The bass/treble output signal is connected to the power limiter input and is relative to the

Fraction of Full Scale (FFS), from −1 to +1.

Equation 10 shows the relationship between these settings and the output voltage

between pins OUTA and OUTB in the audio bandwidth:

(10)

Equation 10 only applies with no load and with clip control off (see Section 9.3). Clip

control and the RDSon of the po wer switches reduce the maximum clipped output signal.

The power limiter gain can be reduced in 249 steps of 0.5 dB in the range 0 dB to

−124 dB.

Table 12. DRC atta ck and release rates

Control value:

attack rate[1] Attack rate (dB/ms) Control value:

release rate[2] Release rate (dB/ms)

0000 3 0000 0.5

0001 2.7 0001 0.137

0010[3] 2.25 0010 0.075

0011 1.8 0011 0.05

0100 1.35 0100 0.036

0101 0.9 0101 0.03

0110 0.45 0110 0.026

0111 0.225 0111 0.021

1000 0.15 1000 0.020

1001 0.11 1001 0.017

1010 0.09 1010[3] 0.015

1011 0.075 1011 0.014

1100 0.065 1100 0.013

1101 0.06 1101 0.012

1110 0.055 1110 0.011

1111 0.05 1111 0.01

XiG×5.91×

VDDP

⎝

⎜

⎛

=XiG×5.91 VDDP

<×

XIG×5.91 VDDP

≥× (V)

Product data sheet Rev. 02 — 15 October 2010 22 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The maximum peak output voltage for the first ten power limiter gain settings is given in

Table 13.

[1] The control value is selected via bits P_LIM in the De-emphasis, soft/hard mute and power limiter control

[2] Default value.

9.3 Class-D amplification and clip control

A fourth order sigma delta PWM converter converts the digital audio streams into 3-level

modulated PWM signals. The analog back end amplifies the two PWM signals in a BTL

configuration with complementary output stages.

One of two clip control configurations can be selected :

•Smooth clipping , clip control on

•Maximum power, clip control off

If smooth clipping is selected (CLIPCTRL = 0; see Table 27), the clipping behavior will

have no artefa cts . To obtain th e maximum possible ou tput power, the device can be set to

maximum power.

The PWM frequency is related to the I2S input sample rate as detailed in Table 4.

9.4 Protection

The TF A9879 incorporates a wide range of protection circuit s to facilitate optimal and safe

application.

The following protection circuits are included in the TFA9879:

Table 13. Power limiter control settings

All parameters are guaranteed for VDDP = 5 V; no load; fi = 1 kHz; fs = 48 kHz; clip control off;

Tamb =25

C unless otherwise specified.

Control value [1] Power limiter gain (dB) Maximum peak output voltage (V)

00h[2] 0.0 VDDP

01h −0.5 VDDP

02h −1.0 VDDP

03h −1.5 VDDP

04h −2.0 4.7

05h −2.5 4.4

06h −3.0 4.2

07h −3.5 4.0

08h −4.0 3.7

09h −4.5 3.5

Table 14. Power limiter control settings

PWM frequency (kHz) Sample rate (kHz) SCK relative to sample rate

256 8, 16, 32, 64 32 ×, 64 ×

352.8 11.025, 22.05, 44.1, 88.2 32 ×, 64 ×

384 12, 24, 48, 96 32 ×, 64 ×

Product data sheet Rev. 02 — 15 October 2010 23 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

•OverTemperature Protection (OTP)

•OverCurrent Protection (OCP)

•UnderFrequency Protection (UFP)

•OverFrequency Protection (OFP)

•Invalid Bit-clock Prot ec tio n (IBP )

•DC-blocking via high-pass filter (see Section 9.2.3)

The reaction of the device to fault conditions differs depending on the protection circuit

involved.

9.4.1 OverTemperature Protection (OTP)

This is a ‘hard’ protection to prevent heat damage to the TFA9879. Overtemperature

protection is triggered when the junction temperature exceeds 130 °C. When this

happens, the output stages are set floating. OTP can be cleared automatically via a

programmable timer or via the I 2C-bus interface, after which the output stages will start to

operate normally again. The programmable timer settings, selected via bits L_OTP in the

Bypass control register (Table 27), are:

•4.5 μs

•100 ms

•1 s

OTP can also be set to no recovery. Setting the TFA9879 to Off mode and subsequently

to Amplifier mode clears the OTP when no recovery is selected.

9.4.2 OverCurrent Protection (OCP)

The output current of the class-D amplifiers is current limited. When an output stage

exceeds a current in the range 1.3 A to 2.3 A, the output stages are set floating. OCP can

be cleared automatically via a programmable timer or via the I2C-bus interface, after

which the output stages will start to operate normally again. The programmable timer

settings, selected via bits L_OCP in the Bypass control register (Table 27), are:

•4.5 μs

•27.5 μs

•10 ms

The OCP can also be set to no recovery. Setting the TFA9879 to Off mode and

subsequently to Amplifier mode clears the OCP when no recovery is selected.

9.4.3 UnderFrequency Protection (UFP)

UFP sets the output stages floating when the clock input source is too low (< fUFP). This

can happen if, for example, the selected sample frequency (bits I2S_FS in Table 22) is not

in line with the applied sample rate. The PWM switching frequency can become critically

low when the frequency of the input clock is lower than the selected sample frequency.

Without UFP, peripheral devices in an application might be damaged.

The UFP status can be monitored by polling the I2C status register (Table 33). The alarm

will be raised when the input sample rate is too low.

Product data sheet Rev. 02 — 15 October 2010 24 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

9.4.4 OverFrequency Protection (OFP)

OFP sets the output stages floating when the clock input source is too high (>fOFP). This

can happen if, for example, the selected sample frequency (bits I2S_FS in Table 22) is not

in line with the applied sample rate. The PWM controller can become unstable when the

frequency of the input clock is higher than the selected sample frequency. Without OFP,

peripheral devices in an application might be damaged.

The OFP status can be monitored by polling the I2C status register (Table 33). The alarm

will be raised when the input sample rate is too high.

9.4.5 Invalid Bit-clock Protection (IBP)

If the SCK-to-LRCK ratio is not supported, the audio signal will be distorted. This occurs

because the sound processing blocks will be operating at frequencies out of

synchronization with the sample rate.

IBP prevents this happening by shutting down the TFA9879 if the IBP alarm is raised for

the selected channel. This will disconnect the digital audio path.

Valid SCK-to-LRCK ratios for PCM interface formats are 16, 32, 48, 64, 96, 128 and 192.

For I2S interface formats, valid SCK-to-LRCK ratios are 32 and 64.

9.4.6 Overview of protection circuits

Table 15 provides an overview of the protection circuits implemented.

10. I2C-bus interface and register settings

10.1 I2C-bus interface

The TFA9879 supports the 40 0 kHz I2C-bus microcontroller in terface mode st andard. The

I2C-bus is used to control the TFA9879 and to transmit and receive data.

The TFA9879 can operate only in I2C slave mode, as a slave receiver or as a slave

transmitter.

Table 15 . Overview of protection circuits

Protection circuits

Symbol Conditions I2C flag Output Recovery

OTP Tj > 130 °C OTP floating automatic when timer set to 4.5 μs, 100 ms or 1 s (via bits

L_OTP in Table 27) and Tj< 130 °C;

via I2C-bus when no recovery is selected

OCP IO > IO(ocp) OCP floating automatic when ti mer set to 4.5 μs, 27.5 μs or 10 μs (via

bits L_OCP in Table 27) and IO< I

O(ocp);

via I2C-bus when no recovery is selected

UFP PWM frequency <

96 kHz UFP floating restart (fault to operating when PWM frequency > 96 kHz)

OFP PWM frequency >

1031 kHz OFP floating restart (fault to operating when PWM frequency <

1031 kHz)

IBP SCK/WS is not 16 ±1, 32 ±1,

48 ± 1, 64 ± 1 or 128 ±1IBP floating restart (fault to operating when SCK/WS is 16 ±1, 32 ±1,

48 ± 1, 64 ± 1 or 128 ±1)

Product data sheet Rev. 02 — 15 October 2010 25 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The TFA9879 is accessed via an 8-bit code (see Table 16). Bits 1 to 7 contain the device

address. Bit 0 (R/W) indicates whether a read (1) or a write (0) operation has been

requested. Four separate addresses are supported for multichannel applications.

Applying the appropriate voltage to pins ADSEL1 (A1) and ADSEL2 (A2) select the

required I2C address as detailed in Table 16.

10.2 I2C-bus write cycle

The sequence of events that needs to be followed when writing data to the TFA9879’s

I2C-bus registers is detailed in Table 18. One byte is transmitted at a time. Each register

stores two bytes of data. Data is always written in byte pairs. Data transfer is always MSB

first.

The write cycle sequence using SDA is as follows:

1. The microcontroller asserts a start condition (S).

2. The microcontroller transmits the 7-bit device address of the TFA9879, followed by

the R/W bit set to 0.

3. The TFA9879 asserts an acknowledge (A).

4. The microcontroller transmits the 8-bit TFA9879 register address to which the first

data byte will be written.

5. The TFA9879 asserts an acknowledge.

6. The microcontroller transmits the first byte (the most significant byte).

7. The TFA9879 asserts an acknowledge.

8. The microcontroller transmits the second byte (the least significant byte).

9. The TFA9879 asserts an acknowledge.

10. The microcontroller can either assert the stop condition (P) or continue transmitting

data by send ing another p air of data bytes, re peating the sequence fr om step 6. In the

latter case, the targeted register address will have been auto-incremented by the

TFA9879.

Table 16. I2C-bus device address

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

1 1011A2A1R/W

Table 17. I2C pin volt ages in I2C control mode

Logic value Voltag e on pins ADSEL1 an d ADSEL2

0< V

1> V

Table 18 . I2C-bus write cycle

Start TFA9879

Address R/W TFA9879 first

data... Stop

S 11011A2A10 A ADDR A MS1 A LS1 A <....> P

Product data sheet Rev. 02 — 15 October 2010 26 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.3 I2C-bus read cycle

The sequence of event s that ne eds to be followed wh en reading da t a from the TFA9879’s

I2C-bus registers is detailed in Table 19. One byte is transmitted at a time. Each of the

registers stores two bytes of dat a. Data is always written in byte pairs. Data transfer is

always MSB first.

The read cycle sequence using SDA is as follows:

1. The microcontroller asserts a start condition (S).

2. The microcontroller transmits the 7-bit device address of the TFA9879, followed by

the R/W bit set to 0.

3. The TFA9879 asserts an acknowledge (A).

4. The microcontroller transmits the 8-bit TFA9879 register address from which the first

data byte will be read.

5. The TFA9879 asserts an acknowledge.

6. The microcontroller asserts a repeated start (Sr).

7. The microc on tr olle r re -tr a nsm its the device addr es s follo we d by th e R/W bit set to 1.

8. The TFA9879 asserts an acknowledge.

9. The TFA9879 transmits the first byte (the MSB).

10. The microcontroller asserts an acknowledge.

11. The TFA9879 transmits the second byte (the LSB).

12. The microcontroller asserts either an acknowledge or a negative acknowledge (NA).

–If the microcontroller asserts an acknowledge, the target register address is

auto-increased by the TFA9879 and steps 9 to 12 are repeated.

–If the microcontroller asserts a negative acknowledge, th e TFA9879 frees the

I2C-bus and the microcontroller generates a stop condition (P).

10.4 Top-level register map

Table 20 describes the top-level assignment of register a ddresses to the functional control

and status are as. There are 21 control registers and 1 status register.

Table 19 . I2C-bus read cycle

Start TFA9879

address R/W First

address

TFA9879

address R/W MSB LSB More

data... Stop

S11011A

2A10AADDRASr11011A

2A11 A MS1 A LS1 A <....> NA P

Table 20. Top-level register map

00h 0x0000 R/W device control; see Table 21

01h 0x0A18 R/W serial Interface input 1; see Table 22

02h 0x0007 R/W PCM/IOM2 format input 1; see Table 23

03h 0x0A18 R/W serial Interface input 2; see Table 22

04h 0x0007 R/W PCM/IOM2 format input 2; see Table 23

05h 0x59DD R/W equalizer_A word_1; see Table 24

Product data sheet Rev. 02 — 15 October 2010 27 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

The following subsections provide details of the of the bits in these registers and the

control and status functionality assigned to each.

10.4.1 Device control

06h 0xC63E R/W equalizer_A word_2; see Table 25

07h 0x651A R/W equalizer_B word_1; see Table 24

08h 0xE53E R/W equalizer_B word_2; see Table 25

09h 0x4616 R/W equalizer_C word_1; see Table 24

0Ah 0xD33E R/W equalizer_C word_2; see Table 25

0Bh 0x4DF3 R/W equalizer_D word_1; see Table 24

0Ch 0xEA3E R/W equalizer_D word_2; see Table 25

0Dh 0x5EE0 R/W equalizer_E word_1; see Table 24

0Eh 0xF93E R/W equalizer_E word_2; see Table 25

0Fh 0x0093 R/W bypass control; see Table 27

10h 0x92BA R/W dynamic range compressor; see Table 28

11h 0x12A5 R/W bass and treble; see Table 29

12h 0x0004 R/W high-pass filter; see Table 30

13h 0x10BD R/W volume control; see Table 31

14h 0x0000 R/W de-emphasis, soft/hard mute and power

limiter; see Table 32

15h - R miscellaneous status; see Table 33

Table 20. Top-level register map …continued

Table 21. Device control register (address 00h) bit descrip t ion

Bit Symbol Access Default Description

15:5 reserved 0x000

4 INPUT_SEL R/W 0 serial interface input selection:

0: serial interface input 1

1: serial interface input 2

3 OPMOD E R/W 0 opera ting mode selection:

0: Off mode

1: Amplifier mode

2 reserved 0

1 RESET R/W 0 I2C reset activation:

0: reset inactive

1: reset active; 1 is written to generate a reset, after

which the RESET bit is automatically reset to 0

0 POWERUP R/W 0 Power-down mode selection:

0: Power-down mode

1: operating mode (dependent on OPMODE)

Product data sheet Rev. 02 — 15 October 2010 28 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.2 Serial interface control

Table 22. Serial interface control registers (addr esses 01h and 03h[1]) bit description

Bit Symbol Access Default Description

15:12 reserved 0000

11:10 MONO_SEL R/W 10 mono selection:

00: left channel; left channel content is amplified in

Amplifier mode

01: right channel; right channel content is amplified in

Amplifier mode

10: left + right channels; sum of left and right

channels, divided by two, is amplified in Amplifier

mode

11: reserved

9:6 I2S_FS R/W 1000 sample frequency (fs) of digital-in signal:

0000: 8 kHz

0001: 11.025 kHz

0010: 12 kHz

0011: 16 kHz

0100: 22.05 kH z

0101: 24 kHz

0110: 32 kHz

0111: 44.1 kHz

1000: 48 kHz

1001: 64 kHz

1010: 88.2 kHz

1011: 96 kHz

1100 to 1111: reserved

5:3 I2S_SET R/W 011 I2S format selection:

000: reserved

001: reserved

010: MSB-justified data up to 24 bits

011: I2S data up to 24 bits

100: LSB-justified 16-bit data

101: LSB-justified 18-bit data

110: LSB-justified 20-bit data

111: LSB-justified 24-bit data

2 SCK_POL R/W 0 enable SCK signal polarity inversion:

0: no SCK signal polarity inversion

1: SCK signal polarity inversion enabled

Product data sheet Rev. 02 — 15 October 2010 29 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

[1] Serial interface 1 settings are controlled via register 01h; serial interface 2 settings are controlled via

[1] PCM/IOM2 format settings of serial interface 1 are controlled via register 02h; PCM/IOM2 format settings of

serial interface 2 are contro lled via register 04h.

1:0 I_MODE R/W 00 input audio mode selection:

00: I2S mode

01: PCM/IOM2 Short Frame Sync Format

10: PCM/IOM2 Long Frame Sync Format

11: reserved

Table 23. PCM/IOM2 format control registers (addresses 02h and 04h[1]) bit description

Bit Symbol Access Default Description

15:12 reserved 0000

11 PCM_FS R/W 0 PCM sample frequency:

0: 8 kHz

1: 16 kHz

10 A_LA W R/W 0 U-LAW/A-LAW decoding selection (depending on

PCM_COMP):

0: U-law decoding; default value

1: A-law decoding

9 PCM_COMP R/W 0 companded PCM data:

0: linear

1: companded (U/A-law)

8 PCM_DL R/W 0 PCM data length (number of bits per slot):

0: 8-bit; default value

1: 16-bit

7:4 D1_SLOT R/W 0000 slot number position of the first sample (at 8 kHz and

16 kHz):

0000: slot 0

0001: slot 1

.. ..

1111: slot 15

3:0 D2_SLOT R/W 0111 slot number position of the second sample (16 kHz):

0000: slot 0

0001: slot 1

.. ..

0111: slot 7

.. ..

1111: slot 15

Table 22. Serial interface control registers (addr esses 01h and 03h[1]) bit description

Bit Symbol Access Default Description

Product data sheet Rev. 02 — 15 October 2010 30 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.3 Equalizer configuration

[1] Default settings are given in Table 20. The corresponding equalizer configuration is shown in Table 26.

Table 24. Equalizer word1 control registers (addresses 05h, 07h, 09h, 0Bh and 0Dh for

equalizer bands A, B, C, D and E respectively) bit description

‘x’ represents the equalizer band A, B, C, D or E

Bit Symbol Access Default[1] Description

15 EQx_t1 R/W filter configuration parameter t1; see section

Section 9.2.5.1

14:4 EQx_k1m R/W 11 mantissa bits of filter parameter k1’; see

Section 9.2.5.1

3:0 EQx_k1e R/W four exponent bits of filter parameter k1’; see

Section 9.2.5.1

Table 25. Equalizer word2 control register (addresses 06h, 08h, 0Ah, 0Ch and 0Eh for

equalizer bands A, B, C, D and E respectively) bit description

‘x’ represents the equalizer band A, B, C, D or E

Bit Symbol Access Default[1] Description

15 EQx_t2 R/W filter configuration parameter t2; see section

Section 9.2.5.1

14:11 EQx_k2m R/W four ma ntissa bits of filter parameter k2’; see

Section 9.2.5.1

10:8 EQx_k2e R/W three exponent bits of filter parameter k2’; see

Section 9.2.5.1

7:1 EQx_K0 R/W seven-bit of filter gain parameter K0; see

Section 9.2.5.1

0 EQx_s R/W filter scale-factor (s); see Section 9.2.5.1

0: no scaling applied

1: −6 dB amplification enabled

Table 26. Default equalizer configurati on for fs = 48 kH z

Band A B C D E

Frequency (Hz) 100 300 1000 3000 10000

Q-factor 1.65 1.65 1.65 1.65 1.65

Gain (dB)00000

Product data sheet Rev. 02 — 15 October 2010 31 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.4 Bypass control

10.4.5 Dynamic range compressor

Table 27. Bypass control register (addresses 0Fh) bit description

Bit Symbol Access Default Description

15:8 reserved 0x00

7:6 L_OCP R/W 10 overcurren t protection timer setting:

00: 4.5 μs floating when an overcurrent is detected

01: 27.5 μs floating when an overcurrent is detected

10: 10 ms floating when an overcurrent is detected

11: no recovery (stays floating) when an overcurrent

is detected

5:4 L_OTP R/W 01 overtemperature protection timer setting:

00: 4.5 μs floating when an overtemperature is

detected

01: 100 ms floating when an overtemperature is

detected

10: 1 s floating when an overtemperature is detected

11: no recovery (stays floating) when an

overtemperature is detected

3 CLIPCTRL R/W 0 clip control bypass setting, see Section 9.3:

0: clip control on (smooth clipping)

1: clip control off (maximum power)

2 HPF_BP R/W 0 high-pass filter bypass setting:

0: high-pass filter active

1: high-pass filter bypassed

1 DRC_BP R/W 1 dynamic range compressor bypass setting:

0: dynamic range compression active

1: dynamic range compression bypassed

0 EQ_BP R/W 1 equa lizer bypass setting:

0: equalizer active

1: equalizer bypassed

Table 28. DRC control register (addresses 10h) bit description

Bit Symbol Access Default Description

15:12 AT_LVL R/W 1001 dynamic range compressor attack level; see Table 11 for

the attack level as a function of the value of AT_LTV.

11:8 AT_RATE R/W 0010 dynamic range compressor attack rate; see Table 12 for

the attack rate as a function of the value of AT_RATE

37:4 RL_LVL R/W 1011 dynamic range compressor release level; see Table 11

for the release level as a function of the value of

RL_LTV.

3:0 RL_RATE R/W 1010 dynamic range compressor release rate; see Table 12

for the release rate as a function of the value of

RL_RATE

Product data sheet Rev. 02 — 15 October 2010 32 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.6 Bass and treble control

10.4.7 High-pass filter

[1] Default value is 04h. From Equation 1, this gives a high-pass cut-off frequency of approximately 1.6 × fs.

Table 29. Bass and treble control register (add resses 11h) bit desc ription

Bit Symbol Access Default Description

15:14 reserved

13:9 G_TRBLE R/W 01001 treble gain (2 dB steps):

00000: −18 dB

00001: −16 dB

.. ..

01001: 0 dB

.. ..

10001: +16 dB

10010: +18 d8

10011 to 11111: reserved

8:7 F_TRBLE R/W 01 treble control corner frequency, see Table 9 for the

corner frequency as a function of the value of

F_TREBLE

6:2 G_BASS R/W 01001 bass gain (2 dB steps):

−18 dB

−16 dB

.. ..

01001: 0 dB

.. ..

+16 dB

+16 d8

reserved

1:0 F_BASS R/W 01 bass control corner freque ncy, see Table 9 for the

corner frequency as a function of the value of F_BASS

Table 30. High-pass filter control register (addresses 12h ) bit description

Bit Symbol Access Default Description

15:9 reserved

8:0 HP_CTRL R/W 0x04[1] high-pass filter control, see Section 9.2.3 for a

discussion of the high pass corner frequency as a

function of the value of HP_CTRL

Product data sheet Rev. 02 — 15 October 2010 33 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.8 Volume control

10.4.9 De-emphasis, soft/hard mute and power limiter

Table 31. Volume control register (address 13h) bit description

Bit Symbol Access Default Description

15:13 reserved 000

12 ZR_CRSS R/W 1 volume up date at zero crossing audio stream:

0: zero-crossing volume control disabled

1: zero-crossing volume control enabled; default

value

11:8 reserved R/W 0000

7:0 VOL R/W 0xBD volume control; see Table 10 for the amplification and

suppression factors as a function of the value of bits

VOL

Table 32. De-emphasis, soft/hard mute and power limiter control register (address 14h) bit

description

Bit Symbol Access Default Description

15:12 reserved 0000

11:10 DE_PHAS R/W 00 de-emphasis settings, seeTable 6 for the de-emphasis

configuration for four sample rates as a function of the

value of DE_PHASE

9 H_MUTE R/W 0 hard mute :

0: no hard mute; default value

1: hard mute enabled; implemented by PWM signal

with 50% duty-cycle

8 S_MUTE R/W 0 soft mute; default value:

0: soft mute disabled using raised cosine

1: soft mute enabled using raised cosine

7:0 P_LIM R/W 0xBD power limiter control settings; see Table 13 for

suppressions factors as a function of the value of P_LIM

Product data sheet Rev. 02 — 15 October 2010 34 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

10.4.10 Miscellaneous status

Table 33. Miscellaneous status register (address 15h) bit description

Bit Symbol Access Description

15 reserved

14 PS R power stage status:

0: class-D audio amplifier po wer stage flo ating

1: class-D audio amplifier power stage switching; PWM signals

on pins OUTA and OUTB

13 PORA R analog 1V8 regulator status:

0: 1V8 analog regulator is off or output voltage level is too low

1: 1V8 analog regulator output is available and correct

12:11 reserved

10:9 AMP R Amplifier mode status:

00: amplifier is off

01: startup

10: startup

11: amplifier is functional

8 IBP(2) R invalid bit clock protection on serial interface input 2:

0: the ratio in frequency be tween the signal on pin SCK2 and

the signal on pin LRCK2 is valid for the selected in terface

format

1: the ratio in frequency be tween the signal on pin SCK2 and

the signal on pin LRCK2 is invalid for the selected interface

format

7 OFP(2) R overfrequency protection on serial interface input 2:

0: the frequency of the signal on pin LRCK2 is in line with (or

lower than) the selected interface format

1: the frequency of the signal on pin LRCK2 is higher than the

selected interface format

6 UFP(2) R underfrequency protection on serial interface input 2:

0: the frequency of the signal on pin LRCK2 is in line with (or

higher than) the selected interface format

1: the frequency of the signal on pin LRCK2 is lower than the

selected interface format

5 IBP(1) R invalid bit clock protection on serial interface input 1:

0: the ratio in frequency be tween the signal on pin SCK1 and

the signal on pin LRCK1 is valid for the selected in terface

format

1: the ratio in frequency be tween the signal on pin SCK1 and

the signal on pin LRCK1 is invalid for the selected interface

format

4 OFP(1) R overfrequency protection on serial interface input 1:

0: the frequency of the signal on pin LRCK1 is in line with (or

lower than) the selected interface format

1: the frequency of the signal on pin LRCK1 is higher than the

selected interface format

Product data sheet Rev. 02 — 15 October 2010 35 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

3 UFP(1) R underfrequency protection on serial interface input 1:

0: the frequency of the signal on pin LRCK1 is in line with (or

higher than) the selected interface format

1: the frequency of the signal on pin LRCK1 is lower than the

selected interface format

2 OCPOKA R overcurrent protection on pin OUTA:

0: overcurrent protection on pin OUTA active

1: overcurrent protection on pin OUTA inactive

1 OCPOKB R overcurrent protection on pin OUTB:

0: overcurrent protection on pin OUTB active

1: overcurrent protection on pin OUTB inactive

1 OTPOK R overtemperature protection:

0: overtemperature protecti on active

1: overtemperature protection inactive

Table 33. Miscellaneous status register (address 15h) bit description …continued

Bit Symbol Access Description

Product data sheet Rev. 02 — 15 October 2010 36 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

11. Internal circuitry

Table 34. Inter nal circuitry

Pin Symbol Equivalent circuit

1SDA

2SCL

3 TEST1

4 ADSEL2

5 TEST3

16 ADSEL1

17 SDI2

18 SCK2

19 LRCK2

20 SDI1

21 SCK1

22 LRCK2

7,8 VDDP

010aaa63

ESD

11, 12, 24

010aaa63

ESD

11, 12, 24

2 to 5

16 to 22

010aaa63

11, 12, 24

7, 8

ESD

Product data sheet Rev. 02 — 15 October 2010 37 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

12. Limiting values

9OUTB

10 OUTA

13 STABA

15 TEST2

Table 34. Inter nal circuitry

Pin Symbol Equivalent circuit

010aaa6

11, 12, 24

7, 8

9, 10

010aaa63

ESD

11, 12, 24

7,8

010aaa63

11, 12, 24

7, 8

ESD

Table 35. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDDA analog supply voltage on pin VDDP −0.3 +5.5 V

VDDD digital supply voltage on pin VDDD −0.3 +1.95 V

Tjjunction temperature - +150 °C

Tstg storage temperature −55 +150 °C

Tamb ambient temperature −20 +85 °C

Vxvoltage on pin x pins LRCKx, SCKx, SDIx, SDA, SCL,

ADSEL1, ADSEL2, TEST1 and TEST3 −0.3 +3.6 V

pin TEST2 −0.3 VDDP +0.3 V

pins OUTA and OUTB −0.6 VDDP +0.6 V

pin STABA −0.3 +1.95

VESD electrostatic discharge voltage according to Human Body Model (HBM) −2+2 kV

according to Charge Device Model (CDM) −500 +500 V

Product data sheet Rev. 02 — 15 October 2010 38 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

13. Thermal characteristics

[1] Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7).

[2] Value depends on where measurement is taken on package.

Table 36 . Thermal cha racteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient in free air with natural convection

JEDEC test board [1] 49 K/W

2-layer application board 67 K/W

Ψj-lead thermal characterization parameter from

junction to lead 23 K/W

Ψj-top thermal characterization parameter from

junction to top of package [2] 6K/W

Rth(j-c) thermal resistance from junction to case in free air with natural convection 5 K/W

Product data sheet Rev. 02 — 15 October 2010 39 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

14. Characteristics

14.1 DC Characteristics

[1] After switching from Off/Amplifier mode to Power-down mode.

Table 37 . DC characteristics

All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8

; LL = 44

H; fi = 1 kHz; fs = 48 kHz; clip control off;

Tamb = 25

C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VDDP power supply voltage on pin VDDP 2.5 - 5.5 V

VDDD digital supply voltage on pin VDDD 1.65 1.8 1.95 V

IPsupply current on pin VDDP; Amplifier mode with

load; soft mute on -5.7-mA

on pin VDDP; Power-down mode - - 20 μA

IDDD digital supply current on pin VDDD; Amplifier mode - 1.2 - mA

on pin VDDD; Power-down mode [1] -515μA

Series resistance output power switches

RDSon drain-source on-state resistance lower switch (NMOS) - 190 - mΩ

upper switch (PMOS) - 260 - mΩ

Amplifier output pins; OUTA and OUTB

VO(offset) output offset voltage −15 0 +15 mV

Regulator, pin STABA

VO(reg) regulator output voltage STABA to GNDP 1.65 - 1.95 V

LRCK1, SCK1, SDI1, LRCK2, SCK2, SDI2, SDA, SCL, ADSEL1 and ADSEL2

VIH HIGH-level input voltage 0.7VDDD -- V

VIL LOW-level input voltage - - 0.3VDDD V

Ciinput capacitance - - 3 pF

VOL LOW-level output voltage at IOL = 2.6 mA - - 400 mV

Protection

Tact(th_prot) thermal protection activation

temperature 130 - - °C

IO(ocp) overcurrent protection output current 1 .3 - 2.3 A

fOFP overfrequency protection frequency at PWM output frequency - 710 1031 kHz

fUFP underfrequency protection frequency at PWM output frequency 96 175 - kHz

Product data sheet Rev. 02 — 15 October 2010 40 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

14.2 AC characteristics

Table 38 . AC characteristics

All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8

; LL = 44

H; fi = 1 kHz; fs = 48 kHz; clip control off;

Tamb = 25

C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Class D amplifier

Po(RMS) RMS outpu t po w e r RL=8Ω

THD+N = 1 % 0.65 0.7 - W

THD+N = 10 % - 0.85 - W

RL=4Ω

THD+N = 1 % - 1.2 - W

THD+N = 10 % - 1.5 - W

RL=8Ω; VDDP = 4.2 V

THD+N = 1 % - 0.9 - W

THD+N = 10 % - 1.1 - W

RL=4Ω; VDDP = 4.2 V

THD+N = 1 % - 1.6 - W

THD+N = 10 % - 1.95 - W

RL=8Ω; VDDP = 5.0 V

THD+N = 1 % - 1.35 - W

THD+N = 10 % - 1.6 - W

RL=4Ω; VDDP = 5.0 V

THD+N = 1 % - 2.35 - W

THD+N = 10 % - 2.75 - W

ηpo output power efficiency Po(RMS) = 850 mW - 92 - %

THD+N total harmonic distortion-plus-noise Po(RMS) = 100 mW - 0.02 0.1 %

Vn(o) output noise voltage soft mute; A-weighted - 60 - μV

S/N signal-to-noise ratio VPVDD = 5 V; Po(RMS) = 1.3 W; A-weighted - 94 - dB

PSRR pow er supply rejection ratio Vripple =200 mV; f

ripple = 217 Hz 65 80 - dB

Vo(RMS) RMS output voltage At −9 dBFS (RMS) digital input

volume control = 0 dB

bass and treble control = 0 dB

equalizer bypassed and DRC bypassed

1.9 2.1 2.3 V

Power-up, power-down and propagation times

td(on) turn-on delay time Off mode to Operating mode, soft de-mute

excluded -- 5.6ms

td(mute_off) mute off delay time - - 2.67 ms

td(soft_mute) soft mute delay time - - 2.67 ms

tPD propagation delay bass and treble control = 0 dB, equalizer

bypassed and DRC bypassed. -600-μs

Product data sheet Rev. 02 — 15 October 2010 41 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

14.3 I2C timing characteristics

[1] Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.

[2] After this period, the first clock pulse is generated.

Table 39 . I2C-bus interface characteristics; see Figure 14

All parameters are guaranteed for VDDP = 3.7 V, RL = 8

, LL = 44

H; fi = 1 kHz; fs = 48 kHz; clip control off; Tamb = 25

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fSCL SCL clock frequency - - 400 kHz

tLOW LOW period of the SCL clock 1.3 - - μs

tHIGH HIGH period of the SCL clock 0.6 - - μs

trrise time SDA and SCL signals [1] 2 0 + 0. 1 C b-- ns

tffall time SDA and SCL signals [1] 20 + 0.1 Cb-- ns

tHD;STA hold time (repeated) START

condition [2] 0.6 - - μs

tSU;STA set-up time for a repeated START

condition 0.6 - - μs

tSU;STO set-up time for STOP condition 0.6 - - μs

tBUF bus free time between a STOP and

START condition 1.3 - - μs

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - μs

tSP pulse width of spikes that must be

suppressed by the input filter 0 - 50 ns

Cbcapacitive load for each bus line - - 400 pF

Fig 14. I2C tim ing

tBUF tLOW trtf

tHD;STA tSU;STA

tHD;DAT tHIGH tSU;DAT

tHD;STA

tSU;STO

tSP

P S Sr P

SDA

SCL

010aaa22

Product data sheet Rev. 02 — 15 October 2010 42 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

14.4 I2S timing characteristics

[1] RL = load resistance; LL = load inductance.

Table 40 . I2S bus interface characteristics; see Figure 15

All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V, RL = 8

[1], LL = 44

H[1]; fi = 1 kHz; clip control off;

Tamb =25

C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fssampling frequency on LRCK1 or LRCK2 pins 8 - 96 kHz

fclk clock frequency on SCK1 or SCK2 pins 32fs-64f

sHz

tsu set-up time LRCK edge to SCK HIGH 10 - - n s

SDI edge to SCK HIGH 10 - - ns

thhold time SCK HIGH to LRCK edge 10 - - ns

SCK HIGH to SDI edge 10 - - ns

Fig 15. I2S timing

SCK

LRCK

SDI

thtsu

010aaa62

Product data sheet Rev. 02 — 15 October 2010 43 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

14.5 PCM/IOM2 timing characteristics

[1] RL = load resistance; LL = load inductance.

Table 41 . PCM/IOM2 characteristics; see Figure 16

All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V, RL = 8

[1], LL = 44

H[1]; fi = 1 kHz; clip control off;

Tamb =25

C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fppulse frequency on LRCK1 or LRCK2 pins - - 8 kHz

fclk clock frequency on SCK1 or SCK2 pin 16fp- 192fpHz

tsu set-up time SCK HIGH to LRCK edge 10 - - ns

SCK HIGH to SDI edge 10 - - ns

thhold time LRCK edge to SCK HIGH 10 - - ns

SDI edge to SCK HIGH 10 - - ns

tppulse duration pulse on LRCK1 pin or LRCK2 pin 1/fclk -- s

Fig 16. PCM/IOM2 timin g

SCK

LRCK, FSC (long)

thtsu

LRCK, FSC (short)

SDI

010aaa62

Product data sheet Rev. 02 — 15 October 2010 44 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

15. Application information

The TFA9879 is a filter-free BTL class-D amplifier that uses a fixed frequency PWM

modulation scheme (see the simplified application schematic in Figure 18). When the

TFA9879 is idle (no audio inp ut signal), the voltage across the speaker is 0 V, generating

no additional cu rrent. Even when the PWM output is modula ted by the audio input signal,

the out-of-band AC ripple current in the voice coil is very small compared to the audio

current. This is due to the inductive behavior of the voice coil at the PWM switching

frequency. A typical voice coil inductance is in the range 30 μH to 80 μH.

15.1 Power capability

15.1.1 Estimating the RMS output power (Po(RMS))

The RMS output power, Po(RMS), at THD + N = 1 % just before clipping can be estimated

using Equation 11, with clip-con tr ol off, or using Equation 12, with clip-control on.

Clip control off:

(11)

Clip control on:

(12)

where:

RL= load resistance (Ω)

RS= total series resistance of application

RDSon = on-resistance of power switch (typically 230 mΩ)

VDDP = power supply voltage (V)

Mmax = maxim um mo dula tio n de pt h (clip control on); typically 0.9

Example (clip control off):

With VDDP =5V, R

DSon =0.23

(at Tj=25

C), RS=0.14

Po(RMS)1% = 1.35 W in an 8

load or

Po(RMS)1% = 2.35 W in a 4

load

The RMS output power at THD + N = 10 % can be estimated using Equation 13:

(13)

PoRMS()1%

RLRS2R

DSon

×()++

------------------------------------------------------

⎝⎠

⎛⎞

VDDP

⎝⎠

⎛⎞

----------------------------------------------------------------------------------------

PoRMS()1%

RLRS2R

DSon

×()++

------------------------------------------------------

⎝⎠

⎛⎞

Mmax VDDP

××

⎝⎠

⎛⎞

-----------------------------------------------------------------------------------------------------------

P0RMS()10%1.25 P0RMS()1%

×=

Product data sheet Rev. 02 — 15 October 2010 45 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

15.1.2 Output current limiting

The peak output current IO(max) is limited internally by OCP. The minimum OCP trigger

level is 1.3 A. During normal operation, the output current should not exceed this

threshold level, otherwise the audio signal will be distorted. The peak output current in

BTL configu ratio n ca n be calcu lat ed usin g Equation 14:

(14)

where:

VDDP = power supply voltage (V)

RL= load resistance (Ω)

RDSon = drain-source on-state resistance (Ω)

Example:

A 4

speaker can be used with a 5 V sup ply without trigge ring OCP.

15.2 PWM output filtering

The TFA9879 PWM power stage is optimized to meet the legal limits (FCC) for radiated

emissions without requiring an external filter (speaker cable < 5 cm). But a low-pass LC

filter is recommended if a long speake r cable can’t b e avoided or ot her component s in the

application are sensitive to frequencies in the 10 MHz to 150 MHz range (e.g. an FM

tuner). The suggested differential low-pass filter consists of a ferrite bead inductor (Z >

80 Ω at 100 MHz) and a small ceramic capacitor of about 1 nF (see Figure 17).

15.3 Supply decoupling and filtering

A ceramic decoupling capacitor of between 1 μF and 10 μF should be placed clo se to the

TFA9879 to minimize the size of the h igh-freque ncy current lo op, there by optimizing EMC

performance. Optionally, a small 1 nF ceramic capacitor can be connected in parallel to

further reduce the impedance.

IOmax()

IOOCP()

VDDP

DSon RL

+×

-------------------------------------1.3A≤≤ ≤

Fig 17. Optional low-pass LC filter

1 nF1 nF

speaker cables > 5 cm

OUTA

OUTB

TFA9879

CLASS-D AMPLIFIER

ferrite bead

010aaa62

Product data sheet Rev. 02 — 15 October 2010 46 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

15.4 PCB layout considerations

Great care should be taken when designing the PCB layout for a Class-D amplifier circuit

as the layout can affect the audio performance, the EMC performance and/or the thermal

performance, and can even affect the fu nct i on a lity of the TFA9879.

15.4.1 EMC considerations

The decoupling capacitors on pins VDDD, VDDP and STABA should be placed close to the

TFA9879, referenced to a solid ground plane. The exposed DAP should also be

connected to this gr ou nd pla ne.

15.4.2 Thermal considerations

The TFA9879 is available in a thermally enhanced HVQFN24 (SOT616-3) package for

reflow soldering. The HVQFN24 has an exposed DAP that significantly reduces the

thermal resistance, Rth(j-a). To achieve a lower overall thermal resistance, the exposed

DAP should be soldered to a thermal copper plane. Increasing the area of the thermal

plane, the number of planes or the copper thickness can further re duce the thermal

resistance. The typical thermal resistance (free air and natural convection) of a practical

PCB implementation is:

Rth(j-a) = 67 K/W for a two-layer application board (18 mm × 22 mm, 35 μm cop per, FR4

base material).

Equation 15 describes the relationship betwee n the maximum allowable power dissipation

(P) and the thermal resistance from junction to ambient.

(15)

where:

Rth(j-a) = thermal resistance from junction to ambient

Tj(max) = maximum junction temperature (125 °C)

Tamb = ambient temperature

P = power dissipated in the TFA9879

OTP will limit the maximum junction temperature to 130 °C to avoid thermal damage.

Rth j-a() Tjmax()

Tamb

–

-----------------------------------

Product data sheet Rev. 02 — 15 October 2010 47 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

15.5 Typical application diagram (simplified)

Fig 18. Typical application (simplified)

TFA8979HN

CSTABA

100 nF

VDDP

LRCK1

VDDP

SCK1

SDI1

OUTA

LRCK2

SCK2 OUTB

SDI2

ADSEL1

SCL

SDA

STABA

010aaa545

VDDD 23 13

GNDP

GNDD 24

BASEBAND

PROCESSOR

I2S output

MULTIMEDIA

PROCESSOR

I2S output

address select 1

SCL

SDA

1.8 V

CVDDD

100 nF

TEST2

DAP

battery

CVDDP

10 μF

speaker

4 Ω or 8 Ω

TEST1

TEST3

n.c.

6, 14

ADSEL2 4

address select 2

Product data sheet Rev. 02 — 15 October 2010 48 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

15.6 Curves measured in reference design (demonstration board)

All measurements were taken with VDDD =1.8V, f

s= 48 kHz, clip control on and the

high-pass filter off, unless otherwise specified .

(1) fi = 6 kHz.

(2) fi = 1 kHz.

(3) fi = 100 Hz.

(1) fi = 6 kHz.

(2) fi = 1 kHz.

(3) fi = 100 Hz.

a. VDDP =3.7V,R

L=8Ωb. VDDP =5V,R

L=8Ω

(1) fi = 6 kHz.

(2) fi = 1 kHz.

(3) fi = 100 Hz.

(1) fi = 6 kHz.

(2) fi = 1 kHz.

(3) fi = 100 Hz.

c. VDDP =3.7V,R

L=4Ωd. VDDP =5V,R

L=4Ω

Fig 19. Total harmonic distortion-plus-noise as a function of output power

(2)

(1)

(3)

010aaa675

Po (W)

10−210110−1

10−1

10−2

102

THD+N

(%)

10−3

(2)

010aaa676

Po (W)

10−210110−1

10−1

10−2

102

THD+N

(%)

10−3

(3)

(1)

010aaa677

Po (W)

10−210110−1

10−1

10−2

102

THD+N

(%)

10−3

(1)

(3)

(2)

(1)

(3)

010aaa678

Po (W)

10−210110−1

10−1

10−2

102

THD+N

(%)

10−3

(2)

Product data sheet Rev. 02 — 15 October 2010 49 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

(1) Po = 100 mW

(2) Po = 500 mW (1) Po = 100 mW

(2) Po = 500 mW

a. VDDP =3.7V,R

L=8Ωb. VDDP =5V,R

L=8Ω

(1) Po = 100 mW

(2) Po = 500 mW (1) Po = 100 mW

(2) Po = 1 W

c. VDDP =3.7V,R

L=4Ωd. VDDP =5V,R

L=4Ω

Fig 20. Tota l ha rmo ni c di stortion-plus-n oise as a function of frequenc y

010aaa679

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

010aaa680

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

010aaa681

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

010aaa682

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

Product data sheet Rev. 02 — 15 October 2010 50 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

(1) Vripple = 0 V (fripple = 0 Hz)

(2) fripple = 217 Hz

(3) fripple = 1 kHz

(4) fripple = 6 kHz

(1) Vripple = 0 V (fripple = 0 Hz)

(2) fripple = 217 Hz

(3) fripple = 1 kHz

(4) fripple = 6 kHz

a. VDDP =3.7V,R

L=8Ω, Po= 100 mW,

Vripple = 200 mV (RMS) b. VDDP =5V,R

L=8Ω, Po= 100 mW,

Vripple = 200 mV (RMS)

Fig 21. Total harmonic distortion-plus-noise and power supply intermodulation distortion as a function of

frequency

(1)

(3)

(4)

(2)

010aaa683

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

(2)

(1)

(3)

(4)

010aaa684

10−1

10−2

102

THD+N

(%)

10−3

f (Hz)

10 105

104

102103

VDDP = 3.7 V, RL=8Ω, Po= 500 mW

(1) high-pass filter off

(2) high-pass filter cut-off frequency: 100 Hz

(3) high-pass filter cut-off frequency: 500 Hz

VDDP =5V, R

L=8Ω, ripple = 200 mV (RMS)

(1) VDDP = 3.7 V

(2) VDDP = 5 V

Fig 22. Normalized gain as a function of frequency Fig 23. Power supply rejection ration as a function of

ripple frequency

010aaa685

−20

−10

−30

−40

f (Hz)

10 105

104

102103

(1)

(2)

(3)

010aaa686

−60

−40

−80

−20

PSRR

(dB)

−100

fripple (Hz)

10 105

104

102103

(1)

(2)

Product data sheet Rev. 02 — 15 October 2010 51 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

VDDP =5V, R

L=8Ω, reference signal: 3.5 V (RMS)

(1) A-weighted

(2) 20 kHz brickwall filter

Fig 24. Signal-to-noise ratio as a function of output power

Po (W)

10−210110−1

010aaa687

100

120

S/N

(dB)

(1)

(2)

(1) THD+N = 1 %, RL=8 Ω

(2) THD+N = 10 %, RL=8 Ω

(3) THD+N = 1 %, RL=4 Ω

(4) THD+N = 10 %, RL=4 Ω

(1) THD+N = 1 %, RL=8 Ω

(2) THD+N = 10 %, RL=8 Ω

(3) THD+N = 1 %, RL=4 Ω

(4) THD+N = 10 %, RL=4 Ω

a. fi= 100 Hz, clip control on b. fi= 100 Hz, clip control off

Fig 25. Output power as a function of supply voltage

VDDP (V)

26534

010aaa688

(W)

(4)

(3)

(2)

(1)

VDDP (V)

26534

010aaa689

(W)

(4)

(3)

(2)

(1)

Product data sheet Rev. 02 — 15 October 2010 52 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

(1) VDDP =3.7V

(2) VDDP =5V (1) VDDP =3.7V

(2) VDDP =5V

a. RL=8 Ω, fi= 1 kHz, clip control off b. RL=4 Ω, fi= 1 kHz, clip control off

Fig 26. Power dissipation as a function of output power

010aaa694

0.10

0.05

0.15

0.20

(W)

0.00

Po (W)

10−310110−210−1

(2)

(1)

(2)

(1)

010aaa696

0.2

0.3

0.1

0.4

0.5

(W)

0.0

Po (W)

10−310110−210−1

(1) VDDP =3.7V

(2) VDDP =5V (1) VDDP =3.7V

(2) VDDP =5V

a. RL=8 Ω, fi= 1 kHz, clip control off b. RL=4 Ω, fi= 1 kHz, clip control off

Fig 27. Efficiency as a function of output power

(1)

(2)

Po (W)

021.50.5 1

010aaa695

100

(%)

010aaa697

Po (W)

0321

100

(%)

(1)

(2)

Product data sheet Rev. 02 — 15 October 2010 53 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

16. Package outline

Fig 28. Package outline TFA9879 (HVQFN24)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.75

2.45

4.1

3.9

2.75

2.45

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-3 MO-220 04-11-19

05-03-10

- - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616

-3

VQFN24: plastic thermal enhanced very thin quad flat package; no leads;

4 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1

detail X

y1C

712

24 19

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 02 — 15 October 2010 54 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperatur e profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 02 — 15 October 2010 55 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

17.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards ar e not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 42 and 43

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

Table 42. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 43. Lead -free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 02 — 15 October 2010 56 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 02 — 15 October 2010 57 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

18. Revision history

Table 44. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TFA9879 v.2 201010 15 Product data sheet - TFA98 79 v.1

Modifications: •Specification status changed to Product data sheet

TFA9879 v.1 20100408 Preliminary data sheet - -

Product data sheet Rev. 02 — 15 October 2010 58 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full dat a

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

19.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 02 — 15 October 2010 59 of 60

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

19.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors TFA9879

Mono BTL class-D audio amplifier with digital input

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 October 2010

Document identifier: TFA9879

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

21. Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 General description. . . . . . . . . . . . . . . . . . . . . . 1

3 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3.1 General features. . . . . . . . . . . . . . . . . . . . . . . . 1

3.2 Programmable Digital Sound Processor (DSP) 2

3.3 Interface format support for digital audio inputs 2

4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

6 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

8.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Functional description . . . . . . . . . . . . . . . . . . . 6

9.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 7

9.1.1 Power-up/power-down . . . . . . . . . . . . . . . . . . . 7

9.1.2 Supported Digital audio data formats . . . . . . . . 8

9.2 Digital Signal Processor (DSP) features. . . . . 11

9.2.1 Serial interface selection . . . . . . . . . . . . . . . . 11

9.2.2 Mono selection . . . . . . . . . . . . . . . . . . . . . . . . 11

9.2.3 Programmable high-pass filter . . . . . . . . . . . . 11

9.2.4 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.2.5 Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

9.2.5.1 Equalizer band function . . . . . . . . . . . . . . . . . 12

9.2.5.2 Equalizer band control . . . . . . . . . . . . . . . . . . 14

9.2.6 Bass and treble control. . . . . . . . . . . . . . . . . . 16

9.2.7 Muting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9.2.8 Digital volume control . . . . . . . . . . . . . . . . . . . 18

9.2.9 Zero-crossing volume control . . . . . . . . . . . . . 18

9.2.10 Dynamic Range Compressor (DRC) . . . . . . . 18

9.2.10.1 Functional description . . . . . . . . . . . . . . . . . . . 19

9.2.10.2 DRC control . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.2.11 Power limiter. . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.3 Class-D amplification and clip control. . . . . . . 22

9.4 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.4.1 OverTemperature Protection (OTP) . . . . . . . . 23

9.4.2 OverCurrent Protection (OCP) . . . . . . . . . . . . 23

9.4.3 UnderFrequency Protection (UFP). . . . . . . . . 23

9.4.4 OverFrequency Protection (OFP). . . . . . . . . . 24

9.4.5 Invalid Bit-clock Protection (IBP) . . . . . . . . . . 24

9.4.6 Overview of protection circuits . . . . . . . . . . . . 24

10 I2C-bus interface and register settings . . . . . 24

10.1 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 24

10.2 I2C-bus write cycle . . . . . . . . . . . . . . . . . . . . . 25

10.3 I2C-bus read cycle . . . . . . . . . . . . . . . . . . . . . 26

10.4 Top-level register map . . . . . . . . . . . . . . . . . . 26

10.4.1 Device control . . . . . . . . . . . . . . . . . . . . . . . . 27

10.4.2 Serial interface control . . . . . . . . . . . . . . . . . . 28

10.4.3 Equalizer configuration . . . . . . . . . . . . . . . . . 30

10.4.4 Bypass control . . . . . . . . . . . . . . . . . . . . . . . . 31

10.4.5 Dynamic range compressor. . . . . . . . . . . . . . 31

10.4.6 Bass and treble control . . . . . . . . . . . . . . . . . 32

10.4.7 High-pass filter. . . . . . . . . . . . . . . . . . . . . . . . 32

10.4.8 Volume control. . . . . . . . . . . . . . . . . . . . . . . . 33

10.4.9 De-emphasis, soft/hard mute and power

limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.4.10 Miscellaneous status . . . . . . . . . . . . . . . . . . . 34

11 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 36

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

13 Thermal characteristics . . . . . . . . . . . . . . . . . 38

14 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39

14.1 DC Characteristics. . . . . . . . . . . . . . . . . . . . . 39

14.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . 40

14.3 I2C timing characteristics. . . . . . . . . . . . . . . . 41

14.4 I2S timing characteristics . . . . . . . . . . . . . . . . 42

14.5 PCM/IOM2 timing characteristics. . . . . . . . . . 43

15 Application information . . . . . . . . . . . . . . . . . 44

15.1 Power capability. . . . . . . . . . . . . . . . . . . . . . . 44

15.1.1 Estimating the RMS output power (Po(RMS)) . 44

15.1.2 Output current limiting . . . . . . . . . . . . . . . . . . 45

15.2 PWM output filtering. . . . . . . . . . . . . . . . . . . . 45

15.3 Supply decoupling and filtering . . . . . . . . . . . 45

15.4 PCB layout considerations. . . . . . . . . . . . . . . 46

15.4.1 EMC considerations. . . . . . . . . . . . . . . . . . . . 46

15.4.2 Thermal considerations . . . . . . . . . . . . . . . . . 46

15.5 Typical application diagram (simplified) . . . . . 47

15.6 Curves measured in reference design

(demonstration board) . . . . . . . . . . . . . . . . . . 48

16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 53

17 Soldering of SMD packages. . . . . . . . . . . . . . 54

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 54

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 54

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 54

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 55

18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

19 Legal information . . . . . . . . . . . . . . . . . . . . . . 58

19.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 58

19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58

19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 59

20 Contact information . . . . . . . . . . . . . . . . . . . . 59

21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60