UPD17149CT(A1)-XXX - NEC Electronics - Pdf.Support

The information in this document is subject to change without notice.

MOS INTEGRATED CIRCUIT

Document No. U13233EJ1V1DS00 (1st edition)

(Previous No. IC-3580)

Date Published January 1998 N CP(K)

Printed in Japan

SMALL, GENERAL-PURPOSE

4-BIT SINGLE-CHIP MICROCONTROLLERS

µ

PD17145(A1), 17147(A1), 17149(A1)

The

µ

PD17145(A1), 17147(A1), and 17149(A1) are 4-bit single-chip microcontrollers integrating an 8-bit

A/D converter (4 channels), a timer function (3 channels), and a serial interface.

These microcontrollers employ a CPU of the general-purpose register type that can execute direct memory

operations and direct memory-to-memory data transfer for efficient programming. All the instructions consist

of 16 bits per word.

In addition, a one-time PROM version, the

µ

PD17P149, is also available for program evaluation.

The functions of these microcontrollers are described in detail in the following User’s Manual. Be sure

to read the following manual when designing your system:

µ

PD17145 Subseries User’s Manual: IEU-1383

FEATURES

• 17K architecture : General-purpose register type

: Instruction length fixed to 16 bits

• Program memory (ROM) :

µ

PD17145(A1) : 2 KB (1024 × 16 bits)

:

µ

PD17147(A1) : 4 KB (2048 × 16 bits)

:

µ

PD17149(A1) : 8 KB (4096 × 16 bits)

• Data memory (RAM) : 110 × 4 bits

• External interrupt : 1 (INT pin, with sense input)

• Instruction execution time : 2

µ

s (at 8 MHz: ceramic oscillation)

• 8-bit A/D converter : 4 channels, absolute accuracy: ±1.5 LSB MAX. (VDD = 4.0 to 5.5 V)

• Timer : 3 channels

• Serial interface : 1 channel (clocked 3-wire)

• POC circuit (mask option)

• Operating voltage : VDD = 2.7 to 5.5 V (at 400 kHz to 2 MHz)

:VDD = 4.5 to 5.5 V (at 400 kHz to 8 MHz)

• Operating temperature : Ta = –40 to +110 ˚C

APPLICATIONS

Automotive electronics, etc.

Unless contextually excluded, references in this data sheet to the

µ

PD17149 (A1) mean the

µ

PD17145

(A1) and

µ

PD17147 (A1).

©

1995

DATA SHEET

2

µ

PD17145(A1), 17147(A1), 17149(A1)

ORDERING INFORMATION

Remark ××× indicates ROM code suffix.

Part Number Package Quality Grade

µ

PD17145CT(A1)-××× 28-pin plastic shrink DIP (400 mil) Special

µ

PD17145GT(A1)-××× 28-pin plastic SOP (375 mil) Special

µ

PD17147CT(A1)-××× 28-pin plastic shrink DIP (400 mil) Special

µ

PD17147GT(A1)-××× 28-pin plastic SOP (375 mil) Special

µ

PD17149CT(A1)-××× 28-pin plastic shrink DIP (400 mil) Special

µ

PD17149GT(A1)-××× 28-pin plastic SOP (375 mil) Special

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

3

µ

PD17145(A1), 17147(A1), 17149(A1)

POC circuit

Operating voltage

Package

One-time PROM version

µ

PD17P149

Timer 3 channels

• Internal interrupt: 4

FUNCTION LIST

Part Number

µ

PD17145 (A1)

µ

PD17147 (A1)

µ

PD17149 (A1)

Item

ROM capacity 2 KB (1024 × 16 bits) 4 KB (2048 × 16 bits) 8 KB (4096 × 16 bits)

RAM capacity 110 × 4 bits

Stack Address stack × 5, interrupt stack × 3

• I/O : 20

I/O ports 23 • Input : 2

• Sense input (INT pinNote):1

A/D converter input 4 channels (shared with port pins), absolute accuracy: ±1.5 LSB MAX.

• 8-bit timer/counter:

2 channels (can be used as 1 channel of 16-bit timer)

• 7-bit basic interval timer:

1 channel (can be used as watchdog timer)

Serial interface 1 channel (3-wire)

• Multiple interrupt by hardware (3 levels MAX.)

• External interrupt (INT): 1 Rising edge, falling edge, or both rising and falling

edges selectable for detection.

Interrupt • Timer 0 (TM0)

• Timer 1 (TM1)

• Basic interval timer (BTM)

• Serial interface (SIO)

Instruction execution time 2

µ

s (at 8 MHz, ceramic oscillation)

Standby function HALT, STOP

Mask option

(Can be used in application circuit that operates on V

DD

= 5 V ± 10 %, 400 kHz to 4 MHz)

2.7 to 5.5 V (at 400 kHz to 2 MHz)

4.5 to 5.5 V (at 400 kHz to 8 MHz)

28-pin plastic shrink DIP (400 mil)

28-pin plastic SOP (375 mil)

Quality grade is "standard" and not (A1).

Operating temperature range: Ta = –40 to +85 ˚C

Note The INT pin is used as an input pin (sense input) when the external interrupt function is not used.

The status of this pin is read by using the INT flag of a control register, not by a port register.

Caution The PROM version is functionally compatible with the mask ROM versions but its internal

circuit and part of the electrical characteristics are different from those of the mask ROM

versions. To replace the PROM version with a mask ROM version, thoroughly conduct

application evaluation by using a sample of the mask ROM version.

4

µ

PD17145(A1), 17147(A1), 17149(A1)

PIN CONFIGURATION (Top View)

28-pin plastic shrink DIP (400 mil)

28-pin plastic SOP (375 mil)

ADC0-ADC3: analog input

GND : ground

INT : external interrupt input

P0A0 to P0A3: port 0A

P0B0 to P0B3: port 0B

P0C0 to P0C3: port 0C

P0D0 to P0D3: port 0D

P0E0 to P0E3: port 0E

P0F0 and P0F1: port 0F

RESET : reset input

RLS : standby release signal input

SCK : serial clock I/O

SI : serial data input

SO : serial data output

TM1OUT : timer 1 output

VDD : power

VREF : A/D converter reference voltage

XIN, XOUT : for system clock oscillation

V

DD

P0F

1

/V

REF

P0C

3

/ADC

3

P0C

2

/ADC

2

P0C

1

/ADC

1

P0C

0

/ADC

0

P0B

3

P0B

2

P0B

1

P0B

0

P0A

3

P0A

2

P0A

1

P0A

0

GND

X

IN

X

OUT

RESET

INT

P0F

0

/RLS

P0D

0

/SCK

P0D

2

/SI

P0D

3

/TM1OUT

P0E

1

P0E

2

P0E

3

P0D

1

/SO

P0E

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

µ

µ

µ

µ

µ

µ

PD17145CT(A1) - ×××

PD17145GT(A1) - ×××

PD17147CT(A1) - ×××

PD17147GT(A1) - ×××

PD17149CT(A1) - ×××

PD17149GT(A1) - ×××

5

µ

PD17145(A1), 17147(A1), 17149(A1)

BLOCK DIAGRAM

Notes 1. The ROM capacity of each product is as follows:

1024 × 16 bits:

µ

PD17145(A1)

2048 × 16 bits:

µ

PD17147(A1)

4096 × 16 bits:

µ

PD17149(A1)

2. The stack capacity of each product is as follows:

5 × 10 bits:

µ

PD17145(A1)

5 × 11 bits:

µ

PD17147(A1)

5 × 12 bits:

µ

PD17149(A1)

Remark CMOS or N-ch in ( ) indicate the output format of the port.

CMOS: CMOS push-pull output

N-ch : N-ch open-drain output

V

DD

P0A

3

P0A

2

P0A

1

P0A

0

P0B

3

P0B

2

P0B

1

P0B

0

P0C

3

/ADC

3

P0C

2

/ADC

2

P0C

1

/ADC

1

P0C

0

/ADC

0

P0F

1

/V

REF

P0F

0

/RLS

P0D

3

/TM1OUT

P0D

2

/SI

P0D

1

/SO

P0D

0

/SCK

TM1

Serial

Interface

P0D

(N-ch)

P0F

A/D

Converter

P0C

(CMOS)

P0B

(CMOS)

P0A

(CMOS)

RF

RAM

110 ×4 bits

SYSTEM REG.

ALU

ROM

Note 1

Program Counter

Stack

Note 2

IRQSIO

Instruction

Decoder

P0E

(N-ch)

Timer 0

Timer 1

Basic Interval Timer

Interrupt

Controller

Clock

Divider System Clock

Generator

fx/2

N

CPU CLOCK CLK STOP

X

IN

X

OUT

INT

IRQTM0

IRQTM1

IRQBTM

IRQSIO

IRQBTM

fx/2

N

fx/2

N

fx/2

N

IRQTM1

IRQTM0

P0E

3

P0E

2

P0E

1

P0E

0

RESET

GND

6

µ

PD17145(A1), 17147(A1), 17149(A1)

CONTENTS

1. PIN .....................................................................................................................................9

1.1. Pin Function .....................................................................................................................................9

1.2 Equivalent Circuit of Pin...............................................................................................................11

1.3 Handling of Unused Pins..............................................................................................................15

1.4 Note on Using RESET and P0F0/RLS Pins ...............................................................................16

2. PROGRAM MEMORY (ROM)...................................................................................... 17

2.1 Configuration of Program Memory ..............................................................................................17

3. PROGRAM COUNTER (PC) ....................................................................................... 18

3.1 Configuration of Program Counter ..............................................................................................18

3.2 Operation of Program Counter ....................................................................................................18

4. STACK ........................................................................................................................... 19

4.1 Configuration of Stack ..................................................................................................................19

4.2 Stack Function ...............................................................................................................................19

5. DATA MEMORY (RAM)............................................................................................... 20

5.1 Configuration of Data Memory.....................................................................................................20

6. GENERAL REGISTER (GR) ........................................................................................ 21

6.1 General Register Pointer (RP) .....................................................................................................21

7. SYSTEM REGISTER (SYSREG) ................................................................................ 22

7.1 Configuration of System Register ...............................................................................................22

8. REGISTER FILE (RF) .................................................................................................. 24

8.1 Configuration of Register File......................................................................................................24

8.2 Function of Register File ..............................................................................................................25

9. DATA BUFFER (DBF) ................................................................................................. 26

9.1 Configuration of Data Buffer ........................................................................................................26

9.2 Function of Data Buffer ................................................................................................................27

10. ALU BLOCK.................................................................................................................. 28

10.1 Configuration of ALU Block..........................................................................................................28

11. PORTS ........................................................................................................................... 30

11.1 Port 0A (P0A0, P0A1, P0A2, P0A3) ..............................................................................................30

11.2 Port 0B (P0B0, P0B1, P0B2, P0B3) ..............................................................................................31

11.3 Port 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3)...................................................32

11.4 Port 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM1OUT) ........................................................33

11.5 Port 0E (P0E0, P0E1, P0E2, P0E3) ..............................................................................................34

11.6 Port 0F (P0F0/RLS, P0F1/VREF) ...................................................................................................34

7

µ

PD17145(A1), 17147(A1), 17149(A1)

12. 8-BIT TIMERS/COUNTERS (TM0, TM1) ................................................................... 35

12.1 Configuration of 8-Bit Timers/Counters..................................................................................... 35

13. BASIC INTERVAL TIMER (BTM)............................................................................... 39

13.1 Configuration of Basic Interval Timer ........................................................................................ 39

13.2 Registers Controlling Basic Interval Timer ............................................................................... 41

13.3 Watchdog Timer Function ........................................................................................................... 43

14. A/D CONVERTER......................................................................................................... 45

14.1 Configuration of A/D Converter .................................................................................................. 45

14.2 Function of A/D Converter ........................................................................................................... 46

14.3 Operation of A/D Converter ........................................................................................................ 47

15. SERIAL INTERFACE (SIO)......................................................................................... 50

15.1 Function of Serial Interface......................................................................................................... 50

15.2 Operation Mode of 3-Wire Serial Interface ............................................................................... 52

16. INTERRUPT FUNCTION.............................................................................................. 54

16.1 Types of Interrupt Causes and Vector Addresses ................................................................... 54

16.2 Hardware of Interrupt Control Circuit ......................................................................................... 55

17. STANDBY FUNCTION ................................................................................................. 56

17.1 Outline of Standby Function ....................................................................................................... 56

17.2 HALT Mode ................................................................................................................................... 58

17.3 STOP Mode................................................................................................................................... 60

18. RESET............................................................................................................................ 63

18.1 Reset Function.............................................................................................................................. 63

18.2 Reset Operation ........................................................................................................................... 64

19. POC CIRCUIT (MASK OPTION) ................................................................................. 65

19.1 Function of POC Circuit............................................................................................................... 65

19.2 Conditions to Use POC Circuit ................................................................................................... 66

20. INSTRUCTION SET...................................................................................................... 67

20.1 Outline of Instruction Set ............................................................................................................. 67

20.2 Legend........................................................................................................................................... 68

20.3 Instruction Set............................................................................................................................... 69

20.4 Assembler (AS17K) Embedded Macro Instruction................................................................... 71

21. ASSEMBLER RESERVED WORDS........................................................................... 72

21.1 Mask Option Directive.................................................................................................................. 72

21.2 Reserved Symbols ....................................................................................................................... 74

22. ELECTRICAL SPECIFICATIONS............................................................................... 82

23. CHARACTERISTIC CURVE (REFERENCE VALUE) ............................................... 88

8

µ

PD17145(A1), 17147(A1), 17149(A1)

24. PACKAGE DRAWINGS ....................................................................................................90

25. RECOMMENDED SOLDERING CONDITIONS..............................................................94

APPENDIX A. FUNCTION COMPARISON BETWEEN

µ

PD17145 SUBSERIES AND

THE

µ

PD17135A AND 17137A ......................................................................96

APPENDIX B. DEVELOPMENT TOOLS.................................................................................98

9

µ

PD17145(A1), 17147(A1), 17149(A1)

Symbol

VDD

P0F1/VREF

P0C3/ADC3

to

P0C0/ADC0

P0B3

P0B2

P0B1

P0B0

P0A3

P0A2

P0A1

P0A0

P0E3

P0E2

P0E1

P0E0

P0D3/TM1OUT

P0D2/SI

P0D1/SO

P0D0/SCK

1. PIN

1.1. Pin Function

Function

Power supply.

Reference voltage input to port 0F and A/D converter.

• Pull-up resistor can be connected by mask

option.

• P0F1

• Bit 1 of 2-bit input port (P0F)

•VREF

• Reference voltage input pin of A/D converter

Analog input to port 0C and A/D converter.

• P0C3-P0C0

• 4-bit I/O port

• Can be set in input or output mode bitwise.

• ADC3-ADC0

• Analog inputs to A/D converter.

Port 0B.

• 4-bit I/O port

• Can be set in input or output mode in 4-bit

units.

• Pull-up resistor can be connected in 4-bit units

via software.

Port 0A.

• 4-bit I/O port.

• Can be set in input or output mode in 4-bit

units.

• Pull-up resistor can be connected in 4-bit units

via software.

Port 0E.

• 4-bit I/O port.

• Can be set in input or output mode in 4-bit

units.

• Pull-up resistor can be connected in 4-bit units

via software.

Port 0D that is also used for timer 1 output, serial

data input, serial data output, and serial clock I/O.

• Pull-up resistor can be connected bitwise via

software.

• P0D3-P0D0

• 4-bit I/O port.

• Can be set in input or output mode bitwise.

• TM1OUT

• Timer 1 output

•SI

• Serial data input

•SO

• Serial data output

• SCK

• Serial clock I/O

Output Format

—

Input

CMOS push-pull

CMOS push-pull

CMOS push-pull

N-ch

open-drain

N-ch

open-drain

After Reset

—

Input (P0F1)

Input (P0C)

Input

Input

Input

Input (P0D)

Pin Number

1

2

3 to 6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

10

µ

PD17145(A1), 17147(A1), 17149(A1)

Output Format

Input

Input

Input

—

—

After Reset

Input (P0F0)

Input

Input

—

—

Function

Port 0F or standby mode release signal input.

• Pull-up resistor can be connected by mask

option.

• R0F0

• Bit 0 of 2-bit input port (P0F)

• RLS

• Standby mode release signal input

External interrupt request signal input. Also used

to release standby mode.

• Pull-up resistor can be connected by mask

option.

System reset input.

• Pull-up resistor can be connected by mask

option.

For system clock oscillation.

Connect ceramic resonator across XIN and XOUT.

GND

Symbol

P0F0/RLS

INT

RESET

XOUT

XIN

GND

Pin Number

23

24

25

26

27

28

11

µ

PD17145(A1), 17147(A1), 17149(A1)

1.2 Equivalent Circuit of Pin

The input/output circuit of each pin is shown below, partially simplified.

(1) P0A0 to P0A3 and P0B0 to P0B3

data

output

disable

pull-up

flag

V

DD

P-ch

P-ch

N-ch

V

DD

Output latch

Selector

Input buffer

12

µ

PD17145(A1), 17147(A1), 17149(A1)

(2) P0C0/ADC0 to P0C3/ADC3

(3) P0D3/TM1OUT and P0D1/SO

data

VDD

P-ch

N-ch

output

disable

input

disable

Output latch

Selector

A/D

converter

Input buffer

pull-up flag P-ch

V

DD

data

output

disable N-ch

Output

latch

Selector

Input buffer

13

µ

PD17145(A1), 17147(A1), 17149(A1)

(4) P0D2/SI and P0D0/SCK

(5) P0E0 to P0E3

(6) P0F0/RLS

VDD

P-ch

pull-up flag

N-ch

output

disable

data Output

latch

Selector

Input buffer

V

DD

data

output

disable N-ch

P-ch pull-up

flag

Output

latch

Selector

Input buffer

V

DD

stand-by

release

Input buffer Mask option

14

µ

PD17145(A1), 17147(A1), 17149(A1)

(7) P0F1/VREF

(8) RESET and INT

V

DD

A/D end

STOP mode

P-ch

V

REF

A/D select Input buffer

Mask option

V

DD

Input buffer

Mask option

15

µ

PD17145(A1), 17147(A1), 17149(A1)

1.3 Handling of Unused Pins

Handle unused pins as shown in the table below.

Table 1-1. Handling of Unused Pins

Handling

Pin Name Internally Externally

Open

Connect to VDD via pull-up resistor, or

to GND via pull-down resistorNote 1.

Directly connect to VDD or GND.

Open

Directly connect to GND.

Directly connect to VDD or GND.

Open

Directly connect to VDD.

Notes 1. Take into consideration the drive capability and current dissipation of a port when the port is

externally pulled up or down. To pull up or down the port with a high resistance, exercise care

so that noise is not superimposed on the port pin. The appropriate value of the pull-up or pull-

down resistor differs depending on the application circuit. Generally, select a resistor of several

10 kΩ.

2. The P0F0/RLS pin is also used to set a test mode. When this pin is not used, do not connect a

pull-up resistor to it by mask option, but directly connect it to GND.

3. In an application circuit where a high reliability is required, be sure to input the RESET signal from

an external source. The RESET pin is also used to set a test mode. When this pin is not used,

directly connect it to VDD.

Caution It is recommended to fix the input/output mode, pull-up resistor by software, and the output

level of the pin by repeatedly setting them in each loop of the program.

Connect on-chip pull-up resistor via

software.

—

Do not connect on-chip pull-up resistor

by mask option.

Connect on-chip pull-up resistor by mask

option.

Do not connect on-chip pull-up resistor

by mask option.

—

Output low level.

Do not connect pull-up on-chip resistor

via software, but output low level.

Connect on-chip pull-up resistor via

software and output high level.

Do not connect on-chip pull-up resistor

by mask option.

Connect on-chip pull-up resistor by mask

option.

Do not connect on-chip pull-up resistor

by mask option.

Connect on chip pull-up resistor by

mask option.

P0A, P0B, P0D, P0E

P0C

P0F1

P0F0Note 2

P0A, P0B, P0C (CMOS

port)

P0D

(N-ch open-drain port)

P0E

(N-ch open-drain port)

External interrupt (INT)

RESETNote 3

(when only internal

POC circuit is used)

Input

mode

Output

mode

Port

Open

16

µ

PD17145(A1), 17147(A1), 17149(A1)

1.4 Note on Using RESET and P0F0/RLS Pins

The RESET and P0F0/RLS pins also have a function to set a test mode in which the internal operation of the

µ

PD17149(A1) is tested (for IC test only), in addition to the function described in 1.1 Pin Function.

If a voltage higher than VDD is applied to these pins, the test mode is set. If a noise higher than VDD is

superimposed on these pins during normal operation, therefore, the test mode is set by mistake, affecting normal

operation.

If the wiring length of the RESET or P0F0/RLS pin is too long, for example, noise may be superimposed on

the pin.

To prevent this, the wiring length must be kept as short as possible. Otherwise, use a diode or capacitor as

shown below.

●●Connect a low-VF diode between VDD ●●Connect a capacitor between VDD

and RESET, P0F0/RLS and RESET, P0F0/RLS

V

DD

V

DD

RESET, P0F

0

/RLS

V

DD

V

DD

RESET, P0F

0

/RLS

Diode with

low V

F

17

µ

PD17145(A1), 17147(A1), 17149(A1)

2. PROGRAM MEMORY (ROM)

Table 2-1 shows the program memory configuration of the

µ

PD17145(A1), 17147(A1), and 17149(A1).

Table 2-1. Program Memory Configuration

Part Number Program Memory Capacity Program Memory Address

µ

PD17145(A1) 2 KB (1024 × 16 bits) 0000H-03FFH

µ

PD17147(A1) 4 KB (2048 × 16 bits) 0000H-07FFH

µ

PD17149(A1) 8 KB (4096 × 16 bits) 0000H-0FFFH

The program memory stores programs and constant data tables.

The program memory is addressed by the program counter.

Addresses 0000H-0005H are allocated to a reset start address and various interrupt vector addresses.

2.1 Configuration of Program Memory

Figure 2-1 shows the program memory map. The program memory is divided in units called “pages” each

of which consists of 2K steps with one step made up of 16 bits.

Addresses 0000H-07FFH (page 0) of the program memory can be specified by the direct subroutine call

instruction. The entire address range of the program memory, 0000H-0FFFH, can be specified by the branch,

indirect subroutine call, and table reference instructions.

Figure 2-1. Program Memory Map

0000H

0001H

0002H

0003H

0004H

0005H

03FFH

07FFH

0FFFH

(With PD17145(A1))

(With PD17147(A1))

(With PD17149(A1))

µ

µ

µ

Address

16 bits

Reset start address

Serial interface interrupt vector

Basic interval timer interrupt vector

Timer 1 interrupt vector

Timer 0 interrupt vector

External (INT) interrupt vector Page 0 CALL addr

instruction subroutine

entry address

Page 1

BR addr instruction

branch address

BR @AR instruction

branch address

CALL @AR instruction

subroutine entry address

MOVT DBF,

@AR instruction

table reference address

18

µ

PD17145(A1), 17147(A1), 17149(A1)

3. PROGRAM COUNTER (PC)

The program counter is used to address the program memory.

3.1 Configuration of Program Counter

The program counter is a 10-/11-/12-bit binary counter as shown in Figure 3-1.

Figure 3-1. Program Counter

3.2 Operation of Program Counter

Usually, the contents of the program counter are automatically incremented each time an instruction has been

executed. When reset has been effected, when a branch, subroutine call, return, or table reference instruction

has been executed, or when an interrupt has been acknowledged, the address of the program memory to be

executed next is set to the program counter.

Figure 3-2. Value of Program Counter after Instruction Execution

Bit of Program Counter Value of Program Counter

Instruction PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

At reset 000000000000

0

1 Value specified by addr

CALL addr 0

BR @AR

CALL @AR Contents of address register (AR)

(MOVT DBF, @AR)

RET

RETSK Contents of address stack indicated by stack pointer (return address)

RETI

When interrupt is acknowledged Vector address of each interrupt

Remark The

µ

PD17145(A1) does not have PC11 and PC10. The

µ

PD17147(A1) does not have PC11.

BR addr

MSB

PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PC ( PD17145(A1))

PC ( PD17147(A1))

PC ( PD17149(A1))

LSB

µ

µ

µ

19

µ

PD17145(A1), 17147(A1), 17149(A1)

4. STACK

The stack is a register to which the return address of the program or the contents of the system registers,

which are described later, are saved when a subroutine call instruction is executed or when an interrupt is

acknowledged.

4.1 Configuration of Stack

Figure 4-1 shows the configuration of the stack.

The stack consists of a 3-bit binary counter, stack pointer (SP), five 10-bit (

µ

PD17145(A1)), 11-bit

(

µ

PD17147(A1)), or 12-bit (

µ

PD17149(A1)) address stack registers (ASRs), and three 5-bit interrupt stack

registers (INTSKs).

Figure 4-1. Configuration of Stack

4.2 Stack Function

The stack is used to save a return address when the subroutine call or table reference instruction is executed.

When an interrupt is acknowledged, the return address of the program and the contents of the program status

word (PSWORD) are automatically saved to the stack. After they are saved to the stack, all the bits of PSWORD

are cleared to 0.

b

2

SPb

2

b

1

SPb

1

b

0

SPb

0

0H

1H

2H

3H

4H

b

11

b

10

b

9

b

8

b

7

b

6

b

5

b

4

b

3

b

2

b

1

b

0

BCDSK0

BCDSK1

BCDSK2

CMPSK0

CMPSK1

CMPSK2

CYSK0

CYSK1

CYSK2

ZSK0

ZSK1

ZSK2

IXESK0

IXESK1

IXESK2

0H

1H

2H

Stack pointer

(SP)

SP is initialized to 5H at

reset.

Address stack registers

(ASRs)

Address stack register 0

Address stack register 1

Address stack register 2

Address stack register 3

Address stack register 4

Interrupt stack registers

(INTSKs)

20

µ

PD17145(A1), 17147(A1), 17149(A1)

5. DATA MEMORY (RAM)

The data memory is used to store data for operation and control. Data can always be written to or read from

this memory by using an instruction.

5.1 Configuration of Data Memory

The data memory is assigned addresses each consisting of 7 bits. The higher 3 bits of an address are called

a “row address”, while the lower 4 bits are called a “column address”.

Take address 1AH for example. The row address of this address is 1H and the column address is 0AH.

One address consists of 4 bits (= 1 nibble) of memory.

The data memory consists of an area to which the user can save data, and areas to which special functions

are allocated in advance. These areas are:

• System register (SYSREG) (Refer to 7. SYSTEM REGISTER (SYSREG).)

• Data buffer (DBF) (Refer to 9. DATA BUFFER (DBF).)

• Port register (Refer to 11. PORT.)

Figure 5-1. Configuration of Data Memory

0123456789ABCDEF

DBF3 DBF2 DBF1 DBF0

P0E

(4 bits) P0F

(2 bits)

P0A

(4 bits) P0B

(4 bits) P0C

(4 bits) P0D

(4 bits)

0

1

2

3

4

5

6

7

BANK0

Example :

Address

1AH of BANK0

System register

Column address

21

µ

PD17145(A1), 17147(A1), 17149(A1)

6. GENERAL REGISTER (GR)

As its name implies, the general register is used for general purposes such as data transfer and operation.

The general register of the 17K series is not a fixed area, but an area specified on the data memory by using

the general register pointer (RP). Therefore, a part of the data memory area can be specified as a general

register as necessary, so that data can be transferred between data memory areas and the data in the data

memory can be operated with a single instruction.

6.1 General Register Pointer (RP)

RP is a pointer that specifies part of the data memory as the general register. RP specifies the bank and

row addresses of a data memory area that is to be specified as the general register. Consisting of a total of

7 bits, RP is assigned to 7DH (RPH) and 7EH (RPL), and the higher 3 bits of the system register (refer to 7.

SYSTEM REGISTER (SYSREG)).

RPH specifies a bank, and RPL specifies a data memory row address.

Figure 6-1. Configuration of General Register Pointer

BANK0

RP

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

1

2

3

4

5

6

7

7DH 7EH

RPH RPL

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

0000 D

0000000

C

B

0

Row addresses

0H to 7H can be

specified by

general register

pointer (RP).

Row

address

Column address

System register

General register

area when

RPH = 0000B,

RPL = 010×B

Address

Name

Symbol

Bit

Data

Reset

General register

pointer (RP)

General register (16 nibbles)General register (16 nibbles)

22

µ

PD17145(A1), 17147(A1), 17149(A1)

7. SYSTEM REGISTER (SYSREG)

The system register (SYSREG) is a register that directly controls the CPU, and is located on the data memory.

7.1 Configuration of System Register

Figure 7-1 shows the location of the system register on the data memory. As shown in this figure, the system

register is located at addresses 74H-7FH of the data memory.

Because the system register is located on the data memory, it can be manipulated by all the data memory

manipulation instructions. It is therefore possible to specify the system register as a general register.

Figure 7-1. Location of System Register on Data Memory

Figure 7-2 shows the configuration of the system register. As shown in this figure, the system register consists

of the following seven registers:

• Address register (AR)

• Window register (WR)

• Bank register (BANK)

• Index register (IX)

• Data memory row address pointer (MP)

• General register pointer (RP)

• Program status word (PSWORD)

0123456789ABCDEF

0

1

2

3

4

5

6

7

456789ABCDEF

0123

Data memory

(BANK0)

Column address

Row address

Port register System register (SYSREG)

23

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 7-2. Configuration of System Register

Notes 1. 0 in this field means that the bit is “fixed to 0”.

2. b3 and b2 of AR2 of the

µ

PD17145(A1) are fixed to 0. b3 of AR2 of the

µ

PD17147(A1) is fixed to

0.

74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH

AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW

MPH MPL

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

0000000000000000 0000000000000000000000000000

000 0000 0000 0000

(RP)(MP)

(IX)

(BANK)(AR)

M

P

E

B

C

D

C

M

P

C

YZ I

X

E

Address

Name

Symbol

Bit

DataNote1

Initial

value at

reset

0

Note2

Undefi-

ned

Address register

(AR)

Window

register

(WR)

Bank

register

(BANK)

Index register

(IX)

Data memory

row address

pointer (MP)

General register

pointer

(RP)

Program

status

word

(PSWORD)

24

µ

PD17145(A1), 17147(A1), 17149(A1)

8. REGISTER FILE (RF)

The register file is a register that mainly sets the conditions of the peripheral hardware.

8.1 Configuration of Register File

8.1.1 Configuration of register file

Figure 8-1 shows the configuration of the register file.

As shown in this figure, the register file consists of 128 nibbles (128 × 4 bits). Like the data memory, the

register file is assigned addresses in 4-bit units, with row addresses 0H-7H and column addresses 0H-0FH.

Addresses 00H-3FH of the register file are called a control register.

Figure 8-1. Configuration of Register File

8.1.2 Register file and data memory

Figure 8-2 shows the relationships between the register file and data memory.

As shown in this figure, addresses 40H to 7FH of the register file overlaps the data memory.

It seems from the program as if addresses 40H to 7FH of the data memory exist at addresses 40H-7FH of

the register file.

0123456789ABCDEF

0

1

2

3

4

5

6

7

Control register

Row address

Column addressRegister file

25

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 8-2. Relationships between Register File and Data Memory

8.2 Function of Register File

8.2.1 Function of register file

The register file is a collection of registers that set the conditions of the peripheral hardware by using the PEEK

or POKE instruction.

The registers that control the peripheral hardware are allocated to addresses 00H-3FH. These registers are

called control registers.

Addresses 40H-7FH of the register file overlap the ordinary data memory. These addresses can therefore

be read or written by not only the MOV instruction but also the PEEK and POKE instructions.

8.2.2 Functions of control registers

The control registers are used to set the conditions of the peripheral hardware listed below.

For the details of the peripheral hardware and control registers, refer to the description of each peripheral

hardware.

• Port

• 8-bit timers/counters (TM0, TM1)

• Basic interval timer (BTM)

• A/D converter

• Serial interface (SIO)

• Interrupt function

• Stack pointer (SP)

0

1

2

3

0

1

2

3

4

5

7

6

0123456789ABCDEF

BANK0

Column address

Data memory

Port register System register

Control register

Register file

Row address

26

µ

PD17145(A1), 17147(A1), 17149(A1)

9. DATA BUFFER (DBF)

The data buffer consists of 4 nibbles allocated to addresses 0CH-0FH of BANK0 of the data memory.

This area is a data storage area that transfers data with the peripheral hardware of the CPU (address register,

serial interface, timers 0 and 1, and A/D converter) by using the GET or PUT instruction. Moreover, the constants

on the program memory can be read to the data buffer by using the MOVT DBF, @AR instruction.

9.1 Configuration of Data Buffer

Figure 9-1 shows the location of the data buffer on the data memory.

As shown in this figure, the data buffer is allocated addresses 0CH-0FH of the data memory, and consists

of a total of 16 bits or 4 nibbles (4 × 4 bits).

Figure 9-1. Location of Data Buffer

Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer consists of 16

bits of the data memory, with the bit 0 of address 0FH as the LSB and bit 3 of address 0CH as the MSB.

Figure 9-2. Configuration of Data Buffer

Because the data buffer is located on the data memory, it can be manipulated by all the data memory

manipulation instructions.

0 F123456789ABCDE

0

1

2

3

4

5

6

7

Data memory

BANK0

Column address

Data buffer

(DBF)

System register (SYSREG)

Row address

Data memory

BANK0

0CH 0DH 0EH 0FH

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

11

b

10

b

9

b

8

b

7

b

6

b

5

b

4

b

3

b

2

b

1

b

0

b

15

b

14

b

13

b

12

DBF3 DBF2 DBF1 DBF0

M

S

B

< >

L

S

B

<

<

Address

Bit

Bit

Symbol

Data Data

Data buffer

27

µ

PD17145(A1), 17147(A1), 17149(A1)

9.2 Function of Data Buffer

The data buffer has two main functions.

One is to transfer data with the peripheral hardware, and the other is to read the constant data on the program

memory (table reference). Figure 9-3 shows the relationships between the data buffer and peripheral hardware.

Figure 9-3. Data Buffer and Peripheral Hardware

01H

02H

03H

04H

40H

45H

Shift register (SIOSFR)

Timer 0 modulo register (TM0M)

Timer 1 modulo register (TM1M)

A/D converter data

register (ADCR)

Address register (AR)

Timer 0 timer 1 count

register (TM0TM1C)

Data buffer

(DBF)

Internal bus

Program memory

(ROM)

Constant data

Peripheral address Peripheral hardware

28

µ

PD17145(A1), 17147(A1), 17149(A1)

10. ALU BLOCK

The ALU executes arithmetic and logical operations, bit judgment, and rotation processing of 4-bit data.

10.1 Configuration of ALU Block

Figure 10-1 shows the configuration of the ALU block.

As shown, the ALU block consists of an ALU that processes 4-bit data, and peripheral circuits such as

temporary registers A and B, status flip-flops that control the status of the ALU, and a decimal adjustment circuit

that is used when a BCD operation is performed.

The status flip-flops are a zero flag FF, carry flag FF, compare flag FF, and BCD flag FF, as shown in Figure

10-1.

The status flip-flops correspond to the zero flag (Z), carry flag (CY), compare flag (CMP), and BCD flag (BCD)

of the program status word (PSWORD: addresses 7EH, 7FH) on a one-to-one basis.

29

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 10-1. Configuration of ALU Block

ALU

7EH 7FH

Program status word

(PSWORD)

b

0

b

3

b

2

b

1

b

0

BCD CMP CY Z IXE

BCD

flag

FF

CMP

flag

FF

CY

flag

FF

Z

flag

FF

Data bus

Status flip-flop

Temporary register

B

Temporary register

A

• Arithmetic operation

• Logical operation

• Bit judgment

• Compare judgment

• Rotation processing

Decimal adjustment

circuit

Address

Name

Bit

Flag

Status flip-flop

Functional Outline

Indicates that result of arithmetic operation is 0.

Stores carry or borrow resulting from arithmetic

operation.

Specifies whether result of arithmetic operation

is stored.

Specifies whether decimal adjustment is

performed when arithmetic operation is executed.

30

µ

PD17145(A1), 17147(A1), 17149(A1)

11. PORTS

11.1 Port 0A (P0A0, P0A1, P0A2, P0A3)

Port 0A is a 4-bit I/O port with an output latch. It is mapped at address 70H of BANK0 of the data memory.

The output format is CMOS push-pull output.

This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0AGIO

(bit 0 of address 2CH) on the register file.

When P0AGIO = 0, all the pins of port 0A are set in the input mode. When an instruction that reads the data

of the port register is executed at this time, the pin status is read.

When P0AGIO = 1, all the pins of port 0A are set in the output mode, and the contents written to the output

latch are output to the pins. When an instruction that reads the port status is executed with the port set in the

output mode, the contents of the output latch, instead of the pin status, are read.

A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is

connected is specified by P0AGPU (bit 0 at address 0CH) of the register file. All the four pins are pulled up

when P0AGPU = 1. When P0AGPU = 0, the pull-up resistor is not connected.

P0AGIO and P0AGPU are cleared to “0” at reset, and all the P0A pins are set in the input mode without the

pull-up resistor connected. The value of the output latch is also cleared to “0”.

Table 11-1. Writing and Reading Port Register (0.70H)

P0AGIO Input/Output BANK0 70H

RF: 2CH, bit 0 Mode of Pin Write Read

0 Input Enabled P0A pin status

1 Output Write to P0A latch P0A latch contents

31

µ

PD17145(A1), 17147(A1), 17149(A1)

11.2 Port 0B (P0B0, P0B1, P0B2, P0B3)

Port 0B is a 4-bit I/O port with an output latch. It is mapped at address 71H of BANK0 of the data memory.

The output format is CMOS push-pull output.

This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0BGIO

(bit 1 of address 2CH) on the register file.

When P0BGIO = 0, all the pins of port 0B are set in the input mode. When an instruction that reads the data

of the port register is executed at this time, the pin status is read.

When P0BGIO = 1, all the pins of port 0B are set in the output mode, and the contents written to the output

latch are output to the pins. When an instruction that reads the port status is executed with the port set in the

output mode, the contents of the output latch, instead of the pin status, are read.

A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is

connected is specified by P0BGPU (bit 1 at address 0CH) of the register file. All the four-bit pins are pulled

up when P0BGPU = 1. When P0BGPU = 0, the pull-up resistor is not connected.

P0BGIO and P0BGPU are cleared to “0” at reset, and all the P0B pins are set in the input mode without the

pull-up resistor connected. The value of the output latch is also cleared to “0”.

Table 11-2. Writing and Reading Port Register (0.71H)

P0BGIO Input/Output BANK0 71H

RF: 2CH, bit 1 Mode of Pin Write Read

0 Input Enabled P0B pin status

1 Output Write to P0B latch P0B latch contents

32

µ

PD17145(A1), 17147(A1), 17149(A1)

11.3 Port 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3)

Port 0C is a 4-bit I/O port with an output latch. It is mapped at address 72H of BANK0 of the data memory.

The output format is CMOS push-pull output.

This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by

P0CBIO0-P0CBIO3 (address 1CH) on the register file.

When P0CBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Cn, is set in the input mode. When an instruction

that reads the data of the port register is executed at this time, the pin status is read. When P0CBIOn = 1 (n

= 0 to 3), the P0Cn pin is set in the output mode, and the contents written to the output latch are output to the

pin. When an instruction that reads the port status is executed with a port pin set in the output mode, the contents

of the output latch, instead of the pin status, are read.

At reset, P0CBIO0-P0CBIO3 are cleared to “0”, setting all the P0C pins in the input mode. The contents of

the output latch are also cleared to “0” at this time.

Port 0C is also used to input analog voltages to the A/D converter. Whether each pin of the port is used as

a port pin or analog input pin is specified by P0C0IDI-P0C3IDI (address 1BH) on the register file.

When P0CnIDI = 0 (n = 0-3), the P0Cn/ADCn pin functions as a port pin. When P0CnIDI = 1 (n = 0 to 3), the

P0Cn/ADCn pin functions as an analog input pin of the A/D converter. If any of the P0CnIDI (n = 0 to 3) bits

is set to “1”, the P0F1/VREF pin is used as the VREF pin.

When a pin of port 0C is used as an analog input pin of the A/D converter, set the P0CnIDI corresponding

to the pin to which an analog voltage is applied to 1, to disable the port input function. Moreover, clear P0CBIOn

(n = 0-3) to 0 to set the input port mode. The pin used as an analog input pin is selected by ADCCH0 and ADCCH1

(bits 1 and 0 of address 22H) on the register file.

At reset, P0CBIO0-P0CBIO3, P0C0IDI-P0C3IDI, ADCCH0, and ADCCH1 are cleared to 0, setting the input

port mode.

Table 11-3. Selecting Port or A/D Converter Mode (n = 0 to 3)

P0CnIDI P0CBIOn BANK0 72H

Function

RF:1BH RF:1CH Write Read

0 Input port Enabled. P0C latch Pin status

1 Port output Enabled. P0C latch Contents of P0C latch

0 Analog input of A/DNote 1 Enabled. P0C latch Contents of P0C latch

1 Output port and analog

1 Enabled. P0C latch Contents of P0C latch

input of A/DNote 2

Notes 1. Normal setting when the P0C pins are used as the analog input pins of the A/D converter.

2. The P0C pins function as output port pins. At this time, the analog input voltages change with

the output from the port. To use the pins as analog input pins, be sure to clear P0CBIOn to

0.

0

33

µ

PD17145(A1), 17147(A1), 17149(A1)

11.4 Port 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM1OUT)

Port 0D is a 4-bit I/O port with an output latch. It is mapped at address 73H of BANK0 of the data memory.

The output format is N-ch open-drain output.

This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by

P0DBIO0-P0DBIO3 (address 2BH) on the register file.

When P0DBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Dn, is set in the input mode. When an instruction

that reads the data of the port register is executed at this time, the pin status is read. When P0DBIOn = 1, the

P0Dn pin is set in the output mode, and the contents written to the output latch are output to the pin. When

an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the

output latch, instead of the pin status, are read.

A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is

connected or not is specified bitwise by using P0DBPU0-P0DBPU3 (address 0DH) on the register file. When

P0DBPUn = 1, the P0Dn pin is pulled up. When P0DBPUn = 0, the pull-up resistor is not connected.

At reset, P0DBIOn is cleared to “0”, setting all the P0D pins in the input mode. The contents of the output

latch are also cleared to “0” at this time. Note that the contents of the output latch are not changed even if the

status of P0DBIOn is changed from “1” to “0”.

Port 0D is also used as serial interface input/output and timer 1 output pins. Whether the P0D0 to P0D2 pins

are used as port pins or serial interface I/O pins (SCK, SO, and SI) is specified by SIOEN (bit 0 of 0BH) on the

register file. Whether the P0D3 pin is used as a port pin or timer 1 output (TM1OUT) pin is specified by TM1OSEL

(bit 3 of 0BH) on the register file. If TM1OSEL = 1, “1” is output when timer 1 is reset, and the output is inverted

each time the count value of timer 1 coincides with the contents of the modulo register.

Table 11-4. Contents of Register File and Pin Function (n = 0 to 3)

Value of Register File Pin Function

TM1OSEL SIOEN P0DBIOn

RF: 0BH RF: 0BH RF: 2BH P0D0/SCK P0D1/SO P0D2/SI P0D3/TM1OUT

Bit 3 Bit 0 Bit n

0 Input port

1 Output port

0 Input port

1 Output port

0 Input port

1 Output port

0

1

SCK SO SI

SCK SO SI

TM1OUT

0

0

1

0

1

1

34

µ

PD17145(A1), 17147(A1), 17149(A1)

Table 11-5. Read Contents of Port Register (0.73H)

Port Mode Read Contents of Port Register (0.73H)

Input port Pin status

Output port Contents of output latch

Internal clock selected as serial clock Contents of output latch

External clock selected as serial clock Pin status

SI Pin status

SO Contents of output latch

TM1OUT Contents of output latch

11.5 Port 0E (P0E0, P0E1, P0E2, P0E3)

Port 0E is a 4-bit I/O port with an output latch. It is mapped at address 6EH of BANK0 of the data memory.

The output format is N-ch open-drain output.

This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0EGIO

(bit 2 of address 2CH) on the register file.

When P0EGIO = 0, all the pins of port 0E are set in the input mode. When an instruction that reads the data

of the port register is executed at this time, the pin status is read.

When P0EGIO = 1, all the pins of port 0E are set in the output port, and the contents written to the output

latch are output to the pins. When an instruction that reads the port status is executed with the port set in the

output mode, the contents of the output latch, instead of the pin status, are read.

A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is

connected is specified by P0EGPU (bit 2 at address 0CH) of the register file. All the four-bit pins are pulled

up when P0EGPU = 1. When P0EGPU = 0, the pull-up resistor is not connected.

P0EGIO is cleared to “0” at reset, and all the P0E pins are set in the input mode. The value of the output

latch is also cleared to “0”.

Table 11-6. Writing and Reading Port Register (0.6EH) (n = 0 to 3)

P0EGIO Input/Output BANK0 6EH

RF: 2CH, bit 2 Mode of Pin Write Read

0 Input Enabled P0E pin status

1 Output Write to P0E latch P0E latch contents

11.6 Port 0F (P0F0/RLS, P0F1/VREF)

Port 0F is a 2-bit input port and mapped at address 6FH of BANK0 of the data memory. A pull-up resistor

can be connected on-chip bitwise to this port by mask option.

If a read instruction that reads the port register is executed when both pins of port 0F are used as input port

pins, the higher 2 bits of the register are fixed to 0, and the pin statuses are read to the lower 2 bits. Executing

a write instruction is meaningless as the contents of the port register remain unchanged.

The P0F0/RLS pin is also used to input a standby mode release signal.

The P0F1/VREF pin inputs a reference voltage to the A/D converter when even one of the bits of P0CnIDI (RF:

address 1BH, n = 0 to 3) is set to “1”. If an instruction is executed to read the port register when the P0F1/VREF

pin functions as the VREF pin, bit 1 of address 6FH is always cleared to 0.

SCK

35

µ

PD17145(A1), 17147(A1), 17149(A1)

12. 8-BIT TIMERS/COUNTERS (TM0, TM1)

The

µ

PD17149(A1) is provided with two 8-bit timers/counters: timer 0 (TM0) and timer 1 (TM1).

By using the count-up signal of timer 0 as the count pulse to timer 1, the two 8-bit timers can be used as a

16-bit timer.

Each timer is controlled through hardware manipulation by using the PUT or GET instruction or manipulation

of the registers on the register file by using the PEEK or POKE instruction.

12.1 Configuration of 8-Bit Timers/Counters

Figure 12-1 shows the configuration of the 8-bit timers/counters. An 8-bit timer/counter consists of an 8-bit

count register, an 8-bit modulo register, a comparator that compares the value of the count register with that

of the modulo register, and a selector that selects the count pulse.

Cautions 1. The modulo register is a write register.

2. The count register is a read register.

36

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 12-1. Configuration of 8-Bit Timer/Counter

Data buffer

(DBF)

INT TM0EN TM0RES TM0CK1 TM0CK0

2

INT

DQ

CLK

R

TM1OSEL P0DBIO3

P0D

3

/

TM1OUT

TM1OUT

FF

DQ

CLK

R

2

TM1EN TM1RES TM1CK1 TM1CK0

Internal bus

Interrupt control

register (RF:0FH) Timer 0 mode

register (RF:11H)

Selector

System clock/16

System clock/512

System clock/64

Latch

Reset Clear

Timer 0 modulo

register (8)

(TM0M)

Timer 0

comparator (8)

Timer 0

count register (8)

(TM0C)

Coincidence Timer 0 count-up signal

(to timer 1)

IRQTM0 set signal

IRQTM0 clear signal

Internal reset

Data buffer

(DBF)

Internal bus

System clock/128

Latch

Reset

Timer 1 modulo

register (8)

(TM1M)

Timer 1

comparator (8)

Timer 1

count register (8)

(TM1C)

Timer 1 mode

register (RF:12H)

Coincidence

Reset

IRQTM1 set signal

IRQTM1 clear signal

Clear

System clock/8192

System clock/16

Timer 0 count up

Selector

Internal reset

Serial interface

control register

(RF:0BH)

Port control

register of bit I/O

(RF:2BH)

P0DB

3

output latch

37

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 12-2. Timer 0 Mode Register

RF : 11H Bit 3

TM0EN

0

Bit 2

TM0RES

0

Bit 1

TM0CK1

0

Bit 0

TM0CK0

0

R/W

TM0CK1

0

0

1

1

TM0CK0

0

1

0

1

TM0RES

0

1

TM0EN

0

1

Read/write

Initial value at reset Read = R, write = W

Selects count pulse of timer 0

System clock/16

System clock/512

System clock/64

INT pin

Resets timer 0

Resets timer 0 count register and

IRQTM0

Does not affect timer 0

Remark TM0RES is automatically cleared to 0 after it has been

set to 1. When it is read, "0" is always read.

Timer 0 start command

Resumes counting of timer 0

Stops counting of timer 0

Remark TM0EN can be used as a status flag that detects

the count status of timer 0 (1 : counting in progress,

0 : counting stopped)

38

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 12-3. Timer 1 Mode Register

RF : 12H Bit 3

TM1EN

1

R/W

Bit 2

TM1RES

0

Bit 1

TM1CK1

0

Bit 0

TM1CK0

0

TM1CK1

0

0

1

TM1CK0

0

1

0

TM1RES

0

11

1

TM1EN

0

1

Read/write

Initial value at reset

Selects count pulse of timer 1

System clock/128

System clock/8192

System clock/16

Resets timer 1

Resets timer 1 count register and

IRQTM1

Does not affect timer 1

Remark TM1RES is automatically cleared to 0 after it has been

set to 1. When it is read, "0" is always read.

Timer 1 start command

Resumes counting of timer 1

Stops counting of timer 1

Remark TM1EN can be used as a status flag that detects

the count status of timer 1 (1 : counting in progress,

0 : countin

g

stopped

)

Count-up signal from

timer 0

39

µ

PD17145(A1), 17147(A1), 17149(A1)

13. BASIC INTERVAL TIMER (BTM)

The

µ

PD17149(A1) is provided with a 7-bit basic interval timer. This timer has the following functions:

(1) Generates reference time.

(2) Selects and counts wait time when standby mode is released.

(3) Watchdog timer function to detect program runaway.

13.1 Configuration of Basic Interval Timer

Figure 13-1 shows the configuration of the basic interval timer.

40

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 13-1. Configuration of Basic Interval Timer

Remark (1) to (4) in the figure correspond to the signals in the timing chart in Figure 13-4.

BTM mode

register (RF:13H)

Watchdog timer mode

register (RF:13H)

BTMISEL BTMRES BTMCK1 BTMCK0 WDTRES 0 0 WDTEN

2

Reset

Selector

System clock/16384

System clock/4096

System clock/512

System clock/16

Basic interval timer

(7-bit divider)

IRQBTM

set signal

Reset

signal

R

S

Outputs "1" while counting 0 to 7 during counting

from 0 to 255.

f

BTM

2

7

f

BTM

2

5

f

BTM

Q

1-bit

divider

1-shot pulse

generator

Reset

Internal bus

(1)

(3)

(4)

(2)

Selector

41

µ

PD17145(A1), 17147(A1), 17149(A1)

13.2 Registers Controlling Basic Interval Timer

The basic interval timer is controlled by the BTM mode register and watchdog timer mode register.

Figures 13-2 and 13-3 show the configuration of each register.

Figure 13-2. BTM Mode Register

Selects count pulse to BTM

System clock/16

(1 instruction execution time)

System clock/16384

(1024 instruction execution time)

System clock/4096

(256 instruction execution time)

System clock/512

(32 instruction execution time)

BTMCK1

0

0

1

1

BTMCK0

0

1

0

1

Resets BTM

Does not affect basic interval timer

(BTM)

Resets binary counter of basic interval

timer (BTM)

BTMRES

0

1

Selects interval timer

Sets interval timer to 1/128 of count pulse

Sets interval timer to 1/32 of count pulse

BTMISEL

0

1

Remark

Read = R, Write = W

RF : 13H Bit 3

BTMISEL

0

Bit 2

BTMRES

0

Bit 1

BTMCK1

0

Bit 0

BTMCK0

0

BTMRES is automatically cleared to 0

after it has been set to 1. When it is read,

"0" is always read.

Read/write

Initial value at reset

R/W

42

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 13-3. Watchdog Timer Mode Register

Read = R, Write = W

RF : 03H

Enable watchdog timer

Stops watchdog timer.

Starts watchdog timer.

WDTEN

0

1

Resets watchdog timer

Does not affect watchdog timer.

Resets flip-flop that retains overflow carry of

BTM used for watchdog timer.

WDTRES

0

1

R/W

Remark 1.

2.

WDTEN cannot be cleared to 0 by

program.

WDTEN is automatically cleared to 0

after it has been set to 1. When it is

read, "0" is always read.

Read/write

Initial value at reset

Bit 3

WDTRES

0

Bit 2

0

0

Bit 1

0

0

Bit 0

WDTEN

0

Remark WDTRES is automatically cleared to 0

after it has been set to 1. When it is

read, "0" is alwa

y

s read.

43

µ

PD17145(A1), 17147(A1), 17149(A1)

13.3 Watchdog Timer Function

The basic interval timer can also be used as a watchdog timer that detects a program runaway.

13.3.1 Function of watchdog timer

The watchdog timer is a counter that generates a reset signal at fixed time intervals. By inhibiting generation

of this reset signal by program, the system can be reset (started from address 0000H) if the system becomes

runaway due to external noise (if the watchdog timer is not reset within specific time).

This function allows the program to escape from the runaway status because a reset signal is generated at

fixed time intervals even when the program jumps to an unexpected routine and enters an indefinite loop due

to external noise.

13.3.2 Operation of watchdog timer

When WDTEN is set to 1, the 1-bit divider is enabled to operate, and the basic interval timer starts operating

as an 8-bit watchdog timer.

Once the watchdog timer has been started, it cannot be stopped until the device is reset and WDTEN is

cleared to 0.

Reset effected by the watchdog timer can be inhibited in the following two ways:

(1) Repeatedly set WDTRES in the program.

(2) Repeatedly set BTMRES in the program.

In the case of (1), WDTRES must be set while the count value of the watchdog timer is 8 to 191 (before it

reaches 192). Therefore, program so that “SET1 WDTRES” is executed at least once in a cycle shorter than

that in which the watchdog timer counts 184.

In the case of (2), BTMRES must be set before the basic interval timer (BTM) counts 128. Therefore, program

so that “SET1 BTMRES” is executed at least once in a cycle shorter than that in which BTM counts 128. In this

case, however, interrupts cannot be processed with BTM.

Caution BTM is not reset even if WDTEN is set. Therefore, before setting WDTEN first, be sure to

set BTMRES to reset BTM.

Example

SET1 BTMRES

SET2 WDTEN, WDTRES

……

44

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 13-4. Timing Chart of Watchdog Timer (when WDTRES flag is used)

WDTEN

WDTRES

(4)

f

BTM

/2

8

(3)

Watchdog reset signal

(active high)

WDTRES

acknowledge period WDTRES

acknowledge period WDTRES

acknowledge period

Count value of watchdog timer

08

128

192

255

8

128

192

255 255

192 192

128 128

8

64

00 0

1-shot pulse generator

output (1)

f

BTM

/2

7

(2)

( ↓ IRQBTM set)

Reset signal is not generated

45

µ

PD17145(A1), 17147(A1), 17149(A1)

14. A/D CONVERTER

The

µ

PD17149(A1) is provided with an A/D converter with 4 analog input channels (P0C0/ADC0-P0C3/ADC3)

and a resolution of 8 bits.

This A/D converter is of the successive approximation type and operates in the following two modes:

1 Successive mode in which 8-bit A/D conversion is sequentially performed starting from the most

significant bit

2 Single mode in which an input analog voltage is compared with the set value of an 8-bit data register

14.1 Configuration of A/D Converter

Figure 14-1 shows the configuration of the A/D converter.

Figure 14-1. Block Diagram of A/D Converter

Note The 8-bit data register (ADCR) is cleared to 00H when the STOP instruction is executed.

Internal bus

Read signal

P0Cn/ADCn

RF: 22H RF: 20H RF: 21H

0 0 ADCCH1 ADCCH0 0 0 0

ADCSTRT ADCSOFT

0

ADCCMP ADCEND

Control circuit

Comparator

Selector

Tap decoder

8-bit data register

Note

(ADCR)

8

8

D/A converter

R/2RR3R/2

Remark n = 0 to 3

Output

latch

4

Selector

P0CnIDI

P0CBIOn

P0F

1

input data

A/D end signal

STOP instruction signal

P0F

1

/V

REF

P0CnIDI 4

46

µ

PD17145(A1), 17147(A1), 17149(A1)

14.2 Function of A/D Converter

(1) ADC0 to ADC3 pins

These pins input analog voltages to the four channels of the A/D converter. The analog voltages are

converted into digital signals. The A/D converter is provided with a sample and hold circuit, and an analog

input voltage being converted into a digital signal is internally held.

(2) VREF pin

This pin inputs a reference voltage to the A/D converter.

The signals input to ADC0 to ADC3 are converted into digital signals based on the voltage applied across

VREF and GND. The A/D converter of the

µ

PD17149(A1) has a function to automatically stop the current

flowing into the VREF pin when the A/D converter does not operate. A current flows into the VREF pin in the

following cases:

1 In successive mode (ADCSOFT = 0)

Since the ADCSTRT flag has been set to 1 until the ADCEND flag is set to 1.

2 In single mode (ADCSOFT = 1)

Since the ADCSTRT flag has been set to 1 or a value has been written to the 8-bit data register until

the result of comparison by the comparator is written to the ADCCMP flag.

Remarks 1. If the HALT instruction is executed during A/D conversion, the A/D converter operates,

in the successive mode, until the ADCEND flag is set, or in the single mode, until the

result of conversion is stored to the ADCCMP flag. Therefore, a current flows to the VREF

pin during this period.

2. A/D conversion in progress is stopped if the STOP instruction is executed. In this case,

the A/D converter is initialized, and the current flowing to the VREF pin is cut (the A/D

converter does not operate even if the STOP mode has been released).

(3) 8-bit data register (ADCR)

This is an 8-bit register that stores the result of A/D conversion of successive approximation type in the

successive mode. The contents of this register are read by using the GET instruction. In the single mode,

the contents of the 8-bit data register are converted into an analog voltage by an internal D/A converter and

is compared by the comparator with an analog signal input from the ADCn pin. A value can be written to

this register by using the PUT instruction.

(4) Comparator

The comparator compares the analog input voltage with the voltage output by the D/A converter. If the

analog input voltage is high, it outputs “1”; if the voltage is low, the comparator outputs “0”. The result of

comparison is stored to the 8-bit data register (ADCR) in the successive mode, and to the ADCCMP flag

in the single mode.

47

µ

PD17145(A1), 17147(A1), 17149(A1)

14.3 Operation of A/D Converter

The operation of the A/D converter can be executed in two modes, depending on the setting of the ADCSOFT

flag: successive and single modes.

ADCSOFT Operation Mode of A/D Converter

0 Successive mode (A/D conversion)

1 Single mode (compare operation)

Figure 14-2. Relationships between Analog Input Voltage and Digital Conversion Result

N

256

Ideal conversion result

FFH

FEH

FDH

N

03H

02H

01H

00H

Digital conversion result

1

256 255

256 256

256

(× V

DD

)

Analo

g

input volta

g

e

(

V

)

0 2

256 254

256

48

µ

PD17145(A1), 17147(A1), 17149(A1)

(1) Timing in successive mode (A/D conversion)

Figure 14-3. Timing in Successive Mode (A/D Conversion)

Caution Sampling is performed eight times while A/D conversion is executed once.

If the analog input voltage changes heavily during A/D conversion, A/D conversion cannot

be performed accurately. To obtain an accurate conversion result, it is necessary to

minimize the changes in the analog input voltage during A/D conversion.

Remark One sampling time = 14/fx (1.75

µ

s, at 8 MHz)

Sampling repeat cycle = 48/fx (6

µ

s, at 8 MHz)

Sampling capacitor capacitance = 100 pF (MAX.)

Sampling Sampling Sampling

ADCSTRT executed ADCR read

→Number of executed instructions (instruction cycle)

ADCSTRT

ADCEND

8-bit data

register Previous data Initial value:80H Highest 1 bit

determined All 8 bits

determined

POKE

123456789 24GET

Highest 2 bits

determined

49

µ

PD17145(A1), 17147(A1), 17149(A1)

(2) Timing in single mode (compare operation)

Figure 14-4. Timing in Single Mode (Compare Operation)

After 1 has been written to ADCSTRT in the single mode (execution of the POKE instruction), a value is

stored to ADCCMP three instructions after, and the result of comparison can be read by the PEEK

instruction. Even if data is set to ADCR (execution of the PUT instruction), comparison is started in the same

manner as ADCSTRT, and the result of comparison can be read three instructions after.

The ADCCMP flag is cleared to 0 when reset is executed or when an instruction that writes data to ADCR

is executed.

Caution Be sure to set ADCSOFT to 1 before setting a value to ADCR. When ADCSOFT = 0, no value

can be set to ADCR (the PUT ADCR, DBF instruction is invalidated).

Remark Sampling time = 14/fx (1.75

µ

s, at 8 MHz)

Sampling capacitor capacitance = 100 pF (MAX.)

Sampling Sampling

POKE PEEK PUT PEEK12 12

ADCSTRT

ADCEND

ADCCMP

ADCSTRT executed

→ Number of executed instructions (instruction cycle)

Previous data Comparison result Comparison result

ADCCMP read ADCCMP read

50

µ

PD17145(A1), 17147(A1), 17149(A1)

15. SERIAL INTERFACE (SIO)

The serial interface of the

µ

PD17149(A1) consists of an 8-bit shift register (SIOSFR), a serial mode register,

and a serial clock counter, and is used to input/output serial data.

15.1 Function of Serial Interface

The serial interface can transmit or receive 8-bit data in synchronization with the clock by using three wires:

serial clock input (SCK), serial data output (SO), and serial data input (SI) pins. This serial interface can connect

various peripheral I/O devices in a mode compatible with the method employed for the

µ

PD7500 series and 75X

series.

(1) Serial clock

Four types of serial clocks, three internal and one external, can be selected. If an internal clock is selected

as the serial clock, the selected clock is automatically output to the P0D 0/SCK pin.

Table 15-1. Serial Clocks

SIOCK1 SIOCK0 Selected Serial Clock

0 0 External clock from SCK pin

0 1 System clock/16

1 0 System clock/128

1 1 System clock/1024

(2) Transfer operation

Each pin of port 0D (P0D0/SCK, P0D1/SO, P0D2/SI) functions as a serial interface pin when SIOEN is set

to 1. If SIOTS is set to 1 at this time, the serial interface starts its operation in synchronization with the falling

edge of the external or internal clock. If SIOTS is set, IRQSIO is automatically cleared.

Data is transferred starting from the most significant bit of the shift register in synchronization with the rising

edge of the serial clock, and the information on the SI pin is stored to the shift register, starting from the

least significant bit, in synchronization with the rising edge of the serial clock.

When 8-bit data has been completely transferred, SIOTS is automatically cleared, and IRQSIO is set.

Remark When serial transfer is executed, transfer is started only from the most significant bit of the

contents of the shift register. In other words, transfer cannot be started from the least significant

bit. The status of the SI pin is always loaded to the shift register in synchronization with the rising

edge of the serial clock.

51

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 15-1. Block Diagram of Serial Interface

Caution The output latch of the shift register is independent of the output latch of P0D 1. Therefore,

even if an output instruction is executed to P0D1, the status of the output latch of the shift

register is not affected. The output latch of the shift register is cleared to “0” by RESET

input. After that, it holds the status of the LSB of the previously transferred data.

P0D

2

/SI

P0D

1

/SO

P0D

0

/SCK

Shift register (SIOSFR)

P0D

1

output latch

Serial clock

counter

Clear

Selector

SIOTS SIOHIZ SIOCK1 SIOCK0

IRQSIO

clear signal

IRQSIO

set signal

One shot

f

x

/1024

f

x

/128

f

x

/16

SIOEN

P0DBIO0

P0DBIO1

QS

R

Output

latch

LSB MSB

Clock

Carry

P0D

0

output latch

Selector

Serial start

Selector

52

µ

PD17145(A1), 17147(A1), 17149(A1)

15.2 Operation Mode of 3-Wire Serial Interface

The serial interface can operate in the following two modes. When the serial interface function is selected,

the P0D2/SI pin always inputs data in synchronization with the serial clock.

• 8-bit transmission/reception mode (simultaneous transmission/reception)

• 8-bit reception mode (SO pin: high-impedance state)

Table 15-2. Operation Modes of Serial Interface

SIOEN SIOHIZ P0D0/SI Pin P0D1/SO Pin Operation Mode of Serial Interface

1 0 SI SO 8-bit transmission/reception mode

1 1 SI P0D1 (input) 8-bit reception mode

0×P0D0 (I/O) P0D1 (I/O) General-purpose port mode

× : Don't care

(1) 8-bit transmission/reception mode (simultaneous transmission/reception)

Input or output of serial data is controlled by the serial clock. The MSB of the shift register is output to the

SO line at the falling edge of the serial clock (SCK pin signal). The contents of the shift register are shifted

1 bit at the rising edge of the serial clock. At the same time, the data on the SI line is loaded to the LSB

of the shift register.

The serial clock counter (3-bit counter) sets an interrupt request flag (IRQSIO <- 1) each time it has counted

eight serial clocks.

Figure 15-2. Timing in 8-Bit Transmission/Reception Mode (Simultaneous Transmission/Reception)

Remark DI: serial data input

DO: serial data output

12345678

DI7 DI6 DI5 DI4 DI3 DI2 DI1

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

DI0

SCK pin

SI pin

SO pin

IRQSIO

Starts transfer in synchronization with falling of SCK pin

Executes instruction that writes "1" to SIOTS

(

transfer start command

)

End of transfer

53

µ

PD17145(A1), 17147(A1), 17149(A1)

(2) 8-bit reception mode (SO pin: high-impedance state)

The P0D1/SO pin goes into a high-impedance state when SIOHIZ = 1. If supply of the serial clock is started

at this time by writing “1” to SIOTS, the serial interface only receives data.

Because the P0D1/SO pin goes into a high-impedance state, it can be used as an input port pin (P0D1).

Figure 15-3. Timing in 8-Bit Reception Mode

Remark DI: serial data input

(3) Operation stop mode

When the value of SIOTS (RF: address 02H, bit 3) is 0, the serial interface is set in the operation stop mode.

In this mode, serial transfer is not executed.

Because the shift register does not perform the shift operation in this mode, it can be used as an ordinary

8-bit register.

12345678

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SCK pin

SI pin

SO pin

IRQSIO

Hi - Z

Starts transfer in synchronization with falling of SCK pin

Executes instruction that writes "1" to SIOTS

(

transfer start command

)

End of transfer

54

µ

PD17145(A1), 17147(A1), 17149(A1)

16. INTERRUPT FUNCTION

The

µ

PD17149(A1) has five interrupt causes, of which four are internal and one is external, enabling various

applications.

The interrupt control circuit of the

µ

PD17149(A1) has the following features and can perform interrupt

processing at extremely high speeds:

(a) Acknowledging an interrupt can be controlled by interrupt mask enable flag (INTE) and interrupt enable

flag (IP×××).

(b) Interrupt request flags (IRQ×××) can be tested and cleared (occurrence of an interrupt can be checked

by software).

(c) Multiple interrupts of up to 3 levels can be processed.

(d) The standby mode (STOP or HALT) can be released by an interrupt request (releasing condition can be

selected by the interrupt enable flag).

Caution Only the BCD, CMP, CY, Z, and IXE flags are automatically saved to the stack by

hardware when interrupt processing is performed. Up to three levels of multiple

interrupts can be processed. If the peripheral hardware (timers, A/D converter, etc.)

is accessed during interrupt processing, the contents of DBF and WR are not saved by

the hardware. It is therefore recommended that DBF and WR be saved to the RAM by

software at the beginning of interrupt processing, and that their contents be restored

immediately before the interrupt processing.

16.1 Types of Interrupt Causes and Vector Addresses

All the interrupts of the

µ

PD17149 (A1) are vectored interrupts, and therefore, program execution branches

to a vector address corresponding to the interrupt cause when an interrupt has been acknowledged. Table 16-

1 shows the types of interrupt causes and vector addresses.

If two or more interrupts occur at the same time, or if two or more pending interrupts are enabled all at once,

processing is performed according to the priority shown in Table 16-1.

Table 16-1. Types of Interrupt Causes

Vector Internal

Interrupt Cause Priority IRQ Flag IP Flag IEG Flag Remark

Address /External

INT pin 1 0005H IRQ IP IEGMD0, 1 External Rising, falling, or

(RF: 0FH, bit 0) RF: 3FH, RF: 2FH, RF:1FH both rising and fall-

bit 0 bit 0 ing edges selectable

Timer 0 2 0004H IRQTM0 IPTM0 Internal

RF: 3EH, RF: 2FH, —

bit 0 bit 1

Timer 1 3 0003H IRQTM1 IPTM1 Internal

RF: 3DH, RF: 2FH, —

bit 0 bit 2

Basic interval 4 0002H IRQBTM IPBTM — Internal

timer RF: 3CH, RF: 2FH,

bit 0 bit 3

Serial interface 5 0001H IRQSIO IPSIO Internal

RF: 3BH, RF: 2EH, —

bit 0 bit 0

55

µ

PD17145(A1), 17147(A1), 17149(A1)

16.2 Hardware of Interrupt Control Circuit

This section describes each flag of the interrupt control circuit.

(1) Interrupt request flags and interrupt enable flags

An interrupt request flag (IRQ×××) is set to 1 when an interrupt request is generated, and automatically

cleared to 0 when interrupt processing is executed.

An interrupt enable flag (IP×××) is provided for each interrupt request flag. The corresponding interrupt is

enabled when this flag is “1”, and disabled when the flag is “0”.

(2) EI/DI instruction

Whether an interrupt that has been acknowledged is executed is specified by the EI or DI instruction.

When the EI instruction is executed, an interrupt enable flag (INTE) that enables acknowledging an interrupt

is set to 1. The INTE flag is not registered on the register file. Therefore, the status of this flag cannot be

checked by an instruction.

The DI instruction clears the INTE flag to “0”, disabling all the interrupts.

The INTE flag is also cleared to 0 at reset, and therefore all the interrupts are disabled.

Table 16-2. Interrupt Request Flags and Interrupt Enable Flags

Interrupt Request Flag Interrupt Request Flag Setting Signal Interrupt Enable Flag

IRQ Sets when edge of INT pin input signal is detected. IP

Edge to be detected is selected by IEGMD0 and IEGMD1

flags.

IRQTM0 Set by coincidence signal from timer 0. IPTM0

IRQTM1 Set by coincidence signal from timer 1. IPTM1

IRQBTM Set by overflow from basic interval timer (reference time IPBTM

interval signal).

IRQSIO Set when serial interface completes serial data transfer. IPSIO

56

µ

PD17145(A1), 17147(A1), 17149(A1)

17. STANDBY FUNCTION

17.1 Outline of Standby Function

The current dissipation of the

µ

PD17149(A1) can be reduced by using the standby function. This function

can be effected in two modes: STOP and HALT.

The STOP mode stops the system clock. In this mode, the current dissipation by the CPU is minimized with

only leakage current flowing. The CPU therefore does not operate, but the contents of the data memory are

retained.

In the HALT mode, oscillation of the clock continues. However, supply of the clock to the CPU is stopped.

Therefore, the CPU stops operating. This mode cannot reduce the current dissipation as much as the STOP

mode. However, because the system clock continues oscillating, the operation can be started immediately after

the HALT mode has been released. In both the STOP and HALT modes, the statuses of the data memory,

registers, and the output latches of the output ports immediately before the standby mode is set are retained

(except STOP 0000B). Therefore, set the port status so that the current dissipation of the entire system is

reduced before the standby mode is set.

57

µ

PD17145(A1), 17147(A1), 17149(A1)

Table 17-1. Status in Standby Mode

STOP Mode HALT Mode

Setting STOP instruction HALT instruction

instruction

Clock

oscillation Stops oscillation Continues oscillation

circuit

CPU • Stops operation

RAM • Retains previous status

Port • Retains previous statusNote

TM0 • Can operate only when INT input is selected • Operable

as count clock

• Stops when system clock is selected

(count value is retained)

TM1 • Stops operation • Operable

(count value is reset to “0”)

(count up is disabled)

BTM • Stops operation (count value is retained) • Operable

SIO • Can operate only when external clock is • Operable

selected as serial clockNote

A/D • Stops operationNote (ADCR <- 00H) • Operable

INT • Can operate • Operable

Note As soon as the STOP 0000B instruction is executed, the pins of these peripherals are set in the input

port mode, even when the control signal functions of the pins are used.

Cautions 1. Be sure to execute the NOP instruction immediately before the STOP and HALT

instructions.

2. If both the interrupt request flag and interrupt enable flag corresponding to an interrupt

are set, and if the interrupt is specified to release the standby mode, the standby mode

is not set even if the STOP or HALT instruction is executed.

Operating status

58

µ

PD17145(A1), 17147(A1), 17149(A1)

17.2 HALT Mode

17.2.1 Setting HALT mode

The HALT mode is set when the HALT instruction is executed.

The operand of the HALT instruction, b3b2b1b0, specifies the condition under which the HALT mode is

released.

Table 17-2. HALT Mode Releasing Condition

Format: HALT b3b2b1b0B

Bit HALT mode releasing conditionNote 1

b3Enables releasing HALT mode by IRQ××× when 1Notes 2, 4

b2Fixed to “0”

b1Enables forced release of HALT mode by IRQTM1 when 1Notes 3, 4

b0Enables releasing HALT mode by RLS input when 1Note 4

Notes 1. Only reset (RESET input or POC) is valid when HALT 0000B is specified.

2. IP××× must be set to 1.

3. The HALT mode is released regardless of the status of IPTM1.

4. Even if the HALT instruction is executed with IRQ××× = 1 or RLS input being low, the HALT

instruction is ignored (treated as an NOP instruction), and the HALT mode is not set.

17.2.2 Start address after HALT mode is released

The start address from which the program execution is started after the HALT mode has been released differs

depending on the interrupt enable condition and the condition under which the HALT mode has been released.

Table 17-3. Start Address after HALT Mode Is Released

Releasing Condition Start Address after Release

ResetNote 1 Address 0

RLS Address next to that of HALT instruction

Address next to that of HALT instruction in DI status

IRQ×××Note 2 Interrupt vector in EI status

(if two or more IRQ××× flags are set, interrupt vector with higher priority)

Notes 1. RESET input and POC are valid as reset.

2. IP××× must be set to 1 except when the HALT mode is forcibly released by IRQTM1.

59

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 17-1. Releasing HALT Mode

(a) By RESET input

(b) By RLS input

(c) By IRQ××× (in DI status)

(d) By IRQ××× (in EI status)

Interrupt processing

acknowledged

↓

IRQ×××

HALT instruction executed

↓

Operation mode HALT mode Operation mode

HALT instruction executed

↓TM1 counts up

↓

Operation mode HALT mode

System reset status

WAIT a Operation mode

(starts from address 0)

WAIT a : Wait time until TM1 counts 256 clocks divided by 128

256×128/fX (approx. 4 ms at fX=8 MHz)

RESET

HALT instruction executed

↓

Operation mode HALT mode Operation mode

RLS

IRQ×××

HALT instruction executed

↓

Operation mode HALT mode Operation mode

60

µ

PD17145(A1), 17147(A1), 17149(A1)

17.3 STOP Mode

17.3.1 Setting STOP mode

The STOP mode is set when the STOP instruction is executed.

The operand of the STOP instruction, b3b2b1b0, specifies the condition under which the STOP mode is

released.

Table 17-4. STOP Mode Releasing Condition

Format: STOP b3b2b1b0B

Bit STOP mode releasing conditionNote 1

b3Enables releasing HALT mode by IRQ××× when 1Notes 2, 4

b2Fixed to “0”

b1Fixed to “0”

b0Enables releasing STOP mode by RLS input when 1Notes 3, 4

Notes 1. Only reset (RESET input or POC) is valid when STOP 0000B is specified. When STOP

0000B is executed, the internal circuitry of the microcontroller is initialized to the status

immediately after reset.

2. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1.

3. b0 alone cannot be set to 1 (STOP 0001B is prohibited).

Before setting b0 to 1, be sure to set b3 to 1.

4. Even if the STOP instruction is executed with IRQ××× = 1 or the RLS input being low, the

STOP instruction is ignored (treated as an NOP instruction), and the STOP mode is not set.

17.3.2 Start address after STOP mode is released

The start address from which the program execution is started after the STOP mode has been released differs

depending on the condition under which the STOP mode has been released, and interrupt enable condition.

Table 17-5. Start Address after STOP Mode Is Released

Releasing Condition Start Address after Release

ResetNote 1 Address 0

RLS Address next to that of STOP instruction

Address next to that of HALT instruction in DI status

IRQ×××Note 2 Interrupt vector in EI status

(if two or more IRQ××× flags are set, interrupt vector with higher priority)

Notes 1. RESET input and POC are valid as reset.

2. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1.

61

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 17-2. Releasing STOP Mode

(a) By RESET input

(b) By RLS input

(c) By IRQ××× (in DI status)

RESET

STOP instruction executed

↓TM1 counts up

↓

Operation mode STOP mode System reset status WAIT b Operation mode

(starts from address 0)

WAIT b : Wait time until TM1 counts 256 clocks divided by 128

256 × 128/f

X

+ (apporox. 4 ms + at f

X

= 8 MHz)

: Oscillation growth time (differs depending on the oscillator)

ααα

RLS

STOP instruction executed

↓TM1 counts up

↓

Operation mode STOP mode WAIT c Operation mode

WAIT c : Wait time until TM1 counts clocks divided by m n times

n × m/f

X

+ (n and m are values immediately before STOP mode is set)

: Oscillation growth time (differs depending on the oscillator)

α

α

IRQ×××

TM1 counts up

↓

Operation mode STOP mode WAIT c Operation mode

WAIT c : Wait time until TM1 counts clocks divided by m n times

n × m/f

X

+ (n and m are values immediately before STOP mode is set)

: Oscillation

g

rowth time

(

differs dependin

g

on the oscillator

)

STOP instruction executed

↓

α

α

62

µ

PD17145(A1), 17147(A1), 17149(A1)

(d) By IRQ××× (in EI status)

IRQ×××

STOP instruction executed

↓

TM1 counts up, interrupt

processing acknowledged

↓

Operation mode STOP mode WAIT c Operation mode

WAIT c : Wait time until TM1 counts clocks divided by m n times

n ×m/f

X

+ (n and m are values immediately before STOP mode is set)

: Oscillation growth time (differs depending on the oscillator)

α

α

63

µ

PD17145(A1), 17147(A1), 17149(A1)

18. RESET

The

µ

PD17149 (A1) can be reset not only by the RESET input, but also by the internal POC circuit that detects

a supply voltage drop, watchdog timer function that resets the microcontroller if program runaway occurs, and

overflow or underflow of the address stack. Note, however, that the internal POC circuit is a mask option.

18.1 Reset Function

The reset function initializes the device operation. How the device is initialized differs depending on the type

of reset. Table 18-1. Hardware Status at Reset

• Overflow of Watchdog

Timer

• Overflow and

Underflow of Stack

• RESET Input in

Standby Mode

• Reset by Internal

POC Circuit in

Standby Mode

• RESET Input

during Operation

• Reset by Internal

POC Circuit

Program counter 0000H 0000H 0000H

Input/output Input Input Input

Contents of output

latch

General-purpose

data memory Undefined Retains contents Undefined

(except DBF)

DBF Undefined Undefined Undefined

System register

(except WR)

WR Undefined Retains contents Undefined

Control register

Timer 0: 00H,

timer 1: undefined

Modulo register FFH FFH FFH

Binary counter of basic interval timer Undefined Undefined

Shift register (SIOSFR) Undefined Retains contents Undefined

Output latch 0 0 Undefined

Data register of A/D converter (ADCR) 00H 00H 00H

Type of Reset

Port 0 0 Undefined

00 0

Count register 00H 00H

Timer 0 and

timer 1

SP = 5H, IRQTM1 = 1, TM1EN = 1,

IRQBTM = 1, INT = status at that time.

Others are 0. Refer to 8. REGISTER FILE

(RF).

SP = 5H, INT = status

at that time. Others

retain contents.

Undefined. However,

40H if watchdog timer

overflows.

Serial interface

General-purpose

data memory

Hardware

64

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 18-1. Configuration of Reset Block

18.2 Reset Operation

Figure 18-2 shows the operation when the system is reset by using the RESET pin.

When the RESET pin is made high, oscillation of the system clock is started, oscillation stabilization wait time

specified by timer 1 elapses, and program execution is started from address 0000H.

These operations are also performed if the system is reset by the POC circuit.

If the system is reset by using an overflow of the watchdog timer or an overflow or underflow of the stack,

the oscillation stabilization wait time (WAIT a) does not elapse, and program execution is started from address

0000H after the internal circuitry has been initialized.

Figure 18-2. Reset Operation

Note Oscillation stabilization wait time. An operation mode is set when system clock is counted

128 × 256 times by timer 1 (time required to executed 2048 instructions: approx. 4 ms at 8 MHz).

Mask option

RESET

V

DD

Internal

reset signal

POC circuit

(mask option)

RESET

TM1EN

TM1RES

Operation mode Reset WAIT a

Note

Operation mode

65

µ

PD17145(A1), 17147(A1), 17149(A1)

19. POC CIRCUIT (MASK OPTION)

The POC circuit monitors the supply voltage. When the supply voltage is turned ON/OFF, it automatically

resets the internal circuitry of the microcontroller. This circuit can be used in an application circuit with a clock

frequency of 400 kHz to 4 MHz.

The

µ

PD17149 (A1) can be provided with the POC circuit by mask option.

Caution The POC circuit is not provided to the PROM model (

µ

PD17P149).

19.1 Function of POC Circuit

The POC circuit has the following functions:

• Generates internal reset signal when VDD ≤ VPOC

• Clears internal reset signal when VDD > VPOC

(where, VDD: supply voltage, VPOC: POC detection voltage)

Figure 19-1. Operation of POC Circuit

5.5 V

4.5 V

V

POC

2.7 V

0 V

Note 3

V

DD

Note 1

→ t

ResetOperation mode

Note 4

Reset

Operation guaranteed range

Internal reset signal

↑

Note 2

Note 3

66

µ

PD17145(A1), 17147(A1), 17149(A1)

Notes 1. Actually, oscillation stabilization wait time specified by timer 1 elapses before the operation mode

is set. This time is equal to that required for executing about 2048 instructions (approx. 8 ms at

4 MHz).

2. To reset the microcontroller again when the supply voltage drops, the status in which the voltage

drops below VPOC must be maintained at least for the duration of the reset detection pulse width

tSAMP.

Therefore, reset is actually effected with a delay time of up to tSAMP.

3. The operation is not guaranteed if the supply voltage drops below the rated minimum value (2.7

V).

However, the POC circuit is designed to generate the internal reset signal so long as it is possible,

regardless of oscillation. Therefore, the internal circuitry is reset when the voltage supplied to

it has reached the level at which the circuitry can operate.

4. If the supply voltage abruptly increases (3 V/ms MIN.), the POC circuit may generate the internal

reset signal, even in an operation mode, to prevent program runaway.

Remark For the values of VPOC and tSAMP, refer to 22. ELECTRICAL SPECIFICATIONS.

19.2 Conditions to Use POC Circuit

The POC circuit can be used when the application circuit satisfies the following conditions:

• The application circuit does not require a high reliability.

• The operating voltage must range from 4.5 to 5.5 V.

• The clock frequency must range from 400 kHz to 4 MHz.

• The supply voltage must satisfy the ratings of the POC circuit.

Cautions 1. If the application circuit requires an extremely high reliability, design the circuit so that

the RESET signal is input from an external source.

2. The current dissipation in the standby mode slightly increases if the POC circuit is

used.

Remark The guaranteed operating voltage range of the POC circuit is VDD = 2.7 to 5.5 V.

67

µ

PD17145(A1), 17147(A1), 17149(A1)

20. INSTRUCTION SET

20.1 Outline of Instruction Set

b15

b14-b11 01

BIN HEX

0000 0 ADD r, m ADD m, #n4

0001 1 SUB r, m SUB m, #n4

0010 2 ADDC r, m ADDC m, #n4

0011 3 SUBC r, m SUBC m, #n4

0100 4 AND r, m AND m, #n4

0101 5 XOR r, m XOR m, #n4

0110 6 OR r, m OR m, #n4

INC AR

INC IX

MOVT DBF, @AR

BR @AR

CALL @AR

RET

RETSK

EI

DI

0111 7 RETI

PUSH AR

POP AR

GET DBF, p

PUT p, DBF

PEEK WR, rf

POKE rf, WR

RORC r

STOP s

HALT h

NOP

1000 8 LD r, m ST m, r

1001 9 SKE m, #n4 SKGE m, #n4

1010 A MOV @r, m MOV m, @r

1011 B SKNE m, #n4 SKLT m, #n4

1100 C BR addr (page 0) CALL addr

1101 D BR addr (page 1) MOV m, #n4

1110 E SKT m, #n

1111 F SKF m, #n

68

µ

PD17145(A1), 17147(A1), 17149(A1)

20.2 Legend

AR : address register

ASR : address stack register indicated by stack pointer

addr : program memory address (lower 11 bits)

BANK : bank register

CMP : compare flag

CY : carry flag

DBF : data buffer

h : halt release condition

INTEF : interrupt enable flag

INTR : register automatically saved to the stack when interrupt processing is performed

INTSK : interrupt stack register

IX : index register

MP : data memory row address pointer

MP E : memory pointer enable flag

m : data memory address indicated by mR, mC

mR: data memory row address (high)

mC: data memory column address (low)

n : bit position (4 bits)

n4 : immediate data (4 bits)

PAGE : page (bit 11 of program counter)

PC : program counter

p : peripheral address

pH: peripheral address (higher 3 bits)

pL: peripheral address (lower 4 bits)

r : general register column address

rf : register file address

rfR: register file row address (higher 3 bits)

rfC: register file column address (lower 4 bits)

SP : stack pointer

s : stop release condition

WR : window register

(×) : contents addressed by ×

69

µ

PD17145(A1), 17147(A1), 17149(A1)

In-

struc-

tion

m, @r 11010 mRmCr

@r, m 01010 mRmCr

RORC r 00111 000 0111 r

AdditionSubtractionLogical operation

Judgment

Comparison

Rotation

Transfer

ADD

ADDC

INC

SUB

SUBC

OR

AND

XOR

MOVT DVF, @AR 00111 000 0001 0000

20.3 Instruction Set

Instruction code

Mnemonic Operand Operation op code Operand

r, m (r) ← (r) + (m) 00000 mRmCr

m, #n4 (m) ← (m) + n4 10000 mRmCn4

r, m (r) ← (r) + (m) + CY 00010 mRmCr

m, #n4 (m) ← (m) + n4 + CY 10010 mRmCn4

AR AR ← AR + 1 00111 000 1001 0000

IX IX ← IX + 1 00111 000 1000 0000

r, m (r) ← (r) – (m) 00001 mRmCr

m, #n4 (m) ← (m) – n4 10001 mRmCn4

r, m (r) ← (r) – (m) – CY 00011 mRmCr

m, #n4 (m) ← (m) – n4 – CY 10011 mRmCn4

r, m (r) ← (r) ∨ (m) 00110 mRmCr

m, #n4 (m) ← (m) ∨ n4 10110 mRmCn4

r, m (r) ← (r) ∧ (m) 00100 mRmCr

m, #n4 (m) ← (m) ∧ n4 10100 mRmCn4

r, m (r) ← (r) ∨ (m) 00101 mRmCr

m, #n4 (m) ← (m) ∨ n4 10101 mRmCn4

SKT m, #n CMP ← 0, if (m) ∧ n = n, then skip 11110 mRmCn

SKF m, #n CMP ← 0, if (m) ∧ n = 0, then skip 11111 mRmCn

SKE m, #n4 (m) – n4, skip if zero 01001 mRmCn4

SKNE m, #n4 (m) – n4, skip if not zero 01011 mRmCn4

SKGE m, #n4 (m) – n4, skip if not borrow 11001 mRmCn4

SKLT m, #n4 (m) – n4, skip if borrow 11011 mRmCn4

→ CY → (r) b3 → (r) b2 → (r) b1 → (r) b0

LD r, m (r) ← (m) 01000 mRmCr

ST m, r (m) ← (r) 11000 mRmCr

if MPE = 1: (MP, (r)) ← (m)

if MPE = 0: (BANK, mR, (r)) ← (m)

MOV if MPE = 1: (m) ← (MP, (r))

if MPE = 0: (m) ← (BANK, mR, (r))

m, #n4 (m) ← n4 11101 mRmCn4

SP ← SP –1, ASR ← PC, PC ← AR,

DBF ← (PC), PC ← ASR, SP ← SP +1

PUSH AR SP ← SP –1, ASR ← AR 00111 000 1101 0000

POP AR AR ← ASR, SP ← SP +1 00111 000 1100 0000

PEEK WR, rf WR ← (rf) 00111 rfR0011 rfC

POKE rf, WR (rf) ← WR 00111 rfR0010 rfC

GET DBF, p DBF ← (p) 00111 pH1011 pL

PUT p, DBF (p) ← DBF 00111 pH1010 pL

70

µ

PD17145(A1), 17147(A1), 17149(A1)

BR addr

Instruction code

Mnemonic Operand Operation op code Operand

addr Note Note addr

@AR PC ← AR 00111 000 0100 0000

SP ← SP – 1, ASR ← PC,

PC ← addr

SP ← SP – 1, ASR ← PC,

PC ← AR

RET PC ← ASR, SP ← SP + 1 00111 000 1110 0000

RETSK PC ← ASR, SP ← SP + 1 and skip 00111 001 1110 0000

RETI PC ← ASR, INTR ← INTSK, SP ← SP + 1 00111 100 1110 0000

EI INTEF ← 1 00111 000 1111 0000

DI INTEF ← 0 00111 001 1111 0000

STOP s STOP 00111 010 1111 s

HALT h HALT 00111 011 1111 h

NOP No operation 00111 100 1111 0000

Note The operation and op code of “BR addr” of the

µ

PD17145(A1), 17147(A1), and

µ

PD17149(A1) are

as follows:

(a)

µ

PD17145(A1), 17147(A1)

Mnemonic Operand Operation op code

BR addr PC ← addr, PAGE ← 0 01100

(b)

µ

PD17149(A1)

Mnemonic Operand Operation op code

PC ← addr, PAGE ← 0 01100

PC ← addr, PAGE ← 1 01101

In-

struc-

tion

BR

CALL

@AR 00111 000 0101 0000

addr 11100 addr

BranchSubroutine

Interrupt

Others

71

µ

PD17145(A1), 17147(A1), 17149(A1)

20.4 Assembler (AS17K) Embedded Macro Instruction

Legend

flag n: FLG type symbol

< >: Can be omitted

Mnemonic Operand Operation n

SKTn flag 1, …flag n if (flag 1) to (flag n) = all “1”, then skip 1 ≤ n ≤ 4

SKFn flag 1, …flag n if (flag 1) to (flag n) = all“0”, then skip 1 ≤ n ≤ 4

SETn flag 1, …flag n (flag 1) to (flag n) ← 11 ≤ n ≤ 4

CLRn flag 1, …flag n (flag 1) to (flag n) ← 01 ≤ n ≤ 4

if (flag n) = “0”, then (flag n) ← 1

if (flag n) = “1”, then (flag n) ← 0

<NOT> flag 1, if description = NOT flag n, then (flag n) ← 0

…<<NOT> flag n> if description = flag n, then (flag n) ← 1

BANKn (BANK) ← nn = 0

Embedded macro

NOTn flag 1, …flag n 1 ≤ n ≤ 4

INITFLG 1 ≤ n ≤ 4

72

µ

PD17145(A1), 17147(A1), 17149(A1)

21. ASSEMBLER RESERVED WORDS

21.1 Mask Option Directive

The

µ

PD17149 (A1) has the following mask options:

• Internal pull-up resistor of RESET pin

• Internal pull-up resistor of P0F1 and P0F0 pins

• Internal pull-up resistor of INT pin

• Internal POC circuit

When developing a program, it is necessary to specify all the above mask options in the source program by

using a mask option definition directive (pseudo instruction).

21.1.1 Specifying mask option

The mask option is described in the assembler source program by using the following directives:

• OPTION directive, ENDOP directive

• Mask option definition directive

(1) OPTION and ENDOP directives

These directives specify the range in which the mask option is specified (mask option definition block).

Specify the mask option by describing a mask option definition directive in the area sandwiched between

the OPTION and ENDOP directives.

Format

Symbol field Mnemonic field Operand field Comment field

[label:] OPTION [;comment]

ENDOP

…

73

µ

PD17145(A1), 17147(A1), 17149(A1)

(2) Mask option definition directives

Table 21-1. Mask Option Definition Directives

Option Definition Directive and Format Operand Defined Contents

Internal pull-up resistor OPTRES <operand> OPEN None

of RESET pin PULLUP Defined

Internal pull-up resistor OPTP0F <operand 1>, <operand 2>Note OPEN None

of P0F1 and P0F0 pins PULLUP Defined

Internal pull-up resistor OPTINT <operand> OPEN None

of INT pin PULLUP Defined

Internal POC circuit OPTPOC <operand> NOUSE Not used

USE Used

Note <operand 1> specifies the mask option of the P0F1 pin, and <operand 2> specifies that of the P0F 0

pin.

(3) Example of mask option description

; Example of describing mask option of the

µ

PD17149 (A1)

MASK_OPTION:

OPTION ; start of mask option definition block

OPTRES PULLUP ; connects internal pull-up resistor to RESET pin

OPTP0F PULLUP, OPEN ; connects internal pull-up resistor to P0F1, and leaves P0F0 open (exter-

nally pulled up)

OPTINT PULLUP ; connects internal pull-up resistor to INT pin

OPTPOC NOUSE ; internal POC circuit is not used

ENDOP ; End of mask option definition block

74

µ

PD17145(A1), 17147(A1), 17149(A1)

21.2 Reserved Symbols

The following tables show the reserved symbols defined by the device file (AS17149) of the

µ

PD17149(A1):

System register (SYSREG)

Symbol Name Attribute Value Read/Write Description

AR3 MEM 0.74H R Bits b15-b12 of address register

AR2 MEM 0.75H R/W Bits b11-b8 of address register

AR1 MEM 0.76H R/W Bits b7-b4 of address register

AR0 MEM 0.77H R/W Bits b3-b0 of address register

WR MEM 0.78H R/W Window register

BANK MEM 0.79H R/W Bank register

IXH MEM 0.7AH R/W Index register, high

MPH MEM 0.7AH R/W Data memory row address pointer, high

MPE FLG 0.7AH.3 R/W Memory pointer enable flag

IXM MEM 0.7BH R/W Index register, middle

MPL MEM 0.7BH R/W Data memory row address pointer, low

IXL MEM 0.7CH R/W Index register, low

RPH MEM 0.7DH R/W General register pointer, high

RPL MEM 0.7EH R/W General register pointer, low

PSW MEM 0.7FH R/W Program status word

BCD FLG 0.7EH.0 R/W BCD flag

CMP FLG 0.7FH.3 R/W Compare flag

CY FLG 0.7FH.2 R/W Carry flag

Z FLG 0.7FH.1 R/W Zero flag

IXE FLG 0.7FH.0 R/W Index enable flag

75

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 21-1. Configuration of System Register

Notes 1. “0” in this field means that the bit is fixed to “0”.

2. b3 and b2 of AR2 of the

µ

PD17145 (A1) are fixed to 0. b3 of AR2 of the

µ

PD17147 (A1) is fixed

to 0.

Address

Name

Symbol

Bit

Data

Note 1

74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH

AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW

MPH MPL

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

b

3

b

2

b

1

b

0

0000000000000000 0000000000000000000000000000

0000 0000 0000 0000

(RP)(MP)

(IX)

(BANK)(AR)

M

P

E

B

C

D

C

M

P

C

YZ I

X

E

Address register

(AR) Bank

register

(BANK)

Index register

(IX)

Data memory row

address pointer

(MP)

Undefined

Note 2

Initial

value

at reset

Window

register

(WR)

General register

pointer

(RP)

Program

status word

(PSWORD)

76

µ

PD17145(A1), 17147(A1), 17149(A1)

Data buffer (DBF)

Symbol Name Attribute Value Read/Write Description

DBF3 MEM 0.0CH R/W Bits 15 to 12 of DBF

DBF2 MEM 0.0DH R/W Bits 11 to 8 of DBF

DBF1 MEM 0.0EH R/W Bits 7 to 4 of DBF

DBF0 MEM 0.0FH R/W Bits 3 to 0 of DBF

Port register

Symbol Name Attribute Value Read/Write Description

P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A

P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A

P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A

P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A

P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B

P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B

P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B

P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B

P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C

P0C2 FLG 0.72H.2 R/W Bit 2 of port 0C

P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C

P0C0 FLG 0.72H.0 R/W Bit 0 of port 0C

P0D3 FLG 0.73H.3 R/W Bit 3 of port 0D

P0D2 FLG 0.73H.2 R/W Bit 2 of port 0D

P0D1 FLG 0.73H.1 R/W Bit 1 of port 0D

P0D0 FLG 0.73H.0 R/W Bit 0 of port 0D

P0E3 FLG 0.6EH.3 R/W Bit 3 of port 0E

P0E2 FLG 0.6EH.2 R/W Bit 2 of port 0E

P0E1 FLG 0.6EH.1 R/W Bit 1 of port 0E

P0E0 FLG 0.6EH.0 R/W Bit 0 of port 0E

P0F1 FLG 0.6FH.1 R Bit 1 of port 0F

P0F0 FLG 0.6FH.0 R Bit 0 of port 0F

77

µ

PD17145(A1), 17147(A1), 17149(A1)

Register file (control registers)

Symbol Name Attribute Value Read/Write Description

SP MEM 0.81H R/W Stack pointer

SIOTS FLG 0.82H.3 R/W Serial interface start flag

SIOHIZ FLG 0.82H.2 R/W P0D1/SO pin function select flag

SIOCK1 FLG 0.82H.1 R/W Bit 1 of serial clock select flag

SIOCK0 FLG 0.82H.0 R/W Bit 0 of serial clock select flag

WDTRES FLG 0.83H.3 R/W Watchdog timer reset flag

WDTEN FLG 0.83H.0 R/W Watchdog timer enable flag

TM1OSEL FLG 0.8BH.3 R/W P0D3/TM1OUT pin function select flag

SIOEN FLG 0.8BH.0 R/W Serial interface enable flag

P0EGPU FLG 0.8CH.2 R/W P0E group pull-up select flag (pull-up = 1)

P0BGPU FLG 0.8CH.1 R/W P0B group pull-up select flag (pull-up = 1)

P0AGPU FLG 0.8CH.0 R/W P0A group pull-up select flag (pull-up = 1)

P0DBPU3 FLG 0.8DH.3 R/W P0D3 pull-up select flag (pull-up = 1)

P0DBPU2 FLG 0.8DH.2 R/W P0D2 pull-up select flag (pull-up = 1)

P0DBPU1 FLG 0.8DH.1 R/W P0D1 pull-up select flag (pull-up = 1)

P0DBPU0 FLG 0.8DH.0 R/W P0D0 pull-up select flag (pull-up = 1)

INT FLG 0.8FH.0 R INT pin status flag

TM0EN FLG 0.91H.3 R/W Timer 0 enable flag

TM0RES FLG 0.91H.2 R/W Timer 0 reset flag

TM0CK1 FLG 0.91H.1 R/W Bit 1 of timer 0 count pulse select flag

TM0CK0 FLG 0.91H.0 R/W Bit 0 of timer 0 count pulse select flag

TM1EN FLG 0.92H.3 R/W Timer 1 enable flag

TM1RES FLG 0.92H.2 R/W Timer 1 reset flag

TM1CK1 FLG 0.92H.1 R/W Bit 1 of timer 1 count pulse select flag

TM1CK0 FLG 0.92H.0 R/W Bit 0 of timer 1 count pulse select flag

BTMISEL FLG 0.93H.3 R/W Basic interval timer interrupt request clock select flag

BTMRES FLG 0.93H.2 R/W Basic interval timer reset flag

BTMCK1 FLG 0.93H.1 R/W Bit 1 of basic interval timer count pulse select flag

BTMCK0 FLG 0.93H.0 R/W Bit 0 of basic interval timer count pulse select flag

P0C3IDI FLG 0.9BH.3 R/W P0C3 input port disable flag (selects ADC3/P0C3 pin function)

P0C2IDI FLG 0.9BH.2 R/W P0C2 input port disable flag (selects ADC2/P0C2 pin function)

P0C1IDI FLG 0.9BH.1 R/W P0C1 input port disable flag (selects ADC1/P0C1 pin function)

P0C0IDI FLG 0.9BH.0 R/W P0C0 input port disable flag (selects ADC0/P0C0 pin function)

P0CBIO3 FLG 0.9CH.3 R/W P0C3 input/output select flag (1 = output port)

P0CBIO2 FLG 0.9CH.2 R/W P0C2 input/output select flag (1 = output port)

P0CBIO1 FLG 0.9CH.1 R/W P0C1 input/output select flag (1 = output port)

P0CBIO0 FLG 0.9CH.0 R/W P0C0 input/output select flag (1 = output port)

IEGMD1 FLG 0.9FH.1 R/W Bit 1 of INT pin edge detection select flag

IEGMD0 FLG 0.9FH.0 R/W Bit 0 of INT pin edge detection select flag

78

µ

PD17145(A1), 17147(A1), 17149(A1)

Register file (control registers)

Symbol Name Attribute Value Read/Write Description

ADCSTRT FLG 0.0A0H.0 R/W A/D converter start flag (read: always “0”)

ADCSOFT FLG 0.0A1H.3 R/W A/D converter mode select flag (1 = single mode)

ADCCMP FLG 0.0A1H.1 R A/D converter comparator comparison result flag

(valid only in single mode)

ADCEND FLG 0.0A1H.0 R A/D converter conversion end flag

ADCCH3 FLG 0.0A2H.3 R/W Dummy flag

ADCCH2 FLG 0.0A2H.2 R/W Dummy flag

ADCCH1 FLG 0.0A2H.1 R/W Bit 1 of A/D converter channel select flag

ADCCH0 FLG 0.0A2H.0 R/W Bit 0 of A/D converter channel select flag

P0DBIO3 FLG 0.0ABH.3 R/W P0D3 input/output select flag (1 = output port)

P0DBIO2 FLG 0.0ABH.2 R/W P0D2 input/output select flag (1 = output port)

P0DBIO1 FLG 0.0ABH.1 R/W P0D1 input/output select flag (1 = output port)

P0DBIO0 FLG 0.0ABH.0 R/W P0D0 input/output select flag (1 = output port)

P0EGIO FLG 0.0ACH.2 R/W P0E group input/output select flag

(1 = all P0E as output port)

P0BGIO FLG 0.0ACH.1 R/W P0B group input/output select flag

(1 = all P0B as output port)

P0AGIO FLG 0.0ACH.0 R/W P0A group input/output select flag

(1 = all P0A as output port)

IPSIO FLG 0.0AEH.0 R/W Serial interface interrupt enable flag

IPBTM FLG 0.0AFH.3 R/W Basic interval timer interrupt enable flag

IPTM1 FLG 0.0AFH.2 R/W Timer 1 interrupt enable flag

IPTM0 FLG 0.0AFH.1 R/W Timer 0 interrupt enable flag

IP FLG 0.0AFH.0 R/W INT pin interrupt enable flag

IRQSIO FLG 0.0BBH.0 R/W Serial interface interrupt request flag

IRQBTM FLG 0.0BCH.0 R/W Basic interval timer interrupt request flag

IRQTM1 FLG 0.0BDH.0 R/W Timer 1 interrupt request flag

IRQTM0 FLG 0.0BEH.0 R/W Timer 0 interrupt request flag

IRQ FLG 0.0BFH.0 R/W INT pin interrupt request flag

79

µ

PD17145(A1), 17147(A1), 17149(A1)

Peripheral hardware registers

Symbol Name Attribute Value Read/Write Description

SIOSFR DAT 01H R/W Peripheral address of shift register

TM0M DAT 02H W Peripheral address of timer 0 modulo register

TM1M DAT 03H W Peripheral address of timer 1 modulo register

ADCR DAT 04H R/W Peripheral address of A/D converter data register

TM0TM1C DAT 45H R Peripheral address of timer 0 timer 1 count register

AR DAT 40H R/W Peripheral address of address register for GET/PUT/

PUSH/CALL/BR/MOVT/INC instruction

Others

Symbol Name Attribute Value Description

DBF DAT 0FH Fixed operand value of PUT, GET, and MOVT instructions

IX DAT 01H Fixed operand value of INC instruction

80

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 21-2. Configuration of Control Register

Remark ( ) is the address when the assembler (AS17K) is used.

All the flags of the control register are registered to the device file as assembler reserved words,

and are convenient for program development.

Column address

Row

address Item

0

(8)

1

(9)

2

(A)

3

(B)

01 234 567

Symbol

S

I

O

T

S

S

I

O

H

I

Z

S

I

O

C

K

1

S

I

O

C

K

0

W

D

T

R

E

S

00

W

D

T

E

N

0

S

P

010100000000

R/W R/W R/W

Read/

Write

At reset

Symbol

Symbol

At reset

Read/

Write

At reset

Read/

Write

Symbol

At reset

Read/

Write

R/W R/W R/W

R/W R/W R/W

T

M

0

E

N

T

M

0

R

E

S

T

M

0

C

K

1

T

M

0

C

K

0

T

M

1

E

N

T

M

1

R

E

S

T

M

1

C

K

1

T

M

1

C

K

0

B

T

M

I

S

E

L

B

T

M

R

E

S

B

T

M

C

K

1

B

T

M

C

K

0

000

A

D

C

S

T

R

T

A

D

C

S

O

F

T

0

A

D

C

C

M

P

A

D

C

E

N

D

A

D

C

C

H

3

A

D

C

C

H

2

A

D

C

C

H

1

A

D

C

C

H

0

000010000000

000000000000

R

81

µ

PD17145(A1), 17147(A1), 17149(A1)

Figure 21-2. Configuration of Control Register

Note INT flag differs depending on the status of the INT pin at that time.

FCEDBA98

Note

000000000000000

000000000000

0000000000000000

00001000100000000000

R/W R/W R/W R/W R/W

R/W R/W R/W R/W

R/W R/W R/W

R/W R/W RR/W

I

N

T

000

P

0

D

B

P

U

0

P

0

D

B

P

U

1

P

0

D

B

P

U

2

P

0

D

B

P

U

3

P

0

A

G

P

U

P

0

B

G

P

U

P

0

E

G

P

U

0

S

I

O

E

N

00

T

M

1

O

S

E

L

P

0

C

0

I

D

I

P

0

C

1

I

D

I

P

0

C

2

I

D

I

P

0

C

3

I

D

I

P

0

C

B

I

O

0

P

0

C

B

I

O

1

P

0

C

B

I

O

2

P

0

C

B

I

O

3

I

E

G

M

D

0

I

E

G

M

D

1

00

I

P

I

P

T

M

0

I

P

T

M

1

I

P

B

T

M

I

P

S

I

O

000

P

0

A

G

I

O

P

0

B

G

I

O

P

0

E

G

I

O

0

P

0

D

B

I

O

0

P

0

D

B

I

O

1

P

0

D

B

I

O

2

P

0

D

B

I

O

3

I

R

Q

S

I

O

000

I

R

Q

B

T

M

000

I

R

Q

T

M

1

000

I

R

Q

T

M

0

000

I

R

Q

000

82

µ

PD17145(A1), 17147(A1), 17149(A1)

22. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (Ta = 25 °C)

Parameter Symbol Condition Ratings Unit

Supply voltage VDD –0.3 to +7.0 V

A/D converter reference voltage VREF –0.3 to VDD + 0.3 V

P0A, P0B, P0C, P0D, P0E, P0F,

INT, RESET, XIN

Output voltage VO–0.3 to VDD + 0.3 V

Per P0A, P0B, or P0C Peak value –15 mA

Effective value –7.5 mA

Total of P0A, P0B, Peak value –30 mA

and P0C Effective value –15 mA

Per P0A, P0B, or P0C Peak value 15 mA

Effective value 7.5 mA

Per P0D or P0E Peak value 30 mA

Effective value 15 mA

Total of P0A, P0B, P0C, Peak value 100 mA

P0D, and P0E Effective value 50 mA

Operating temperature Topt –40 to +110 °C

Storage temperature Tstg –65 to +150 °C

28-pin plastic shrink DIP 140 mW

28-pin plastic SOP 85 mW

Note [Effective value] = [Peak value] × √Duty

Caution If the value of even one of the above parameters is exceeded even momentarily, the quality

of the product may be degraded. The absolute maximum ratings are the values exceeding

which may physically damage the product. Be sure to use the product with these values

not exceeded.

Recommended Supply Voltage Range (Ta = –40 to +110 °C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

fx = 400 kHz to 2 MHz 2.7 5.5 V

fx = 400 kHz to 4 MHz 3.6 5.5 V

fx = 400 kHz to 8 MHz 4.5 5.5 V

Supply voltage VDD A/D converter 4.0 5.5 V

POC circuit (mask option) fx = 400 kHz to 4 MHz 4.5 5.5 V

Absolute accuracy:

±1.5LSB, 2.5 V ≤

VREF ≤ VDD

Input voltage VI–0.3 to VDD + 0.3 V

High-level output current IOHNote

Low-level output current IOLNote

Power dissipation PdTa = 85 °C

CPU (other than A/D

converter and POC

circuit)

83

µ

PD17145(A1), 17147(A1), 17149(A1)

Output voltage, low

Output voltage, high VOH P0A, P0B, P0C

DC Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

VIH1 P0A, P0B, P0C, P0D, P0E, P0F 0.7VDD VDD V

Input voltage, high VIH2 RESET, SCK, SI, INT 0.8VDD VDD V

VIH3 XIN

VDD – 0.5

VDD V

VIL1 P0A, P0B, P0C, P0D, P0E, P0F 0 0.3VDD V

Input voltage, low VIL2 RESET, SCK, SI, INT 0 0.2VDD V

VIL3 XIN 0 0.4 V

4.5 ≤ VDD ≤ 5.5

VDD – 0.3

V

IOH = –1.0 mA

2.7 ≤ VDD < 4.5

VDD – 0.3

V

IOH = –0.5 mA

4.5 ≤ VDD ≤ 5.5 0.3 V

IOL = 1.0 mA

2.7 ≤ VDD < 4.5 0.3 V

IOL = 0.5 mA

P0D, P0E 4.5 ≤ VDD ≤ 5.5 1.0 V

VOL2 IOL = 15 mA 2.7 ≤ VDD < 4.5 2.0 V

Input leakage current, high

ILIH P0A, P0B, P0C, P0D, P0E, P0F VIN = VDD 5

µ

A

Input leakage current, low

ILIL P0A, P0B, P0C, P0D, P0E, P0F VIN = 0 V –5

µ

A

Output leakage current, high

ILOH P0A, P0B, P0C, P0D, P0E VOUT = VDD 5

µ

A

Output leakage current, low

ILOL P0A, P0B, P0C, P0D, P0E VOUT = 0 V –5

µ

A

P0A, P0B, P0E, P0F, RESET, INT 50 100 250 kΩ

P0D 3 10 30 kΩ

fx = 8.0 MHz

VDD = 5 V ± 10 %

2.0 4.5 mA

fx = 4.0 MHz

VDD = 5 V ± 10 %

1.4 3.3 mA

IDD1 Operation mode fx = 2.0 MHz

VDD = 3 V ± 10 %

0.5 1.5 mA

fx = 400 kHz

VDD = 5 V ± 10 %

0.9 1.7 mA

VDD = 3 V ± 10 %

0.3 1.0 mA

fx = 8.0 MHz

VDD = 5 V ± 10 %

1.0 2.0 mA

fx = 4.0 MHz

VDD = 5 V ± 10 %

0.9 1.9 mA

IDD2 HALT mode fx = 2.0 MHz

VDD = 3 V ± 10 %

0.3 1.0 mA

fx = 400 kHz

VDD = 5 V ± 10 %

0.7 1.5 mA

VDD = 3 V ± 10 %

0.3 0.9 mA

VDD = 5 V ± 10 % 3.0 30

µ

A

VDD = 3 V ± 10 % 2.0 30

µ

A

Notes 1. The pull-up resistors of P0F, RESET, and INT are mask options.

2. Excluding the current of the A/D converter and POC circuit, and the current flowing into the internal

pull-up resistor.

RPULL

Internal pull-up

resistorNote 1

IDD3 STOP mode

Supply currentNote 2

VOL1 P0A, P0B, P0C, P0D, P0E

84

µ

PD17145(A1), 17147(A1), 17149(A1)

CPU clock cycle time

(instruction execution

time)

fINT 0 400 kHz

RESET low-level width tRSL

RLS low-level width t RLSL

AC Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 ˚C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

VDD = 4.5 to 5.5 V 1.9 41

µ

s

tCY VDD = 3.6 to 5.5 V 3.9 41

µ

s

7.9 41

µ

s

INT input frequency

(TM0 count clock input)

INT high-, low-level width tINTH, VDD = 4.5 to 5.5 V 10

µ

s

(external interrupt input) tINTL 50

µ

s

VDD = 4.5 to 5.5 V 10

µ

s

50

µ

s

VDD = 4.5 to 5.5 V 10

µ

s

50

µ

s

Remark tCY = 16/fx (fx: system clock oscillation frequency)

Interrupt input timing

RESET input timing

RLS input timing

t

INTL

t

INTH

INT

RESET

t

RSL

RLS

t

RLSL

85

µ

PD17145(A1), 17147(A1), 17149(A1)

Serial transfer operation (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

VDD = 4.5 to 5.5 V 2.0

µ

s

10

µ

s

RL = 1 kΩ,VDD = 4.5 to 5.5 V 2.0

µ

s

CL = 100 pF 8

µ

s

Internal pull-up, VDD = 4.5 to 5.5 V 32

µ

s

CL = 100 pF 64

µ

s

VDD = 4.5 to 5.5 V 1.0

µ

s

5.0

µ

s

SCK high-, low-level t KH, RL = 1 kΩ,VDD = 4.5 to 5.5 V

tKCY/2 – 0.6

µ

s

width tKL CL = 100 pF

tKCY/2 – 1.2

µ

s

Internal pull-up, VDD = 4.5 to 5.5 V

tKCY/2 – 12

µ

s

CL = 100 pF

tKCY/2 – 24

µ

s

SI setup time (to SCK ↑)tSIK 100 ns

SI hold time (from SCK ↑)

tKSI 100 ns

RL = 1 kΩ, CL = 100 pF VDD = 4.5 to 5.5 V 0.8

µ

s

SO output delay time 1.4

µ

s

from SCK ↓Internal pull-up, VDD = 4.5 to 5.5 V 14

µ

s

CL = 100 pF 26

µ

s

Remark RL: load resistance of output line

CL: load capacitance of output line

Serial transfer timing

Input

Output

SCK cycle time t KCY

Input

Output

tKSO

VDD

RL

CL

Output line

SCK

SI

SO

t

KCY

t

KL

t

KH

t

SIK

t

KSI

t

KSO

Output data

Input data

86

µ

PD17145(A1), 17147(A1), 17149(A1)

A/D Converter (VDD = 4.0 to 5.5 V, Ta = –40 to +110 °C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

Resolution 888bit

Absolute accuracyNote 1 2.5 V ≤ VREF ≤ VDD ±1.5 LSB

Conversion timeNote 2 tCONV 25 t CY

µ

s

Analog input voltage VADIN 0VREF V

Reference input voltage VREF 2.5 VDD V

A/D converter circuit current I ADC When A/D converter operates 1.0 2.0 mA

VREF pin current I REF 0.1 0.3 mA

Notes 1. Absolute accuracy excluding quantization error (±0.5LSB)

2. Time since a conversion start instruction has been executed until conversion ends (ADCEND =

1) (50

µ

s at 8 MHz).

Remark tCY = 16/fx (fx: system clock oscillation frequency)

POC Circuit (mask optionNote 1) (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)

Parameter Symbol Condition MIN. TYP. MAX. Unit

POC detection voltageNote 2 VPOC 3.6 4.0 4.45 V

Supply voltage fall speed t POCS 0.08 V/ms

Reset detection pulse width t SAMP 1ms

POC circuit current IPOC 3.0 10

µ

A

Notes 1. The POC circuit can be used in an application circuit that operates at VDD = 4.5 to 5.5 V,

fx = 400 kHz to 4 MHz.

2. This is the voltage at which the POC circuit clears its internal reset operation. The internal reset

is cleared when VPOC < VDD.

87

µ

PD17145(A1), 17147(A1), 17149(A1)

Oscillator Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)

ResonatorNote Symbol Condition MIN. TYP. MAX. Unit

0.39 2.04 MHz

Ceramic resonator Oscillation frequency VDD = 3.6 to 5.5 V 0.39 4.08 MHz

VDD = 4.5 to 5.5 V 0.39 8.16 MHz

Note Do not use a resonator whose oscillation growth time exceeds 2 ms.

Recommended Ceramic Resonator (Ta = –40 to +110 °C)

Recommended Constants Operating Supply Voltage [V]

Part Number Remark

C1 [pF] C2 [pF] Rd [kΩ] MIN. MAX.

CSB400JA 220 220 5.6 2.7 5.5

CSA2.00MGA040 100 100 0 2.7 5.5

CST2.00MGA040 Unnecessary (C-contained type) 0 2.7 5.5

CSA4.00MGA 30 30 0 3.6 5.5

CST4.00MGWA Unnecessary (C-contained type) 0 3.6 5.5

CSA8.00MTZA 30 30 0 4.5 5.5

CST8.00MTWA Unnecessary (C-contained type) 0 4.5 5.5

External Circuit Example

Manufac-

turer

Murata

Mfg. Co.

For

automotive

electronics

X

IN

X

OUT

Rd

C2C1

88

µ

PD17145(A1), 17147(A1), 17149(A1)

23. CHARACTERISTIC CURVE (REFERENCE VALUE)

IOL vs. VOL Characteristic Example 1 (P0A, P0B, P0C)

Caution The absolute maximum rating is 15 mA (peak value) per pin.

X

IN

X

OUT

C2

Operation mode (8 MHz)

Operation mode (4 MHz)

Operation mode (2 MHz)

HALT mode (8 MHz)

HALT mode (2 MHz)

HALT mode (4 MHz)

0 2.0 3.0 4.0 5.0

2.7 3.6 5.5

Suppl

y

volta

g

e V

DD

[

V

]

Supply current I

DD

[mA]

1.0

2.0

3.0

4.0 (T

a

= 25 ˚C)

C1

CSA 8.00MTZA (C1 = C2 = 30 pF)

CSA 4.00MGA (C1 = C2 = 30 pF)

CSA 2.00MGA040 (C1 = C2 = 100 pF)

(T

a

= 25 ˚C)

20

15

10

5

0123

Low-level output voltage V

OL

[V]

Low-level output current I

OL

[mA]

V

DD

= 5.0 V V

DD

= 4.5 V

V

DD

= 3.5 V

89

µ

PD17145(A1), 17147(A1), 17149(A1)

IOL vs. VOL Characteristics Example 2 (P0D, P0E)

Caution The absolute maximum rating is 30 mA (peak value) per pin.

IOH vs. (VDD - VOH) Characteristic Example

Caution The absolute maximum rating is –15 mA (peak value) per pin.

(T

a

= 25 ˚C)

30

20

10

012

Low-level output volta

g

e V

OL

[V]

Low-level output current I

OL

[mA]

V

DD

= 5.0 V

V

DD

= 4.5 V

V

DD

= 3.5 V

– 5

0

High-level output current I

OH

[mA]

– 10

– 15

– 20

12

V

DD

– V

OH

[V]

3

V

DD

= 5.0 V V

DD

= 4.5 V

V

DD

= 3.5 V

(T

a

= 25 ˚C)

90

µ

PD17145(A1), 17147(A1), 17149(A1)

24. PACKAGE DRAWINGS

Caution The ES model differs from the mass-produced model in terms of outline dimensions and

materials. Refer to the drawing of the ES model.

28 PIN PLASTIC SHRINK DIP (400 mil)

ITEM MILLIMETERS INCHES

A

B

C

F

G

H

I

J

K

28.46 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

2.67 MAX.

L

0.17

10.16 (T.P.)

5.08 MAX.

8.6

N

0.85 MIN.

1.121 MAX.

0.106 MAX.

0.033 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.400 (T.P.)

0.339

0.007

0.070 (T.P.)

S28C-70-400B-1

A

B

I

J

G

D 0.50±0.10 0.020

M 0.25 0.010

+0.10

–0.05

R 0~15°0~15°

+0.004

–0.005

+0.004

–0.003

NOTES

Each lead centerline is located within 0.17 mm (0.007 inch)

of its true position (T.P.) at maximum material condition.

Item "K" to center of leads when formed parallel.

1)

2)

28 15

114

M

H

C

N

F

DM

R

K

L

91

µ

PD17145(A1), 17147(A1), 17149(A1)

P28GT-50-375B-1

ITEM MILLIMETERS INCHES

NOTE

Each lead centerline is located within 0.12

mm (0.005 inch) of its true position (T.P.) at

maximum material condition.

18.2 MAX.

0.845 MAX.

1.27 (T.P.)

0.40

0.125±0.075

2.9 MAX.

2.50±0.2

10.3±0.3

7.2±0.2

1.6±0.2

0.15

0.8±0.2

0.12

0.10

0.717 MAX.

0.034 MAX.

0.050 (T.P.)

0.016

0.005±0.003

0.115 MAX.

0.098

0.406

0.283

0.063±0.008

0.006

0.031

0.005

0.004

+0.009

–0.008

A

B

C

D

E

F

G

H

I

J

K

L

M

N

+0.10

–0.05

+0.10

–0.05 +0.004

–0.002

+0.009

–0.008

+0.012

–0.013

+0.009

–0.008

+0.004

–0.003

28 PIN PLASTIC SOP (375 mil)

28 15

A

I

M

M

D

CN

K

detail of lead end

E

F

G

B

H

L

J

114

3°

+7°

–3°

Caution The ES model differs from the mass-produced model in terms of outline dimension and

materials. Refer to the drawing of the ES model.

92

µ

PD17145(A1), 17147(A1), 17149(A1)

28 PIN CERAMIC SHRINK DIP (400 mil) (For ES)

ITEM MILLIMETERS INCHES

A

B

C

D

F

G

H

I

J

28.0 MAX.

1.778 (T.P.)

0.8 MIN.

3.0±1.0

1.0 MIN.

5.1 MAX.

4.3 MAX.

2.7

0.46±0.05

1.103 MAX.

0.201 MAX.

0.018±0.002

0.031 MIN.

0.118±0.04

0.039 MIN.

0.106

0.170 MAX.

0.070 (T.P.)

P28D-70-400B-1

A

J

NOTES

1) Each lead centerline is located within 0.25 mm (0.01 inch) of

its true position (T.P.) at maximum material condition.

K

L

M

10.16 (T.P.)

9.84

0.25±0.05

0.400 (T.P.)

0.387

0.010

N 0.25 0.010

R 0~15° 0~15°

+0.002

–0.003

2) ltem "K" to center of leads when formed parallel.

M

I

G

H

F

DN

CBMR

K

L

28 15

114

93

µ

PD17145(A1), 17147(A1), 17149(A1)

X28B-50B1

ITEM MILLIMETERS INCHES

A

C

D

G

I

J

K

T

18.0±0.2

0.4±0.05

16.4

0.15±0.025

1.0

1.27 (T.P.)

1.52±0.15

8.4±0.15

0.709

0.05 (T.P.)

0.06±0.006

0.331

0.646

0.006±0.001

0.039

The lengths of leads ( 1 ) and the height of potting ( 2 ) are

not to be specified because the lead cutting process and

the potting process are not controlled.

+0.008

–0.009

0.016+0.002

–0.003

+0.006

–0.007

28 PIN CERAMIC SOP (For ES)

NOTE

A

I

J 1

DC

T 2

GK

94

µ

PD17145(A1), 17147(A1), 17149(A1)

25. RECOMMENDED SOLDERING CONDITIONS

Solder this product under the following recommended conditions.

For details of the recommended soldering conditions, refer to Information Document Semiconductor Device

Mounting Technology Manual (C10535E).

For the other soldering conditions and methods, consult NEC.

Table 25-1. Soldering Conditions of Surface Mount Type

µ

PD17145GT(A1)-×××: 28-pin plastic SOP (375 mil)

µ

PD17147GT(A1)-×××: 28-pin plastic SOP (375 mil)

µ

PD17149GT(A1)-×××: 28-pin plastic SOP (375 mil)

Symbol of Recommended

Soldering Method Soldering Condition Condition

Package peak temperature: 235 °C, Time: 30 seconds max.

(210 °C min.), Number of times: 2 max., DurationNote:

7 (after that, prebaking is necessary for 20 hours at 125 °C.)

<Remarks>

(1) Start second reflow after the device temperature that has

risen because of the first reflow has fallen to room

temperature.

(2) Do not clean flux with water after the first reflow.

Package peak temperature: 215 °C, Time: 40 seconds max.

(200 ˚C min.), Number of times: 2 max., DurationNote:

7 (after that, prebaking is necessary for 20 hours at 125 °C.)

<Remarks>

(1) Start second reflow after the device temperature that has

risen because of the first reflow has fallen to room

temperature.

(2) Do not clean flux with water after the first reflow.

Pin partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per side

of device)

Note Number of storage days after the dry pack was opened. Storage conditions: 25 °C, 65 %RH max.

Caution Do not use two or more soldering methods in combination (except pin partial heating).

Infrared reflow

VPS

IR35-207-2

VP15-207-2

—

95

µ

PD17145(A1), 17147(A1), 17149(A1)

Table 25-2. Soldering Conditions of Insertion Type

µ

PD17145CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)

µ

PD17147CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)

µ

PD17149CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)

Soldering Method Soldering Condition

Wave soldering (pin only) Solder bath temperature: 260 ˚C max., Time: 10 seconds max.

Pin partial heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of pin)

Caution When performing wave soldering, exercise care that only the pins are wetted with solder

and that no part of the package must be wetted.

96

µ

PD17145(A1), 17147(A1), 17149(A1)

APPENDIX A. FUNCTION COMPARISON BETWEEN

µ

PD17145 SUBSERIES AND THE

µ

PD17135A

AND 17137A

µ

PD17145

µ

PD17147

µ

PD17149

µ

PD17135A

µ

PD17137A

ROM 2 KB 4 KB 8 KB 2 KB 4 KB

RAM 110 × 4 bits 112 × 4 bits

Stack Address stack × 5 levels

Interrupt stack × 3 levels

Instruction execution time 2

µ

s (8 MHz, 4.5 to 5.5 V) 2

µ

s (8 MHz, 4.5 to 5.5 V)

(clock, operating voltage) 4

µ

s (4 MHz, 3.6 to 5.5 V) 4

µ

s (4 MHz, 2.7 to 5.5 V)

8

µ

s (2 MHz, 2.7 to 5.5 V)

CMOS I/O 12 (P0A, P0B, P0C)

Input 2 (P0F0, P0F1) 1 (P1B0)

Sense input 1 (INT) 1 (INT)

I/O Can be pulled up by mask option

N-ch open-drain I/O 8 (P0D, P0E voltage: VDD) 8 (P0D, P1A voltage: 9 V)

P0D pull-up: software P0D pull-up: mask option

P0E pull-up: software P1A pull-up: mask option

Internal pull-up resistor 100 kΩ TYP. (except P0D) 100 kΩ TYP.

10 kΩ TYP. (P0D)

A/D converter 8 bits × 4 channels 8 bits × 4 channels

(operating voltage) (VDD = 4.0 to 5.5 V) (VDD = 4.5 to 5.5 V)

Reference voltage pin VREF (VREF = 2.5 V to VDD) None (VREF = VADC = VDD)

8-bit (TM0, TM1) 2 (timer output: TM1OUT) 2 (timer output: TM0OUT)

TM0 clock: system clock/512 TM0 clock: system clock/256

system clock/64 system clock/64

system clock/16 system clock/16

INT INT

TM1 clock: system clock/8192 TM1 clock: system clock/1024

system clock/128 system clock/512

system clock/16 system clock/256

TM0 count up TM0 count up

Basic interval (BTM) 1 (also used as watchdog timer) 1 (also used as watchdog timer)

Count clock: system clock/16384 Count clock: system clock/8192

system clock/4096 system clock/4096

system clock/512 TM0 count up

system clock/16 INT

Interrupt External 1 1

(with AC zero cross detection)

Internal 4 (TM0, TM1, BTM, SIO)

SIO 1 (clocked 3-wire)

Output latch Independent of P0D1 latch Shared with P0D1 latch

Standby function HALT, STOP HALT, STOP

(can be released by RLS input pin)

Timer

97

µ

PD17145(A1), 17147(A1), 17149(A1)

µ

PD17145

µ

PD17147

µ

PD17149

µ

PD17135A

µ

PD17137A

Oscillation stabilization 128 × 256 counts 512 × 256 counts

wait time

POC function Mask option Internal

Package 28-pin plastic SDIP (400 mil)

28-pin plastic SOP (375 mil)

One-time PROM

µ

PD17P149

µ

PD17P137A

Caution The

µ

PD17145 subseries is not pin-compatible with the

µ

PD17135A and 17137A. The

µ

PD17145 subseries does not include a product equivalent to the

µ

PD17134A and 17136A

(RC oscillation type). For the electrical specifications of each product, refer to the Data

Sheet of the product.

98

µ

PD17145(A1), 17147(A1), 17149(A1)

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for developing programs for the

µ

PD17145(A1), 17147(A1),

and 17149(A1):

Hardware

Notes 1. Low-cost model: external power supply type

2. This is a product of IC Corporation. For details, consult IC Corporation (Tokyo (03) 3447-3793).

3. Two EV-97500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are separately

available as a set.

4. These are products of Ando Electric Corporation. For details, consult Ando Electric Corporation

(Tokyo (03) 3733-1151).

Outline

IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators that can be used with any

products in the 17K series. IE-17K and IE-17K-ET are connected to PC-9800 series

or IBM PC/AT as the host machine with RS-232-C. EMU-17K is inserted into an

expansion slot of the PC-9800 series.

These in-circuit emulators operate as the emulator for a device when used in

combination with the dedicated system evaluation board (SE board) of the device.

When man-machine interface, SIMPLEHOST, is used a sophisticated debugging

environment can be realized. EMU-17K also has a function that allows real-time

monitoring of the contents of the data memory.

SE-17145 is an SE board for the

µ

PD17145 subseries. It can be used alone to

evaluate the system, or in combination with an in-circuit emulator for debugging.

EP-17K28CT is an emulation probe for the 17K series 28-pin shrink DIP (400 mil).

EP-17K28GT is an emulation probe for the 17K series 28-pin SOP (375 mil).

It connects the SE board and target system when used with EV-9500GT-28Note 3.

EV-9500GT-28 is an adapter for the 28-pin SOP (375 mil). It is used to connect EP-

17K28GT and target system.

AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers supporting the

µ

PD17P149. By connecting programmer adapter AF-9808M to these programmers,

the

µ

PD17P149 can be programmed.

AF-9808M is an adapter used to program the

µ

PD17P149, in combination with AF-

9703, AF-9704, AF-9705, or AF-9706.

Name

In-circuit emulator

IE-17K,

IE-17K-ETNote 1,

EMU-17KNote 2

SE board (SE-17145)

Emulation probe

(EP-17K28CT)

Emulation probe

(EP-17K28GT)

Conversion adapter

(EV-9500GT-28Note 3)

PROM programmerNote 4

(AF-9703, AF-9704,

AF-9705 or AF-9706)

Programmer adapterNote 4

(AF-9808M)

99

µ

PD17145(A1), 17147(A1), 17149(A1)

Supply

Media

5"2HD

3.5"2HD

5"2HC

3.5"2HC

5"2HD

3.5"2HD

5"2HC

3.5"2HC

5"2HD

3.5"2HD

5"2HC

3.5"2HC

Order Code

µ

S5A10AS17K

µ

S5A13AS17K

µ

S7B10AS17K

µ

S7B13AS17K

µ

S5A10AS17145Note

µ

S5A13AS17145Note

µ

S7B10AS17145Note

µ

S7B13AS17145Note

µ

S5A10IE17K

µ

S5A13IE17K

µ

S7B10IE17K

µ

S7B13IE17K

OS

MS-DOS

PC DOS

MS-DOS

PC DOS

Host Machine

PC-9800

series

IBM PC/AT

PC-9800

series

IBM PC/AT

PC-9800

series

IBM PC/AT

Outline

AS17K is an assembler that

can be used with any prod-

ucts in the 17K series. To

develop the program of the

µ

PD17145(A1), 17147(A1),

and 17149(A1), the AS17K

and a device file (AS17145,

AS17147, or AS17149) are

used in combination.

AS17145, AS17147, and

AS17149 are device files

for the

µ

PD17145(A1),

17147(A1), 17149(A1),

and

µ

PD17P149. They can

be used in combination with

the assembler for the 17K

series (AS17K).

SIMPLEHOST is software that

serves as man-machine

interface on Windows when

a program is developed by

using an in-circuit emulator

and a personal computer.

MS-DOS

PC DOS

Windows

Name

17K series

assembler

(AS17K)

Device file

AS17145,

AS17147,

AS17149

Support software

(SIMPLEHOST)

Software

Note

µ

S××××AS17145 includes AS17145, AS17147, and AS17149.

Remark The version of the OS supported is as follows:

OS Version

MS-DOS Ver. 3.30 to Ver. 5.00ANote

PC DOS Ver. 3.1 to Ver. 5.0Note

Windows Ver. 3.0 to Ver. 3.1

Note Although MS-DOS Ver.5.00/5.00A and

PC DOS Ver. 5.0 have a task swap

function, this function cannot be used

with this software.

100

µ

PD17145(A1), 17147(A1), 17149(A1)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to VDD or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

101

µ

PD17145(A1), 17147(A1), 17149(A1)

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel:2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel:253-8311

Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil

Tel: 011-6465-6810

Fax: 011-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel:040-2445845

Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel:01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 01-504-2787

Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

J97. 8

µ

PD17145(A1), 17147(A1), 17149(A1)

SIMPLEHOST is a trademark of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corpora-

tion in the United States and/or other countries.

PC/AT and PC DOS are trademarks of IBM Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5