MC74VHC139DR2G - ON SEMICONDUCTOR

May, 2011 − Rev. 4

1Publication Order Number:

MC74VHC139/D

MC74VHC139

Dual 2-to-4 Decoder/

Demultiplexer

The MC74VHC139 is an advanced high speed CMOS 2−to−4

decoder/ demultiplexer fabricated with silicon gate CMOS

technology. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining CMOS low power

dissipation.

When the device is enabled (E = low), it can be used for gating or as

a data input for demultiplexing operations. When the enable input is

held high, all four outputs are fixed high, independent of other inputs.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7 V, allowing the interface of 5 V

systems to 3 V systems.

•High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2 V to 5.5 V Operating Range

•Low Noise: VOLP = 0.8 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: Human Body Model > 2000 V;

Machine Model > 200 V

•Chip Complexity: 100 FETs or 25 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

SOIC−16

D SUFFIX

CASE 751B

MARKING DIAGRAMS

18

9

16

18

16 9

VHC139

AWLYYWW

VHC

139

ALYW

TSSOP−16

DT SUFFIX

CASE 948F

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Ea

A1a

A0a

GND

A1b

A0b

Eb

VCC

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

PIN ASSIGNMENT

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Figure 1. Logic Diagram

A0a

A1a

Ea

A0b

A1b

1

Eb

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

ACTIVE-LOW

OUTPUTS

ADDRESS

INPUTS

ACTIVE-LOW

OUTPUTS

3

2

ADDRESS

INPUTS 13

14

15

4

5

6

7

12

11

10

9

Table 1. FUNCTION TABLE

Inputs Outputs

E A1 A0 Y0 Y1 Y2 Y3

H X X H H H H

L L L L H H H

L L H H L H H

L H L H H L H

L H H H H H L

En

A0

A1

Y0

Y1

Y2

Y3

Figure 2. Expanded Logic Diagram

(1/2 of Device)

INPUT

Figure 3. Input Equivalent Circuit

4

Figure 4. IEC Logic Diagram

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

5

6

7

12

11

10

9

15

14

13

1

2

3

A1a

A0a

Ea

A1b

A0b

Eb

2

1

EN

X/Y

1

0

2

3

0

1

DMUX

1

0

2

3

G0

3

15

14

13

1

2

3

A1a

A0a

Ea

A1b

A0b

Eb

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

4

5

6

7

12

11

10

9

MC74VHC139

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎÎÎ

–0.5 to VCC + 0.5

ÎÎ

V

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎÎ

−20

ÎÎ

mA

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current

ÎÎÎÎÎÎ

±20

ÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

±25

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

±75

ÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎÎÎ

500

450

ÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

–65 to +150

ÎÎ

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating −SOIC Packages: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

2.0

ÎÎÎ

5.5

ÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

0

ÎÎÎ

5.5

ÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎ

0

ÎÎÎ

VCC

ÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

−55

ÎÎÎ

+125

ÎÎ

°C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 3.3 V ±0.3V

(Figure 3) VCC =5.0 V ±0.5V

ÎÎÎ

0

ÎÎÎ

100

20

ÎÎ

ns/V

The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the

expected lifetime of the device per the table and figure below.

DEVICE JUNCTION TEMPERATURE VERSUS

TIME TO 0.1% BOND FAILURES

Junction

Temperature (°C) Time, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1

1 10 100 1000

TIME, YEARS

NORMALIZED FAILURE RATE

TJ= 80 C°

TJ= 90 C°

TJ= 100 C°

TJ= 110 C°

TJ= 130 C°

TJ= 120 C°

FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLICS OCCUR

Figure 5. Failure Rate vs. Time

Junction Temperature

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

(V)

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = ≤ 85°C

ÎÎÎÎÎÎÎ

TA = ≤ 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎ

Minimum

High−Level Input

Voltage

ÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎ

1.5

2.1

3.15

3.85

ÎÎÎ

ÎÎ

ÎÎÎÎ

1.5

2.1

3.15

3.85

ÎÎÎ

ÎÎÎÎ

1.5

2.1

3.15

3.85

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎ

Maximum

Low−Level Input

Voltage

ÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎ

ÎÎ

0.5

0.9

1.35

1.65

ÎÎÎÎ

ÎÎÎ

0.5

0.9

1.35

1.65

ÎÎÎÎ

0.5

0.9

1.35

1.65

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎ

Minimum

High−Level Output

Voltage

VIN = VIH or VIL

ÎÎÎÎÎÎ

VIN = VIH or VIL

IOH = − 50 mA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎ

1.9

2.9

4.4

ÎÎÎ

2.0

3.0

4.5

ÎÎ

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎ

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎÎÎ

VIN = VIH or VIL

IOH = −4 mA

IOH = −8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

2.58

3.94

ÎÎÎ

ÎÎ

ÎÎÎÎ

2.48

3.80

ÎÎÎ

ÎÎÎÎ

2.34

3.66

ÎÎÎÎ

VOL

ÎÎÎÎÎÎ

Maximum

Low−Level Output

Voltage

VIN = VIH or VIL

ÎÎÎÎÎÎ

VIN = VIH or VIL

IOL = 50 mA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎ

0.0

ÎÎ

0.1

ÎÎÎÎ

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎ

VIN = VIH or VIL

IOL = 4 mA

IOL = 8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

ÎÎ

0.36

ÎÎÎÎ

ÎÎÎ

0.44

ÎÎÎÎ

0.52

ÎÎÎÎ

IIN

ÎÎÎÎÎÎ

Maximum Input

Leakage Current

ÎÎÎÎÎÎ

VIN = 5.5 V or GND

ÎÎÎ

0 to

5.5

ÎÎÎ

ÎÎ

±0.1

ÎÎÎÎ

ÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎ

Maximum

Quiescent Supply

Current

ÎÎÎÎÎÎ

VIN = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

4.0

ÎÎÎÎ

ÎÎÎ

40.0

ÎÎÎÎ

40.0

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎÎÎÎÎÎ

TA = − 55 to 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎ

Maximum

Propagation Delay,

A to Y

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 VCL = 15 pF

CL = 50 pF

ÎÎÎ

7.2

9.7

ÎÎ

11.0

14.5

ÎÎÎÎ

1.0

ÎÎÎ

13.0

16.5

ÎÎÎÎ

1.0

ÎÎÎÎ

13.0

16.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 VCL = 15 pF

CL = 50 pF

ÎÎÎ

5.0

6.5

ÎÎ

7.2

9.2

ÎÎÎÎ

1.0

ÎÎÎ

8.5

10.5

ÎÎÎÎ

1.0

ÎÎÎÎ

8.5

10.5

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎ

Maximum

Propagation Delay,

E to Y

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 VCL = 15 pF

CL = 50 pF

ÎÎÎ

6.4

8.9

ÎÎ

9.2

12.7

ÎÎÎÎ

1.0

ÎÎÎ

11.0

14.5

ÎÎÎÎ

1.0

ÎÎÎÎ

11.0

14.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 VCL = 15 pF

CL = 50 pF

ÎÎÎ

4.4

5.9

ÎÎ

6.3

8.3

ÎÎÎÎ

1.0

ÎÎÎ

7.5

9.5

ÎÎÎÎ

1.0

ÎÎÎÎ

7.5

9.5

ÎÎÎÎ

CIN

ÎÎÎÎÎÎ

Maximum Input

Capacitance

ÎÎÎÎÎÎÎÎ

ÎÎÎ

4

ÎÎ

10

ÎÎÎÎ

ÎÎÎ

10

ÎÎÎÎ

10

ÎÎ

pF

CPD Power Dissipation Capacitance (1)

Typical @ 25°C, VCC = 5.0 V

pF

26

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/2 (per decoder). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

MC74VHC139

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Figure 6.

50%

tPHL

tPLH

VCC

GND

Y50% VCC

A

SWITCHING WAVEFORMS

VCC

GND

tPHL tPLH

Y

E

50% VCC

50%

Figure 7.

*Includes all probe and jig capacitance

Figure 8. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

MC74VHC139

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6

ORDERING INFORMATION

Device Package Shipping†

MC74VHC139DR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

MC74VHC139DTR2G TSSOP−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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7

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

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PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

___ _

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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MC74VHC139/D

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